Add ifpoll, which support hardware TX/RX queues based polling.
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
5330213c 68#include "opt_serializer.h"
8434a83b 69#include "opt_rss.h"
e6cde6e6 70#include "opt_emx.h"
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71
72#include <sys/param.h>
73#include <sys/bus.h>
74#include <sys/endian.h>
75#include <sys/interrupt.h>
76#include <sys/kernel.h>
77#include <sys/ktr.h>
78#include <sys/malloc.h>
79#include <sys/mbuf.h>
80#include <sys/proc.h>
81#include <sys/rman.h>
82#include <sys/serialize.h>
bc197380 83#include <sys/serialize2.h>
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84#include <sys/socket.h>
85#include <sys/sockio.h>
86#include <sys/sysctl.h>
87#include <sys/systm.h>
88
89#include <net/bpf.h>
90#include <net/ethernet.h>
91#include <net/if.h>
92#include <net/if_arp.h>
93#include <net/if_dl.h>
94#include <net/if_media.h>
95#include <net/ifq_var.h>
89d8e73d 96#include <net/toeplitz.h>
9cc86e17 97#include <net/toeplitz2.h>
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98#include <net/vlan/if_vlan_var.h>
99#include <net/vlan/if_vlan_ether.h>
b3a7093f 100#include <net/if_poll.h>
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101
102#include <netinet/in_systm.h>
103#include <netinet/in.h>
104#include <netinet/ip.h>
105#include <netinet/tcp.h>
106#include <netinet/udp.h>
107
108#include <bus/pci/pcivar.h>
109#include <bus/pci/pcireg.h>
110
111#include <dev/netif/ig_hal/e1000_api.h>
112#include <dev/netif/ig_hal/e1000_82571.h>
113#include <dev/netif/emx/if_emx.h>
114
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115#ifdef EMX_RSS_DEBUG
116#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117do { \
89d8e73d 118 if (sc->rss_debug >= lvl) \
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119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120} while (0)
121#else /* !EMX_RSS_DEBUG */
122#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123#endif /* EMX_RSS_DEBUG */
124
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125#define EMX_NAME "Intel(R) PRO/1000 "
126
127#define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129#define EMX_DEVICE_NULL { 0, 0, NULL }
130
131static const struct emx_device {
132 uint16_t vid;
133 uint16_t did;
134 const char *desc;
135} emx_devices[] = {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
146
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
150 EMX_DEVICE(82572EI),
151
152 EMX_DEVICE(82573E),
153 EMX_DEVICE(82573E_IAMT),
154 EMX_DEVICE(82573L),
155
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
160
161 EMX_DEVICE(82574L),
162
163 /* required last entry */
164 EMX_DEVICE_NULL
165};
166
167static int emx_probe(device_t);
168static int emx_attach(device_t);
169static int emx_detach(device_t);
170static int emx_shutdown(device_t);
171static int emx_suspend(device_t);
172static int emx_resume(device_t);
173
174static void emx_init(void *);
175static void emx_stop(struct emx_softc *);
176static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
177static void emx_start(struct ifnet *);
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178#ifdef IFPOLL_ENABLE
179static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
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180#endif
181static void emx_watchdog(struct ifnet *);
182static void emx_media_status(struct ifnet *, struct ifmediareq *);
183static int emx_media_change(struct ifnet *);
184static void emx_timer(void *);
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185static void emx_serialize(struct ifnet *, enum ifnet_serialize);
186static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
187static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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188#ifdef INVARIANTS
189static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
190 boolean_t);
191#endif
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192
193static void emx_intr(void *);
c39e3a1f 194static void emx_rxeof(struct emx_softc *, int, int);
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195static void emx_txeof(struct emx_softc *);
196static void emx_tx_collect(struct emx_softc *);
197static void emx_tx_purge(struct emx_softc *);
198static void emx_enable_intr(struct emx_softc *);
199static void emx_disable_intr(struct emx_softc *);
200
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201static int emx_dma_alloc(struct emx_softc *);
202static void emx_dma_free(struct emx_softc *);
5330213c 203static void emx_init_tx_ring(struct emx_softc *);
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204static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
205static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 206static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 207static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 208static void emx_destroy_tx_ring(struct emx_softc *, int);
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209static void emx_destroy_rx_ring(struct emx_softc *,
210 struct emx_rxdata *, int);
211static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 212static int emx_encap(struct emx_softc *, struct mbuf **);
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213static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
214static int emx_txcsum(struct emx_softc *, struct mbuf *,
215 uint32_t *, uint32_t *);
216
217static int emx_is_valid_eaddr(const uint8_t *);
218static int emx_hw_init(struct emx_softc *);
219static void emx_setup_ifp(struct emx_softc *);
220static void emx_init_tx_unit(struct emx_softc *);
221static void emx_init_rx_unit(struct emx_softc *);
222static void emx_update_stats(struct emx_softc *);
223static void emx_set_promisc(struct emx_softc *);
224static void emx_disable_promisc(struct emx_softc *);
225static void emx_set_multi(struct emx_softc *);
226static void emx_update_link_status(struct emx_softc *);
227static void emx_smartspeed(struct emx_softc *);
228
229static void emx_print_debug_info(struct emx_softc *);
230static void emx_print_nvm_info(struct emx_softc *);
231static void emx_print_hw_stats(struct emx_softc *);
232
233static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
234static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
235static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
236static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
237static void emx_add_sysctl(struct emx_softc *);
238
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239static void emx_serialize_skipmain(struct emx_softc *);
240static void emx_deserialize_skipmain(struct emx_softc *);
b3a7093f 241#ifdef IFPOLL_ENABLE
aabfe6fb 242static int emx_tryserialize_skipmain(struct emx_softc *);
b3a7093f 243#endif
bca7c435 244
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245/* Management and WOL Support */
246static void emx_get_mgmt(struct emx_softc *);
247static void emx_rel_mgmt(struct emx_softc *);
248static void emx_get_hw_control(struct emx_softc *);
249static void emx_rel_hw_control(struct emx_softc *);
250static void emx_enable_wol(device_t);
251
252static device_method_t emx_methods[] = {
253 /* Device interface */
254 DEVMETHOD(device_probe, emx_probe),
255 DEVMETHOD(device_attach, emx_attach),
256 DEVMETHOD(device_detach, emx_detach),
257 DEVMETHOD(device_shutdown, emx_shutdown),
258 DEVMETHOD(device_suspend, emx_suspend),
259 DEVMETHOD(device_resume, emx_resume),
260 { 0, 0 }
261};
262
263static driver_t emx_driver = {
264 "emx",
265 emx_methods,
266 sizeof(struct emx_softc),
267};
268
269static devclass_t emx_devclass;
270
271DECLARE_DUMMY_MODULE(if_emx);
272MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
273DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0);
274
275/*
276 * Tunables
277 */
278static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
279static int emx_rxd = EMX_DEFAULT_RXD;
280static int emx_txd = EMX_DEFAULT_TXD;
281static int emx_smart_pwr_down = FALSE;
282
283/* Controls whether promiscuous also shows bad packets */
284static int emx_debug_sbp = FALSE;
285
286static int emx_82573_workaround = TRUE;
287
288TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
289TUNABLE_INT("hw.emx.rxd", &emx_rxd);
290TUNABLE_INT("hw.emx.txd", &emx_txd);
291TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
292TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
293TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
294
295/* Global used in WOL setup with multiport cards */
296static int emx_global_quad_port_a = 0;
297
298/* Set this to one to display debug statistics */
299static int emx_display_debug_stats = 0;
300
301#if !defined(KTR_IF_EMX)
302#define KTR_IF_EMX KTR_ALL
303#endif
304KTR_INFO_MASTER(if_emx);
305KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
306KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
307KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
308KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
309KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
310#define logif(name) KTR_LOG(if_emx_ ## name)
311
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312static __inline void
313emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
314{
315 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 316 /* DD bit must be cleared */
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317 rxd->rxd_staterr = 0;
318}
319
320static __inline void
321emx_rxcsum(uint32_t staterr, struct mbuf *mp)
322{
323 /* Ignore Checksum bit is set */
324 if (staterr & E1000_RXD_STAT_IXSM)
325 return;
326
327 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
328 E1000_RXD_STAT_IPCS)
329 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
330
331 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
332 E1000_RXD_STAT_TCPCS) {
333 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
334 CSUM_PSEUDO_HDR |
335 CSUM_FRAG_NOT_CHECKED;
336 mp->m_pkthdr.csum_data = htons(0xffff);
337 }
338}
339
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340static __inline struct pktinfo *
341emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
342 uint32_t mrq, uint32_t hash, uint32_t staterr)
343{
344 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
345 case EMX_RXDMRQ_IPV4_TCP:
346 pi->pi_netisr = NETISR_IP;
347 pi->pi_flags = 0;
348 pi->pi_l3proto = IPPROTO_TCP;
349 break;
350
351 case EMX_RXDMRQ_IPV6_TCP:
352 pi->pi_netisr = NETISR_IPV6;
353 pi->pi_flags = 0;
354 pi->pi_l3proto = IPPROTO_TCP;
355 break;
356
357 case EMX_RXDMRQ_IPV4:
358 if (staterr & E1000_RXD_STAT_IXSM)
359 return NULL;
360
361 if ((staterr &
362 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
363 E1000_RXD_STAT_TCPCS) {
364 pi->pi_netisr = NETISR_IP;
365 pi->pi_flags = 0;
366 pi->pi_l3proto = IPPROTO_UDP;
367 break;
368 }
369 /* FALL THROUGH */
370 default:
371 return NULL;
372 }
373
374 m->m_flags |= M_HASH;
375 m->m_pkthdr.hash = toeplitz_hash(hash);
376 return pi;
377}
378
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379static int
380emx_probe(device_t dev)
381{
382 const struct emx_device *d;
383 uint16_t vid, did;
384
385 vid = pci_get_vendor(dev);
386 did = pci_get_device(dev);
387
388 for (d = emx_devices; d->desc != NULL; ++d) {
389 if (vid == d->vid && did == d->did) {
390 device_set_desc(dev, d->desc);
391 device_set_async_attach(dev, TRUE);
392 return 0;
393 }
394 }
395 return ENXIO;
396}
397
398static int
399emx_attach(device_t dev)
400{
401 struct emx_softc *sc = device_get_softc(dev);
402 struct ifnet *ifp = &sc->arpcom.ac_if;
6d435846 403 int error = 0, i;
5330213c
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404 uint16_t eeprom_data, device_id;
405
6d435846
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406 lwkt_serialize_init(&sc->main_serialize);
407 lwkt_serialize_init(&sc->tx_serialize);
408 for (i = 0; i < EMX_NRX_RING; ++i)
409 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
410
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411 i = 0;
412 sc->serializes[i++] = &sc->main_serialize;
413 sc->serializes[i++] = &sc->tx_serialize;
414 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
415 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
416 KKASSERT(i == EMX_NSERIALIZE);
417
5330213c
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418 callout_init(&sc->timer);
419
420 sc->dev = sc->osdep.dev = dev;
421
422 /*
423 * Determine hardware and mac type
424 */
425 sc->hw.vendor_id = pci_get_vendor(dev);
426 sc->hw.device_id = pci_get_device(dev);
427 sc->hw.revision_id = pci_get_revid(dev);
428 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
429 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
430
431 if (e1000_set_mac_type(&sc->hw))
432 return ENXIO;
433
434 /* Enable bus mastering */
435 pci_enable_busmaster(dev);
436
437 /*
438 * Allocate IO memory
439 */
440 sc->memory_rid = EMX_BAR_MEM;
441 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
442 &sc->memory_rid, RF_ACTIVE);
443 if (sc->memory == NULL) {
444 device_printf(dev, "Unable to allocate bus resource: memory\n");
445 error = ENXIO;
446 goto fail;
447 }
448 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
449 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
450
451 /* XXX This is quite goofy, it is not actually used */
452 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
453
454 /*
455 * Allocate interrupt
456 */
457 sc->intr_rid = 0;
458 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
459 RF_SHAREABLE | RF_ACTIVE);
460 if (sc->intr_res == NULL) {
461 device_printf(dev, "Unable to allocate bus resource: "
462 "interrupt\n");
463 error = ENXIO;
464 goto fail;
465 }
466
467 /* Save PCI command register for Shared Code */
468 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
469 sc->hw.back = &sc->osdep;
470
471 /* Do Shared Code initialization */
472 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
473 device_printf(dev, "Setup of Shared code failed\n");
474 error = ENXIO;
475 goto fail;
476 }
477 e1000_get_bus_info(&sc->hw);
478
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479 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
480 sc->hw.phy.autoneg_wait_to_complete = FALSE;
481 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
5330213c
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482
483 /*
484 * Interrupt throttle rate
485 */
486 if (emx_int_throttle_ceil == 0) {
487 sc->int_throttle_ceil = 0;
488 } else {
489 int throttle = emx_int_throttle_ceil;
490
491 if (throttle < 0)
492 throttle = EMX_DEFAULT_ITR;
493
494 /* Recalculate the tunable value to get the exact frequency. */
495 throttle = 1000000000 / 256 / throttle;
496
497 /* Upper 16bits of ITR is reserved and should be zero */
498 if (throttle & 0xffff0000)
499 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
500
501 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
502 }
503
504 e1000_init_script_state_82541(&sc->hw, TRUE);
505 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
506
507 /* Copper options */
508 if (sc->hw.phy.media_type == e1000_media_type_copper) {
509 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
510 sc->hw.phy.disable_polarity_correction = FALSE;
511 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
512 }
513
514 /* Set the frame limits assuming standard ethernet sized frames. */
515 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
516 sc->min_frame_size = ETHER_MIN_LEN;
517
518 /* This controls when hardware reports transmit completion status. */
519 sc->hw.mac.report_tx_early = 1;
520
8434a83b 521#ifdef RSS
65c7a6af 522 /* Calculate # of RX rings */
8434a83b 523 if (ncpus > 1)
65c7a6af
SZ
524 sc->rx_ring_cnt = EMX_NRX_RING;
525 else
8434a83b 526#endif
65c7a6af 527 sc->rx_ring_cnt = 1;
8434a83b 528 sc->rx_ring_inuse = sc->rx_ring_cnt;
65c7a6af 529
071699f8
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530 /* Allocate RX/TX rings' busdma(9) stuffs */
531 error = emx_dma_alloc(sc);
532 if (error)
e5b3bcc4 533 goto fail;
e5b3bcc4 534
5330213c
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535 /* Make sure we have a good EEPROM before we read from it */
536 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
537 /*
538 * Some PCI-E parts fail the first check due to
539 * the link being in sleep state, call it again,
540 * if it fails a second time its a real issue.
541 */
542 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
543 device_printf(dev,
544 "The EEPROM Checksum Is Not Valid\n");
545 error = EIO;
546 goto fail;
547 }
548 }
549
550 /* Initialize the hardware */
551 error = emx_hw_init(sc);
552 if (error) {
553 device_printf(dev, "Unable to initialize the hardware\n");
554 goto fail;
555 }
556
557 /* Copy the permanent MAC address out of the EEPROM */
558 if (e1000_read_mac_addr(&sc->hw) < 0) {
559 device_printf(dev, "EEPROM read error while reading MAC"
560 " address\n");
561 error = EIO;
562 goto fail;
563 }
564 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
565 device_printf(dev, "Invalid MAC address\n");
566 error = EIO;
567 goto fail;
568 }
569
5330213c
SZ
570 /* Manually turn off all interrupts */
571 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
572
573 /* Setup OS specific network interface */
574 emx_setup_ifp(sc);
575
576 /* Add sysctl tree, must after emx_setup_ifp() */
577 emx_add_sysctl(sc);
578
579 /* Initialize statistics */
580 emx_update_stats(sc);
581
582 sc->hw.mac.get_link_status = 1;
583 emx_update_link_status(sc);
584
585 /* Indicate SOL/IDER usage */
586 if (e1000_check_reset_block(&sc->hw)) {
587 device_printf(dev,
588 "PHY reset is blocked due to SOL/IDER session.\n");
589 }
590
591 /* Determine if we have to control management hardware */
592 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
593
594 /*
595 * Setup Wake-on-Lan
596 */
597 switch (sc->hw.mac.type) {
598 case e1000_82571:
599 case e1000_80003es2lan:
600 if (sc->hw.bus.func == 1) {
601 e1000_read_nvm(&sc->hw,
602 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
603 } else {
604 e1000_read_nvm(&sc->hw,
605 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
606 }
607 eeprom_data &= EMX_EEPROM_APME;
608 break;
609
610 default:
611 /* APME bit in EEPROM is mapped to WUC.APME */
612 eeprom_data =
613 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
614 break;
615 }
616 if (eeprom_data)
617 sc->wol = E1000_WUFC_MAG;
618 /*
619 * We have the eeprom settings, now apply the special cases
620 * where the eeprom may be wrong or the board won't support
621 * wake on lan on a particular port
622 */
623 device_id = pci_get_device(dev);
624 switch (device_id) {
625 case E1000_DEV_ID_82571EB_FIBER:
626 /*
627 * Wake events only supported on port A for dual fiber
628 * regardless of eeprom setting
629 */
630 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
631 E1000_STATUS_FUNC_1)
632 sc->wol = 0;
633 break;
634
635 case E1000_DEV_ID_82571EB_QUAD_COPPER:
636 case E1000_DEV_ID_82571EB_QUAD_FIBER:
637 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
638 /* if quad port sc, disable WoL on all but port A */
639 if (emx_global_quad_port_a != 0)
640 sc->wol = 0;
641 /* Reset for multiple quad port adapters */
642 if (++emx_global_quad_port_a == 4)
643 emx_global_quad_port_a = 0;
644 break;
645 }
646
647 /* XXX disable wol */
648 sc->wol = 0;
649
650 sc->spare_tx_desc = EMX_TX_SPARE;
651
652 /*
653 * Keep following relationship between spare_tx_desc, oact_tx_desc
654 * and tx_int_nsegs:
655 * (spare_tx_desc + EMX_TX_RESERVED) <=
656 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
657 */
658 sc->oact_tx_desc = sc->num_tx_desc / 8;
659 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
660 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
661 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
662 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
663
664 sc->tx_int_nsegs = sc->num_tx_desc / 16;
665 if (sc->tx_int_nsegs < sc->oact_tx_desc)
666 sc->tx_int_nsegs = sc->oact_tx_desc;
667
668 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
6d435846 669 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
670 if (error) {
671 device_printf(dev, "Failed to register interrupt handler");
672 ether_ifdetach(&sc->arpcom.ac_if);
673 goto fail;
674 }
675
676 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res));
677 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
678 return (0);
679fail:
680 emx_detach(dev);
681 return (error);
682}
683
684static int
685emx_detach(device_t dev)
686{
687 struct emx_softc *sc = device_get_softc(dev);
688
689 if (device_is_attached(dev)) {
690 struct ifnet *ifp = &sc->arpcom.ac_if;
691
6d435846 692 ifnet_serialize_all(ifp);
5330213c
SZ
693
694 emx_stop(sc);
695
696 e1000_phy_hw_reset(&sc->hw);
697
698 emx_rel_mgmt(sc);
699
700 if (sc->hw.mac.type == e1000_82573 &&
701 e1000_check_mng_mode(&sc->hw))
702 emx_rel_hw_control(sc);
703
704 if (sc->wol) {
705 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
706 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
707 emx_enable_wol(dev);
708 }
709
710 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
711
6d435846 712 ifnet_deserialize_all(ifp);
5330213c
SZ
713
714 ether_ifdetach(ifp);
715 }
716 bus_generic_detach(dev);
717
718 if (sc->intr_res != NULL) {
719 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
720 sc->intr_res);
721 }
722
723 if (sc->memory != NULL) {
724 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
725 sc->memory);
726 }
727
071699f8 728 emx_dma_free(sc);
5330213c
SZ
729
730 /* Free sysctl tree */
731 if (sc->sysctl_tree != NULL)
732 sysctl_ctx_free(&sc->sysctl_ctx);
733
734 return (0);
735}
736
737static int
738emx_shutdown(device_t dev)
739{
740 return emx_suspend(dev);
741}
742
743static int
744emx_suspend(device_t dev)
745{
746 struct emx_softc *sc = device_get_softc(dev);
747 struct ifnet *ifp = &sc->arpcom.ac_if;
748
6d435846 749 ifnet_serialize_all(ifp);
5330213c
SZ
750
751 emx_stop(sc);
752
753 emx_rel_mgmt(sc);
754
755 if (sc->hw.mac.type == e1000_82573 &&
756 e1000_check_mng_mode(&sc->hw))
757 emx_rel_hw_control(sc);
758
759 if (sc->wol) {
760 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
761 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
762 emx_enable_wol(dev);
763 }
764
6d435846 765 ifnet_deserialize_all(ifp);
5330213c
SZ
766
767 return bus_generic_suspend(dev);
768}
769
770static int
771emx_resume(device_t dev)
772{
773 struct emx_softc *sc = device_get_softc(dev);
774 struct ifnet *ifp = &sc->arpcom.ac_if;
775
6d435846 776 ifnet_serialize_all(ifp);
5330213c
SZ
777
778 emx_init(sc);
779 emx_get_mgmt(sc);
780 if_devstart(ifp);
781
6d435846 782 ifnet_deserialize_all(ifp);
5330213c
SZ
783
784 return bus_generic_resume(dev);
785}
786
787static void
788emx_start(struct ifnet *ifp)
789{
790 struct emx_softc *sc = ifp->if_softc;
791 struct mbuf *m_head;
792
6d435846 793 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
794
795 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
796 return;
797
798 if (!sc->link_active) {
799 ifq_purge(&ifp->if_snd);
800 return;
801 }
802
803 while (!ifq_is_empty(&ifp->if_snd)) {
804 /* Now do we at least have a minimal? */
805 if (EMX_IS_OACTIVE(sc)) {
806 emx_tx_collect(sc);
807 if (EMX_IS_OACTIVE(sc)) {
808 ifp->if_flags |= IFF_OACTIVE;
809 sc->no_tx_desc_avail1++;
810 break;
811 }
812 }
813
814 logif(pkt_txqueue);
815 m_head = ifq_dequeue(&ifp->if_snd, NULL);
816 if (m_head == NULL)
817 break;
818
819 if (emx_encap(sc, &m_head)) {
820 ifp->if_oerrors++;
821 emx_tx_collect(sc);
822 continue;
823 }
824
825 /* Send a copy of the frame to the BPF listener */
826 ETHER_BPF_MTAP(ifp, m_head);
827
828 /* Set timeout in case hardware has problems transmitting. */
829 ifp->if_timer = EMX_TX_TIMEOUT;
830 }
831}
832
833static int
834emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
835{
836 struct emx_softc *sc = ifp->if_softc;
837 struct ifreq *ifr = (struct ifreq *)data;
838 uint16_t eeprom_data = 0;
839 int max_frame_size, mask, reinit;
840 int error = 0;
841
2c9effcf 842 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
843
844 switch (command) {
845 case SIOCSIFMTU:
846 switch (sc->hw.mac.type) {
847 case e1000_82573:
848 /*
849 * 82573 only supports jumbo frames
850 * if ASPM is disabled.
851 */
852 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
853 &eeprom_data);
854 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
855 max_frame_size = ETHER_MAX_LEN;
856 break;
857 }
858 /* FALL THROUGH */
859
860 /* Limit Jumbo Frame size */
861 case e1000_82571:
862 case e1000_82572:
863 case e1000_82574:
864 case e1000_80003es2lan:
865 max_frame_size = 9234;
866 break;
867
868 default:
869 max_frame_size = MAX_JUMBO_FRAME_SIZE;
870 break;
871 }
872 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
873 ETHER_CRC_LEN) {
874 error = EINVAL;
875 break;
876 }
877
878 ifp->if_mtu = ifr->ifr_mtu;
879 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
880 ETHER_CRC_LEN;
881
882 if (ifp->if_flags & IFF_RUNNING)
883 emx_init(sc);
884 break;
885
886 case SIOCSIFFLAGS:
887 if (ifp->if_flags & IFF_UP) {
888 if ((ifp->if_flags & IFF_RUNNING)) {
889 if ((ifp->if_flags ^ sc->if_flags) &
890 (IFF_PROMISC | IFF_ALLMULTI)) {
891 emx_disable_promisc(sc);
892 emx_set_promisc(sc);
893 }
894 } else {
895 emx_init(sc);
896 }
897 } else if (ifp->if_flags & IFF_RUNNING) {
898 emx_stop(sc);
899 }
900 sc->if_flags = ifp->if_flags;
901 break;
902
903 case SIOCADDMULTI:
904 case SIOCDELMULTI:
905 if (ifp->if_flags & IFF_RUNNING) {
906 emx_disable_intr(sc);
907 emx_set_multi(sc);
b3a7093f
SZ
908#ifdef IFPOLL_ENABLE
909 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
910#endif
911 emx_enable_intr(sc);
912 }
913 break;
914
915 case SIOCSIFMEDIA:
916 /* Check SOL/IDER usage */
917 if (e1000_check_reset_block(&sc->hw)) {
918 device_printf(sc->dev, "Media change is"
919 " blocked due to SOL/IDER session.\n");
920 break;
921 }
922 /* FALL THROUGH */
923
924 case SIOCGIFMEDIA:
925 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
926 break;
927
928 case SIOCSIFCAP:
929 reinit = 0;
930 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
931 if (mask & IFCAP_HWCSUM) {
932 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
933 reinit = 1;
934 }
935 if (mask & IFCAP_VLAN_HWTAGGING) {
936 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
937 reinit = 1;
938 }
8434a83b
SZ
939 if (mask & IFCAP_RSS) {
940 ifp->if_capenable ^= IFCAP_RSS;
941 reinit = 1;
942 }
5330213c
SZ
943 if (reinit && (ifp->if_flags & IFF_RUNNING))
944 emx_init(sc);
945 break;
946
947 default:
948 error = ether_ioctl(ifp, command, data);
949 break;
950 }
951 return (error);
952}
953
954static void
955emx_watchdog(struct ifnet *ifp)
956{
957 struct emx_softc *sc = ifp->if_softc;
958
2c9effcf 959 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
960
961 /*
962 * The timer is set to 5 every time start queues a packet.
963 * Then txeof keeps resetting it as long as it cleans at
964 * least one descriptor.
965 * Finally, anytime all descriptors are clean the timer is
966 * set to 0.
967 */
968
969 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
970 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
971 /*
972 * If we reach here, all TX jobs are completed and
973 * the TX engine should have been idled for some time.
974 * We don't need to call if_devstart() here.
975 */
976 ifp->if_flags &= ~IFF_OACTIVE;
977 ifp->if_timer = 0;
978 return;
979 }
980
981 /*
982 * If we are in this routine because of pause frames, then
983 * don't reset the hardware.
984 */
985 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
986 ifp->if_timer = EMX_TX_TIMEOUT;
987 return;
988 }
989
990 if (e1000_check_for_link(&sc->hw) == 0)
991 if_printf(ifp, "watchdog timeout -- resetting\n");
992
993 ifp->if_oerrors++;
994 sc->watchdog_events++;
995
996 emx_init(sc);
997
998 if (!ifq_is_empty(&ifp->if_snd))
999 if_devstart(ifp);
1000}
1001
1002static void
1003emx_init(void *xsc)
1004{
1005 struct emx_softc *sc = xsc;
1006 struct ifnet *ifp = &sc->arpcom.ac_if;
1007 device_t dev = sc->dev;
1008 uint32_t pba;
3f939c23 1009 int i;
5330213c 1010
2c9effcf 1011 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1012
1013 emx_stop(sc);
1014
1015 /*
1016 * Packet Buffer Allocation (PBA)
1017 * Writing PBA sets the receive portion of the buffer
1018 * the remainder is used for the transmit buffer.
1019 */
1020 switch (sc->hw.mac.type) {
1021 /* Total Packet Buffer on these is 48K */
1022 case e1000_82571:
1023 case e1000_82572:
1024 case e1000_80003es2lan:
1025 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1026 break;
1027
1028 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1029 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1030 break;
1031
1032 case e1000_82574:
1033 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1034 break;
1035
1036 default:
1037 /* Devices before 82547 had a Packet Buffer of 64K. */
1038 if (sc->max_frame_size > 8192)
1039 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1040 else
1041 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1042 }
1043 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1044
1045 /* Get the latest mac address, User can use a LAA */
1046 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1047
1048 /* Put the address into the Receive Address Array */
1049 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1050
1051 /*
1052 * With the 82571 sc, RAR[0] may be overwritten
1053 * when the other port is reset, we make a duplicate
1054 * in RAR[14] for that eventuality, this assures
1055 * the interface continues to function.
1056 */
1057 if (sc->hw.mac.type == e1000_82571) {
1058 e1000_set_laa_state_82571(&sc->hw, TRUE);
1059 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1060 E1000_RAR_ENTRIES - 1);
1061 }
1062
1063 /* Initialize the hardware */
1064 if (emx_hw_init(sc)) {
1065 device_printf(dev, "Unable to initialize the hardware\n");
1066 /* XXX emx_stop()? */
1067 return;
1068 }
1069 emx_update_link_status(sc);
1070
1071 /* Setup VLAN support, basic and offload if available */
1072 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1073
1074 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1075 uint32_t ctrl;
1076
1077 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1078 ctrl |= E1000_CTRL_VME;
1079 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1080 }
1081
1082 /* Set hardware offload abilities */
1083 if (ifp->if_capenable & IFCAP_TXCSUM)
1084 ifp->if_hwassist = EMX_CSUM_FEATURES;
1085 else
1086 ifp->if_hwassist = 0;
1087
1088 /* Configure for OS presence */
1089 emx_get_mgmt(sc);
1090
1091 /* Prepare transmit descriptors and buffers */
1092 emx_init_tx_ring(sc);
1093 emx_init_tx_unit(sc);
1094
1095 /* Setup Multicast table */
1096 emx_set_multi(sc);
1097
8434a83b
SZ
1098 /*
1099 * Adjust # of RX ring to be used based on IFCAP_RSS
1100 */
1101 if (ifp->if_capenable & IFCAP_RSS)
1102 sc->rx_ring_inuse = sc->rx_ring_cnt;
1103 else
1104 sc->rx_ring_inuse = 1;
1105
5330213c 1106 /* Prepare receive descriptors and buffers */
8434a83b 1107 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
1108 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1109 device_printf(dev,
1110 "Could not setup receive structures\n");
1111 emx_stop(sc);
1112 return;
1113 }
5330213c
SZ
1114 }
1115 emx_init_rx_unit(sc);
1116
1117 /* Don't lose promiscuous settings */
1118 emx_set_promisc(sc);
1119
1120 ifp->if_flags |= IFF_RUNNING;
1121 ifp->if_flags &= ~IFF_OACTIVE;
1122
1123 callout_reset(&sc->timer, hz, emx_timer, sc);
1124 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1125
1126 /* MSI/X configuration for 82574 */
1127 if (sc->hw.mac.type == e1000_82574) {
1128 int tmp;
1129
1130 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1131 tmp |= E1000_CTRL_EXT_PBA_CLR;
1132 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1133 /*
1134 * Set the IVAR - interrupt vector routing.
1135 * Each nibble represents a vector, high bit
1136 * is enable, other 3 bits are the MSIX table
1137 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1138 * Link (other) to 2, hence the magic number.
1139 */
1140 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1141 }
1142
b3a7093f 1143#ifdef IFPOLL_ENABLE
5330213c
SZ
1144 /*
1145 * Only enable interrupts if we are not polling, make sure
1146 * they are off otherwise.
1147 */
b3a7093f 1148 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1149 emx_disable_intr(sc);
1150 else
b3a7093f 1151#endif /* IFPOLL_ENABLE */
5330213c
SZ
1152 emx_enable_intr(sc);
1153
1154 /* Don't reset the phy next time init gets called */
1155 sc->hw.phy.reset_disable = TRUE;
1156}
1157
5330213c
SZ
1158static void
1159emx_intr(void *xsc)
1160{
1161 struct emx_softc *sc = xsc;
1162 struct ifnet *ifp = &sc->arpcom.ac_if;
1163 uint32_t reg_icr;
1164
1165 logif(intr_beg);
6d435846 1166 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1167
1168 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1169
1170 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1171 logif(intr_end);
1172 return;
1173 }
1174
1175 /*
1176 * XXX: some laptops trigger several spurious interrupts
df50f778 1177 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1178 * reports all-ones value in this case. Processing such
1179 * interrupts would lead to a freeze. I don't know why.
1180 */
1181 if (reg_icr == 0xffffffff) {
1182 logif(intr_end);
1183 return;
1184 }
1185
1186 if (ifp->if_flags & IFF_RUNNING) {
1187 if (reg_icr &
3f939c23
SZ
1188 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1189 int i;
1190
6d435846
SZ
1191 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1192 lwkt_serialize_enter(
1193 &sc->rx_data[i].rx_serialize);
3f939c23 1194 emx_rxeof(sc, i, -1);
6d435846
SZ
1195 lwkt_serialize_exit(
1196 &sc->rx_data[i].rx_serialize);
1197 }
3f939c23 1198 }
6446af7b 1199 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1200 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1201 emx_txeof(sc);
1202 if (!ifq_is_empty(&ifp->if_snd))
1203 if_devstart(ifp);
6d435846 1204 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1205 }
1206 }
1207
1208 /* Link status change */
1209 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1210 emx_serialize_skipmain(sc);
6d435846 1211
5330213c
SZ
1212 callout_stop(&sc->timer);
1213 sc->hw.mac.get_link_status = 1;
1214 emx_update_link_status(sc);
1215
1216 /* Deal with TX cruft when link lost */
1217 emx_tx_purge(sc);
1218
1219 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1220
bca7c435 1221 emx_deserialize_skipmain(sc);
5330213c
SZ
1222 }
1223
1224 if (reg_icr & E1000_ICR_RXO)
1225 sc->rx_overruns++;
1226
1227 logif(intr_end);
1228}
1229
1230static void
1231emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1232{
1233 struct emx_softc *sc = ifp->if_softc;
1234
2c9effcf 1235 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1236
1237 emx_update_link_status(sc);
1238
1239 ifmr->ifm_status = IFM_AVALID;
1240 ifmr->ifm_active = IFM_ETHER;
1241
1242 if (!sc->link_active)
1243 return;
1244
1245 ifmr->ifm_status |= IFM_ACTIVE;
1246
1247 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1248 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1249 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1250 } else {
1251 switch (sc->link_speed) {
1252 case 10:
1253 ifmr->ifm_active |= IFM_10_T;
1254 break;
1255 case 100:
1256 ifmr->ifm_active |= IFM_100_TX;
1257 break;
1258
1259 case 1000:
1260 ifmr->ifm_active |= IFM_1000_T;
1261 break;
1262 }
1263 if (sc->link_duplex == FULL_DUPLEX)
1264 ifmr->ifm_active |= IFM_FDX;
1265 else
1266 ifmr->ifm_active |= IFM_HDX;
1267 }
1268}
1269
1270static int
1271emx_media_change(struct ifnet *ifp)
1272{
1273 struct emx_softc *sc = ifp->if_softc;
1274 struct ifmedia *ifm = &sc->media;
1275
2c9effcf 1276 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1277
1278 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1279 return (EINVAL);
1280
1281 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1282 case IFM_AUTO:
1283 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1284 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1285 break;
1286
1287 case IFM_1000_LX:
1288 case IFM_1000_SX:
1289 case IFM_1000_T:
1290 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1291 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1292 break;
1293
1294 case IFM_100_TX:
1295 sc->hw.mac.autoneg = FALSE;
1296 sc->hw.phy.autoneg_advertised = 0;
1297 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1298 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1299 else
1300 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1301 break;
1302
1303 case IFM_10_T:
1304 sc->hw.mac.autoneg = FALSE;
1305 sc->hw.phy.autoneg_advertised = 0;
1306 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1307 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1308 else
1309 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1310 break;
1311
1312 default:
1313 if_printf(ifp, "Unsupported media type\n");
1314 break;
1315 }
1316
1317 /*
1318 * As the speed/duplex settings my have changed we need to
1319 * reset the PHY.
1320 */
1321 sc->hw.phy.reset_disable = FALSE;
1322
1323 emx_init(sc);
1324
1325 return (0);
1326}
1327
1328static int
1329emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1330{
1331 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1332 bus_dmamap_t map;
323e5ecd 1333 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ
1334 struct e1000_tx_desc *ctxd = NULL;
1335 struct mbuf *m_head = *m_headp;
1336 uint32_t txd_upper, txd_lower, cmd = 0;
1337 int maxsegs, nsegs, i, j, first, last = 0, error;
1338
3752657e 1339 if (m_head->m_len < EMX_TXCSUM_MINHL &&
5330213c
SZ
1340 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1341 /*
1342 * Make sure that ethernet header and ip.ip_hl are in
1343 * contiguous memory, since if TXCSUM is enabled, later
1344 * TX context descriptor's setup need to access ip.ip_hl.
1345 */
1346 error = emx_txcsum_pullup(sc, m_headp);
1347 if (error) {
1348 KKASSERT(*m_headp == NULL);
1349 return error;
1350 }
1351 m_head = *m_headp;
1352 }
1353
1354 txd_upper = txd_lower = 0;
1355
1356 /*
1357 * Capture the first descriptor index, this descriptor
1358 * will have the index of the EOP which is the only one
1359 * that now gets a DONE bit writeback.
1360 */
1361 first = sc->next_avail_tx_desc;
323e5ecd 1362 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1363 tx_buffer_mapped = tx_buffer;
1364 map = tx_buffer->map;
1365
1366 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1367 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1368 if (maxsegs > EMX_MAX_SCATTER)
1369 maxsegs = EMX_MAX_SCATTER;
1370
1371 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1372 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1373 if (error) {
1374 if (error == ENOBUFS)
1375 sc->mbuf_alloc_failed++;
1376 else
1377 sc->no_tx_dma_setup++;
1378
1379 m_freem(*m_headp);
1380 *m_headp = NULL;
1381 return error;
1382 }
1383 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1384
1385 m_head = *m_headp;
1386 sc->tx_nsegs += nsegs;
1387
1388 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1389 /* TX csum offloading will consume one TX desc */
1390 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1391 }
1392 i = sc->next_avail_tx_desc;
1393
1394 /* Set up our transmit descriptors */
1395 for (j = 0; j < nsegs; j++) {
323e5ecd 1396 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1397 ctxd = &sc->tx_desc_base[i];
1398
1399 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1400 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1401 txd_lower | segs[j].ds_len);
1402 ctxd->upper.data = htole32(txd_upper);
1403
1404 last = i;
1405 if (++i == sc->num_tx_desc)
1406 i = 0;
5330213c
SZ
1407 }
1408
1409 sc->next_avail_tx_desc = i;
1410
1411 KKASSERT(sc->num_tx_desc_avail > nsegs);
1412 sc->num_tx_desc_avail -= nsegs;
1413
1414 /* Handle VLAN tag */
1415 if (m_head->m_flags & M_VLANTAG) {
1416 /* Set the vlan id. */
1417 ctxd->upper.fields.special =
1418 htole16(m_head->m_pkthdr.ether_vlantag);
1419
1420 /* Tell hardware to add tag */
1421 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1422 }
1423
1424 tx_buffer->m_head = m_head;
1425 tx_buffer_mapped->map = tx_buffer->map;
1426 tx_buffer->map = map;
1427
1428 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1429 sc->tx_nsegs = 0;
4e4e8481
SZ
1430
1431 /*
1432 * Report Status (RS) is turned on
1433 * every tx_int_nsegs descriptors.
1434 */
5330213c
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1435 cmd = E1000_TXD_CMD_RS;
1436
b4b0a2b4
SZ
1437 /*
1438 * Keep track of the descriptor, which will
1439 * be written back by hardware.
1440 */
5330213c
SZ
1441 sc->tx_dd[sc->tx_dd_tail] = last;
1442 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1443 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1444 }
1445
1446 /*
1447 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1448 */
1449 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1450
1451 /*
5330213c
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1452 * Advance the Transmit Descriptor Tail (TDT), this tells
1453 * the E1000 that this frame is available to transmit.
1454 */
1455 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1456
1457 return (0);
1458}
1459
1460static void
1461emx_set_promisc(struct emx_softc *sc)
1462{
1463 struct ifnet *ifp = &sc->arpcom.ac_if;
1464 uint32_t reg_rctl;
1465
1466 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1467
1468 if (ifp->if_flags & IFF_PROMISC) {
1469 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1470 /* Turn this on if you want to see bad packets */
1471 if (emx_debug_sbp)
1472 reg_rctl |= E1000_RCTL_SBP;
1473 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1474 } else if (ifp->if_flags & IFF_ALLMULTI) {
1475 reg_rctl |= E1000_RCTL_MPE;
1476 reg_rctl &= ~E1000_RCTL_UPE;
1477 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1478 }
1479}
1480
1481static void
1482emx_disable_promisc(struct emx_softc *sc)
1483{
1484 uint32_t reg_rctl;
1485
1486 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1487
1488 reg_rctl &= ~E1000_RCTL_UPE;
1489 reg_rctl &= ~E1000_RCTL_MPE;
1490 reg_rctl &= ~E1000_RCTL_SBP;
1491 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1492}
1493
1494static void
1495emx_set_multi(struct emx_softc *sc)
1496{
1497 struct ifnet *ifp = &sc->arpcom.ac_if;
1498 struct ifmultiaddr *ifma;
1499 uint32_t reg_rctl = 0;
1500 uint8_t mta[512]; /* Largest MTS is 4096 bits */
1501 int mcnt = 0;
1502
1503 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1504 if (ifma->ifma_addr->sa_family != AF_LINK)
1505 continue;
1506
1507 if (mcnt == EMX_MCAST_ADDR_MAX)
1508 break;
1509
1510 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1511 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1512 mcnt++;
1513 }
1514
1515 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1516 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1517 reg_rctl |= E1000_RCTL_MPE;
1518 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1519 } else {
1520 e1000_update_mc_addr_list(&sc->hw, mta,
1521 mcnt, 1, sc->hw.mac.rar_entry_count);
1522 }
1523}
1524
1525/*
1526 * This routine checks for link status and updates statistics.
1527 */
1528static void
1529emx_timer(void *xsc)
1530{
1531 struct emx_softc *sc = xsc;
1532 struct ifnet *ifp = &sc->arpcom.ac_if;
1533
6d435846 1534 ifnet_serialize_all(ifp);
5330213c
SZ
1535
1536 emx_update_link_status(sc);
1537 emx_update_stats(sc);
1538
1539 /* Reset LAA into RAR[0] on 82571 */
1540 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1541 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1542
1543 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1544 emx_print_hw_stats(sc);
1545
1546 emx_smartspeed(sc);
1547
1548 callout_reset(&sc->timer, hz, emx_timer, sc);
1549
6d435846 1550 ifnet_deserialize_all(ifp);
5330213c
SZ
1551}
1552
1553static void
1554emx_update_link_status(struct emx_softc *sc)
1555{
1556 struct e1000_hw *hw = &sc->hw;
1557 struct ifnet *ifp = &sc->arpcom.ac_if;
1558 device_t dev = sc->dev;
1559 uint32_t link_check = 0;
1560
1561 /* Get the cached link value or read phy for real */
1562 switch (hw->phy.media_type) {
1563 case e1000_media_type_copper:
1564 if (hw->mac.get_link_status) {
1565 /* Do the work to read phy */
1566 e1000_check_for_link(hw);
1567 link_check = !hw->mac.get_link_status;
1568 if (link_check) /* ESB2 fix */
1569 e1000_cfg_on_link_up(hw);
1570 } else {
1571 link_check = TRUE;
1572 }
1573 break;
1574
1575 case e1000_media_type_fiber:
1576 e1000_check_for_link(hw);
1577 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1578 break;
1579
1580 case e1000_media_type_internal_serdes:
1581 e1000_check_for_link(hw);
1582 link_check = sc->hw.mac.serdes_has_link;
1583 break;
1584
1585 case e1000_media_type_unknown:
1586 default:
1587 break;
1588 }
1589
1590 /* Now check for a transition */
1591 if (link_check && sc->link_active == 0) {
1592 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1593 &sc->link_duplex);
1594
1595 /*
1596 * Check if we should enable/disable SPEED_MODE bit on
1597 * 82571EB/82572EI
1598 */
1599 if (hw->mac.type == e1000_82571 ||
1600 hw->mac.type == e1000_82572) {
1601 int tarc0;
1602
1603 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1604 if (sc->link_speed != SPEED_1000)
1605 tarc0 &= ~EMX_TARC_SPEED_MODE;
1606 else
1607 tarc0 |= EMX_TARC_SPEED_MODE;
1608 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1609 }
1610 if (bootverbose) {
1611 device_printf(dev, "Link is up %d Mbps %s\n",
1612 sc->link_speed,
1613 ((sc->link_duplex == FULL_DUPLEX) ?
1614 "Full Duplex" : "Half Duplex"));
1615 }
1616 sc->link_active = 1;
1617 sc->smartspeed = 0;
1618 ifp->if_baudrate = sc->link_speed * 1000000;
1619 ifp->if_link_state = LINK_STATE_UP;
1620 if_link_state_change(ifp);
1621 } else if (!link_check && sc->link_active == 1) {
1622 ifp->if_baudrate = sc->link_speed = 0;
1623 sc->link_duplex = 0;
1624 if (bootverbose)
1625 device_printf(dev, "Link is Down\n");
1626 sc->link_active = 0;
1627#if 0
1628 /* Link down, disable watchdog */
1629 if->if_timer = 0;
1630#endif
1631 ifp->if_link_state = LINK_STATE_DOWN;
1632 if_link_state_change(ifp);
1633 }
1634}
1635
1636static void
1637emx_stop(struct emx_softc *sc)
1638{
1639 struct ifnet *ifp = &sc->arpcom.ac_if;
1640 int i;
1641
2c9effcf 1642 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1643
1644 emx_disable_intr(sc);
1645
1646 callout_stop(&sc->timer);
1647
1648 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1649 ifp->if_timer = 0;
1650
3f939c23
SZ
1651 /*
1652 * Disable multiple receive queues.
1653 *
1654 * NOTE:
1655 * We should disable multiple receive queues before
1656 * resetting the hardware.
1657 */
1658 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1659
5330213c
SZ
1660 e1000_reset_hw(&sc->hw);
1661 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1662
1663 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1664 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1665
1666 if (tx_buffer->m_head != NULL) {
1667 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1668 m_freem(tx_buffer->m_head);
1669 tx_buffer->m_head = NULL;
1670 }
1671 }
1672
8434a83b 1673 for (i = 0; i < sc->rx_ring_inuse; ++i)
3f939c23 1674 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ
1675
1676 sc->csum_flags = 0;
1677 sc->csum_ehlen = 0;
1678 sc->csum_iphlen = 0;
1679
1680 sc->tx_dd_head = 0;
1681 sc->tx_dd_tail = 0;
1682 sc->tx_nsegs = 0;
1683}
1684
1685static int
1686emx_hw_init(struct emx_softc *sc)
1687{
1688 device_t dev = sc->dev;
1689 uint16_t rx_buffer_size;
1690
1691 /* Issue a global reset */
1692 e1000_reset_hw(&sc->hw);
1693
1694 /* Get control from any management/hw control */
1695 if (sc->hw.mac.type == e1000_82573 &&
1696 e1000_check_mng_mode(&sc->hw))
1697 emx_get_hw_control(sc);
1698
1699 /* Set up smart power down as default off on newer adapters. */
1700 if (!emx_smart_pwr_down &&
1701 (sc->hw.mac.type == e1000_82571 ||
1702 sc->hw.mac.type == e1000_82572)) {
1703 uint16_t phy_tmp = 0;
1704
1705 /* Speed up time to link by disabling smart power down. */
1706 e1000_read_phy_reg(&sc->hw,
1707 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1708 phy_tmp &= ~IGP02E1000_PM_SPD;
1709 e1000_write_phy_reg(&sc->hw,
1710 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1711 }
1712
1713 /*
1714 * These parameters control the automatic generation (Tx) and
1715 * response (Rx) to Ethernet PAUSE frames.
1716 * - High water mark should allow for at least two frames to be
1717 * received after sending an XOFF.
1718 * - Low water mark works best when it is very near the high water mark.
1719 * This allows the receiver to restart by sending XON when it has
1720 * drained a bit. Here we use an arbitary value of 1500 which will
1721 * restart after one full frame is pulled from the buffer. There
1722 * could be several smaller frames in the buffer and if so they will
1723 * not trigger the XON until their total number reduces the buffer
1724 * by 1500.
1725 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1726 */
1727 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1728
1729 sc->hw.fc.high_water = rx_buffer_size -
1730 roundup2(sc->max_frame_size, 1024);
1731 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1732
1733 if (sc->hw.mac.type == e1000_80003es2lan)
1734 sc->hw.fc.pause_time = 0xFFFF;
1735 else
1736 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1737 sc->hw.fc.send_xon = TRUE;
1738 sc->hw.fc.requested_mode = e1000_fc_full;
1739
1740 if (e1000_init_hw(&sc->hw) < 0) {
1741 device_printf(dev, "Hardware Initialization Failed\n");
1742 return (EIO);
1743 }
1744
1745 e1000_check_for_link(&sc->hw);
1746
1747 return (0);
1748}
1749
1750static void
1751emx_setup_ifp(struct emx_softc *sc)
1752{
1753 struct ifnet *ifp = &sc->arpcom.ac_if;
1754
1755 if_initname(ifp, device_get_name(sc->dev),
1756 device_get_unit(sc->dev));
1757 ifp->if_softc = sc;
1758 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1759 ifp->if_init = emx_init;
1760 ifp->if_ioctl = emx_ioctl;
1761 ifp->if_start = emx_start;
b3a7093f
SZ
1762#ifdef IFPOLL_ENABLE
1763 ifp->if_qpoll = emx_qpoll;
5330213c
SZ
1764#endif
1765 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1766 ifp->if_serialize = emx_serialize;
1767 ifp->if_deserialize = emx_deserialize;
1768 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1769#ifdef INVARIANTS
1770 ifp->if_serialize_assert = emx_serialize_assert;
1771#endif
5330213c
SZ
1772 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1773 ifq_set_ready(&ifp->if_snd);
1774
ae474cfa 1775 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ
1776
1777 ifp->if_capabilities = IFCAP_HWCSUM |
1778 IFCAP_VLAN_HWTAGGING |
1779 IFCAP_VLAN_MTU;
8434a83b
SZ
1780 if (sc->rx_ring_cnt > 1)
1781 ifp->if_capabilities |= IFCAP_RSS;
5330213c
SZ
1782 ifp->if_capenable = ifp->if_capabilities;
1783 ifp->if_hwassist = EMX_CSUM_FEATURES;
1784
1785 /*
1786 * Tell the upper layer(s) we support long frames.
1787 */
1788 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1789
1790 /*
1791 * Specify the media types supported by this sc and register
1792 * callbacks to update media and link information
1793 */
1794 ifmedia_init(&sc->media, IFM_IMASK,
1795 emx_media_change, emx_media_status);
1796 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1797 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1798 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1799 0, NULL);
1800 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1801 } else {
1802 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1803 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1804 0, NULL);
1805 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1806 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1807 0, NULL);
1808 if (sc->hw.phy.type != e1000_phy_ife) {
1809 ifmedia_add(&sc->media,
1810 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1811 ifmedia_add(&sc->media,
1812 IFM_ETHER | IFM_1000_T, 0, NULL);
1813 }
1814 }
1815 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1816 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1817}
1818
1819/*
1820 * Workaround for SmartSpeed on 82541 and 82547 controllers
1821 */
1822static void
1823emx_smartspeed(struct emx_softc *sc)
1824{
1825 uint16_t phy_tmp;
1826
1827 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1828 sc->hw.mac.autoneg == 0 ||
1829 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1830 return;
1831
1832 if (sc->smartspeed == 0) {
1833 /*
1834 * If Master/Slave config fault is asserted twice,
1835 * we assume back-to-back
1836 */
1837 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1838 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1839 return;
1840 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1841 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1842 e1000_read_phy_reg(&sc->hw,
1843 PHY_1000T_CTRL, &phy_tmp);
1844 if (phy_tmp & CR_1000T_MS_ENABLE) {
1845 phy_tmp &= ~CR_1000T_MS_ENABLE;
1846 e1000_write_phy_reg(&sc->hw,
1847 PHY_1000T_CTRL, phy_tmp);
1848 sc->smartspeed++;
1849 if (sc->hw.mac.autoneg &&
1850 !e1000_phy_setup_autoneg(&sc->hw) &&
1851 !e1000_read_phy_reg(&sc->hw,
1852 PHY_CONTROL, &phy_tmp)) {
1853 phy_tmp |= MII_CR_AUTO_NEG_EN |
1854 MII_CR_RESTART_AUTO_NEG;
1855 e1000_write_phy_reg(&sc->hw,
1856 PHY_CONTROL, phy_tmp);
1857 }
1858 }
1859 }
1860 return;
1861 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1862 /* If still no link, perhaps using 2/3 pair cable */
1863 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1864 phy_tmp |= CR_1000T_MS_ENABLE;
1865 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1866 if (sc->hw.mac.autoneg &&
1867 !e1000_phy_setup_autoneg(&sc->hw) &&
1868 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1869 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1870 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1871 }
1872 }
1873
1874 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1875 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1876 sc->smartspeed = 0;
1877}
1878
1879static int
5330213c
SZ
1880emx_create_tx_ring(struct emx_softc *sc)
1881{
1882 device_t dev = sc->dev;
323e5ecd 1883 struct emx_txbuf *tx_buffer;
bdca134f
SZ
1884 int error, i, tsize;
1885
1886 /*
1887 * Validate number of transmit descriptors. It must not exceed
1888 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1889 */
1890 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1891 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1892 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1893 EMX_DEFAULT_TXD, emx_txd);
1894 sc->num_tx_desc = EMX_DEFAULT_TXD;
1895 } else {
1896 sc->num_tx_desc = emx_txd;
1897 }
1898
1899 /*
1900 * Allocate Transmit Descriptor ring
1901 */
1902 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1903 EMX_DBA_ALIGN);
a596084c
SZ
1904 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1905 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1906 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1907 &sc->tx_desc_paddr);
1908 if (sc->tx_desc_base == NULL) {
bdca134f 1909 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 1910 return ENOMEM;
bdca134f 1911 }
5330213c 1912
323e5ecd
SZ
1913 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1914 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
1915
1916 /*
1917 * Create DMA tags for tx buffers
1918 */
1919 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1920 1, 0, /* alignment, bounds */
1921 BUS_SPACE_MAXADDR, /* lowaddr */
1922 BUS_SPACE_MAXADDR, /* highaddr */
1923 NULL, NULL, /* filter, filterarg */
1924 EMX_TSO_SIZE, /* maxsize */
1925 EMX_MAX_SCATTER, /* nsegments */
1926 EMX_MAX_SEGSIZE, /* maxsegsize */
1927 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1928 BUS_DMA_ONEBPAGE, /* flags */
1929 &sc->txtag);
1930 if (error) {
1931 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ
1932 kfree(sc->tx_buf, M_DEVBUF);
1933 sc->tx_buf = NULL;
5330213c
SZ
1934 return error;
1935 }
1936
1937 /*
1938 * Create DMA maps for tx buffers
1939 */
1940 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1941 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1942
1943 error = bus_dmamap_create(sc->txtag,
1944 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1945 &tx_buffer->map);
1946 if (error) {
1947 device_printf(dev, "Unable to create TX DMA map\n");
1948 emx_destroy_tx_ring(sc, i);
1949 return error;
1950 }
1951 }
1952 return (0);
1953}
1954
1955static void
1956emx_init_tx_ring(struct emx_softc *sc)
1957{
1958 /* Clear the old ring contents */
1959 bzero(sc->tx_desc_base,
1960 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1961
1962 /* Reset state */
1963 sc->next_avail_tx_desc = 0;
1964 sc->next_tx_to_clean = 0;
1965 sc->num_tx_desc_avail = sc->num_tx_desc;
1966}
1967
1968static void
1969emx_init_tx_unit(struct emx_softc *sc)
1970{
1971 uint32_t tctl, tarc, tipg = 0;
1972 uint64_t bus_addr;
1973
1974 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 1975 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
1976 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
1977 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1978 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
1979 (uint32_t)(bus_addr >> 32));
1980 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
1981 (uint32_t)bus_addr);
1982 /* Setup the HW Tx Head and Tail descriptor pointers */
1983 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
1984 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
1985
1986 /* Set the default values for the Tx Inter Packet Gap timer */
1987 switch (sc->hw.mac.type) {
1988 case e1000_80003es2lan:
1989 tipg = DEFAULT_82543_TIPG_IPGR1;
1990 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
1991 E1000_TIPG_IPGR2_SHIFT;
1992 break;
1993
1994 default:
1995 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1996 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1997 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1998 else
1999 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2000 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2001 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2002 break;
2003 }
2004
2005 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2006
2007 /* NOTE: 0 is not allowed for TIDV */
2008 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2009 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2010
2011 if (sc->hw.mac.type == e1000_82571 ||
2012 sc->hw.mac.type == e1000_82572) {
2013 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2014 tarc |= EMX_TARC_SPEED_MODE;
2015 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2016 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2017 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2018 tarc |= 1;
2019 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2020 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2021 tarc |= 1;
2022 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2023 }
2024
2025 /* Program the Transmit Control Register */
2026 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2027 tctl &= ~E1000_TCTL_CT;
2028 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2029 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2030 tctl |= E1000_TCTL_MULR;
2031
2032 /* This write will effectively turn on the transmit unit. */
2033 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2034}
2035
2036static void
2037emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2038{
323e5ecd 2039 struct emx_txbuf *tx_buffer;
5330213c
SZ
2040 int i;
2041
bdca134f 2042 /* Free Transmit Descriptor ring */
a596084c
SZ
2043 if (sc->tx_desc_base) {
2044 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2045 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2046 sc->tx_desc_dmap);
2047 bus_dma_tag_destroy(sc->tx_desc_dtag);
2048
2049 sc->tx_desc_base = NULL;
2050 }
bdca134f 2051
323e5ecd 2052 if (sc->tx_buf == NULL)
5330213c
SZ
2053 return;
2054
2055 for (i = 0; i < ndesc; i++) {
323e5ecd 2056 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2057
2058 KKASSERT(tx_buffer->m_head == NULL);
2059 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2060 }
2061 bus_dma_tag_destroy(sc->txtag);
2062
323e5ecd
SZ
2063 kfree(sc->tx_buf, M_DEVBUF);
2064 sc->tx_buf = NULL;
5330213c
SZ
2065}
2066
2067/*
2068 * The offload context needs to be set when we transfer the first
2069 * packet of a particular protocol (TCP/UDP). This routine has been
2070 * enhanced to deal with inserted VLAN headers.
2071 *
2072 * If the new packet's ether header length, ip header length and
2073 * csum offloading type are same as the previous packet, we should
2074 * avoid allocating a new csum context descriptor; mainly to take
2075 * advantage of the pipeline effect of the TX data read request.
2076 *
2077 * This function returns number of TX descrptors allocated for
2078 * csum context.
2079 */
2080static int
2081emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2082 uint32_t *txd_upper, uint32_t *txd_lower)
2083{
2084 struct e1000_context_desc *TXD;
323e5ecd 2085 struct emx_txbuf *tx_buffer;
5330213c
SZ
2086 struct ether_vlan_header *eh;
2087 struct ip *ip;
2088 int curr_txd, ehdrlen, csum_flags;
2089 uint32_t cmd, hdr_len, ip_hlen;
2090 uint16_t etype;
2091
2092 /*
2093 * Determine where frame payload starts.
2094 * Jump over vlan headers if already present,
2095 * helpful for QinQ too.
2096 */
2097 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2098 ("emx_txcsum_pullup is not called (eh)?\n"));
2099 eh = mtod(mp, struct ether_vlan_header *);
2100 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2101 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2102 ("emx_txcsum_pullup is not called (evh)?\n"));
2103 etype = ntohs(eh->evl_proto);
2104 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2105 } else {
2106 etype = ntohs(eh->evl_encap_proto);
2107 ehdrlen = ETHER_HDR_LEN;
2108 }
2109
2110 /*
2111 * We only support TCP/UDP for IPv4 for the moment.
2112 * TODO: Support SCTP too when it hits the tree.
2113 */
2114 if (etype != ETHERTYPE_IP)
2115 return 0;
2116
2117 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2118 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2119
2120 /* NOTE: We could only safely access ip.ip_vhl part */
2121 ip = (struct ip *)(mp->m_data + ehdrlen);
2122 ip_hlen = ip->ip_hl << 2;
2123
2124 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2125
2126 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2127 sc->csum_flags == csum_flags) {
2128 /*
2129 * Same csum offload context as the previous packets;
2130 * just return.
2131 */
2132 *txd_upper = sc->csum_txd_upper;
2133 *txd_lower = sc->csum_txd_lower;
2134 return 0;
2135 }
2136
2137 /*
2138 * Setup a new csum offload context.
2139 */
2140
2141 curr_txd = sc->next_avail_tx_desc;
323e5ecd 2142 tx_buffer = &sc->tx_buf[curr_txd];
5330213c
SZ
2143 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2144
2145 cmd = 0;
2146
2147 /* Setup of IP header checksum. */
2148 if (csum_flags & CSUM_IP) {
2149 /*
2150 * Start offset for header checksum calculation.
2151 * End offset for header checksum calculation.
2152 * Offset of place to put the checksum.
2153 */
2154 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2155 TXD->lower_setup.ip_fields.ipcse =
2156 htole16(ehdrlen + ip_hlen - 1);
2157 TXD->lower_setup.ip_fields.ipcso =
2158 ehdrlen + offsetof(struct ip, ip_sum);
2159 cmd |= E1000_TXD_CMD_IP;
2160 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2161 }
2162 hdr_len = ehdrlen + ip_hlen;
2163
2164 if (csum_flags & CSUM_TCP) {
2165 /*
2166 * Start offset for payload checksum calculation.
2167 * End offset for payload checksum calculation.
2168 * Offset of place to put the checksum.
2169 */
2170 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2171 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2172 TXD->upper_setup.tcp_fields.tucso =
2173 hdr_len + offsetof(struct tcphdr, th_sum);
2174 cmd |= E1000_TXD_CMD_TCP;
2175 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2176 } else if (csum_flags & CSUM_UDP) {
2177 /*
2178 * Start offset for header checksum calculation.
2179 * End offset for header checksum calculation.
2180 * Offset of place to put the checksum.
2181 */
2182 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2183 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2184 TXD->upper_setup.tcp_fields.tucso =
2185 hdr_len + offsetof(struct udphdr, uh_sum);
2186 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2187 }
2188
2189 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2190 E1000_TXD_DTYP_D; /* Data descr */
2191
2192 /* Save the information for this csum offloading context */
2193 sc->csum_ehlen = ehdrlen;
2194 sc->csum_iphlen = ip_hlen;
2195 sc->csum_flags = csum_flags;
2196 sc->csum_txd_upper = *txd_upper;
2197 sc->csum_txd_lower = *txd_lower;
2198
2199 TXD->tcp_seg_setup.data = htole32(0);
2200 TXD->cmd_and_length =
2201 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2202
2203 if (++curr_txd == sc->num_tx_desc)
2204 curr_txd = 0;
2205
2206 KKASSERT(sc->num_tx_desc_avail > 0);
2207 sc->num_tx_desc_avail--;
2208
2209 sc->next_avail_tx_desc = curr_txd;
2210 return 1;
2211}
2212
2213static int
2214emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2215{
2216 struct mbuf *m = *m0;
2217 struct ether_header *eh;
2218 int len;
2219
2220 sc->tx_csum_try_pullup++;
2221
2222 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2223
2224 if (__predict_false(!M_WRITABLE(m))) {
2225 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2226 sc->tx_csum_drop1++;
2227 m_freem(m);
2228 *m0 = NULL;
2229 return ENOBUFS;
2230 }
2231 eh = mtod(m, struct ether_header *);
2232
2233 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2234 len += EVL_ENCAPLEN;
2235
3752657e 2236 if (m->m_len < len) {
5330213c
SZ
2237 sc->tx_csum_drop2++;
2238 m_freem(m);
2239 *m0 = NULL;
2240 return ENOBUFS;
2241 }
2242 return 0;
2243 }
2244
2245 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2246 sc->tx_csum_pullup1++;
2247 m = m_pullup(m, ETHER_HDR_LEN);
2248 if (m == NULL) {
2249 sc->tx_csum_pullup1_failed++;
2250 *m0 = NULL;
2251 return ENOBUFS;
2252 }
2253 *m0 = m;
2254 }
2255 eh = mtod(m, struct ether_header *);
2256
2257 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2258 len += EVL_ENCAPLEN;
2259
3752657e 2260 if (m->m_len < len) {
5330213c
SZ
2261 sc->tx_csum_pullup2++;
2262 m = m_pullup(m, len);
2263 if (m == NULL) {
2264 sc->tx_csum_pullup2_failed++;
2265 *m0 = NULL;
2266 return ENOBUFS;
2267 }
2268 *m0 = m;
2269 }
2270 return 0;
2271}
2272
2273static void
2274emx_txeof(struct emx_softc *sc)
2275{
2276 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2277 struct emx_txbuf *tx_buffer;
5330213c
SZ
2278 int first, num_avail;
2279
2280 if (sc->tx_dd_head == sc->tx_dd_tail)
2281 return;
2282
2283 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2284 return;
2285
2286 num_avail = sc->num_tx_desc_avail;
2287 first = sc->next_tx_to_clean;
2288
2289 while (sc->tx_dd_head != sc->tx_dd_tail) {
2290 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2291 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2292
2293 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2294 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2295 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2296
2297 if (++dd_idx == sc->num_tx_desc)
2298 dd_idx = 0;
2299
2300 while (first != dd_idx) {
2301 logif(pkt_txclean);
2302
5330213c
SZ
2303 num_avail++;
2304
323e5ecd 2305 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2306 if (tx_buffer->m_head) {
2307 ifp->if_opackets++;
2308 bus_dmamap_unload(sc->txtag,
2309 tx_buffer->map);
2310 m_freem(tx_buffer->m_head);
2311 tx_buffer->m_head = NULL;
2312 }
2313
2314 if (++first == sc->num_tx_desc)
2315 first = 0;
2316 }
2317 } else {
2318 break;
2319 }
2320 }
2321 sc->next_tx_to_clean = first;
2322 sc->num_tx_desc_avail = num_avail;
2323
2324 if (sc->tx_dd_head == sc->tx_dd_tail) {
2325 sc->tx_dd_head = 0;
2326 sc->tx_dd_tail = 0;
2327 }
2328
2329 if (!EMX_IS_OACTIVE(sc)) {
2330 ifp->if_flags &= ~IFF_OACTIVE;
2331
2332 /* All clean, turn off the timer */
2333 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2334 ifp->if_timer = 0;
2335 }
2336}
2337
2338static void
2339emx_tx_collect(struct emx_softc *sc)
2340{
2341 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2342 struct emx_txbuf *tx_buffer;
5330213c
SZ
2343 int tdh, first, num_avail, dd_idx = -1;
2344
2345 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2346 return;
2347
2348 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2349 if (tdh == sc->next_tx_to_clean)
2350 return;
2351
2352 if (sc->tx_dd_head != sc->tx_dd_tail)
2353 dd_idx = sc->tx_dd[sc->tx_dd_head];
2354
2355 num_avail = sc->num_tx_desc_avail;
2356 first = sc->next_tx_to_clean;
2357
2358 while (first != tdh) {
2359 logif(pkt_txclean);
2360
5330213c
SZ
2361 num_avail++;
2362
323e5ecd 2363 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2364 if (tx_buffer->m_head) {
2365 ifp->if_opackets++;
2366 bus_dmamap_unload(sc->txtag,
2367 tx_buffer->map);
2368 m_freem(tx_buffer->m_head);
2369 tx_buffer->m_head = NULL;
2370 }
2371
2372 if (first == dd_idx) {
2373 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2374 if (sc->tx_dd_head == sc->tx_dd_tail) {
2375 sc->tx_dd_head = 0;
2376 sc->tx_dd_tail = 0;
2377 dd_idx = -1;
2378 } else {
2379 dd_idx = sc->tx_dd[sc->tx_dd_head];
2380 }
2381 }
2382
2383 if (++first == sc->num_tx_desc)
2384 first = 0;
2385 }
2386 sc->next_tx_to_clean = first;
2387 sc->num_tx_desc_avail = num_avail;
2388
2389 if (!EMX_IS_OACTIVE(sc)) {
2390 ifp->if_flags &= ~IFF_OACTIVE;
2391
2392 /* All clean, turn off the timer */
2393 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2394 ifp->if_timer = 0;
2395 }
2396}
2397
2398/*
2399 * When Link is lost sometimes there is work still in the TX ring
2400 * which will result in a watchdog, rather than allow that do an
2401 * attempted cleanup and then reinit here. Note that this has been
2402 * seens mostly with fiber adapters.
2403 */
2404static void
2405emx_tx_purge(struct emx_softc *sc)
2406{
2407 struct ifnet *ifp = &sc->arpcom.ac_if;
2408
2409 if (!sc->link_active && ifp->if_timer) {
2410 emx_tx_collect(sc);
2411 if (ifp->if_timer) {
2412 if_printf(ifp, "Link lost, TX pending, reinit\n");
2413 ifp->if_timer = 0;
2414 emx_init(sc);
2415 }
2416 }
2417}
2418
2419static int
c39e3a1f 2420emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2421{
2422 struct mbuf *m;
2423 bus_dma_segment_t seg;
2424 bus_dmamap_t map;
323e5ecd 2425 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2426 int error, nseg;
2427
2428 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2429 if (m == NULL) {
c39e3a1f 2430 rdata->mbuf_cluster_failed++;
5330213c
SZ
2431 if (init) {
2432 if_printf(&sc->arpcom.ac_if,
2433 "Unable to allocate RX mbuf\n");
2434 }
2435 return (ENOBUFS);
2436 }
2437 m->m_len = m->m_pkthdr.len = MCLBYTES;
2438
2439 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2440 m_adj(m, ETHER_ALIGN);
2441
c39e3a1f
SZ
2442 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2443 rdata->rx_sparemap, m,
5330213c
SZ
2444 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2445 if (error) {
2446 m_freem(m);
2447 if (init) {
2448 if_printf(&sc->arpcom.ac_if,
2449 "Unable to load RX mbuf\n");
2450 }
2451 return (error);
2452 }
2453
323e5ecd 2454 rx_buffer = &rdata->rx_buf[i];
5330213c 2455 if (rx_buffer->m_head != NULL)
c39e3a1f 2456 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2457
2458 map = rx_buffer->map;
c39e3a1f
SZ
2459 rx_buffer->map = rdata->rx_sparemap;
2460 rdata->rx_sparemap = map;
5330213c
SZ
2461
2462 rx_buffer->m_head = m;
235b9d30 2463 rx_buffer->paddr = seg.ds_addr;
5330213c 2464
235b9d30 2465 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2466 return (0);
2467}
2468
2469static int
c39e3a1f 2470emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2471{
2472 device_t dev = sc->dev;
323e5ecd 2473 struct emx_rxbuf *rx_buffer;
bdca134f
SZ
2474 int i, error, rsize;
2475
2476 /*
2477 * Validate number of receive descriptors. It must not exceed
2478 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2479 */
3f939c23 2480 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
bdca134f
SZ
2481 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2482 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2483 EMX_DEFAULT_RXD, emx_rxd);
c39e3a1f 2484 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2485 } else {
c39e3a1f 2486 rdata->num_rx_desc = emx_rxd;
bdca134f
SZ
2487 }
2488
2489 /*
2490 * Allocate Receive Descriptor ring
2491 */
235b9d30 2492 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2493 EMX_DBA_ALIGN);
235b9d30 2494 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2495 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2496 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2497 &rdata->rx_desc_paddr);
235b9d30 2498 if (rdata->rx_desc == NULL) {
bdca134f 2499 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2500 return ENOMEM;
bdca134f 2501 }
5330213c 2502
323e5ecd
SZ
2503 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2504 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2505
2506 /*
2507 * Create DMA tag for rx buffers
2508 */
2509 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2510 1, 0, /* alignment, bounds */
2511 BUS_SPACE_MAXADDR, /* lowaddr */
2512 BUS_SPACE_MAXADDR, /* highaddr */
2513 NULL, NULL, /* filter, filterarg */
2514 MCLBYTES, /* maxsize */
2515 1, /* nsegments */
2516 MCLBYTES, /* maxsegsize */
2517 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2518 &rdata->rxtag);
5330213c
SZ
2519 if (error) {
2520 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2521 kfree(rdata->rx_buf, M_DEVBUF);
2522 rdata->rx_buf = NULL;
5330213c
SZ
2523 return error;
2524 }
2525
2526 /*
2527 * Create spare DMA map for rx buffers
2528 */
c39e3a1f
SZ
2529 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2530 &rdata->rx_sparemap);
5330213c
SZ
2531 if (error) {
2532 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2533 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2534 kfree(rdata->rx_buf, M_DEVBUF);
2535 rdata->rx_buf = NULL;
5330213c
SZ
2536 return error;
2537 }
2538
2539 /*
2540 * Create DMA maps for rx buffers
2541 */
c39e3a1f 2542 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2543 rx_buffer = &rdata->rx_buf[i];
5330213c 2544
c39e3a1f 2545 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2546 &rx_buffer->map);
2547 if (error) {
2548 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2549 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ
2550 return error;
2551 }
2552 }
2553 return (0);
2554}
2555
c39e3a1f
SZ
2556static void
2557emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2558{
2559 int i;
2560
2561 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2562 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2563
2564 if (rx_buffer->m_head != NULL) {
2565 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2566 m_freem(rx_buffer->m_head);
2567 rx_buffer->m_head = NULL;
2568 }
2569 }
2570
2571 if (rdata->fmp != NULL)
2572 m_freem(rdata->fmp);
2573 rdata->fmp = NULL;
2574 rdata->lmp = NULL;
2575}
2576
5330213c 2577static int
c39e3a1f 2578emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2579{
2580 int i, error;
2581
2582 /* Reset descriptor ring */
235b9d30 2583 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2584
2585 /* Allocate new ones. */
c39e3a1f
SZ
2586 for (i = 0; i < rdata->num_rx_desc; i++) {
2587 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ
2588 if (error)
2589 return (error);
2590 }
2591
2592 /* Setup our descriptor pointers */
c39e3a1f 2593 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2594
2595 return (0);
2596}
2597
2598static void
2599emx_init_rx_unit(struct emx_softc *sc)
2600{
2601 struct ifnet *ifp = &sc->arpcom.ac_if;
2602 uint64_t bus_addr;
89d8e73d 2603 uint32_t rctl, rxcsum, rfctl;
3f939c23 2604 int i;
5330213c
SZ
2605
2606 /*
2607 * Make sure receives are disabled while setting
2608 * up the descriptor ring
2609 */
2610 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2611 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2612
2613 /*
2614 * Set the interrupt throttling rate. Value is calculated
2615 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2616 */
2617 if (sc->int_throttle_ceil) {
2618 E1000_WRITE_REG(&sc->hw, E1000_ITR,
2619 1000000000 / 256 / sc->int_throttle_ceil);
2620 } else {
2621 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0);
2622 }
2623
235b9d30
SZ
2624 /* Use extended RX descriptor */
2625 rfctl = E1000_RFCTL_EXTEN;
2626
5330213c 2627 /* Disable accelerated ackknowledge */
235b9d30
SZ
2628 if (sc->hw.mac.type == e1000_82574)
2629 rfctl |= E1000_RFCTL_ACK_DIS;
2630
2631 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c
SZ
2632
2633 /* Setup the Base and Length of the Rx Descriptor Ring */
8434a83b 2634 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
2635 struct emx_rxdata *rdata = &sc->rx_data[i];
2636
2637 bus_addr = rdata->rx_desc_paddr;
2638 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2639 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2640 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2641 (uint32_t)(bus_addr >> 32));
2642 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2643 (uint32_t)bus_addr);
2644 }
5330213c
SZ
2645
2646 /* Setup the Receive Control Register */
2647 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2648 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
0acc29d6 2649 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
5330213c
SZ
2650 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2651
2652 /* Make sure VLAN Filters are off */
2653 rctl &= ~E1000_RCTL_VFE;
2654
80d8e1ca
SZ
2655 /* Don't store bad paket */
2656 rctl &= ~E1000_RCTL_SBP;
5330213c 2657
c39e3a1f
SZ
2658 /* MCLBYTES */
2659 rctl |= E1000_RCTL_SZ_2048;
5330213c
SZ
2660
2661 if (ifp->if_mtu > ETHERMTU)
2662 rctl |= E1000_RCTL_LPE;
2663 else
2664 rctl &= ~E1000_RCTL_LPE;
2665
65c7a6af
SZ
2666 /*
2667 * Receive Checksum Offload for TCP and UDP
2668 *
2669 * Checksum offloading is also enabled if multiple receive
2670 * queue is to be supported, since we need it to figure out
2671 * packet type.
2672 */
8434a83b 2673 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
5330213c 2674 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2675
2676 /*
2677 * NOTE:
2678 * PCSD must be enabled to enable multiple
2679 * receive queues.
2680 */
2681 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2682 E1000_RXCSUM_PCSD;
5330213c
SZ
2683 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2684 }
2685
2686 /*
65c7a6af 2687 * Configure multiple receive queue (RSS)
3f939c23 2688 */
8434a83b 2689 if (ifp->if_capenable & IFCAP_RSS) {
89d8e73d
SZ
2690 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2691 uint32_t reta;
2692
2693 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2694 ("invalid number of RX ring (%d)",
2695 sc->rx_ring_inuse));
2696
65c7a6af
SZ
2697 /*
2698 * NOTE:
2699 * When we reach here, RSS has already been disabled
2700 * in emx_stop(), so we could safely configure RSS key
2701 * and redirect table.
2702 */
3f939c23 2703
65c7a6af
SZ
2704 /*
2705 * Configure RSS key
2706 */
89d8e73d
SZ
2707 toeplitz_get_key(key, sizeof(key));
2708 for (i = 0; i < EMX_NRSSRK; ++i) {
2709 uint32_t rssrk;
2710
2711 rssrk = EMX_RSSRK_VAL(key, i);
2712 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2713
2714 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2715 }
3f939c23 2716
65c7a6af 2717 /*
89d8e73d
SZ
2718 * Configure RSS redirect table in following fashion:
2719 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2720 */
89d8e73d
SZ
2721 reta = 0;
2722 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2723 uint32_t q;
2724
2725 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2726 reta |= q << (8 * i);
2727 }
2728 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2729
65c7a6af
SZ
2730 for (i = 0; i < EMX_NRETA; ++i)
2731 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2732
65c7a6af
SZ
2733 /*
2734 * Enable multiple receive queues.
2735 * Enable IPv4 RSS standard hash functions.
2736 * Disable RSS interrupt.
2737 */
2738 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2739 E1000_MRQC_ENABLE_RSS_2Q |
2740 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2741 E1000_MRQC_RSS_FIELD_IPV4);
2742 }
3f939c23
SZ
2743
2744 /*
5330213c
SZ
2745 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2746 * long latencies are observed, like Lenovo X60. This
2747 * change eliminates the problem, but since having positive
2748 * values in RDTR is a known source of problems on other
2749 * platforms another solution is being sought.
2750 */
2751 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2752 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2753 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2754 }
2755
5330213c
SZ
2756 /*
2757 * Setup the HW Rx Head and Tail Descriptor Pointers
2758 */
8434a83b 2759 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
2760 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2761 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2762 sc->rx_data[i].num_rx_desc - 1);
2763 }
2764
2765 /* Enable Receives */
2766 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2767}
2768
2769static void
c39e3a1f 2770emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2771{
323e5ecd 2772 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2773 int i;
2774
bdca134f 2775 /* Free Receive Descriptor ring */
235b9d30 2776 if (rdata->rx_desc) {
c39e3a1f 2777 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2778 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2779 rdata->rx_desc_dmap);
2780 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2781
235b9d30 2782 rdata->rx_desc = NULL;
a596084c 2783 }
bdca134f 2784
323e5ecd 2785 if (rdata->rx_buf == NULL)
5330213c
SZ
2786 return;
2787
2788 for (i = 0; i < ndesc; i++) {
323e5ecd 2789 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2790
2791 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2792 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2793 }
c39e3a1f
SZ
2794 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2795 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2796
323e5ecd
SZ
2797 kfree(rdata->rx_buf, M_DEVBUF);
2798 rdata->rx_buf = NULL;
5330213c
SZ
2799}
2800
2801static void
c39e3a1f 2802emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2803{
c39e3a1f 2804 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2805 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2806 uint32_t staterr;
235b9d30 2807 emx_rxdesc_t *current_desc;
5330213c
SZ
2808 struct mbuf *mp;
2809 int i;
2810 struct mbuf_chain chain[MAXCPU];
2811
c39e3a1f 2812 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2813 current_desc = &rdata->rx_desc[i];
2814 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2815
235b9d30 2816 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2817 return;
2818
2819 ether_input_chain_init(chain);
2820
235b9d30 2821 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2822 struct pktinfo *pi = NULL, pi0;
235b9d30 2823 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2824 struct mbuf *m = NULL;
0acc29d6 2825 int eop, len;
5330213c
SZ
2826
2827 logif(pkt_receive);
2828
235b9d30 2829 mp = rx_buf->m_head;
5330213c
SZ
2830
2831 /*
2832 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2833 * needs to access the last received byte in the mbuf.
2834 */
235b9d30 2835 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2836 BUS_DMASYNC_POSTREAD);
2837
0acc29d6 2838 len = le16toh(current_desc->rxd_length);
235b9d30 2839 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2840 count--;
2841 eop = 1;
5330213c
SZ
2842 } else {
2843 eop = 0;
5330213c
SZ
2844 }
2845
235b9d30
SZ
2846 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2847 uint16_t vlan = 0;
3f939c23 2848 uint32_t mrq, rss_hash;
235b9d30
SZ
2849
2850 /*
2851 * Save several necessary information,
2852 * before emx_newbuf() destroy it.
2853 */
2854 if ((staterr & E1000_RXD_STAT_VP) && eop)
2855 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2856
3f939c23
SZ
2857 mrq = le32toh(current_desc->rxd_mrq);
2858 rss_hash = le32toh(current_desc->rxd_rss);
2859
2860 EMX_RSS_DPRINTF(sc, 10,
2861 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2862 ring_idx, mrq, rss_hash);
2863
c39e3a1f 2864 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ
2865 ifp->if_iqdrops++;
2866 goto discard;
2867 }
2868
2869 /* Assign correct length to the current fragment */
2870 mp->m_len = len;
2871
c39e3a1f 2872 if (rdata->fmp == NULL) {
5330213c 2873 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2874 rdata->fmp = mp; /* Store the first mbuf */
2875 rdata->lmp = mp;
5330213c
SZ
2876 } else {
2877 /*
2878 * Chain mbuf's together
2879 */
c39e3a1f
SZ
2880 rdata->lmp->m_next = mp;
2881 rdata->lmp = rdata->lmp->m_next;
2882 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2883 }
2884
2885 if (eop) {
c39e3a1f 2886 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2887 ifp->if_ipackets++;
2888
235b9d30
SZ
2889 if (ifp->if_capenable & IFCAP_RXCSUM)
2890 emx_rxcsum(staterr, rdata->fmp);
5330213c 2891
235b9d30 2892 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2893 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2894 vlan;
c39e3a1f 2895 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2896 }
c39e3a1f
SZ
2897 m = rdata->fmp;
2898 rdata->fmp = NULL;
2899 rdata->lmp = NULL;
3f939c23 2900
9cc86e17
SZ
2901 if (ifp->if_capenable & IFCAP_RSS) {
2902 pi = emx_rssinfo(m, &pi0, mrq,
2903 rss_hash, staterr);
2904 }
3f939c23
SZ
2905#ifdef EMX_RSS_DEBUG
2906 rdata->rx_pkts++;
2907#endif
5330213c
SZ
2908 }
2909 } else {
2910 ifp->if_ierrors++;
2911discard:
235b9d30 2912 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2913 if (rdata->fmp != NULL) {
2914 m_freem(rdata->fmp);
2915 rdata->fmp = NULL;
2916 rdata->lmp = NULL;
5330213c
SZ
2917 }
2918 m = NULL;
2919 }
2920
5330213c 2921 if (m != NULL)
9cc86e17 2922 ether_input_chain(ifp, m, pi, chain);
5330213c
SZ
2923
2924 /* Advance our pointers to the next descriptor. */
c39e3a1f 2925 if (++i == rdata->num_rx_desc)
5330213c 2926 i = 0;
235b9d30
SZ
2927
2928 current_desc = &rdata->rx_desc[i];
2929 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2930 }
c39e3a1f 2931 rdata->next_rx_desc_to_check = i;
5330213c
SZ
2932
2933 ether_input_dispatch(chain);
2934
3f939c23 2935 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2936 if (--i < 0)
c39e3a1f 2937 i = rdata->num_rx_desc - 1;
3f939c23 2938 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ
2939}
2940
2941static void
5330213c
SZ
2942emx_enable_intr(struct emx_softc *sc)
2943{
6d435846 2944 lwkt_serialize_handler_enable(&sc->main_serialize);
5330213c
SZ
2945 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2946}
2947
2948static void
2949emx_disable_intr(struct emx_softc *sc)
2950{
2951 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
6d435846 2952 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
2953}
2954
2955/*
2956 * Bit of a misnomer, what this really means is
2957 * to enable OS management of the system... aka
2958 * to disable special hardware management features
2959 */
2960static void
2961emx_get_mgmt(struct emx_softc *sc)
2962{
2963 /* A shared code workaround */
2964 if (sc->has_manage) {
2965 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2966 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2967
2968 /* disable hardware interception of ARP */
2969 manc &= ~(E1000_MANC_ARP_EN);
2970
2971 /* enable receiving management packets to the host */
2972 manc |= E1000_MANC_EN_MNG2HOST;
2973#define E1000_MNG2HOST_PORT_623 (1 << 5)
2974#define E1000_MNG2HOST_PORT_664 (1 << 6)
2975 manc2h |= E1000_MNG2HOST_PORT_623;
2976 manc2h |= E1000_MNG2HOST_PORT_664;
2977 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2978
2979 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2980 }
2981}
2982
2983/*
2984 * Give control back to hardware management
2985 * controller if there is one.
2986 */
2987static void
2988emx_rel_mgmt(struct emx_softc *sc)
2989{
2990 if (sc->has_manage) {
2991 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2992
2993 /* re-enable hardware interception of ARP */
2994 manc |= E1000_MANC_ARP_EN;
2995 manc &= ~E1000_MANC_EN_MNG2HOST;
2996
2997 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2998 }
2999}
3000
3001/*
3002 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3003 * For ASF and Pass Through versions of f/w this means that
3004 * the driver is loaded. For AMT version (only with 82573)
3005 * of the f/w this means that the network i/f is open.
3006 */
3007static void
3008emx_get_hw_control(struct emx_softc *sc)
3009{
3010 uint32_t ctrl_ext, swsm;
3011
3012 /* Let firmware know the driver has taken over */
3013 switch (sc->hw.mac.type) {
3014 case e1000_82573:
3015 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3016 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3017 swsm | E1000_SWSM_DRV_LOAD);
3018 break;
3019
3020 case e1000_82571:
3021 case e1000_82572:
3022 case e1000_80003es2lan:
3023 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3024 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3025 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3026 break;
3027
3028 default:
3029 break;
3030 }
3031}
3032
3033/*
3034 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3035 * For ASF and Pass Through versions of f/w this means that the
3036 * driver is no longer loaded. For AMT version (only with 82573)
3037 * of the f/w this means that the network i/f is closed.
3038 */
3039static void
3040emx_rel_hw_control(struct emx_softc *sc)
3041{
3042 uint32_t ctrl_ext, swsm;
3043
3044 /* Let firmware taken over control of h/w */
3045 switch (sc->hw.mac.type) {
3046 case e1000_82573:
3047 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3048 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3049 swsm & ~E1000_SWSM_DRV_LOAD);
3050 break;
3051
3052 case e1000_82571:
3053 case e1000_82572:
3054 case e1000_80003es2lan:
3055 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3056 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3057 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3058 break;
3059
3060 default:
3061 break;
3062 }
3063}
3064
3065static int
3066emx_is_valid_eaddr(const uint8_t *addr)
3067{
3068 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3069
3070 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3071 return (FALSE);
3072
3073 return (TRUE);
3074}
3075
3076/*
3077 * Enable PCI Wake On Lan capability
3078 */
3079void
3080emx_enable_wol(device_t dev)
3081{
3082 uint16_t cap, status;
3083 uint8_t id;
3084
3085 /* First find the capabilities pointer*/
3086 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3087
3088 /* Read the PM Capabilities */
3089 id = pci_read_config(dev, cap, 1);
3090 if (id != PCIY_PMG) /* Something wrong */
3091 return;
3092
3093 /*
3094 * OK, we have the power capabilities,
3095 * so now get the status register
3096 */
3097 cap += PCIR_POWER_STATUS;
3098 status = pci_read_config(dev, cap, 2);
3099 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3100 pci_write_config(dev, cap, status, 2);
3101}
3102
3103static void
3104emx_update_stats(struct emx_softc *sc)
3105{
3106 struct ifnet *ifp = &sc->arpcom.ac_if;
3107
3108 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3109 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3110 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3111 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3112 }
3113 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3114 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3115 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3116 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3117
3118 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3119 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3120 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3121 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3122 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3123 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3124 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3125 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3126 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3127 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3128 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3129 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3130 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3131 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3132 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3133 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3134 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3135 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3136 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3137 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3138
3139 /* For the 64-bit byte counters the low dword must be read first. */
3140 /* Both registers clear on the read of the high dword */
3141
3142 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3143 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3144
3145 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3146 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3147 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3148 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3149 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3150
3151 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3152 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3153
3154 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3155 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3156 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3157 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3158 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3159 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3160 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3161 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3162 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3163 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3164
3165 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3166 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3167 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3168 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3169 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3170 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3171
3172 ifp->if_collisions = sc->stats.colc;
3173
3174 /* Rx Errors */
3175 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3176 sc->stats.crcerrs + sc->stats.algnerrc +
3177 sc->stats.ruc + sc->stats.roc +
3178 sc->stats.mpc + sc->stats.cexterr;
3179
3180 /* Tx Errors */
3181 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3182 sc->watchdog_events;
3183}
3184
3185static void
3186emx_print_debug_info(struct emx_softc *sc)
3187{
3188 device_t dev = sc->dev;
3189 uint8_t *hw_addr = sc->hw.hw_addr;
3190
3191 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3192 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3193 E1000_READ_REG(&sc->hw, E1000_CTRL),
3194 E1000_READ_REG(&sc->hw, E1000_RCTL));
3195 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3196 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3197 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3198 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3199 sc->hw.fc.high_water, sc->hw.fc.low_water);
3200 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3201 E1000_READ_REG(&sc->hw, E1000_TIDV),
3202 E1000_READ_REG(&sc->hw, E1000_TADV));
3203 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3204 E1000_READ_REG(&sc->hw, E1000_RDTR),
3205 E1000_READ_REG(&sc->hw, E1000_RADV));
3206 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3207 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3208 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3209 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3210 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3211 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3212 device_printf(dev, "Num Tx descriptors avail = %d\n",
3213 sc->num_tx_desc_avail);
3214 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3215 sc->no_tx_desc_avail1);
3216 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3217 sc->no_tx_desc_avail2);
3218 device_printf(dev, "Std mbuf failed = %ld\n",
3219 sc->mbuf_alloc_failed);
3220 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3221 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ
3222 device_printf(dev, "Driver dropped packets = %ld\n",
3223 sc->dropped_pkts);
3224 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3225 sc->no_tx_dma_setup);
3226
3227 device_printf(dev, "TXCSUM try pullup = %lu\n",
3228 sc->tx_csum_try_pullup);
3229 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3230 sc->tx_csum_pullup1);
3231 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3232 sc->tx_csum_pullup1_failed);
3233 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3234 sc->tx_csum_pullup2);
3235 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3236 sc->tx_csum_pullup2_failed);
3237 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3238 sc->tx_csum_drop1);
3239 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3240 sc->tx_csum_drop2);
3241}
3242
3243static void
3244emx_print_hw_stats(struct emx_softc *sc)
3245{
3246 device_t dev = sc->dev;
3247
3248 device_printf(dev, "Excessive collisions = %lld\n",
3249 (long long)sc->stats.ecol);
3250#if (DEBUG_HW > 0) /* Dont output these errors normally */
3251 device_printf(dev, "Symbol errors = %lld\n",
3252 (long long)sc->stats.symerrs);
3253#endif
3254 device_printf(dev, "Sequence errors = %lld\n",
3255 (long long)sc->stats.sec);
3256 device_printf(dev, "Defer count = %lld\n",
3257 (long long)sc->stats.dc);
3258 device_printf(dev, "Missed Packets = %lld\n",
3259 (long long)sc->stats.mpc);
3260 device_printf(dev, "Receive No Buffers = %lld\n",
3261 (long long)sc->stats.rnbc);
3262 /* RLEC is inaccurate on some hardware, calculate our own. */
3263 device_printf(dev, "Receive Length Errors = %lld\n",
3264 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3265 device_printf(dev, "Receive errors = %lld\n",
3266 (long long)sc->stats.rxerrc);
3267 device_printf(dev, "Crc errors = %lld\n",
3268 (long long)sc->stats.crcerrs);
3269 device_printf(dev, "Alignment errors = %lld\n",
3270 (long long)sc->stats.algnerrc);
3271 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3272 (long long)sc->stats.cexterr);
3273 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3274 device_printf(dev, "watchdog timeouts = %ld\n",
3275 sc->watchdog_events);
3276 device_printf(dev, "XON Rcvd = %lld\n",
3277 (long long)sc->stats.xonrxc);
3278 device_printf(dev, "XON Xmtd = %lld\n",
3279 (long long)sc->stats.xontxc);
3280 device_printf(dev, "XOFF Rcvd = %lld\n",
3281 (long long)sc->stats.xoffrxc);
3282 device_printf(dev, "XOFF Xmtd = %lld\n",
3283 (long long)sc->stats.xofftxc);
3284 device_printf(dev, "Good Packets Rcvd = %lld\n",
3285 (long long)sc->stats.gprc);
3286 device_printf(dev, "Good Packets Xmtd = %lld\n",
3287 (long long)sc->stats.gptc);
3288}
3289
3290static void
3291emx_print_nvm_info(struct emx_softc *sc)
3292{
3293 uint16_t eeprom_data;
3294 int i, j, row = 0;
3295
3296 /* Its a bit crude, but it gets the job done */
3297 kprintf("\nInterface EEPROM Dump:\n");
3298 kprintf("Offset\n0x0000 ");
3299 for (i = 0, j = 0; i < 32; i++, j++) {
3300 if (j == 8) { /* Make the offset block */
3301 j = 0; ++row;
3302 kprintf("\n0x00%x0 ",row);
3303 }
3304 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3305 kprintf("%04x ", eeprom_data);
3306 }
3307 kprintf("\n");
3308}
3309
3310static int
3311emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3312{
3313 struct emx_softc *sc;
3314 struct ifnet *ifp;
3315 int error, result;
3316
3317 result = -1;
3318 error = sysctl_handle_int(oidp, &result, 0, req);
3319 if (error || !req->newptr)
3320 return (error);
3321
3322 sc = (struct emx_softc *)arg1;
3323 ifp = &sc->arpcom.ac_if;
3324
6d435846 3325 ifnet_serialize_all(ifp);
5330213c
SZ
3326
3327 if (result == 1)
3328 emx_print_debug_info(sc);
3329
3330 /*
3331 * This value will cause a hex dump of the
3332 * first 32 16-bit words of the EEPROM to
3333 * the screen.
3334 */
3335 if (result == 2)
3336 emx_print_nvm_info(sc);
3337
6d435846 3338 ifnet_deserialize_all(ifp);
5330213c
SZ
3339
3340 return (error);
3341}
3342
3343static int
3344emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3345{
3346 int error, result;
3347
3348 result = -1;
3349 error = sysctl_handle_int(oidp, &result, 0, req);
3350 if (error || !req->newptr)
3351 return (error);
3352
3353 if (result == 1) {
3354 struct emx_softc *sc = (struct emx_softc *)arg1;
3355 struct ifnet *ifp = &sc->arpcom.ac_if;
3356
6d435846 3357 ifnet_serialize_all(ifp);
5330213c 3358 emx_print_hw_stats(sc);
6d435846 3359 ifnet_deserialize_all(ifp);
5330213c
SZ
3360 }
3361 return (error);
3362}
3363
3364static void
3365emx_add_sysctl(struct emx_softc *sc)
3366{
3367#ifdef PROFILE_SERIALIZER
3368 struct ifnet *ifp = &sc->arpcom.ac_if;
3369#endif
3f939c23
SZ
3370#ifdef EMX_RSS_DEBUG
3371 char rx_pkt[32];
3372 int i;
3373#endif
5330213c
SZ
3374
3375 sysctl_ctx_init(&sc->sysctl_ctx);
3376 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3377 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3378 device_get_nameunit(sc->dev),
3379 CTLFLAG_RD, 0, "");
3380 if (sc->sysctl_tree == NULL) {
3381 device_printf(sc->dev, "can't add sysctl node\n");
3382 return;
3383 }
3384
3385 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3386 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3387 emx_sysctl_debug_info, "I", "Debug Information");
3388
3389 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3390 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3391 emx_sysctl_stats, "I", "Statistics");
3392
3393 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3394 OID_AUTO, "rxd", CTLFLAG_RD,
3395 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3396 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3397 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3398
6d435846 3399#ifdef notyet
5330213c
SZ
3400#ifdef PROFILE_SERIALIZER
3401 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3402 OID_AUTO, "serializer_sleep", CTLFLAG_RW,
3403 &ifp->if_serializer->sleep_cnt, 0, NULL);
3404 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3405 OID_AUTO, "serializer_tryfail", CTLFLAG_RW,
3406 &ifp->if_serializer->tryfail_cnt, 0, NULL);
3407 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3408 OID_AUTO, "serializer_enter", CTLFLAG_RW,
3409 &ifp->if_serializer->enter_cnt, 0, NULL);
3410 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3411 OID_AUTO, "serializer_try", CTLFLAG_RW,
3412 &ifp->if_serializer->try_cnt, 0, NULL);
3413#endif
6d435846 3414#endif
5330213c
SZ
3415
3416 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3417 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3418 sc, 0, emx_sysctl_int_throttle, "I",
3419 "interrupt throttling rate");
3420 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3421 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3422 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3423 "# segments per TX interrupt");
3f939c23 3424
8434a83b
SZ
3425 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3426 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3427 &sc->rx_ring_inuse, 0, "RX ring in use");
3428
3f939c23
SZ
3429#ifdef EMX_RSS_DEBUG
3430 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3431 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3432 0, "RSS debug level");
65c7a6af 3433 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3434 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3435 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3436 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3437 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3438 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3439 }
3440#endif
5330213c
SZ
3441}
3442
3443static int
3444emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3445{
3446 struct emx_softc *sc = (void *)arg1;
3447 struct ifnet *ifp = &sc->arpcom.ac_if;
3448 int error, throttle;
3449
3450 throttle = sc->int_throttle_ceil;
3451 error = sysctl_handle_int(oidp, &throttle, 0, req);
3452 if (error || req->newptr == NULL)
3453 return error;
3454 if (throttle < 0 || throttle > 1000000000 / 256)
3455 return EINVAL;
3456
3457 if (throttle) {
3458 /*
3459 * Set the interrupt throttling rate in 256ns increments,
3460 * recalculate sysctl value assignment to get exact frequency.
3461 */
3462 throttle = 1000000000 / 256 / throttle;
3463
3464 /* Upper 16bits of ITR is reserved and should be zero */
3465 if (throttle & 0xffff0000)
3466 return EINVAL;
3467 }
3468
6d435846 3469 ifnet_serialize_all(ifp);
5330213c
SZ
3470
3471 if (throttle)
3472 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3473 else
3474 sc->int_throttle_ceil = 0;
3475
3476 if (ifp->if_flags & IFF_RUNNING)
3477 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle);
3478
6d435846 3479 ifnet_deserialize_all(ifp);
5330213c
SZ
3480
3481 if (bootverbose) {
3482 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3483 sc->int_throttle_ceil);
3484 }
3485 return 0;
3486}
3487
3488static int
3489emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3490{
3491 struct emx_softc *sc = (void *)arg1;
3492 struct ifnet *ifp = &sc->arpcom.ac_if;
3493 int error, segs;
3494
3495 segs = sc->tx_int_nsegs;
3496 error = sysctl_handle_int(oidp, &segs, 0, req);
3497 if (error || req->newptr == NULL)
3498 return error;
3499 if (segs <= 0)
3500 return EINVAL;
3501
6d435846 3502 ifnet_serialize_all(ifp);
5330213c
SZ
3503
3504 /*
3505 * Don't allow int_tx_nsegs to become:
3506 * o Less the oact_tx_desc
3507 * o Too large that no TX desc will cause TX interrupt to
3508 * be generated (OACTIVE will never recover)
3509 * o Too small that will cause tx_dd[] overflow
3510 */
3511 if (segs < sc->oact_tx_desc ||
3512 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3513 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3514 error = EINVAL;
3515 } else {
3516 error = 0;
3517 sc->tx_int_nsegs = segs;
3518 }
3519
6d435846 3520 ifnet_deserialize_all(ifp);
5330213c
SZ
3521
3522 return error;
3523}
071699f8
SZ
3524
3525static int
3526emx_dma_alloc(struct emx_softc *sc)
3527{
3f939c23 3528 int error, i;
071699f8
SZ
3529
3530 /*
3531 * Create top level busdma tag
3532 */
3533 error = bus_dma_tag_create(NULL, 1, 0,
3534 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3535 NULL, NULL,
3536 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3537 0, &sc->parent_dtag);
3538 if (error) {
3539 device_printf(sc->dev, "could not create top level DMA tag\n");
3540 return error;
3541 }
3542
3543 /*
3544 * Allocate transmit descriptors ring and buffers
3545 */
3546 error = emx_create_tx_ring(sc);
3547 if (error) {
3548 device_printf(sc->dev, "Could not setup transmit structures\n");
3549 return error;
3550 }
3551
3552 /*
3553 * Allocate receive descriptors ring and buffers
3554 */
65c7a6af 3555 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3556 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3557 if (error) {
3558 device_printf(sc->dev,
3559 "Could not setup receive structures\n");
3560 return error;
3561 }
071699f8
SZ
3562 }
3563 return 0;
3564}
3565
3566static void
3567emx_dma_free(struct emx_softc *sc)
3568{
3f939c23
SZ
3569 int i;
3570
071699f8 3571 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3572
65c7a6af 3573 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3574 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3575 sc->rx_data[i].num_rx_desc);
3576 }
071699f8
SZ
3577
3578 /* Free top level busdma tag */
3579 if (sc->parent_dtag != NULL)
3580 bus_dma_tag_destroy(sc->parent_dtag);
3581}
6d435846
SZ
3582
3583static void
3584emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3585{
3586 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3587
3588 switch (slz) {
3589 case IFNET_SERIALIZE_ALL:
f61533ad 3590 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
6d435846
SZ
3591 break;
3592
aabfe6fb
SZ
3593 case IFNET_SERIALIZE_MAIN:
3594 lwkt_serialize_enter(&sc->main_serialize);
3595 break;
3596
6d435846
SZ
3597 case IFNET_SERIALIZE_TX:
3598 lwkt_serialize_enter(&sc->tx_serialize);
3599 break;
3600
067b3d6b 3601 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3602 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3603 break;
3604
067b3d6b 3605 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3606 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3607 break;
3608
3609 default:
3610 panic("%s unsupported serialize type\n", ifp->if_xname);
3611 }
3612}
3613
3614static void
3615emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3616{
3617 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3618
3619 switch (slz) {
3620 case IFNET_SERIALIZE_ALL:
f61533ad 3621 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
6d435846
SZ
3622 break;
3623
aabfe6fb
SZ
3624 case IFNET_SERIALIZE_MAIN:
3625 lwkt_serialize_exit(&sc->main_serialize);
3626 break;
3627
6d435846
SZ
3628 case IFNET_SERIALIZE_TX:
3629 lwkt_serialize_exit(&sc->tx_serialize);
3630 break;
3631
067b3d6b 3632 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3633 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3634 break;
3635
067b3d6b 3636 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3637 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3638 break;
3639
3640 default:
3641 panic("%s unsupported serialize type\n", ifp->if_xname);
3642 }
3643}
3644
3645static int
3646emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3647{
3648 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3649
3650 switch (slz) {
3651 case IFNET_SERIALIZE_ALL:
f61533ad
SZ
3652 return lwkt_serialize_array_try(sc->serializes,
3653 EMX_NSERIALIZE, 0);
6d435846 3654
aabfe6fb
SZ
3655 case IFNET_SERIALIZE_MAIN:
3656 return lwkt_serialize_try(&sc->main_serialize);
3657
6d435846
SZ
3658 case IFNET_SERIALIZE_TX:
3659 return lwkt_serialize_try(&sc->tx_serialize);
3660
067b3d6b 3661 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3662 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3663
067b3d6b 3664 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3665 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3666
3667 default:
3668 panic("%s unsupported serialize type\n", ifp->if_xname);
3669 }
3670}
bca7c435
SZ
3671
3672static void
3673emx_serialize_skipmain(struct emx_softc *sc)
3674{
3675 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3676}
3677
b3a7093f 3678#ifdef IFPOLL_ENABLE
aabfe6fb
SZ
3679static int
3680emx_tryserialize_skipmain(struct emx_softc *sc)
3681{
3682 return lwkt_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 1);
3683}
b3a7093f 3684#endif
aabfe6fb 3685
bca7c435
SZ
3686static void
3687emx_deserialize_skipmain(struct emx_softc *sc)
3688{
3689 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3690}
2c9effcf
SZ
3691
3692#ifdef INVARIANTS
3693
3694static void
3695emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3696 boolean_t serialized)
3697{
3698 struct emx_softc *sc = ifp->if_softc;
3699 int i;
3700
3701 switch (slz) {
3702 case IFNET_SERIALIZE_ALL:
3703 if (serialized) {
3704 for (i = 0; i < EMX_NSERIALIZE; ++i)
3705 ASSERT_SERIALIZED(sc->serializes[i]);
3706 } else {
3707 for (i = 0; i < EMX_NSERIALIZE; ++i)
3708 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3709 }
3710 break;
3711
aabfe6fb
SZ
3712 case IFNET_SERIALIZE_MAIN:
3713 if (serialized)
3714 ASSERT_SERIALIZED(&sc->main_serialize);
3715 else
3716 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3717 break;
3718
2c9effcf
SZ
3719 case IFNET_SERIALIZE_TX:
3720 if (serialized)
3721 ASSERT_SERIALIZED(&sc->tx_serialize);
3722 else
3723 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3724 break;
3725
067b3d6b 3726 case IFNET_SERIALIZE_RX(0):
2c9effcf
SZ
3727 if (serialized)
3728 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3729 else
3730 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3731 break;
3732
067b3d6b 3733 case IFNET_SERIALIZE_RX(1):
2c9effcf
SZ
3734 if (serialized)
3735 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3736 else
3737 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3738 break;
3739
3740 default:
3741 panic("%s unsupported serialize type\n", ifp->if_xname);
3742 }
3743}
3744
3745#endif /* INVARIANTS */
b3a7093f
SZ
3746
3747#ifdef IFPOLL_ENABLE
3748
3749static void
3750emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3751{
3752 struct emx_softc *sc = ifp->if_softc;
3753 uint32_t reg_icr;
3754
3755 ASSERT_SERIALIZED(&sc->main_serialize);
3756
3757 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3758 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3759 if (emx_tryserialize_skipmain(sc)) {
3760 callout_stop(&sc->timer);
3761 sc->hw.mac.get_link_status = 1;
3762 emx_update_link_status(sc);
3763 callout_reset(&sc->timer, hz, emx_timer, sc);
3764 emx_deserialize_skipmain(sc);
3765 }
3766 }
3767}
3768
3769static void
3770emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3771{
3772 struct emx_softc *sc = ifp->if_softc;
3773
3774 ASSERT_SERIALIZED(&sc->tx_serialize);
3775
3776 emx_txeof(sc);
3777 if (!ifq_is_empty(&ifp->if_snd))
3778 if_devstart(ifp);
3779}
3780
3781static void
3782emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3783{
3784 struct emx_softc *sc = ifp->if_softc;
3785 struct emx_rxdata *rdata = arg;
3786
3787 ASSERT_SERIALIZED(&rdata->rx_serialize);
3788
3789 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3790}
3791
3792static void
3793emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3794{
3795 struct emx_softc *sc = ifp->if_softc;
3796
3797 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3798
3799 if (info) {
3800 int i;
3801
3802 info->ifpi_status.status_func = emx_qpoll_status;
3803 info->ifpi_status.serializer = &sc->main_serialize;
3804
3805 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3806 info->ifpi_tx[0].arg = NULL;
3807 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3808
3809 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3810 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3811 info->ifpi_rx[i].arg = &sc->rx_data[i];
3812 info->ifpi_rx[i].serializer =
3813 &sc->rx_data[i].rx_serialize;
3814 }
3815
3816 if (ifp->if_flags & IFF_RUNNING)
3817 emx_disable_intr(sc);
3818 } else if (ifp->if_flags & IFF_RUNNING) {
3819 emx_enable_intr(sc);
3820 }
3821}
3822
3823#endif /* IFPOLL_ENABLE */