rl(4): Fix an old typo
[dragonfly.git] / sys / dev / netif / rl / if_rl.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
95893fe4 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.38 2008/08/17 04:32:34 sephe Exp $
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34 */
35
36/*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48/*
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
54 *
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
63 *
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
69 * levels.
70 *
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
74 *
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
79 * filter.
80 *
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
85 */
86
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87#include "opt_polling.h"
88
984263bc 89#include <sys/param.h>
ca59556a 90#include <sys/endian.h>
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91#include <sys/systm.h>
92#include <sys/sockio.h>
93#include <sys/mbuf.h>
94#include <sys/malloc.h>
95#include <sys/kernel.h>
ca59556a 96#include <sys/module.h>
984263bc 97#include <sys/socket.h>
78195a76 98#include <sys/serialize.h>
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99#include <sys/bus.h>
100#include <sys/rman.h>
a3fbe745 101#include <sys/thread2.h>
9db4b353 102#include <sys/interrupt.h>
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103
104#include <net/if.h>
c2ffa639 105#include <net/ifq_var.h>
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106#include <net/if_arp.h>
107#include <net/ethernet.h>
108#include <net/if_dl.h>
109#include <net/if_media.h>
110
111#include <net/bpf.h>
112
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113#include <dev/netif/mii_layer/mii.h>
114#include <dev/netif/mii_layer/miivar.h>
984263bc 115
598e5ef7 116#include <bus/pci/pcidevs.h>
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117#include <bus/pci/pcireg.h>
118#include <bus/pci/pcivar.h>
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119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123/*
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
130 */
131#define RL_USEIOSPACE
132
ca59556a 133#include <dev/netif/rl/if_rlreg.h>
984263bc 134
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135/*
136 * Various supported device vendors/types and their names.
137 */
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138static struct rl_type {
139 uint16_t rl_vid;
140 uint16_t rl_did;
141 const char *rl_name;
142} rl_devs[] = {
598e5ef7 143 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129,
984263bc 144 "RealTek 8129 10/100BaseTX" },
598e5ef7 145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
984263bc 146 "RealTek 8139 10/100BaseTX" },
598e5ef7 147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B,
ca59556a 148 "RealTek 8139 10/100BaseTX CardBus" },
598e5ef7 149 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030,
984263bc 150 "Accton MPX 5030/5038 10/100BaseTX" },
598e5ef7 151 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139,
984263bc 152 "Delta Electronics 8139 10/100BaseTX" },
598e5ef7 153 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139,
3f625015 154 "Addtron Technology 8139 10/100BaseTX" },
598e5ef7 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS,
984263bc 156 "D-Link DFE-530TX+ 10/100BaseTX" },
598e5ef7 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD,
ca59556a 158 "D-Link DFE-690TX 10/100BaseTX" },
598e5ef7 159 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21,
984263bc 160 "Nortel Networks 10/100BaseTX" },
598e5ef7 161 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF,
984263bc 162 "Peppercon AG ROL/F" },
598e5ef7 163 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD,
ca59556a 164 "Corega FEther CB-TXD" },
598e5ef7 165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD,
ca59556a 166 "Corega FEtherII CB-TXD" },
598e5ef7 167 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX,
ca59556a 168 "Planex FNW-3800-TX" },
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169 { 0, 0, NULL }
170};
171
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172static int rl_probe(device_t);
173static int rl_attach(device_t);
174static int rl_detach(device_t);
175
176static int rl_encap(struct rl_softc *, struct mbuf * );
177
178static void rl_rxeof(struct rl_softc *);
179static void rl_txeof(struct rl_softc *);
180static void rl_intr(void *);
181static void rl_tick(void *);
182static void rl_start(struct ifnet *);
183static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
184static void rl_init(void *);
185static void rl_stop (struct rl_softc *);
186static void rl_watchdog(struct ifnet *);
187static int rl_suspend(device_t);
188static int rl_resume(device_t);
189static void rl_shutdown(device_t);
190static int rl_ifmedia_upd(struct ifnet *);
191static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
192
193static void rl_eeprom_putbyte(struct rl_softc *, int);
194static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
195static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
196static void rl_mii_sync(struct rl_softc *);
197static void rl_mii_send(struct rl_softc *, uint32_t, int);
198static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
199static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
200
201static int rl_miibus_readreg(device_t, int, int);
202static int rl_miibus_writereg(device_t, int, int, int);
203static void rl_miibus_statchg(device_t);
204
205static void rl_setmulti(struct rl_softc *);
206static void rl_reset(struct rl_softc *);
207static void rl_list_tx_init(struct rl_softc *);
208
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209#ifdef DEVICE_POLLING
210static poll_handler_t rl_poll;
211#endif
984263bc 212
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213static int rl_dma_alloc(struct rl_softc *);
214static void rl_dma_free(struct rl_softc *);
215
984263bc 216#ifdef RL_USEIOSPACE
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217#define RL_RES SYS_RES_IOPORT
218#define RL_RID RL_PCI_LOIO
984263bc 219#else
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220#define RL_RES SYS_RES_MEMORY
221#define RL_RID RL_PCI_LOMEM
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222#endif
223
224static device_method_t rl_methods[] = {
225 /* Device interface */
226 DEVMETHOD(device_probe, rl_probe),
227 DEVMETHOD(device_attach, rl_attach),
228 DEVMETHOD(device_detach, rl_detach),
229 DEVMETHOD(device_suspend, rl_suspend),
230 DEVMETHOD(device_resume, rl_resume),
231 DEVMETHOD(device_shutdown, rl_shutdown),
232
233 /* bus interface */
234 DEVMETHOD(bus_print_child, bus_generic_print_child),
235 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
236
237 /* MII interface */
238 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
239 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
240 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
241
242 { 0, 0 }
243};
244
ca59556a 245static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
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246static devclass_t rl_devclass;
247
32832096 248DECLARE_DUMMY_MODULE(if_rl);
984263bc 249DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
ca59556a 250DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
984263bc 251DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
ca59556a 252MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
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253
254#define EE_SET(x) \
ca59556a 255 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
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256
257#define EE_CLR(x) \
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258 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
259
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260/*
261 * Send a read command and address to the EEPROM, check for ACK.
262 */
ca59556a
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263static void
264rl_eeprom_putbyte(struct rl_softc *sc, int addr)
984263bc 265{
ca59556a 266 int d, i;
984263bc 267
ca59556a 268 d = addr | sc->rl_eecmd_read;
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269
270 /*
271 * Feed in each bit and strobe the clock.
272 */
273 for (i = 0x400; i; i >>= 1) {
ca59556a 274 if (d & i)
984263bc 275 EE_SET(RL_EE_DATAIN);
ca59556a 276 else
984263bc 277 EE_CLR(RL_EE_DATAIN);
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278 DELAY(100);
279 EE_SET(RL_EE_CLK);
280 DELAY(150);
281 EE_CLR(RL_EE_CLK);
282 DELAY(100);
283 }
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284}
285
286/*
287 * Read a word of data stored in the EEPROM at address 'addr.'
288 */
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289static void
290rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
984263bc 291{
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292 int i;
293 uint16_t word = 0;
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294
295 /* Enter EEPROM access mode. */
296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
297
298 /*
299 * Send address of word we want to read.
300 */
301 rl_eeprom_putbyte(sc, addr);
302
303 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
304
305 /*
306 * Start reading bits from EEPROM.
307 */
308 for (i = 0x8000; i; i >>= 1) {
309 EE_SET(RL_EE_CLK);
310 DELAY(100);
311 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
312 word |= i;
313 EE_CLR(RL_EE_CLK);
314 DELAY(100);
315 }
316
317 /* Turn off EEPROM access mode. */
318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
319
320 *dest = word;
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321}
322
323/*
324 * Read a sequence of words from the EEPROM.
325 */
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326static void
327rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 328{
ca59556a
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329 int i;
330 u_int16_t word = 0, *ptr;
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331
332 for (i = 0; i < cnt; i++) {
333 rl_eeprom_getword(sc, off + i, &word);
334 ptr = (u_int16_t *)(dest + (i * 2));
335 if (swap)
336 *ptr = ntohs(word);
337 else
338 *ptr = word;
339 }
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340}
341
342
343/*
344 * MII access routines are provided for the 8129, which
345 * doesn't have a built-in PHY. For the 8139, we fake things
346 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
347 * direct access PHY registers.
348 */
ca59556a
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349#define MII_SET(x) \
350 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
984263bc 351
ca59556a
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352#define MII_CLR(x) \
353 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
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354
355/*
356 * Sync the PHYs by setting data bit and strobing the clock 32 times.
357 */
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358static void
359rl_mii_sync(struct rl_softc *sc)
984263bc 360{
ca59556a 361 int i;
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362
363 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
364
365 for (i = 0; i < 32; i++) {
366 MII_SET(RL_MII_CLK);
367 DELAY(1);
368 MII_CLR(RL_MII_CLK);
369 DELAY(1);
370 }
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371}
372
373/*
374 * Clock a series of bits through the MII.
375 */
ca59556a
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376static void
377rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
984263bc 378{
ca59556a 379 int i;
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380
381 MII_CLR(RL_MII_CLK);
382
383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
ca59556a 384 if (bits & i)
984263bc 385 MII_SET(RL_MII_DATAOUT);
ca59556a 386 else
984263bc 387 MII_CLR(RL_MII_DATAOUT);
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388 DELAY(1);
389 MII_CLR(RL_MII_CLK);
390 DELAY(1);
391 MII_SET(RL_MII_CLK);
392 }
393}
394
395/*
396 * Read an PHY register through the MII.
397 */
ca59556a
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398static int
399rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 400{
a3fbe745 401 int ack, i;
984263bc 402
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403 /*
404 * Set up frame for RX.
405 */
406 frame->mii_stdelim = RL_MII_STARTDELIM;
407 frame->mii_opcode = RL_MII_READOP;
408 frame->mii_turnaround = 0;
409 frame->mii_data = 0;
410
411 CSR_WRITE_2(sc, RL_MII, 0);
412
413 /*
414 * Turn on data xmit.
415 */
416 MII_SET(RL_MII_DIR);
417
418 rl_mii_sync(sc);
419
420 /*
421 * Send command/address info.
422 */
423 rl_mii_send(sc, frame->mii_stdelim, 2);
424 rl_mii_send(sc, frame->mii_opcode, 2);
425 rl_mii_send(sc, frame->mii_phyaddr, 5);
426 rl_mii_send(sc, frame->mii_regaddr, 5);
427
428 /* Idle bit */
429 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
430 DELAY(1);
431 MII_SET(RL_MII_CLK);
432 DELAY(1);
433
434 /* Turn off xmit. */
435 MII_CLR(RL_MII_DIR);
436
437 /* Check for ack */
438 MII_CLR(RL_MII_CLK);
439 DELAY(1);
440 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
441 MII_SET(RL_MII_CLK);
442 DELAY(1);
443
444 /*
445 * Now try reading data bits. If the ack failed, we still
446 * need to clock through 16 cycles to keep the PHY(s) in sync.
447 */
448 if (ack) {
449 for(i = 0; i < 16; i++) {
450 MII_CLR(RL_MII_CLK);
451 DELAY(1);
452 MII_SET(RL_MII_CLK);
453 DELAY(1);
454 }
ca59556a
JS
455 } else {
456 for (i = 0x8000; i; i >>= 1) {
457 MII_CLR(RL_MII_CLK);
458 DELAY(1);
459 if (!ack) {
460 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
461 frame->mii_data |= i;
462 DELAY(1);
463 }
464 MII_SET(RL_MII_CLK);
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465 DELAY(1);
466 }
984263bc
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467 }
468
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469 MII_CLR(RL_MII_CLK);
470 DELAY(1);
471 MII_SET(RL_MII_CLK);
472 DELAY(1);
473
ca59556a 474 return(ack ? 1 : 0);
984263bc
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475}
476
477/*
478 * Write to a PHY register through the MII.
479 */
ca59556a
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480static int
481rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 482{
984263bc
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483 /*
484 * Set up frame for TX.
485 */
984263bc
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486 frame->mii_stdelim = RL_MII_STARTDELIM;
487 frame->mii_opcode = RL_MII_WRITEOP;
488 frame->mii_turnaround = RL_MII_TURNAROUND;
489
490 /*
491 * Turn on data output.
492 */
493 MII_SET(RL_MII_DIR);
494
495 rl_mii_sync(sc);
496
497 rl_mii_send(sc, frame->mii_stdelim, 2);
498 rl_mii_send(sc, frame->mii_opcode, 2);
499 rl_mii_send(sc, frame->mii_phyaddr, 5);
500 rl_mii_send(sc, frame->mii_regaddr, 5);
501 rl_mii_send(sc, frame->mii_turnaround, 2);
502 rl_mii_send(sc, frame->mii_data, 16);
503
504 /* Idle bit. */
505 MII_SET(RL_MII_CLK);
506 DELAY(1);
507 MII_CLR(RL_MII_CLK);
508 DELAY(1);
509
510 /*
511 * Turn off xmit.
512 */
513 MII_CLR(RL_MII_DIR);
514
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515 return(0);
516}
517
ca59556a
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518static int
519rl_miibus_readreg(device_t dev, int phy, int reg)
984263bc 520{
ca59556a
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521 struct rl_softc *sc;
522 struct rl_mii_frame frame;
523 uint16_t rval = 0;
524 uint16_t rl8139_reg = 0;
984263bc
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525
526 sc = device_get_softc(dev);
527
528 if (sc->rl_type == RL_8139) {
529 /* Pretend the internal PHY is only at address 0 */
530 if (phy)
531 return(0);
ca59556a 532 switch (reg) {
984263bc
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533 case MII_BMCR:
534 rl8139_reg = RL_BMCR;
535 break;
536 case MII_BMSR:
537 rl8139_reg = RL_BMSR;
538 break;
539 case MII_ANAR:
540 rl8139_reg = RL_ANAR;
541 break;
542 case MII_ANER:
543 rl8139_reg = RL_ANER;
544 break;
545 case MII_ANLPAR:
546 rl8139_reg = RL_LPAR;
547 break;
548 case MII_PHYIDR1:
549 case MII_PHYIDR2:
550 return(0);
551 break;
552 /*
553 * Allow the rlphy driver to read the media status
554 * register. If we have a link partner which does not
555 * support NWAY, this is the register which will tell
556 * us the results of parallel detection.
557 */
558 case RL_MEDIASTAT:
559 rval = CSR_READ_1(sc, RL_MEDIASTAT);
560 return(rval);
984263bc 561 default:
ca59556a 562 device_printf(dev, "bad phy register\n");
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563 return(0);
564 }
565 rval = CSR_READ_2(sc, rl8139_reg);
566 return(rval);
567 }
568
ca59556a 569 bzero(&frame, sizeof(frame));
984263bc
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570
571 frame.mii_phyaddr = phy;
572 frame.mii_regaddr = reg;
573 rl_mii_readreg(sc, &frame);
574
575 return(frame.mii_data);
576}
577
ca59556a
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578static int
579rl_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 580{
ca59556a
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581 struct rl_softc *sc;
582 struct rl_mii_frame frame;
583 u_int16_t rl8139_reg = 0;
984263bc
MD
584
585 sc = device_get_softc(dev);
586
587 if (sc->rl_type == RL_8139) {
588 /* Pretend the internal PHY is only at address 0 */
589 if (phy)
590 return(0);
ca59556a 591 switch (reg) {
984263bc
MD
592 case MII_BMCR:
593 rl8139_reg = RL_BMCR;
594 break;
595 case MII_BMSR:
596 rl8139_reg = RL_BMSR;
597 break;
598 case MII_ANAR:
599 rl8139_reg = RL_ANAR;
600 break;
601 case MII_ANER:
602 rl8139_reg = RL_ANER;
603 break;
604 case MII_ANLPAR:
605 rl8139_reg = RL_LPAR;
606 break;
607 case MII_PHYIDR1:
608 case MII_PHYIDR2:
609 return(0);
984263bc 610 default:
ca59556a 611 device_printf(dev, "bad phy register\n");
984263bc
MD
612 return(0);
613 }
614 CSR_WRITE_2(sc, rl8139_reg, data);
615 return(0);
616 }
617
ca59556a 618 bzero(&frame, sizeof(frame));
984263bc
MD
619
620 frame.mii_phyaddr = phy;
621 frame.mii_regaddr = reg;
622 frame.mii_data = data;
623
624 rl_mii_writereg(sc, &frame);
625
626 return(0);
627}
628
ca59556a
JS
629static void
630rl_miibus_statchg(device_t dev)
984263bc 631{
984263bc
MD
632}
633
634/*
635 * Program the 64-bit multicast hash filter.
636 */
ca59556a
JS
637static void
638rl_setmulti(struct rl_softc *sc)
984263bc 639{
ca59556a
JS
640 struct ifnet *ifp;
641 int h = 0;
642 uint32_t hashes[2] = { 0, 0 };
643 struct ifmultiaddr *ifma;
644 uint32_t rxfilt;
645 int mcnt = 0;
984263bc
MD
646
647 ifp = &sc->arpcom.ac_if;
648
649 rxfilt = CSR_READ_4(sc, RL_RXCFG);
650
651 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
652 rxfilt |= RL_RXCFG_RX_MULTI;
653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
656 return;
657 }
658
659 /* first, zot all the existing hash bits */
660 CSR_WRITE_4(sc, RL_MAR0, 0);
661 CSR_WRITE_4(sc, RL_MAR4, 0);
662
663 /* now program new ones */
441d34b2 664 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
665 if (ifma->ifma_addr->sa_family != AF_LINK)
666 continue;
ca59556a
JS
667 h = ether_crc32_be(
668 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
527b7d96 669 ETHER_ADDR_LEN) >> 26;
984263bc
MD
670 if (h < 32)
671 hashes[0] |= (1 << h);
672 else
673 hashes[1] |= (1 << (h - 32));
674 mcnt++;
675 }
676
677 if (mcnt)
678 rxfilt |= RL_RXCFG_RX_MULTI;
679 else
680 rxfilt &= ~RL_RXCFG_RX_MULTI;
681
682 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
683 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
684 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
984263bc
MD
685}
686
ca59556a
JS
687static void
688rl_reset(struct rl_softc *sc)
984263bc 689{
ca59556a 690 int i;
984263bc
MD
691
692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
693
694 for (i = 0; i < RL_TIMEOUT; i++) {
695 DELAY(10);
696 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
697 break;
698 }
699 if (i == RL_TIMEOUT)
ca59556a 700 device_printf(sc->rl_dev, "reset never completed!\n");
984263bc
MD
701}
702
703/*
704 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
705 * IDs against our list and return a device name if we find a match.
49c37738
JS
706 *
707 * Return with a value < 0 to give re(4) a change to attach.
984263bc 708 */
ca59556a
JS
709static int
710rl_probe(device_t dev)
984263bc 711{
ca59556a
JS
712 struct rl_type *t;
713 uint16_t product = pci_get_device(dev);
714 uint16_t vendor = pci_get_vendor(dev);
984263bc 715
49c37738 716 for (t = rl_devs; t->rl_name != NULL; t++) {
ca59556a
JS
717 if (vendor == t->rl_vid && product == t->rl_did) {
718 device_set_desc(dev, t->rl_name);
49c37738 719 return(-100);
ca59556a 720 }
984263bc
MD
721 }
722
723 return(ENXIO);
724}
725
726/*
727 * Attach the interface. Allocate softc structures, do ifmedia
728 * setup and ethernet/BPF attach.
729 */
ca59556a
JS
730static int
731rl_attach(device_t dev)
984263bc 732{
ca59556a
JS
733 uint8_t eaddr[ETHER_ADDR_LEN];
734 uint16_t as[3];
735 struct rl_softc *sc;
736 struct ifnet *ifp;
737 uint16_t rl_did = 0;
738 int error = 0, rid, i;
984263bc
MD
739
740 sc = device_get_softc(dev);
ca59556a 741 sc->rl_dev = dev;
984263bc
MD
742
743 /*
744 * Handle power management nonsense.
745 */
746
ca59556a
JS
747 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
748 uint32_t iobase, membase, irq;
984263bc 749
ca59556a
JS
750 /* Save important PCI config data. */
751 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
752 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
753 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
984263bc 754
ca59556a 755 /* Reset the power state. */
c045389b 756 device_printf(dev, "chip is in D%d power mode "
ca59556a
JS
757 "-- setting to D0\n", pci_get_powerstate(dev));
758 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
984263bc 759
ca59556a
JS
760 /* Restore PCI config data. */
761 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
762 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
763 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
984263bc
MD
764 }
765
ca59556a 766 pci_enable_busmaster(dev);
984263bc
MD
767
768 rid = RL_RID;
4e6d744d 769 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
984263bc
MD
770
771 if (sc->rl_res == NULL) {
ca59556a 772 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
773 error = ENXIO;
774 goto fail;
775 }
776
777 sc->rl_btag = rman_get_bustag(sc->rl_res);
778 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
779
780 rid = 0;
ca59556a
JS
781 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
782 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
783
784 if (sc->rl_irq == NULL) {
ca59556a 785 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
786 error = ENXIO;
787 goto fail;
788 }
789
b3a81bea 790 callout_init(&sc->rl_stat_timer);
984263bc
MD
791
792 /* Reset the adapter. */
793 rl_reset(sc);
794
ca59556a
JS
795 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
796 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
797 if (rl_did != 0x8129)
798 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
799
984263bc
MD
800 /*
801 * Get station address from the EEPROM.
802 */
ca59556a
JS
803 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
804 for (i = 0; i < 3; i++) {
805 eaddr[(i * 2) + 0] = as[i] & 0xff;
806 eaddr[(i * 2) + 1] = as[i] >> 8;
807 }
984263bc
MD
808
809 /*
810 * Now read the exact device type from the EEPROM to find
811 * out if it's an 8129 or 8139.
812 */
813 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
814
598e5ef7
SW
815 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 ||
816 rl_did == PCI_PRODUCT_ACCTON_MPX5030 ||
817 rl_did == PCI_PRODUCT_DELTA_8139 ||
818 rl_did == PCI_PRODUCT_ADDTRON_8139 ||
819 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS ||
820 rl_did == PCI_PRODUCT_REALTEK_RT8139B ||
821 rl_did == PCI_PRODUCT_DLINK_DFE690TXD ||
822 rl_did == PCI_PRODUCT_COREGA_CB_TXD ||
823 rl_did == PCI_PRODUCT_COREGA_2CB_TXD ||
d9893ddf 824 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) {
984263bc 825 sc->rl_type = RL_8139;
d9893ddf 826 } else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) {
984263bc 827 sc->rl_type = RL_8129;
d9893ddf 828 } else {
ca59556a 829 device_printf(dev, "unknown device ID: %x\n", rl_did);
d9893ddf
SZ
830 sc->rl_type = RL_8139;
831 /*
832 * Read RL_IDR register to get ethernet address as accessing
833 * EEPROM may not extract correct address.
834 */
835 for (i = 0; i < ETHER_ADDR_LEN; i++)
836 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
984263bc
MD
837 }
838
8705209e
SZ
839 error = rl_dma_alloc(sc);
840 if (error)
984263bc 841 goto fail;
984263bc
MD
842
843 /* Do MII setup */
ca59556a
JS
844 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
845 rl_ifmedia_sts)) {
846 device_printf(dev, "MII without any phy!\n");
984263bc
MD
847 error = ENXIO;
848 goto fail;
849 }
850
851 ifp = &sc->arpcom.ac_if;
852 ifp->if_softc = sc;
ca59556a 853 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
854 ifp->if_mtu = ETHERMTU;
855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
856 ifp->if_ioctl = rl_ioctl;
984263bc
MD
857 ifp->if_start = rl_start;
858 ifp->if_watchdog = rl_watchdog;
859 ifp->if_init = rl_init;
860 ifp->if_baudrate = 10000000;
ca59556a
JS
861 ifp->if_capabilities = IFCAP_VLAN_MTU;
862#ifdef DEVICE_POLLING
9c095379 863 ifp->if_poll = rl_poll;
ca59556a 864#endif
c2ffa639
JS
865 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
866 ifq_set_ready(&ifp->if_snd);
984263bc
MD
867
868 /*
869 * Call MI attach routine.
870 */
78195a76 871 ether_ifattach(ifp, eaddr, NULL);
984263bc 872
95893fe4 873 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr,
78195a76 874 sc, &sc->rl_intrhand, ifp->if_serializer);
ca59556a
JS
875
876 if (error) {
877 device_printf(dev, "couldn't set up irq\n");
878 ether_ifdetach(ifp);
879 goto fail;
880 }
881
9db4b353
SZ
882 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->rl_irq));
883 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
884
ca59556a
JS
885 return(0);
886
984263bc 887fail:
ca59556a 888 rl_detach(dev);
984263bc
MD
889 return(error);
890}
891
ca59556a
JS
892static int
893rl_detach(device_t dev)
984263bc 894{
ca59556a
JS
895 struct rl_softc *sc;
896 struct ifnet *ifp;
984263bc
MD
897
898 sc = device_get_softc(dev);
899 ifp = &sc->arpcom.ac_if;
900
ca59556a 901 if (device_is_attached(dev)) {
cdf89432 902 lwkt_serialize_enter(ifp->if_serializer);
ca59556a 903 rl_stop(sc);
cdf89432
SZ
904 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
905 lwkt_serialize_exit(ifp->if_serializer);
906
ca59556a
JS
907 ether_ifdetach(ifp);
908 }
984263bc 909
ca59556a
JS
910 if (sc->rl_miibus)
911 device_delete_child(dev, sc->rl_miibus);
984263bc 912 bus_generic_detach(dev);
984263bc 913
ca59556a
JS
914 if (sc->rl_irq)
915 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
916 if (sc->rl_res)
917 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
984263bc 918
8705209e 919 rl_dma_free(sc);
984263bc
MD
920
921 return(0);
922}
923
924/*
925 * Initialize the transmit descriptors.
926 */
ca59556a
JS
927static void
928rl_list_tx_init(struct rl_softc *sc)
984263bc 929{
ca59556a
JS
930 struct rl_chain_data *cd;
931 int i;
984263bc
MD
932
933 cd = &sc->rl_cdata;
934 for (i = 0; i < RL_TX_LIST_CNT; i++) {
935 cd->rl_tx_chain[i] = NULL;
8705209e
SZ
936 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
937 0x0000000);
984263bc
MD
938 }
939
940 sc->rl_cdata.cur_tx = 0;
941 sc->rl_cdata.last_tx = 0;
984263bc
MD
942}
943
944/*
945 * A frame has been uploaded: pass the resulting mbuf chain up to
946 * the higher level protocols.
947 *
948 * You know there's something wrong with a PCI bus-master chip design
949 * when you have to use m_devget().
950 *
951 * The receive operation is badly documented in the datasheet, so I'll
952 * attempt to document it here. The driver provides a buffer area and
953 * places its base address in the RX buffer start address register.
954 * The chip then begins copying frames into the RX buffer. Each frame
ca59556a 955 * is preceded by a 32-bit RX status word which specifies the length
984263bc
MD
956 * of the frame and certain other status bits. Each frame (starting with
957 * the status word) is also 32-bit aligned. The frame length is in the
958 * first 16 bits of the status word; the lower 15 bits correspond with
959 * the 'rx status register' mentioned in the datasheet.
960 *
961 * Note: to make the Alpha happy, the frame payload needs to be aligned
962 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
963 * the ring buffer starting at an address two bytes before the actual
964 * data location. We can then shave off the first two bytes using m_adj().
965 * The reason we do this is because m_devget() doesn't let us specify an
966 * offset into the mbuf storage space, so we have to artificially create
967 * one. The ring is allocated in such a way that there are a few unused
968 * bytes of space preceecing it so that it will be safe for us to do the
969 * 2-byte backstep even if reading from the ring at offset 0.
970 */
ca59556a
JS
971static void
972rl_rxeof(struct rl_softc *sc)
984263bc 973{
ca59556a
JS
974 struct mbuf *m;
975 struct ifnet *ifp;
976 int total_len = 0;
977 uint32_t rxstat;
978 caddr_t rxbufpos;
979 int wrap = 0;
980 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
984263bc
MD
981
982 ifp = &sc->arpcom.ac_if;
983
984 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
985
986 /* Do not try to read past this point. */
987 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
988
989 if (limit < cur_rx)
990 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
991 else
992 max_bytes = limit - cur_rx;
993
994 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
995#ifdef DEVICE_POLLING
46f25451 996 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
997 if (sc->rxcycles <= 0)
998 break;
999 sc->rxcycles--;
1000 }
1001#endif /* DEVICE_POLLING */
1002 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
ca59556a 1003 rxstat = le32toh(*(uint32_t *)rxbufpos);
984263bc
MD
1004
1005 /*
1006 * Here's a totally undocumented fact for you. When the
1007 * RealTek chip is in the process of copying a packet into
1008 * RAM for you, the length will be 0xfff0. If you spot a
1009 * packet header with this value, you need to stop. The
1010 * datasheet makes absolutely no mention of this and
1011 * RealTek should be shot for this.
1012 */
ca59556a 1013 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
984263bc
MD
1014 break;
1015
ca59556a 1016 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
984263bc
MD
1017 ifp->if_ierrors++;
1018 rl_init(sc);
1019 return;
1020 }
1021
1022 /* No errors; receive the packet. */
1023 total_len = rxstat >> 16;
1024 rx_bytes += total_len + 4;
1025
1026 /*
1027 * XXX The RealTek chip includes the CRC with every
1028 * received frame, and there's no way to turn this
1029 * behavior off (at least, I can't find anything in
1030 * the manual that explains how to do it) so we have
1031 * to trim off the CRC manually.
1032 */
1033 total_len -= ETHER_CRC_LEN;
1034
1035 /*
1036 * Avoid trying to read more bytes than we know
1037 * the chip has prepared for us.
1038 */
1039 if (rx_bytes > max_bytes)
1040 break;
1041
1042 rxbufpos = sc->rl_cdata.rl_rx_buf +
ca59556a 1043 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
984263bc
MD
1044
1045 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1046 rxbufpos = sc->rl_cdata.rl_rx_buf;
1047
1048 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1049
1050 if (total_len > wrap) {
1051 /*
1052 * Fool m_devget() into thinking we want to copy
1053 * the whole buffer so we don't end up fragmenting
1054 * the data.
1055 */
1056 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
b4877f07 1057 wrap + RL_ETHER_ALIGN, 0, ifp, NULL);
984263bc
MD
1058 if (m == NULL) {
1059 ifp->if_ierrors++;
1060 } else {
1061 m_adj(m, RL_ETHER_ALIGN);
1062 m_copyback(m, wrap, total_len - wrap,
1063 sc->rl_cdata.rl_rx_buf);
1064 }
1065 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1066 } else {
1067 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1068 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1069 if (m == NULL) {
1070 ifp->if_ierrors++;
1071 } else
1072 m_adj(m, RL_ETHER_ALIGN);
1073 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1074 }
1075
1076 /*
1077 * Round up to 32-bit boundary.
1078 */
1079 cur_rx = (cur_rx + 3) & ~3;
1080 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1081
1082 if (m == NULL)
1083 continue;
1084
984263bc
MD
1085 ifp->if_ipackets++;
1086
78195a76 1087 ifp->if_input(ifp, m);
984263bc 1088 }
984263bc
MD
1089}
1090
1091/*
1092 * A frame was downloaded to the chip. It's safe for us to clean up
1093 * the list buffers.
1094 */
ca59556a
JS
1095static void
1096rl_txeof(struct rl_softc *sc)
984263bc 1097{
ca59556a
JS
1098 struct ifnet *ifp;
1099 uint32_t txstat;
984263bc
MD
1100
1101 ifp = &sc->arpcom.ac_if;
1102
1103 /*
1104 * Go through our tx list and free mbufs for those
1105 * frames that have been uploaded.
1106 */
1107 do {
ca59556a
JS
1108 if (RL_LAST_TXMBUF(sc) == NULL)
1109 break;
984263bc 1110 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
ca59556a
JS
1111 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1112 RL_TXSTAT_TXABRT)) == 0)
984263bc
MD
1113 break;
1114
1115 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1116
8705209e 1117 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
ca59556a
JS
1118 m_freem(RL_LAST_TXMBUF(sc));
1119 RL_LAST_TXMBUF(sc) = NULL;
ef042148 1120 RL_INC(sc->rl_cdata.last_tx);
ca59556a 1121
ef042148
JS
1122 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1123 sc->rl_txthresh += 32;
1124 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1125 sc->rl_txthresh = RL_TX_THRESH_MAX;
1126 }
ca59556a 1127
ef042148
JS
1128 if (txstat & RL_TXSTAT_TX_OK) {
1129 ifp->if_opackets++;
1130 } else {
984263bc 1131 ifp->if_oerrors++;
ef042148 1132 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
984263bc 1133 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
984263bc 1134 }
984263bc
MD
1135 ifp->if_flags &= ~IFF_OACTIVE;
1136 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1137
ca59556a
JS
1138 if (RL_LAST_TXMBUF(sc) == NULL)
1139 ifp->if_timer = 0;
1140 else if (ifp->if_timer == 0)
1141 ifp->if_timer = 5;
984263bc
MD
1142}
1143
ca59556a
JS
1144static void
1145rl_tick(void *xsc)
984263bc 1146{
ca59556a
JS
1147 struct rl_softc *sc = xsc;
1148 struct mii_data *mii;
984263bc 1149
78195a76 1150 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc 1151
984263bc 1152 mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1153 mii_tick(mii);
1154
b3a81bea 1155 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
a3fbe745 1156
78195a76 1157 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1158}
1159
1160#ifdef DEVICE_POLLING
984263bc
MD
1161
1162static void
ca59556a 1163rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
984263bc
MD
1164{
1165 struct rl_softc *sc = ifp->if_softc;
1166
9c095379
MD
1167 switch(cmd) {
1168 case POLL_REGISTER:
1169 /* disable interrupts */
1170 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1171 break;
1172 case POLL_DEREGISTER:
1173 /* enable interrupts */
ca59556a 1174 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
9c095379
MD
1175 break;
1176 default:
1177 sc->rxcycles = count;
1178 rl_rxeof(sc);
1179 rl_txeof(sc);
1180 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1181 if_devstart(ifp);
9c095379
MD
1182
1183 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1184 uint16_t status;
1185
1186 status = CSR_READ_2(sc, RL_ISR);
1187 if (status == 0xffff)
1188 return;
1189 if (status)
1190 CSR_WRITE_2(sc, RL_ISR, status);
1191
1192 /*
1193 * XXX check behaviour on receiver stalls.
1194 */
984263bc 1195
9c095379
MD
1196 if (status & RL_ISR_SYSTEM_ERR) {
1197 rl_reset(sc);
1198 rl_init(sc);
1199 }
984263bc 1200 }
9c095379 1201 break;
984263bc
MD
1202 }
1203}
1204#endif /* DEVICE_POLLING */
1205
ca59556a
JS
1206static void
1207rl_intr(void *arg)
984263bc 1208{
ca59556a
JS
1209 struct rl_softc *sc;
1210 struct ifnet *ifp;
1211 uint16_t status;
984263bc
MD
1212
1213 sc = arg;
1214
ca59556a 1215 if (sc->suspended)
984263bc 1216 return;
984263bc
MD
1217
1218 ifp = &sc->arpcom.ac_if;
984263bc
MD
1219
1220 for (;;) {
984263bc 1221 status = CSR_READ_2(sc, RL_ISR);
ca59556a
JS
1222 /* If the card has gone away, the read returns 0xffff. */
1223 if (status == 0xffff)
1224 break;
1225
1226 if (status != 0)
984263bc
MD
1227 CSR_WRITE_2(sc, RL_ISR, status);
1228
1229 if ((status & RL_INTRS) == 0)
1230 break;
1231
1232 if (status & RL_ISR_RX_OK)
1233 rl_rxeof(sc);
1234
1235 if (status & RL_ISR_RX_ERR)
1236 rl_rxeof(sc);
1237
1238 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1239 rl_txeof(sc);
1240
1241 if (status & RL_ISR_SYSTEM_ERR) {
1242 rl_reset(sc);
1243 rl_init(sc);
1244 }
1245
1246 }
ca59556a 1247
c2ffa639 1248 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1249 if_devstart(ifp);
984263bc
MD
1250}
1251
1252/*
1253 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1254 * pointers to the fragment pointers.
1255 */
ca59556a
JS
1256static int
1257rl_encap(struct rl_softc *sc, struct mbuf *m_head)
984263bc 1258{
ca59556a 1259 struct mbuf *m_new = NULL;
8705209e
SZ
1260 bus_dma_segment_t seg;
1261 int nseg, error;
984263bc
MD
1262
1263 /*
1264 * The RealTek is brain damaged and wants longword-aligned
1265 * TX buffers, plus we can only have one fragment buffer
8705209e 1266 * per packet. We have to copy pretty much all the time.
984263bc 1267 */
ca59556a 1268 m_new = m_defrag(m_head, MB_DONTWAIT);
ca59556a
JS
1269 if (m_new == NULL) {
1270 m_freem(m_head);
8705209e 1271 return ENOBUFS;
984263bc 1272 }
984263bc
MD
1273 m_head = m_new;
1274
1275 /* Pad frames to at least 60 bytes. */
1276 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
8705209e
SZ
1277 error = m_devpad(m_head, RL_MIN_FRAMELEN);
1278 if (error) {
1279 m_freem(m_head);
1280 return error;
1281 }
984263bc
MD
1282 }
1283
8705209e
SZ
1284 /* Extract physical address. */
1285 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag,
1286 RL_CUR_DMAMAP(sc), m_head,
1287 &seg, 1, &nseg, BUS_DMA_NOWAIT);
1288 if (error) {
1289 m_freem(m_head);
1290 return error;
1291 }
984263bc 1292
8705209e
SZ
1293 /* Sync the loaded TX buffer. */
1294 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1295 BUS_DMASYNC_PREWRITE);
1296
1297 /* Transmit */
1298 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr);
1299 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1300 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len);
1301
1302 RL_CUR_TXMBUF(sc) = m_head;
1303 return 0;
984263bc
MD
1304}
1305
1306/*
1307 * Main transmit routine.
1308 */
1309
ca59556a
JS
1310static void
1311rl_start(struct ifnet *ifp)
984263bc 1312{
9db4b353 1313 struct rl_softc *sc = ifp->if_softc;
ca59556a 1314 struct mbuf *m_head = NULL;
984263bc 1315
9db4b353
SZ
1316 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1317 return;
984263bc 1318
9db4b353 1319 while (RL_CUR_TXMBUF(sc) == NULL) {
d2c71fa0 1320 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1321 if (m_head == NULL)
1322 break;
1323
ca59556a 1324 if (rl_encap(sc, m_head))
8705209e 1325 continue;
984263bc
MD
1326
1327 /*
1328 * If there's a BPF listener, bounce a copy of this frame
1329 * to him.
1330 */
ca59556a 1331 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
984263bc 1332
984263bc 1333 RL_INC(sc->rl_cdata.cur_tx);
ca59556a
JS
1334
1335 /*
1336 * Set a timeout in case the chip goes out to lunch.
1337 */
1338 ifp->if_timer = 5;
984263bc
MD
1339 }
1340
1341 /*
1342 * We broke out of the loop because all our TX slots are
1343 * full. Mark the NIC as busy until it drains some of the
1344 * packets from the queue.
1345 */
1346 if (RL_CUR_TXMBUF(sc) != NULL)
1347 ifp->if_flags |= IFF_OACTIVE;
984263bc
MD
1348}
1349
ca59556a
JS
1350static void
1351rl_init(void *xsc)
984263bc 1352{
ca59556a
JS
1353 struct rl_softc *sc = xsc;
1354 struct ifnet *ifp = &sc->arpcom.ac_if;
1355 struct mii_data *mii;
ca59556a 1356 uint32_t rxcfg = 0;
984263bc 1357
984263bc
MD
1358 mii = device_get_softc(sc->rl_miibus);
1359
1360 /*
1361 * Cancel pending I/O and free all RX/TX buffers.
1362 */
1363 rl_stop(sc);
1364
ca59556a
JS
1365 /*
1366 * Init our MAC address. Even though the chipset documentation
1367 * doesn't mention it, we need to enter "Config register write enable"
1368 * mode to modify the ID registers.
1369 */
1370 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1371 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1372 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1373 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1374 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1375 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
984263bc
MD
1376
1377 /* Init the RX buffer pointer register. */
8705209e 1378 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr);
984263bc
MD
1379
1380 /* Init TX descriptors. */
1381 rl_list_tx_init(sc);
1382
1383 /*
1384 * Enable transmit and receive.
1385 */
1386 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1387
1388 /*
1389 * Set the initial TX and RX configuration.
1390 */
1391 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1392 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1393
1394 /* Set the individual bit to receive frames for this host only. */
1395 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1396 rxcfg |= RL_RXCFG_RX_INDIV;
1397
1398 /* If we want promiscuous mode, set the allframes bit. */
1399 if (ifp->if_flags & IFF_PROMISC) {
1400 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1401 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1402 } else {
1403 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1404 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1405 }
1406
1407 /*
1408 * Set capture broadcast bit to capture broadcast frames.
1409 */
1410 if (ifp->if_flags & IFF_BROADCAST) {
1411 rxcfg |= RL_RXCFG_RX_BROAD;
1412 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1413 } else {
1414 rxcfg &= ~RL_RXCFG_RX_BROAD;
1415 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1416 }
1417
1418 /*
1419 * Program the multicast filter, if necessary.
1420 */
1421 rl_setmulti(sc);
1422
1423#ifdef DEVICE_POLLING
1424 /*
1425 * Only enable interrupts if we are polling, keep them off otherwise.
1426 */
46f25451 1427 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1428 CSR_WRITE_2(sc, RL_IMR, 0);
1429 else
1430#endif /* DEVICE_POLLING */
1431 /*
1432 * Enable interrupts.
1433 */
1434 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1435
1436 /* Set initial TX threshold */
1437 sc->rl_txthresh = RL_TX_THRESH_INIT;
1438
1439 /* Start RX/TX process. */
1440 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1441
1442 /* Enable receiver and transmitter. */
1443 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1444
1445 mii_mediachg(mii);
1446
1447 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1448
1449 ifp->if_flags |= IFF_RUNNING;
1450 ifp->if_flags &= ~IFF_OACTIVE;
1451
b3a81bea 1452 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
984263bc
MD
1453}
1454
1455/*
1456 * Set media options.
1457 */
ca59556a
JS
1458static int
1459rl_ifmedia_upd(struct ifnet *ifp)
984263bc 1460{
ca59556a
JS
1461 struct rl_softc *sc;
1462 struct mii_data *mii;
984263bc
MD
1463
1464 sc = ifp->if_softc;
1465 mii = device_get_softc(sc->rl_miibus);
1466 mii_mediachg(mii);
1467
1468 return(0);
1469}
1470
1471/*
1472 * Report current media status.
1473 */
ca59556a
JS
1474static void
1475rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1476{
ca59556a
JS
1477 struct rl_softc *sc = ifp->if_softc;
1478 struct mii_data *mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1479
1480 mii_pollstat(mii);
1481 ifmr->ifm_active = mii->mii_media_active;
1482 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1483}
1484
ca59556a
JS
1485static int
1486rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1487{
ca59556a
JS
1488 struct rl_softc *sc = ifp->if_softc;
1489 struct ifreq *ifr = (struct ifreq *) data;
1490 struct mii_data *mii;
a3fbe745 1491 int error = 0;
984263bc 1492
ca59556a 1493 switch (command) {
984263bc
MD
1494 case SIOCSIFFLAGS:
1495 if (ifp->if_flags & IFF_UP) {
1496 rl_init(sc);
1497 } else {
1498 if (ifp->if_flags & IFF_RUNNING)
1499 rl_stop(sc);
1500 }
1501 error = 0;
1502 break;
1503 case SIOCADDMULTI:
1504 case SIOCDELMULTI:
1505 rl_setmulti(sc);
1506 error = 0;
1507 break;
1508 case SIOCGIFMEDIA:
1509 case SIOCSIFMEDIA:
1510 mii = device_get_softc(sc->rl_miibus);
1511 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1512 break;
ca59556a 1513 case SIOCSIFCAP:
ca59556a 1514 break;
984263bc 1515 default:
ca59556a 1516 error = ether_ioctl(ifp, command, data);
984263bc
MD
1517 break;
1518 }
1519
984263bc
MD
1520 return(error);
1521}
1522
ca59556a
JS
1523static void
1524rl_watchdog(struct ifnet *ifp)
984263bc 1525{
ca59556a 1526 struct rl_softc *sc = ifp->if_softc;
984263bc 1527
ca59556a 1528 device_printf(sc->rl_dev, "watchdog timeout\n");
a3fbe745 1529
984263bc
MD
1530 ifp->if_oerrors++;
1531
1532 rl_txeof(sc);
1533 rl_rxeof(sc);
1534 rl_init(sc);
984263bc
MD
1535}
1536
1537/*
1538 * Stop the adapter and free any mbufs allocated to the
1539 * RX and TX lists.
1540 */
ca59556a
JS
1541static void
1542rl_stop(struct rl_softc *sc)
984263bc 1543{
ca59556a
JS
1544 struct ifnet *ifp = &sc->arpcom.ac_if;
1545 int i;
984263bc 1546
984263bc
MD
1547 ifp->if_timer = 0;
1548
b3a81bea 1549 callout_stop(&sc->rl_stat_timer);
984263bc 1550 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1551
1552 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1553 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1554
1555 /*
1556 * Free the TX list buffers.
1557 */
1558 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1559 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
8705209e 1560 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
ca59556a 1561 sc->rl_cdata.rl_tx_dmamap[i]);
984263bc
MD
1562 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1563 sc->rl_cdata.rl_tx_chain[i] = NULL;
ca59556a
JS
1564 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1565 0x0000000);
984263bc
MD
1566 }
1567 }
984263bc
MD
1568}
1569
1570/*
1571 * Stop all chip I/O so that the kernel's probe routines don't
1572 * get confused by errant DMAs when rebooting.
1573 */
ca59556a
JS
1574static void
1575rl_shutdown(device_t dev)
984263bc 1576{
ca59556a 1577 struct rl_softc *sc;
984263bc
MD
1578
1579 sc = device_get_softc(dev);
78195a76 1580 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc 1581 rl_stop(sc);
78195a76 1582 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1583}
1584
1585/*
1586 * Device suspend routine. Stop the interface and save some PCI
1587 * settings in case the BIOS doesn't restore them properly on
1588 * resume.
1589 */
ca59556a
JS
1590static int
1591rl_suspend(device_t dev)
984263bc 1592{
ca59556a
JS
1593 struct rl_softc *sc = device_get_softc(dev);
1594 int i;
984263bc 1595
78195a76 1596 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1597 rl_stop(sc);
1598
1599 for (i = 0; i < 5; i++)
ca59556a 1600 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
984263bc
MD
1601 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1602 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1603 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1604 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1605
1606 sc->suspended = 1;
1607
78195a76 1608 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1609 return (0);
1610}
1611
1612/*
1613 * Device resume routine. Restore some PCI settings in case the BIOS
1614 * doesn't, re-enable busmastering, and restart the interface if
1615 * appropriate.
1616 */
7b9f668c
SW
1617static int
1618rl_resume(device_t dev)
984263bc 1619{
ca59556a
JS
1620 struct rl_softc *sc = device_get_softc(dev);
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
3d0f5f54 1622 int i;
984263bc 1623
78195a76
MD
1624 lwkt_serialize_enter(ifp->if_serializer);
1625
984263bc
MD
1626 /* better way to do this? */
1627 for (i = 0; i < 5; i++)
ca59556a 1628 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
984263bc
MD
1629 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1630 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1631 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1632 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1633
1634 /* reenable busmastering */
1635 pci_enable_busmaster(dev);
1636 pci_enable_io(dev, RL_RES);
1637
1638 /* reinitialize interface if necessary */
1639 if (ifp->if_flags & IFF_UP)
1640 rl_init(sc);
1641
1642 sc->suspended = 0;
78195a76 1643 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1644 return (0);
1645}
8705209e
SZ
1646
1647static int
1648rl_dma_alloc(struct rl_softc *sc)
1649{
1650 bus_dmamem_t dmem;
1651 int error, i;
1652
1653 error = bus_dma_tag_create(NULL, /* parent */
1654 1, 0, /* alignment, boundary */
1655 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1656 BUS_SPACE_MAXADDR, /* highaddr */
1657 NULL, NULL, /* filter, filterarg */
1658 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1659 0, /* nsegments */
1660 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1661 0, /* flags */
1662 &sc->rl_parent_tag);
1663 if (error) {
1664 device_printf(sc->rl_dev, "can't create parent tag\n");
1665 return error;
1666 }
1667
1668 /* Allocate a chunk of coherent memory for RX */
1669 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0,
1670 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1671 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem);
1672 if (error)
1673 return error;
1674
1675 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag;
1676 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map;
1677 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr;
1678
1679 /* NOTE: Apply same adjustment to vaddr and paddr */
1680 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t);
1681 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t);
1682
1683 /*
1684 * Allocate TX mbuf's DMA tag and maps
1685 */
1686 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */
2e9bffe9 1687 RL_TXBUF_ALIGN, 0, /* alignment, boundary */
8705209e
SZ
1688 BUS_SPACE_MAXADDR, /* lowaddr */
1689 BUS_SPACE_MAXADDR, /* highaddr */
1690 NULL, NULL, /* filter, filterarg */
1691 MCLBYTES, /* maxsize */
1692 1, /* nsegments */
1693 MCLBYTES, /* maxsegsize */
1694 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
1695 BUS_DMA_ALIGNED, /* flags */
1696 &sc->rl_cdata.rl_tx_tag);
1697 if (error) {
1698 device_printf(sc->rl_dev, "can't create TX mbuf tag\n");
1699 return error;
1700 }
1701
1702 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1703 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag,
1704 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]);
1705 if (error) {
1706 int j;
1707
1708 for (j = 0; j < i; ++j) {
1709 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1710 sc->rl_cdata.rl_tx_dmamap[j]);
1711 }
1712 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1713 sc->rl_cdata.rl_tx_tag = NULL;
1714
1715 device_printf(sc->rl_dev, "can't create TX mbuf map\n");
1716 return error;
1717 }
1718 }
1719 return 0;
1720}
1721
1722static void
1723rl_dma_free(struct rl_softc *sc)
1724{
1725 if (sc->rl_cdata.rl_tx_tag != NULL) {
1726 int i;
1727
1728 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1729 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1730 sc->rl_cdata.rl_tx_dmamap[i]);
1731 }
1732 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1733 }
1734
1735 if (sc->rl_cdata.rl_rx_tag != NULL) {
1736 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1737 sc->rl_cdata.rl_rx_dmamap);
1738 /* NOTE: Use rl_rx_buf_ptr here */
1739 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1740 sc->rl_cdata.rl_rx_buf_ptr,
1741 sc->rl_cdata.rl_rx_dmamap);
1742 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1743 }
1744
1745 if (sc->rl_parent_tag)
1746 bus_dma_tag_destroy(sc->rl_parent_tag);
1747}