kernel: Move GPL'd kernel files to sys/gnu to have them all in one place.
[dragonfly.git] / sys / dev / sound / pci / csa.c
CommitLineData
558a398b 1/*-
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2 * Copyright (c) 1999 Seigo Tanimura
3 * All rights reserved.
4 *
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
1de703da 29 *
558a398b 30 * $FreeBSD: src/sys/dev/sound/pci/csa.c,v 1.33.2.1 2005/12/30 19:55:53 netchild Exp $
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31 */
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/malloc.h>
38#include <sys/module.h>
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39#include <sys/rman.h>
40#include <sys/soundcard.h>
1f7ab7c9 41
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42#include <dev/sound/pcm/sound.h>
43#include <dev/sound/chip.h>
44#include <dev/sound/pci/csareg.h>
45#include <dev/sound/pci/csavar.h>
46
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47#include <bus/pci/pcireg.h>
48#include <bus/pci/pcivar.h>
984263bc 49
b993bb87 50#include <gnu/dev/sound/pci/csaimg.h>
984263bc 51
558a398b 52SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $");
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53
54/* This is the pci device id. */
55#define CS4610_PCI_ID 0x60011013
56#define CS4614_PCI_ID 0x60031013
57#define CS4615_PCI_ID 0x60041013
58
59/* Here is the parameter structure per a device. */
60struct csa_softc {
61 device_t dev; /* device */
62 csa_res res; /* resources */
63
64 device_t pcm; /* pcm device */
65 driver_intr_t* pcmintr; /* pcm intr */
66 void *pcmintr_arg; /* pcm intr arg */
67 device_t midi; /* midi device */
68 driver_intr_t* midiintr; /* midi intr */
69 void *midiintr_arg; /* midi intr arg */
70 void *ih; /* cookie */
71
72 struct csa_card *card;
73 struct csa_bridgeinfo binfo; /* The state of this bridge. */
74};
75
76typedef struct csa_softc *sc_p;
77
78static int csa_probe(device_t dev);
79static int csa_attach(device_t dev);
80static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
4f7fe8c7 81 u_long start, u_long end, u_long count, u_int flags, int cpuid);
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82static int csa_release_resource(device_t bus, device_t child, int type, int rid,
83 struct resource *r);
84static int csa_setup_intr(device_t bus, device_t child,
85 struct resource *irq, int flags,
558a398b 86 driver_intr_t *intr, void *arg, void **cookiep);
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87static int csa_teardown_intr(device_t bus, device_t child,
88 struct resource *irq, void *cookie);
89static driver_intr_t csa_intr;
90static int csa_initialize(sc_p scp);
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91static int csa_downloadimage(csa_res *resp);
92
93static devclass_t csa_devclass;
94
95static void
96amp_none(void)
97{
98}
99
100static void
101amp_voyetra(void)
102{
103}
104
105static int
106clkrun_hack(int run)
107{
108#ifdef __i386__
109 devclass_t pci_devclass;
110 device_t *pci_devices, *pci_children, *busp, *childp;
111 int pci_count = 0, pci_childcount = 0;
112 int i, j, port;
113 u_int16_t control;
114 bus_space_tag_t btag;
115
116 if ((pci_devclass = devclass_find("pci")) == NULL) {
117 return ENXIO;
118 }
119
120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
121
122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
123 pci_childcount = 0;
124 device_get_children(*busp, &pci_children, &pci_childcount);
125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
128 /* XXX */
129 btag = I386_BUS_SPACE_IO;
130
131 control = bus_space_read_2(btag, 0x0, port);
132 control &= ~0x2000;
133 control |= run? 0 : 0x2000;
134 bus_space_write_2(btag, 0x0, port, control);
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135 kfree(pci_devices, M_TEMP);
136 kfree(pci_children, M_TEMP);
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137 return 0;
138 }
139 }
efda3bd0 140 kfree(pci_children, M_TEMP);
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141 }
142
efda3bd0 143 kfree(pci_devices, M_TEMP);
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144 return ENXIO;
145#else
146 return 0;
147#endif
148}
149
150static struct csa_card cards_4610[] = {
151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
152};
153
154static struct csa_card cards_4614[] = {
155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
164};
165
166static struct csa_card cards_4615[] = {
167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
168};
169
170static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
171
172struct card_type {
173 u_int32_t devid;
174 char *name;
175 struct csa_card *cards;
176};
177
178static struct card_type cards[] = {
179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
181 {CS4615_PCI_ID, "CS4615", cards_4615},
182 {0, NULL, NULL},
183};
184
185static struct card_type *
186csa_findcard(device_t dev)
187{
188 int i;
189
190 i = 0;
191 while (cards[i].devid != 0) {
192 if (pci_get_devid(dev) == cards[i].devid)
193 return &cards[i];
194 i++;
195 }
196 return NULL;
197}
198
199struct csa_card *
200csa_findsubcard(device_t dev)
201{
202 int i;
203 struct card_type *card;
204 struct csa_card *subcard;
205
206 card = csa_findcard(dev);
207 if (card == NULL)
208 return &nocard;
209 subcard = card->cards;
210 i = 0;
211 while (subcard[i].subvendor != 0) {
212 if (pci_get_subvendor(dev) == subcard[i].subvendor
213 && pci_get_subdevice(dev) == subcard[i].subdevice) {
214 return &subcard[i];
215 }
216 i++;
217 }
218 return &subcard[i];
219}
220
221static int
222csa_probe(device_t dev)
223{
224 struct card_type *card;
225
226 card = csa_findcard(dev);
227 if (card) {
228 device_set_desc(dev, card->name);
558a398b 229 return BUS_PROBE_DEFAULT;
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230 }
231 return ENXIO;
232}
233
234static int
235csa_attach(device_t dev)
236{
237 u_int32_t stcmd;
238 sc_p scp;
239 csa_res *resp;
240 struct sndcard_func *func;
241 int error = ENXIO;
242
243 scp = device_get_softc(dev);
244
245 /* Fill in the softc. */
246 bzero(scp, sizeof(*scp));
247 scp->dev = dev;
248
249 /* Wake up the device. */
250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
254 }
255
256 /* Allocate the resources. */
257 resp = &scp->res;
258 scp->card = csa_findsubcard(dev);
259 scp->binfo.card = scp->card;
e3869ec7 260 kprintf("csa: card is %s\n", scp->card->name);
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261 resp->io_rid = PCIR_BAR(0);
262 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
263 &resp->io_rid, RF_ACTIVE);
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264 if (resp->io == NULL)
265 return (ENXIO);
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266 resp->mem_rid = PCIR_BAR(1);
267 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
268 &resp->mem_rid, RF_ACTIVE);
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269 if (resp->mem == NULL)
270 goto err_io;
271 resp->irq_rid = 0;
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272 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
273 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
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274 if (resp->irq == NULL)
275 goto err_mem;
276
277 /* Enable interrupt. */
558a398b 278 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
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279 goto err_intr;
280#if 0
281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
283#endif
284
285 /* Initialize the chip. */
286 if (csa_initialize(scp))
287 goto err_teardown;
288
289 /* Reset the Processor. */
290 csa_resetdsp(resp);
291
292 /* Download the Processor Image to the processor. */
293 if (csa_downloadimage(resp))
294 goto err_teardown;
295
296 /* Attach the children. */
297
298 /* PCM Audio */
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299 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
300 M_WAITOK | M_ZERO);
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301 func->varinfo = &scp->binfo;
302 func->func = SCF_PCM;
303 scp->pcm = device_add_child(dev, "pcm", -1);
304 device_set_ivars(scp->pcm, func);
305
306 /* Midi Interface */
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307 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
308 M_WAITOK | M_ZERO);
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309 func->varinfo = &scp->binfo;
310 func->func = SCF_MIDI;
311 scp->midi = device_add_child(dev, "midi", -1);
312 device_set_ivars(scp->midi, func);
313
314 bus_generic_attach(dev);
315
316 return (0);
317
318err_teardown:
319 bus_teardown_intr(dev, resp->irq, scp->ih);
320err_intr:
321 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
322err_mem:
323 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
324err_io:
325 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
326 return (error);
327}
328
329static int
330csa_detach(device_t dev)
331{
332 csa_res *resp;
333 sc_p scp;
334 int err;
335
336 scp = device_get_softc(dev);
337 resp = &scp->res;
338
339 err = 0;
340 if (scp->midi != NULL)
341 err = device_delete_child(dev, scp->midi);
342 if (err)
343 return err;
344 scp->midi = NULL;
345
346 if (scp->pcm != NULL)
347 err = device_delete_child(dev, scp->pcm);
348 if (err)
349 return err;
350 scp->pcm = NULL;
351
352 bus_teardown_intr(dev, resp->irq, scp->ih);
353 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
354 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
355 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
356
357 return bus_generic_detach(dev);
358}
359
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360static int
361csa_resume(device_t dev)
362{
363 csa_res *resp;
364 sc_p scp;
365
366 scp = device_get_softc(dev);
367 resp = &scp->res;
368
369 /* Initialize the chip. */
370 if (csa_initialize(scp))
371 return (ENXIO);
372
373 /* Reset the Processor. */
374 csa_resetdsp(resp);
375
376 /* Download the Processor Image to the processor. */
377 if (csa_downloadimage(resp))
378 return (ENXIO);
379
380 return (bus_generic_resume(dev));
381}
382
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383static struct resource *
384csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
4f7fe8c7 385 u_long start, u_long end, u_long count, u_int flags, int cpuid __unused)
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386{
387 sc_p scp;
388 csa_res *resp;
389 struct resource *res;
390
391 scp = device_get_softc(bus);
392 resp = &scp->res;
393 switch (type) {
394 case SYS_RES_IRQ:
395 if (*rid != 0)
396 return (NULL);
397 res = resp->irq;
398 break;
399 case SYS_RES_MEMORY:
400 switch (*rid) {
558a398b 401 case PCIR_BAR(0):
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402 res = resp->io;
403 break;
558a398b 404 case PCIR_BAR(1):
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405 res = resp->mem;
406 break;
407 default:
408 return (NULL);
409 }
410 break;
411 default:
412 return (NULL);
413 }
414
415 return res;
416}
417
418static int
419csa_release_resource(device_t bus, device_t child, int type, int rid,
420 struct resource *r)
421{
422 return (0);
423}
424
425/*
426 * The following three functions deal with interrupt handling.
427 * An interrupt is primarily handled by the bridge driver.
428 * The bridge driver then determines the child devices to pass
429 * the interrupt. Certain information of the device can be read
430 * only once(eg the value of HISR). The bridge driver is responsible
431 * to pass such the information to the children.
432 */
433
434static int
435csa_setup_intr(device_t bus, device_t child,
436 struct resource *irq, int flags,
558a398b 437 driver_intr_t *intr, void *arg, void **cookiep)
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438{
439 sc_p scp;
440 csa_res *resp;
441 struct sndcard_func *func;
442
443 scp = device_get_softc(bus);
444 resp = &scp->res;
445
446 /*
447 * Look at the function code of the child to determine
448 * the appropriate hander for it.
449 */
450 func = device_get_ivars(child);
451 if (func == NULL || irq != resp->irq)
452 return (EINVAL);
453
454 switch (func->func) {
455 case SCF_PCM:
456 scp->pcmintr = intr;
457 scp->pcmintr_arg = arg;
458 break;
459
460 case SCF_MIDI:
461 scp->midiintr = intr;
462 scp->midiintr_arg = arg;
463 break;
464
465 default:
466 return (EINVAL);
467 }
468 *cookiep = scp;
469 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
470 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
471
472 return (0);
473}
474
475static int
476csa_teardown_intr(device_t bus, device_t child,
477 struct resource *irq, void *cookie)
478{
479 sc_p scp;
480 csa_res *resp;
481 struct sndcard_func *func;
482
483 scp = device_get_softc(bus);
484 resp = &scp->res;
485
486 /*
487 * Look at the function code of the child to determine
488 * the appropriate hander for it.
489 */
490 func = device_get_ivars(child);
491 if (func == NULL || irq != resp->irq || cookie != scp)
492 return (EINVAL);
493
494 switch (func->func) {
495 case SCF_PCM:
496 scp->pcmintr = NULL;
497 scp->pcmintr_arg = NULL;
498 break;
499
500 case SCF_MIDI:
501 scp->midiintr = NULL;
502 scp->midiintr_arg = NULL;
503 break;
504
505 default:
506 return (EINVAL);
507 }
508
509 return (0);
510}
511
512/* The interrupt handler */
513static void
514csa_intr(void *arg)
515{
516 sc_p scp = arg;
517 csa_res *resp;
518 u_int32_t hisr;
519
520 resp = &scp->res;
521
522 /* Is this interrupt for us? */
523 hisr = csa_readio(resp, BA0_HISR);
524 if ((hisr & 0x7fffffff) == 0) {
525 /* Throw an eoi. */
526 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
527 return;
528 }
529
530 /*
531 * Pass the value of HISR via struct csa_bridgeinfo.
532 * The children get access through their ivars.
533 */
534 scp->binfo.hisr = hisr;
535
536 /* Invoke the handlers of the children. */
537 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
538 scp->pcmintr(scp->pcmintr_arg);
539 hisr &= ~(HISR_VC0 | HISR_VC1);
540 }
541 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
542 scp->midiintr(scp->midiintr_arg);
543 hisr &= ~HISR_MIDI;
544 }
545
546 /* Throw an eoi. */
547 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
548}
549
550static int
551csa_initialize(sc_p scp)
552{
553 int i;
554 u_int32_t acsts, acisv;
555 csa_res *resp;
556
557 resp = &scp->res;
558
559 /*
560 * First, blast the clock control register to zero so that the PLL starts
561 * out in a known state, and blast the master serial port control register
562 * to zero so that the serial ports also start out in a known state.
563 */
564 csa_writeio(resp, BA0_CLKCR1, 0);
565 csa_writeio(resp, BA0_SERMC1, 0);
566
567 /*
568 * If we are in AC97 mode, then we must set the part to a host controlled
569 * AC-link. Otherwise, we won't be able to bring up the link.
570 */
571#if 1
572 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
573#else
574 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
575#endif /* 1 */
576
577 /*
578 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
579 * spec) and then drive it high. This is done for non AC97 modes since
580 * there might be logic external to the CS461x that uses the ARST# line
581 * for a reset.
582 */
583 csa_writeio(resp, BA0_ACCTL, 1);
584 DELAY(50);
585 csa_writeio(resp, BA0_ACCTL, 0);
586 DELAY(50);
587 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
588
589 /*
590 * The first thing we do here is to enable sync generation. As soon
591 * as we start receiving bit clock, we'll start producing the SYNC
592 * signal.
593 */
594 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
595
596 /*
597 * Now wait for a short while to allow the AC97 part to start
598 * generating bit clock (so we don't try to start the PLL without an
599 * input clock).
600 */
601 DELAY(50000);
602
603 /*
604 * Set the serial port timing configuration, so that
605 * the clock control circuit gets its clock from the correct place.
606 */
607 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
608 DELAY(700000);
609
610 /*
611 * Write the selected clock control setup to the hardware. Do not turn on
612 * SWCE yet (if requested), so that the devices clocked by the output of
613 * PLL are not clocked until the PLL is stable.
614 */
615 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
616 csa_writeio(resp, BA0_PLLM, 0x3a);
617 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
618
619 /*
620 * Power up the PLL.
621 */
622 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
623
624 /*
625 * Wait until the PLL has stabilized.
626 */
627 DELAY(5000);
628
629 /*
630 * Turn on clocking of the core so that we can setup the serial ports.
631 */
632 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
633
634 /*
635 * Fill the serial port FIFOs with silence.
636 */
637 csa_clearserialfifos(resp);
638
639 /*
640 * Set the serial port FIFO pointer to the first sample in the FIFO.
641 */
558a398b 642#ifdef notdef
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643 csa_writeio(resp, BA0_SERBSP, 0);
644#endif /* notdef */
645
646 /*
647 * Write the serial port configuration to the part. The master
648 * enable bit is not set until all other values have been written.
649 */
650 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
651 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
652 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
653
654 /*
655 * Wait for the codec ready signal from the AC97 codec.
656 */
657 acsts = 0;
658 for (i = 0 ; i < 1000 ; i++) {
659 /*
660 * First, lets wait a short while to let things settle out a bit,
661 * and to prevent retrying the read too quickly.
662 */
663 DELAY(125);
664
665 /*
666 * Read the AC97 status register to see if we've seen a CODEC READY
667 * signal from the AC97 codec.
668 */
669 acsts = csa_readio(resp, BA0_ACSTS);
670 if ((acsts & ACSTS_CRDY) != 0)
671 break;
672 }
673
674 /*
675 * Make sure we sampled CODEC READY.
676 */
677 if ((acsts & ACSTS_CRDY) == 0)
678 return (ENXIO);
679
680 /*
681 * Assert the vaid frame signal so that we can start sending commands
682 * to the AC97 codec.
683 */
684 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
685
686 /*
687 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
688 * the codec is pumping ADC data across the AC-link.
689 */
690 acisv = 0;
691 for (i = 0 ; i < 1000 ; i++) {
692 /*
693 * First, lets wait a short while to let things settle out a bit,
694 * and to prevent retrying the read too quickly.
695 */
558a398b 696#ifdef notdef
984263bc
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697 DELAY(10000000L); /* clw */
698#else
699 DELAY(1000);
700#endif /* notdef */
701 /*
702 * Read the input slot valid register and see if input slots 3 and
703 * 4 are valid yet.
704 */
705 acisv = csa_readio(resp, BA0_ACISV);
706 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
707 break;
708 }
709 /*
710 * Make sure we sampled valid input slots 3 and 4. If not, then return
711 * an error.
712 */
713 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
714 return (ENXIO);
715
716 /*
717 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
718 * commense the transfer of digital audio data to the AC97 codec.
719 */
720 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
721
722 /*
723 * Power down the DAC and ADC. We will power them up (if) when we need
724 * them.
725 */
558a398b 726#ifdef notdef
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727 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
728#endif /* notdef */
729
730 /*
731 * Turn off the Processor by turning off the software clock enable flag in
732 * the clock control register.
733 */
558a398b 734#ifdef notdef
984263bc
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735 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
736 csa_writeio(resp, BA0_CLKCR1, clkcr1);
737#endif /* notdef */
738
739 /*
740 * Enable interrupts on the part.
741 */
742#if 0
743 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
744#endif /* notdef */
745
746 return (0);
747}
748
749void
750csa_clearserialfifos(csa_res *resp)
751{
752 int i, j, pwr;
753 u_int8_t clkcr1, serbst;
754
755 /*
756 * See if the devices are powered down. If so, we must power them up first
757 * or they will not respond.
758 */
759 pwr = 1;
760 clkcr1 = csa_readio(resp, BA0_CLKCR1);
761 if ((clkcr1 & CLKCR1_SWCE) == 0) {
762 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
763 pwr = 0;
764 }
765
766 /*
767 * We want to clear out the serial port FIFOs so we don't end up playing
768 * whatever random garbage happens to be in them. We fill the sample FIFOs
769 * with zero (silence).
770 */
771 csa_writeio(resp, BA0_SERBWP, 0);
772
773 /* Fill all 256 sample FIFO locations. */
774 serbst = 0;
775 for (i = 0 ; i < 256 ; i++) {
776 /* Make sure the previous FIFO write operation has completed. */
777 for (j = 0 ; j < 5 ; j++) {
778 DELAY(100);
779 serbst = csa_readio(resp, BA0_SERBST);
780 if ((serbst & SERBST_WBSY) == 0)
781 break;
782 }
783 if ((serbst & SERBST_WBSY) != 0) {
784 if (!pwr)
785 csa_writeio(resp, BA0_CLKCR1, clkcr1);
786 }
787 /* Write the serial port FIFO index. */
788 csa_writeio(resp, BA0_SERBAD, i);
789 /* Tell the serial port to load the new value into the FIFO location. */
790 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
791 }
792 /*
793 * Now, if we powered up the devices, then power them back down again.
794 * This is kinda ugly, but should never happen.
795 */
796 if (!pwr)
797 csa_writeio(resp, BA0_CLKCR1, clkcr1);
798}
799
558a398b 800void
984263bc
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801csa_resetdsp(csa_res *resp)
802{
803 int i;
804
805 /*
806 * Write the reset bit of the SP control register.
807 */
808 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
809
810 /*
811 * Write the control register.
812 */
813 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
814
815 /*
816 * Clear the trap registers.
817 */
818 for (i = 0 ; i < 8 ; i++) {
819 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
820 csa_writemem(resp, BA1_TWPR, 0xffff);
821 }
822 csa_writemem(resp, BA1_DREG, 0);
823
824 /*
825 * Set the frame timer to reflect the number of cycles per frame.
826 */
827 csa_writemem(resp, BA1_FRMT, 0xadf);
828}
829
830static int
831csa_downloadimage(csa_res *resp)
832{
833 int i;
834 u_int32_t tmp, src, dst, count, data;
835
836 for (i = 0; i < CLEAR__COUNT; i++) {
837 dst = ClrStat[i].BA1__DestByteOffset;
838 count = ClrStat[i].BA1__SourceSize;
839 for (tmp = 0; tmp < count; tmp += 4)
840 csa_writemem(resp, dst + tmp, 0x00000000);
841 }
842
843 for (i = 0; i < FILL__COUNT; i++) {
844 src = 0;
845 dst = FillStat[i].Offset;
846 count = FillStat[i].Size;
847 for (tmp = 0; tmp < count; tmp += 4) {
848 data = FillStat[i].pFill[src];
849 csa_writemem(resp, dst + tmp, data);
850 src++;
851 }
852 }
853
854 return (0);
855}
856
857int
858csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
859{
860 int i;
861 u_int32_t acsda, acctl, acsts;
862
863 /*
864 * Make sure that there is not data sitting around from a previous
865 * uncompleted access. ACSDA = Status Data Register = 47Ch
866 */
867 acsda = csa_readio(resp, BA0_ACSDA);
868
869 /*
870 * Setup the AC97 control registers on the CS461x to send the
871 * appropriate command to the AC97 to perform the read.
872 * ACCAD = Command Address Register = 46Ch
873 * ACCDA = Command Data Register = 470h
874 * ACCTL = Control Register = 460h
875 * set DCV - will clear when process completed
876 * set CRW - Read command
877 * set VFRM - valid frame enabled
878 * set ESYN - ASYNC generation enabled
879 * set RSTN - ARST# inactive, AC97 codec not reset
880 */
881
882 /*
883 * Get the actual AC97 register from the offset
884 */
885 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
886 csa_writeio(resp, BA0_ACCDA, 0);
887 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
888
889 /*
890 * Wait for the read to occur.
891 */
892 acctl = 0;
893 for (i = 0 ; i < 10 ; i++) {
894 /*
895 * First, we want to wait for a short time.
896 */
897 DELAY(25);
898
899 /*
900 * Now, check to see if the read has completed.
901 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
902 */
903 acctl = csa_readio(resp, BA0_ACCTL);
904 if ((acctl & ACCTL_DCV) == 0)
905 break;
906 }
907
908 /*
909 * Make sure the read completed.
910 */
911 if ((acctl & ACCTL_DCV) != 0)
912 return (EAGAIN);
913
914 /*
915 * Wait for the valid status bit to go active.
916 */
917 acsts = 0;
918 for (i = 0 ; i < 10 ; i++) {
919 /*
920 * Read the AC97 status register.
921 * ACSTS = Status Register = 464h
922 */
923 acsts = csa_readio(resp, BA0_ACSTS);
924 /*
925 * See if we have valid status.
926 * VSTS - Valid Status
927 */
928 if ((acsts & ACSTS_VSTS) != 0)
929 break;
930 /*
931 * Wait for a short while.
932 */
933 DELAY(25);
934 }
935
936 /*
937 * Make sure we got valid status.
938 */
939 if ((acsts & ACSTS_VSTS) == 0)
940 return (EAGAIN);
941
942 /*
943 * Read the data returned from the AC97 register.
944 * ACSDA = Status Data Register = 474h
945 */
946 *data = csa_readio(resp, BA0_ACSDA);
947
948 return (0);
949}
950
951int
952csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
953{
954 int i;
955 u_int32_t acctl;
956
957 /*
958 * Setup the AC97 control registers on the CS461x to send the
959 * appropriate command to the AC97 to perform the write.
960 * ACCAD = Command Address Register = 46Ch
961 * ACCDA = Command Data Register = 470h
962 * ACCTL = Control Register = 460h
963 * set DCV - will clear when process completed
964 * set VFRM - valid frame enabled
965 * set ESYN - ASYNC generation enabled
966 * set RSTN - ARST# inactive, AC97 codec not reset
967 */
968
969 /*
970 * Get the actual AC97 register from the offset
971 */
972 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
973 csa_writeio(resp, BA0_ACCDA, data);
974 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
975
976 /*
977 * Wait for the write to occur.
978 */
979 acctl = 0;
980 for (i = 0 ; i < 10 ; i++) {
981 /*
982 * First, we want to wait for a short time.
983 */
984 DELAY(25);
985
986 /*
987 * Now, check to see if the read has completed.
988 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
989 */
990 acctl = csa_readio(resp, BA0_ACCTL);
991 if ((acctl & ACCTL_DCV) == 0)
992 break;
993 }
994
995 /*
996 * Make sure the write completed.
997 */
998 if ((acctl & ACCTL_DCV) != 0)
999 return (EAGAIN);
1000
1001 return (0);
1002}
1003
1004u_int32_t
1005csa_readio(csa_res *resp, u_long offset)
1006{
1007 u_int32_t ul;
1008
1009 if (offset < BA0_AC97_RESET)
1010 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1011 else {
1012 if (csa_readcodec(resp, offset, &ul))
1013 ul = 0;
1014 return (ul);
1015 }
1016}
1017
1018void
1019csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1020{
1021 if (offset < BA0_AC97_RESET)
1022 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1023 else
1024 csa_writecodec(resp, offset, data);
1025}
1026
1027u_int32_t
1028csa_readmem(csa_res *resp, u_long offset)
1029{
1030 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1031}
1032
1033void
1034csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1035{
1036 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1037}
1038
1039static device_method_t csa_methods[] = {
1040 /* Device interface */
1041 DEVMETHOD(device_probe, csa_probe),
1042 DEVMETHOD(device_attach, csa_attach),
1043 DEVMETHOD(device_detach, csa_detach),
1044 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1045 DEVMETHOD(device_suspend, bus_generic_suspend),
558a398b 1046 DEVMETHOD(device_resume, csa_resume),
984263bc
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1047
1048 /* Bus interface */
1049 DEVMETHOD(bus_print_child, bus_generic_print_child),
1050 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1051 DEVMETHOD(bus_release_resource, csa_release_resource),
1052 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1053 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1054 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1055 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1056
1057 { 0, 0 }
1058};
1059
1060static driver_t csa_driver = {
1061 "csa",
1062 csa_methods,
1063 sizeof(struct csa_softc),
1064};
1065
1066/*
1067 * csa can be attached to a pci bus.
1068 */
aa2b9d05 1069DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, NULL, NULL);
558a398b 1070MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
984263bc 1071MODULE_VERSION(snd_csa, 1);