kernel: Move GPL'd kernel files to sys/gnu to have them all in one place.
[dragonfly.git] / sys / gnu / dev / sound / pci / maestro3_reg.h
CommitLineData
558a398b 1/* $FreeBSD: src/sys/gnu/dev/sound/pci/maestro3_reg.h,v 1.5 2005/01/06 18:27:30 imp Exp $ */
558a398b 2/*-
984263bc
MD
3 * ESS Technology allegro audio driver.
4 *
5 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * Hacked for the maestro3 driver by zab
22 */
23
24/* Allegro PCI configuration registers */
25#define PCI_LEGACY_AUDIO_CTRL 0x40
26#define SOUND_BLASTER_ENABLE 0x00000001
27#define FM_SYNTHESIS_ENABLE 0x00000002
28#define GAME_PORT_ENABLE 0x00000004
29#define MPU401_IO_ENABLE 0x00000008
30#define MPU401_IRQ_ENABLE 0x00000010
31#define ALIAS_10BIT_IO 0x00000020
32#define SB_DMA_MASK 0x000000C0
33#define SB_DMA_0 0x00000040
34#define SB_DMA_1 0x00000040
35#define SB_DMA_R 0x00000080
36#define SB_DMA_3 0x000000C0
37#define SB_IRQ_MASK 0x00000700
38#define SB_IRQ_5 0x00000000
39#define SB_IRQ_7 0x00000100
40#define SB_IRQ_9 0x00000200
41#define SB_IRQ_10 0x00000300
42#define MIDI_IRQ_MASK 0x00003800
43#define SERIAL_IRQ_ENABLE 0x00004000
44#define DISABLE_LEGACY 0x00008000
45
46#define PCI_ALLEGRO_CONFIG 0x50
47#define SB_ADDR_240 0x00000004
48#define MPU_ADDR_MASK 0x00000018
49#define MPU_ADDR_330 0x00000000
50#define MPU_ADDR_300 0x00000008
51#define MPU_ADDR_320 0x00000010
52#define MPU_ADDR_340 0x00000018
53#define USE_PCI_TIMING 0x00000040
54#define POSTED_WRITE_ENABLE 0x00000080
55#define DMA_POLICY_MASK 0x00000700
56#define DMA_DDMA 0x00000000
57#define DMA_TDMA 0x00000100
58#define DMA_PCPCI 0x00000200
59#define DMA_WBDMA16 0x00000400
60#define DMA_WBDMA4 0x00000500
61#define DMA_WBDMA2 0x00000600
62#define DMA_WBDMA1 0x00000700
63#define DMA_SAFE_GUARD 0x00000800
64#define HI_PERF_GP_ENABLE 0x00001000
65#define PIC_SNOOP_MODE_0 0x00002000
66#define PIC_SNOOP_MODE_1 0x00004000
67#define SOUNDBLASTER_IRQ_MASK 0x00008000
68#define RING_IN_ENABLE 0x00010000
69#define SPDIF_TEST_MODE 0x00020000
70#define CLK_MULT_MODE_SELECT_2 0x00040000
71#define EEPROM_WRITE_ENABLE 0x00080000
72#define CODEC_DIR_IN 0x00100000
73#define HV_BUTTON_FROM_GD 0x00200000
74#define REDUCED_DEBOUNCE 0x00400000
75#define HV_CTRL_ENABLE 0x00800000
76#define SPDIF_ENABLE 0x01000000
77#define CLK_DIV_SELECT 0x06000000
78#define CLK_DIV_BY_48 0x00000000
79#define CLK_DIV_BY_49 0x02000000
80#define CLK_DIV_BY_50 0x04000000
81#define CLK_DIV_RESERVED 0x06000000
82#define PM_CTRL_ENABLE 0x08000000
83#define CLK_MULT_MODE_SELECT 0x30000000
84#define CLK_MULT_MODE_SHIFT 28
85#define CLK_MULT_MODE_0 0x00000000
86#define CLK_MULT_MODE_1 0x10000000
87#define CLK_MULT_MODE_2 0x20000000
88#define CLK_MULT_MODE_3 0x30000000
89#define INT_CLK_SELECT 0x40000000
90#define INT_CLK_MULT_RESET 0x80000000
91
92/* M3 */
93#define INT_CLK_SRC_NOT_PCI 0x00100000
94#define INT_CLK_MULT_ENABLE 0x80000000
95
96#define PCI_ACPI_CONTROL 0x54
97#define PCI_ACPI_D0 0x00000000
98#define PCI_ACPI_D1 0xB4F70000
99#define PCI_ACPI_D2 0xB4F7B4F7
100
101#define PCI_USER_CONFIG 0x58
102#define EXT_PCI_MASTER_ENABLE 0x00000001
103#define SPDIF_OUT_SELECT 0x00000002
104#define TEST_PIN_DIR_CTRL 0x00000004
105#define AC97_CODEC_TEST 0x00000020
106#define TRI_STATE_BUFFER 0x00000080
107#define IN_CLK_12MHZ_SELECT 0x00000100
108#define MULTI_FUNC_DISABLE 0x00000200
109#define EXT_MASTER_PAIR_SEL 0x00000400
110#define PCI_MASTER_SUPPORT 0x00000800
111#define STOP_CLOCK_ENABLE 0x00001000
112#define EAPD_DRIVE_ENABLE 0x00002000
113#define REQ_TRI_STATE_ENABLE 0x00004000
114#define REQ_LOW_ENABLE 0x00008000
115#define MIDI_1_ENABLE 0x00010000
116#define MIDI_2_ENABLE 0x00020000
117#define SB_AUDIO_SYNC 0x00040000
118#define HV_CTRL_TEST 0x00100000
119#define SOUNDBLASTER_TEST 0x00400000
120
121#define PCI_USER_CONFIG_C 0x5C
122
123#define PCI_DDMA_CTRL 0x60
124#define DDMA_ENABLE 0x00000001
125
126
127/* Allegro registers */
128#define HOST_INT_CTRL 0x18
129#define SB_INT_ENABLE 0x0001
130#define MPU401_INT_ENABLE 0x0002
131#define ASSP_INT_ENABLE 0x0010
132#define RING_INT_ENABLE 0x0020
133#define HV_INT_ENABLE 0x0040
134#define CLKRUN_GEN_ENABLE 0x0100
135#define HV_CTRL_TO_PME 0x0400
136#define SOFTWARE_RESET_ENABLE 0x8000
137
138/*
139 * should be using the above defines, probably.
140 */
141#define REGB_ENABLE_RESET 0x01
142#define REGB_STOP_CLOCK 0x10
143
144#define HOST_INT_STATUS 0x1A
145#define SB_INT_PENDING 0x01
146#define MPU401_INT_PENDING 0x02
147#define ASSP_INT_PENDING 0x10
148#define RING_INT_PENDING 0x20
149#define HV_INT_PENDING 0x40
150
151#define HARDWARE_VOL_CTRL 0x1B
152#define SHADOW_MIX_REG_VOICE 0x1C
153#define HW_VOL_COUNTER_VOICE 0x1D
154#define SHADOW_MIX_REG_MASTER 0x1E
155#define HW_VOL_COUNTER_MASTER 0x1F
156
157#define CODEC_COMMAND 0x30
158#define CODEC_READ_B 0x80
159
160#define CODEC_STATUS 0x30
161#define CODEC_BUSY_B 0x01
162
163#define CODEC_DATA 0x32
164
165#define RING_BUS_CTRL_A 0x36
166#define RAC_PME_ENABLE 0x0100
167#define RAC_SDFS_ENABLE 0x0200
168#define LAC_PME_ENABLE 0x0400
169#define LAC_SDFS_ENABLE 0x0800
170#define SERIAL_AC_LINK_ENABLE 0x1000
171#define IO_SRAM_ENABLE 0x2000
172#define IIS_INPUT_ENABLE 0x8000
173
174#define RING_BUS_CTRL_B 0x38
175#define SECOND_CODEC_ID_MASK 0x0003
176#define SPDIF_FUNC_ENABLE 0x0010
177#define SECOND_AC_ENABLE 0x0020
178#define SB_MODULE_INTF_ENABLE 0x0040
179#define SSPE_ENABLE 0x0040
180#define M3I_DOCK_ENABLE 0x0080
181
182#define SDO_OUT_DEST_CTRL 0x3A
183#define COMMAND_ADDR_OUT 0x0003
184#define PCM_LR_OUT_LOCAL 0x0000
185#define PCM_LR_OUT_REMOTE 0x0004
186#define PCM_LR_OUT_MUTE 0x0008
187#define PCM_LR_OUT_BOTH 0x000C
188#define LINE1_DAC_OUT_LOCAL 0x0000
189#define LINE1_DAC_OUT_REMOTE 0x0010
190#define LINE1_DAC_OUT_MUTE 0x0020
191#define LINE1_DAC_OUT_BOTH 0x0030
192#define PCM_CLS_OUT_LOCAL 0x0000
193#define PCM_CLS_OUT_REMOTE 0x0040
194#define PCM_CLS_OUT_MUTE 0x0080
195#define PCM_CLS_OUT_BOTH 0x00C0
196#define PCM_RLF_OUT_LOCAL 0x0000
197#define PCM_RLF_OUT_REMOTE 0x0100
198#define PCM_RLF_OUT_MUTE 0x0200
199#define PCM_RLF_OUT_BOTH 0x0300
200#define LINE2_DAC_OUT_LOCAL 0x0000
201#define LINE2_DAC_OUT_REMOTE 0x0400
202#define LINE2_DAC_OUT_MUTE 0x0800
203#define LINE2_DAC_OUT_BOTH 0x0C00
204#define HANDSET_OUT_LOCAL 0x0000
205#define HANDSET_OUT_REMOTE 0x1000
206#define HANDSET_OUT_MUTE 0x2000
207#define HANDSET_OUT_BOTH 0x3000
208#define IO_CTRL_OUT_LOCAL 0x0000
209#define IO_CTRL_OUT_REMOTE 0x4000
210#define IO_CTRL_OUT_MUTE 0x8000
211#define IO_CTRL_OUT_BOTH 0xC000
212
213#define SDO_IN_DEST_CTRL 0x3C
214#define STATUS_ADDR_IN 0x0003
215#define PCM_LR_IN_LOCAL 0x0000
216#define PCM_LR_IN_REMOTE 0x0004
217#define PCM_LR_RESERVED 0x0008
218#define PCM_LR_IN_BOTH 0x000C
219#define LINE1_ADC_IN_LOCAL 0x0000
220#define LINE1_ADC_IN_REMOTE 0x0010
221#define LINE1_ADC_IN_MUTE 0x0020
222#define MIC_ADC_IN_LOCAL 0x0000
223#define MIC_ADC_IN_REMOTE 0x0040
224#define MIC_ADC_IN_MUTE 0x0080
225#define LINE2_DAC_IN_LOCAL 0x0000
226#define LINE2_DAC_IN_REMOTE 0x0400
227#define LINE2_DAC_IN_MUTE 0x0800
228#define HANDSET_IN_LOCAL 0x0000
229#define HANDSET_IN_REMOTE 0x1000
230#define HANDSET_IN_MUTE 0x2000
231#define IO_STATUS_IN_LOCAL 0x0000
232#define IO_STATUS_IN_REMOTE 0x4000
233
234#define SPDIF_IN_CTRL 0x3E
235#define SPDIF_IN_ENABLE 0x0001
236
237#define GPIO_DATA 0x60
238#define GPIO_DATA_MASK 0x0FFF
239#define GPIO_HV_STATUS 0x3000
240#define GPIO_PME_STATUS 0x4000
241
242#define GPIO_MASK 0x64
243#define GPIO_DIRECTION 0x68
244#define GPO_PRIMARY_AC97 0x0001
245#define GPI_LINEOUT_SENSE 0x0004
246#define GPO_SECONDARY_AC97 0x0008
247#define GPI_VOL_DOWN 0x0010
248#define GPI_VOL_UP 0x0020
249#define GPI_IIS_CLK 0x0040
250#define GPI_IIS_LRCLK 0x0080
251#define GPI_IIS_DATA 0x0100
252#define GPI_DOCKING_STATUS 0x0100
253#define GPI_HEADPHONE_SENSE 0x0200
254#define GPO_EXT_AMP_SHUTDOWN 0x1000
255
256/* M3 */
257#define GPO_M3_EXT_AMP_SHUTDN 0x0002
258
259#define ASSP_INDEX_PORT 0x80
260#define ASSP_MEMORY_PORT 0x82
261#define ASSP_DATA_PORT 0x84
262
263#define MPU401_DATA_PORT 0x98
264#define MPU401_STATUS_PORT 0x99
265
266#define CLK_MULT_DATA_PORT 0x9C
267
268#define ASSP_CONTROL_A 0xA2
269#define ASSP_0_WS_ENABLE 0x01
270#define ASSP_CTRL_A_RESERVED1 0x02
271#define ASSP_CTRL_A_RESERVED2 0x04
272#define ASSP_CLK_49MHZ_SELECT 0x08
273#define FAST_PLU_ENABLE 0x10
274#define ASSP_CTRL_A_RESERVED3 0x20
275#define DSP_CLK_36MHZ_SELECT 0x40
276
277#define ASSP_CONTROL_B 0xA4
278#define RESET_ASSP 0x00
279#define RUN_ASSP 0x01
280#define ENABLE_ASSP_CLOCK 0x00
281#define STOP_ASSP_CLOCK 0x10
282#define RESET_TOGGLE 0x40
283
284#define ASSP_CONTROL_C 0xA6
285#define ASSP_HOST_INT_ENABLE 0x01
286#define FM_ADDR_REMAP_DISABLE 0x02
287#define HOST_WRITE_PORT_ENABLE 0x08
288
289#define ASSP_HOST_INT_STATUS 0xAC
290#define DSP2HOST_REQ_PIORECORD 0x01
291#define DSP2HOST_REQ_I2SRATE 0x02
292#define DSP2HOST_REQ_TIMER 0x04
293
294/* AC97 registers */
295/* XXX fix this crap up */
296/*#define AC97_RESET 0x00*/
297
298#define AC97_VOL_MUTE_B 0x8000
299#define AC97_VOL_M 0x1F
300#define AC97_LEFT_VOL_S 8
301
302#define AC97_MASTER_VOL 0x02
303#define AC97_LINE_LEVEL_VOL 0x04
304#define AC97_MASTER_MONO_VOL 0x06
305#define AC97_PC_BEEP_VOL 0x0A
306#define AC97_PC_BEEP_VOL_M 0x0F
307#define AC97_SROUND_MASTER_VOL 0x38
308#define AC97_PC_BEEP_VOL_S 1
309
310/*#define AC97_PHONE_VOL 0x0C
311#define AC97_MIC_VOL 0x0E*/
312#define AC97_MIC_20DB_ENABLE 0x40
313
314/*#define AC97_LINEIN_VOL 0x10
315#define AC97_CD_VOL 0x12
316#define AC97_VIDEO_VOL 0x14
317#define AC97_AUX_VOL 0x16*/
318#define AC97_PCM_OUT_VOL 0x18
319/*#define AC97_RECORD_SELECT 0x1A*/
320#define AC97_RECORD_MIC 0x00
321#define AC97_RECORD_CD 0x01
322#define AC97_RECORD_VIDEO 0x02
323#define AC97_RECORD_AUX 0x03
324#define AC97_RECORD_MONO_MUX 0x02
325#define AC97_RECORD_DIGITAL 0x03
326#define AC97_RECORD_LINE 0x04
327#define AC97_RECORD_STEREO 0x05
328#define AC97_RECORD_MONO 0x06
329#define AC97_RECORD_PHONE 0x07
330
331/*#define AC97_RECORD_GAIN 0x1C*/
332#define AC97_RECORD_VOL_M 0x0F
333
334/*#define AC97_GENERAL_PURPOSE 0x20*/
335#define AC97_POWER_DOWN_CTRL 0x26
336#define AC97_ADC_READY 0x0001
337#define AC97_DAC_READY 0x0002
338#define AC97_ANALOG_READY 0x0004
339#define AC97_VREF_ON 0x0008
340#define AC97_PR0 0x0100
341#define AC97_PR1 0x0200
342#define AC97_PR2 0x0400
343#define AC97_PR3 0x0800
344#define AC97_PR4 0x1000
345
346#define AC97_RESERVED1 0x28
347
348#define AC97_VENDOR_TEST 0x5A
349
350#define AC97_CLOCK_DELAY 0x5C
351#define AC97_LINEOUT_MUX_SEL 0x0001
352#define AC97_MONO_MUX_SEL 0x0002
353#define AC97_CLOCK_DELAY_SEL 0x1F
354#define AC97_DAC_CDS_SHIFT 6
355#define AC97_ADC_CDS_SHIFT 11
356
357#define AC97_MULTI_CHANNEL_SEL 0x74
358
359/*#define AC97_VENDOR_ID1 0x7C
360#define AC97_VENDOR_ID2 0x7E*/
361
362/*
363 * ASSP control regs
364 */
365#define DSP_PORT_TIMER_COUNT 0x06
366
367#define DSP_PORT_MEMORY_INDEX 0x80
368
369#define DSP_PORT_MEMORY_TYPE 0x82
370#define MEMTYPE_INTERNAL_CODE 0x0002
371#define MEMTYPE_INTERNAL_DATA 0x0003
372#define MEMTYPE_MASK 0x0003
373
374#define DSP_PORT_MEMORY_DATA 0x84
375
376#define DSP_PORT_CONTROL_REG_A 0xA2
377#define DSP_PORT_CONTROL_REG_B 0xA4
378#define DSP_PORT_CONTROL_REG_C 0xA6
379
380#define REV_A_CODE_MEMORY_BEGIN 0x0000
381#define REV_A_CODE_MEMORY_END 0x0FFF
382#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
383#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
384
385#define REV_B_CODE_MEMORY_BEGIN 0x0000
386#define REV_B_CODE_MEMORY_END 0x0BFF
387#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
388#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
389
390#define REV_A_DATA_MEMORY_BEGIN 0x1000
391#define REV_A_DATA_MEMORY_END 0x2FFF
392#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
393#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
394
395#define REV_B_DATA_MEMORY_BEGIN 0x1000
396#define REV_B_DATA_MEMORY_END 0x2BFF
397#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
398#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
399
400
401#define NUM_UNITS_KERNEL_CODE 16
402#define NUM_UNITS_KERNEL_DATA 2
403
404#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
405#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
406
407/*
408 * Kernel data layout
409 */
410
411#define DP_SHIFT_COUNT 7
412
413#define KDATA_BASE_ADDR 0x1000
414#define KDATA_BASE_ADDR2 0x1080
415
416#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
417#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
418#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
419#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
420#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
421#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
422#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
423#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
424#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
425
426#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
427#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
428
429#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
430#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
431#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
432#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
433#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
434#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
435#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
436#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
437#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
438#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
439
440#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
441#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
442
443#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
444#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
445
446#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
447#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
448
449#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
450#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
451#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
452
453#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
454#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
455#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
456#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
457#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
458
459#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
460#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
461#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
462
463#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
464#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
465#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
466
467#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
468#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
469#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
470#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
471#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
472#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
473#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
474#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
475#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
476#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
477
478#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
479#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
480#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
481
482#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
483#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
484
485#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
486#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
487#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
488
489#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
490#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
491#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
492#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
493#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
494#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
495
496#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
497#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
498#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
499#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
500#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
501#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
502
b993bb87 503#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
984263bc
MD
504#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
505#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
506#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
507#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
508#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
509
510#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
511#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
512#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
513#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
514
515#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
516#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
517
518#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
519#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
520
521#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
522#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
523#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
524#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
525#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
526
527#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
528#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
529
530#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
531#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
532#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
533
534#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
535#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
536
537#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
538
539#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
540#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
541#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
542#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
543#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
544#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
545#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
546#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
547#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
548#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
549#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
550#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
551
552#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
553#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
554#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
555#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
556
557#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
558#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
559
560#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
561#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
562#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
563#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
564
565#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
566#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
567#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
568#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
569#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
570
571/*
572 * second 'segment' (?) reserved for mixer
573 * buffers..
574 */
575
576#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
577#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
578#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
579#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
580#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
581#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
582#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
583#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
584#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
585#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
586#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
587#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
588#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
589#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
590#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
591#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
592
593#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
594#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
595#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
596#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
597#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
598#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
599#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
600#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
601#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
602#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
603#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
604
605#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
606#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
607#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
608#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
609#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
610#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
611
612#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
613#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
614#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
615#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
616
617/*
618 * client data area offsets
619 */
620#define CDATA_INSTANCE_READY 0x00
621
622#define CDATA_HOST_SRC_ADDRL 0x01
623#define CDATA_HOST_SRC_ADDRH 0x02
624#define CDATA_HOST_SRC_END_PLUS_1L 0x03
625#define CDATA_HOST_SRC_END_PLUS_1H 0x04
626#define CDATA_HOST_SRC_CURRENTL 0x05
627#define CDATA_HOST_SRC_CURRENTH 0x06
628
629#define CDATA_IN_BUF_CONNECT 0x07
630#define CDATA_OUT_BUF_CONNECT 0x08
631
632#define CDATA_IN_BUF_BEGIN 0x09
633#define CDATA_IN_BUF_END_PLUS_1 0x0A
634#define CDATA_IN_BUF_HEAD 0x0B
635#define CDATA_IN_BUF_TAIL 0x0C
636#define CDATA_OUT_BUF_BEGIN 0x0D
637#define CDATA_OUT_BUF_END_PLUS_1 0x0E
638#define CDATA_OUT_BUF_HEAD 0x0F
639#define CDATA_OUT_BUF_TAIL 0x10
640
641#define CDATA_DMA_CONTROL 0x11
642#define CDATA_RESERVED 0x12
643
644#define CDATA_FREQUENCY 0x13
645#define CDATA_LEFT_VOLUME 0x14
646#define CDATA_RIGHT_VOLUME 0x15
647#define CDATA_LEFT_SUR_VOL 0x16
648#define CDATA_RIGHT_SUR_VOL 0x17
649
650#define CDATA_HEADER_LEN 0x18
651
652#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
653#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
654#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
655#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
656#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
657#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
658#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
659#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
660
661#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
662#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
663#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
664#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
665#define MINISRC_BIQUAD_STAGE 2
666#define MINISRC_COEF_LOC 0X175
667
668#define DMACONTROL_BLOCK_MASK 0x000F
669#define DMAC_BLOCK0_SELECTOR 0x0000
670#define DMAC_BLOCK1_SELECTOR 0x0001
671#define DMAC_BLOCK2_SELECTOR 0x0002
672#define DMAC_BLOCK3_SELECTOR 0x0003
673#define DMAC_BLOCK4_SELECTOR 0x0004
674#define DMAC_BLOCK5_SELECTOR 0x0005
675#define DMAC_BLOCK6_SELECTOR 0x0006
676#define DMAC_BLOCK7_SELECTOR 0x0007
677#define DMAC_BLOCK8_SELECTOR 0x0008
678#define DMAC_BLOCK9_SELECTOR 0x0009
679#define DMAC_BLOCKA_SELECTOR 0x000A
680#define DMAC_BLOCKB_SELECTOR 0x000B
681#define DMAC_BLOCKC_SELECTOR 0x000C
682#define DMAC_BLOCKD_SELECTOR 0x000D
683#define DMAC_BLOCKE_SELECTOR 0x000E
684#define DMAC_BLOCKF_SELECTOR 0x000F
685#define DMACONTROL_PAGE_MASK 0x00F0
686#define DMAC_PAGE0_SELECTOR 0x0030
687#define DMAC_PAGE1_SELECTOR 0x0020
688#define DMAC_PAGE2_SELECTOR 0x0010
689#define DMAC_PAGE3_SELECTOR 0x0000
690#define DMACONTROL_AUTOREPEAT 0x1000
691#define DMACONTROL_STOPPED 0x2000
692#define DMACONTROL_DIRECTION 0x0100