kernel - SMP - "Fix AP #%d (PHY# %d) failed" issues
[dragonfly.git] / sys / platform / pc32 / apic / apicreg.h
CommitLineData
984263bc 1/*
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2 * Copyright (c) 2003,2004 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
8a8d5d85 34 * Copyright (c) 1996, by Peter Wemm and Steve Passe, All rights reserved.
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35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. The name of the developer may NOT be used to endorse or promote products
42 * derived from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 *
56 * $FreeBSD: src/sys/i386/include/apic.h,v 1.14.2.2 2003/03/21 21:46:15 jhb Exp $
35408d22 57 * $DragonFly: src/sys/platform/pc32/apic/apicreg.h,v 1.6 2005/11/03 23:45:09 dillon Exp $
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58 */
59
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60#ifndef _MACHINE_APICREG_H_
61#define _MACHINE_APICREG_H_
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62
63/*
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64 * Local && I/O APIC definitions for Pentium P54C+ Built-in APIC.
65 *
66 * A per-cpu APIC resides in memory location 0xFEE00000.
67 *
68 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
69 * +-----------+-----------+-----------+-----------+
70 * 0000 | | | | |
71 * 0010 | | | | |
72 * +-----------+-----------+-----------+-----------+
73 *
74 * +-----------+-----------+-----------+-----------+
75 * 0020 ID | | ID | | | | RW
76 * +-----------+-----------+-----------+-----------+
77 *
78 * The physical APIC ID is used with physical interrupt
79 * delivery modes.
80 *
81 * +-----------+-----------+-----------+-----------+
82 * 0030 VER | | | | |
83 * +-----------+-----------+-----------+-----------+
84 * 0040 | | | | |
85 * 0050 | | | | |
86 * 0060 | | | | |
87 * 0070 | | | | |
88 * +-----------+-----------+-----------+-----------+
89 * 0080 TPR | | | | PRIO SUBC |
90 * 0090 APR | | | | |
91 * 00A0 PPR | | | | |
92 * +-----------+-----------+-----------+-----------+
93 *
94 * The Task Priority Register provides a priority threshold
95 * mechanism for interrupting the processor. Only interrupts
96 * with a higher priority then that specified in the TPR will
97 * be served. Other interrupts are recorded and serviced
98 * as soon as the TPR value decreases enough to allow that
99 * (unless EOId by another APIC).
100 *
101 * PRIO (7:4). Main priority. If 15 the APIC will not
102 * accept any interrupts.
103 * SUBC (3:0) Sub priority. See APR/PPR.
104 *
105 *
106 * The Processor Priority Register determines whether a
107 * pending interrupt can be dispensed to the processor. ISRV
108 * Is the vector of the highest priority ISR bit set or
109 * zero if no ISR bit is set.
110 *
111 * IF TPR[7:4] >= ISRV[7:4]
112 * PPR[7:0] = TPR[7:0]
113 * ELSE
114 * PPR[7:0] = ISRV[7:4].000
115 *
116 * The Arbitration Priority Register holds the current
117 * lowest priority of the procsesor, a value used during
118 * lowest-priority arbitration.
119 *
120 * IF (TPR[7:4] >= IRRV[7:4] AND TPR[7:4] > ISRV[7:4])
121 * APR[7:0] = TPR[7:0]
122 * ELSE
123 * APR[7:4] = max((TPR[7:4]&ISRV[7:4]),IRRV[7:4]).000
124 *
125 * +-----------+-----------+-----------+-----------+
126 * 00B0 EOI | | | | |
127 * +-----------+-----------+-----------+-----------+
128 * 00C0 | | | | |
129 * +-----------+-----------+-----------+-----------+
130 * 00D0 LDR |LOG APICID | | | |
131 * +-----------+-----------+-----------+-----------+
132 * 00E0 DFR |MODEL| | | | |
133 * +-----------+-----------+-----------+-----------+
134 *
135 * The logical APIC ID is used with logical interrupt
136 * delivery modes. Interpretation of logical destination
137 * information depends on the MODEL bits in the Destination
138 * Format Regiuster.
139 *
140 * MODEL=1111 FLAT MODEL - The MDA is interpreted as
141 * a decoded address. By setting
142 * one bit in the LDR for each
143 * local apic 8 APICs can coexist.
144 *
145 * MODEL=0000 CLUSTER MODEL -
146 *
147 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
148 * +-----------+-----------+-----------+-----------+
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149 * 00F0 SVR | | | FE | vvvvvvvv |
150 * +-----------+-----------+-----------+-----------+
151 *
152 * Spurious interrupt vector register. The 4 low
153 * vector bits must be programmed to 1111, e.g.
154 * vvvv1111.
155 *
bb467734 156 * E - LAPIC enable (0 = disable, 1 = enable)
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157 *
158 * F - Focus processor disable (1 = disable, 0 = enable)
159 *
160 * NOTE: The handler for the spurious interrupt vector
161 * should *NOT* issue an EOI because the spurious
162 * interrupt does not effect the ISR.
163 *
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164 * +-----------+-----------+-----------+-----------+
165 * 0100-0170 ISR| | | | |
166 * 0180-01F0 TMR| | | | |
167 * 0200-0270 IRR| | | | |
168 * +-----------+-----------+-----------+-----------+
169 *
170 * These registers represent 256 bits, one bit for each
171 * possible interrupt. Interrupts 0-15 are reserved so
172 * bits 0-15 are also reserved.
173 *
174 * TMR - Trigger mode register. Upon acceptance of an int
175 * the corresponding bit is cleared for edge-trig and
176 * set for level-trig. If the TMR bit is set (level),
177 * the local APIC sends an EOI to all I/O APICs as
178 * a result of software issuing an EOI command.
179 *
180 * IRR - Interrupt Request Register. Contains active
181 * interrupt requests that have been accepted but not
182 * yet dispensed by the current local APIC. The bit is
183 * cleared and the corresponding ISR bit is set when
184 * the INTA cycle is issued.
185 *
186 * ISR - Interrupt In-Service register. Interrupt has been
187 * delivered but not yet fully serviced. Cleared when
188 * an EOI is issued from the processor. An EOI will
189 * also send an EOI to all I/O APICs if TMR was set.
190 *
191 * +-----------+-----------+-----------+-----------+
192 * 0280 ESR | | | | |
193 * 0290-02F0 | | | | |
194 * +--FEDCBA98-+--76543210-+--FEDCBA98-+-----------+
195 * 0300 ICR_LO | | XX | TL SDMMM | vector |
196 * 0310 ICR_HI | DEST FIELD| | | |
197 * +-----------+-----------+-----------+-----------+
198 *
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199 * The interrupt command register. Generally speaking
200 * writing to ICR_LO initiates a command. All fields
201 * are R/W except the 'S' (delivery status) field, which
202 * is read-only. When
203 *
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204 *
205 * XX: Destination Shorthand field:
206 *
207 * 00 Use Destination field
208 * 01 Self only. Dest field ignored.
209 * 10 All including self (uses a
210 * destination field of 0x0F)
211 * 11 All excluding self (uses a
212 * destination field of 0x0F)
213 *
214 * T: 1 = Level 0 = Edge Trigger modde, used for
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215 * the INIT level de-assert delivery mode only
216 * to de-assert a request.
8a8d5d85 217 *
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218 * L: 0 = De-Assert, 1 = Assert. Always write as
219 * 1 when initiating a new command. Can only
220 * write as 0 for INIT mode de-assertion of
221 * command.
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222 *
223 * S: 1 = Send Pending. Interrupt has been injected
224 * but APIC has not yet accepted it.
225 *
226 * D: 0=physical 1=logical. In physical mode
227 * only 24-27 of DEST FIELD is used from ICR_HI.
228 *
229 * MMM: 000 Fixed. Deliver to all processors according
230 * to the ICR. Always treated as edge trig.
231 *
232 * 001 Lowest Priority. Deliver to just the
233 * processor running at the lowest priority.
234 *
235 * 010 SMI. The vector must be 00B. Only edge
236 * triggered is allowed. The vector field
237 * must be programmed to zero (huh?).
238 *
239 * 011 <reserved>
240 *
241 * 100 NMI. Deliver as an NMI to all processors
242 * listed in the destination field. The
243 * vector is ignored. Alawys treated as
244 * edge triggered.
245 *
246 * 101 INIT. Deliver as an INIT signal to all
247 * processors (like FIXED). Vector is ignored
248 * and it is always edge-triggered.
249 *
250 * 110 Start Up. Sends a special message between
251 * cpus. the vector contains a start-up
252 * address for MP boot protocol.
253 * Always edge triggered. Note: a startup
254 * int is not automatically tried in case of
255 * failure.
256 *
257 * 111 <reserved>
258 *
259 * +-----------+--------10-+--FEDCBA98-+-----------+
260 * 0320 LTIMER | | TM | ---S---- | vector |
261 * 0330 | | | | |
262 * +-----------+--------10-+--FEDCBA98-+-----------+
263 * 0340 LVPCINT | | -M | ---S-MMM | vector |
264 * 0350 LVINT0 | | -M | LRPS-MMM | vector |
265 * 0360 LVINT1 | | -M | LRPS-MMM | vector |
266 * 0370 LVERROR | | -M | -------- | vector |
267 * +-----------+-----------+-----------+-----------+
268 *
269 * T: 1 = periodic, 0 = one-shot
270 *
271 * M: 1 = masked
272 *
273 * L: 1 = level, 0 = edge
274 *
275 * R: For level triggered only, set to 1 when a
276 * level int is accepted, cleared by EOI.
277 *
278 * P: Pin Polarity 0 = Active High, 1 = Active Low
279 *
280 * S: 1 = Send Pending. Interrupt has been injected
281 * but APIC has not yet accepted it.
282 *
283 * MMM 000 = Fixed deliver to cpu according to LVT
284 *
285 * MMM 100 = NMI deliver as an NMI. Always edge
286 *
287 * MMM 111 = ExtInt deliver from 8259, routes INTA
288 * bus cycle to external
289 * controller. Controller is
290 * expected to supply vector.
291 * Always level.
292 *
293 * +-----------+-----------+-----------+-----------+
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294 * 0380 TMR_ICR | | | | |
295 * 0390 TMR_CCR | | | | |
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296 * +-----------+-----------+-----------+-----------+
297 *
298 * The timer initial count register and current count
299 * register (32 bits)
300 *
301 * +-----------+-----------+-----------+-----------+
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302 * 03A0 | | | | |
303 * 03B0 | | | | |
304 * 03C0 | | | | |
305 * 03D0 | | | | |
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306 * +-----------+-----------+-----------+-----------+
307 * 03E0 TMR_DCR | | | | d-dd |
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308 * +-----------+-----------+-----------+-----------+
309 *
9d6bf2df 310 * The timer divide configuration register. d-dd is:
96728c05 311 *
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312 * 0000 - divide by 2
313 * 0001 - divide by 4
314 * 0010 - divide by 8
315 * 0011 - divide by 16
316 * 1000 - divide by 32
317 * 1001 - divide by 64
318 * 1010 - divide by 128
319 * 1011 - divide by 1
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320 *
321 * NOTE ON EOI: Upon receiving an EOI the APIC clears the highest priority
322 * interrupt in the ISR and selects the next highest priority interrupt
323 * for posting to the CPU. If the interrupt being EOId was level
324 * triggered the APIC will send an EOI to all I/O APICs. For the moment
325 * you can write garbage to the EOI register but for future compatibility
326 * 0 should be written.
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327 */
328
329#ifndef LOCORE
330#include <sys/types.h>
331
332#define PAD3 int : 32; int : 32; int : 32
333#define PAD4 int : 32; int : 32; int : 32; int : 32
334
335struct LAPIC {
336 /* reserved */ PAD4;
337 /* reserved */ PAD4;
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338 u_int32_t id; PAD3; /* 0020 R/W */
339 u_int32_t version; PAD3; /* 0030 RO */
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340 /* reserved */ PAD4;
341 /* reserved */ PAD4;
342 /* reserved */ PAD4;
343 /* reserved */ PAD4;
344 u_int32_t tpr; PAD3;
345 u_int32_t apr; PAD3;
346 u_int32_t ppr; PAD3;
347 u_int32_t eoi; PAD3;
348 /* reserved */ PAD4;
349 u_int32_t ldr; PAD3;
350 u_int32_t dfr; PAD3;
351 u_int32_t svr; PAD3;
352 u_int32_t isr0; PAD3;
353 u_int32_t isr1; PAD3;
354 u_int32_t isr2; PAD3;
355 u_int32_t isr3; PAD3;
356 u_int32_t isr4; PAD3;
357 u_int32_t isr5; PAD3;
358 u_int32_t isr6; PAD3;
359 u_int32_t isr7; PAD3;
360 u_int32_t tmr0; PAD3;
361 u_int32_t tmr1; PAD3;
362 u_int32_t tmr2; PAD3;
363 u_int32_t tmr3; PAD3;
364 u_int32_t tmr4; PAD3;
365 u_int32_t tmr5; PAD3;
366 u_int32_t tmr6; PAD3;
367 u_int32_t tmr7; PAD3;
368 u_int32_t irr0; PAD3;
369 u_int32_t irr1; PAD3;
370 u_int32_t irr2; PAD3;
371 u_int32_t irr3; PAD3;
372 u_int32_t irr4; PAD3;
373 u_int32_t irr5; PAD3;
374 u_int32_t irr6; PAD3;
375 u_int32_t irr7; PAD3;
376 u_int32_t esr; PAD3;
377 /* reserved */ PAD4;
378 /* reserved */ PAD4;
379 /* reserved */ PAD4;
380 /* reserved */ PAD4;
381 /* reserved */ PAD4;
382 /* reserved */ PAD4;
383 /* reserved */ PAD4;
384 u_int32_t icr_lo; PAD3;
385 u_int32_t icr_hi; PAD3;
386 u_int32_t lvt_timer; PAD3;
387 /* reserved */ PAD4;
388 u_int32_t lvt_pcint; PAD3;
389 u_int32_t lvt_lint0; PAD3;
390 u_int32_t lvt_lint1; PAD3;
391 u_int32_t lvt_error; PAD3;
392 u_int32_t icr_timer; PAD3;
393 u_int32_t ccr_timer; PAD3;
394 /* reserved */ PAD4;
395 /* reserved */ PAD4;
396 /* reserved */ PAD4;
397 /* reserved */ PAD4;
398 u_int32_t dcr_timer; PAD3;
399 /* reserved */ PAD4;
400};
401
402typedef struct LAPIC lapic_t;
403
404/******************************************************************************
405 * I/O APIC structure
406 */
407
408struct IOAPIC {
409 u_int32_t ioregsel; PAD3;
410 u_int32_t iowin; PAD3;
411};
412
413typedef struct IOAPIC ioapic_t;
414
415#undef PAD4
416#undef PAD3
417
418#endif /* !LOCORE */
419
420
421/******************************************************************************
422 * various code 'logical' values
423 */
424
984263bc 425/*
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426 * TPR loads to prioritize which cpu grabs an interrupt
427 *
428 * (note: some fields of the TPR are reserved)
984263bc 429 */
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430#define LOPRIO_LEVEL 0x00000010 /* TPR of CPU accepting INTs */
431#define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */
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432
433/******************************************************************************
434 * LOCAL APIC defines
435 */
436
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437/*
438 * default physical location for the LOCAL (CPU) APIC
439 */
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440#define DEFAULT_APIC_BASE 0xfee00000
441
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442/*
443 * lapic.id (rw)
444 */
445#define APIC_ID_MASK 0xff000000
446#define APIC_ID_SHIFT 24
447#define APIC_ID_CLUSTER 0xf0
448#define APIC_ID_CLUSTER_ID 0x0f
449#define APIC_MAX_CLUSTER 0xe
450#define APIC_MAX_INTRACLUSTER_ID 3
451#define APIC_ID_CLUSTER_SHIFT 4
452
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453#define APIC_ID(id) (((id) & APIC_ID_MASK) >> APIC_ID_SHIFT)
454
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455/*
456 * lapic.ver (ro)
457 */
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458#define APIC_VER_VERSION 0x000000ff
459#define APIC_VER_MAXLVT 0x00ff0000
460#define MAXLVTSHIFT 16
461
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462/*
463 * lapic.ldr (rw)
464 */
465#define APIC_LDR_RESERVED 0x00ffffff
466
467/*
468 * lapic.dfr (rw)
469 *
470 * The logical APIC ID is used with logical interrupt
471 * delivery modes. Interpretation of logical destination
472 * information depends on the MODEL bits in the Destination
473 * Format Regiuster.
474 *
475 * MODEL=1111 FLAT MODEL - The MDA is interpreted as
476 * a decoded address. By setting
477 * one bit in the LDR for each
478 * local apic 8 APICs can coexist.
479 *
480 * MODEL=0000 CLUSTER MODEL -
481 */
482#define APIC_DFR_RESERVED 0x0fffffff
483#define APIC_DFR_MODEL_MASK 0xf0000000
484#define APIC_DFR_MODEL_FLAT 0xf0000000
485#define APIC_DFR_MODEL_CLUSTER 0x00000000
486
487/*
488 * lapic.svr
489 *
490 * Contains the spurious interrupt vector and bits to enable/disable
491 * the local apic and focus processor.
492 */
984263bc 493#define APIC_SVR_VECTOR 0x000000ff
984263bc 494#define APIC_SVR_ENABLE 0x00000100
9d6bf2df 495#define APIC_SVR_FOCUS_DISABLE 0x00000200
984263bc 496
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497/*
498 * lapic.tpr
499 *
500 * PRIO (7:4). Main priority. If 15 the APIC will not
501 * accept any interrupts.
502 * SUBC (3:0) Sub priority. See APR/PPR.
503 */
984263bc 504#define APIC_TPR_PRIO 0x000000ff
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505#define APIC_TPR_INT 0x000000f0
506#define APIC_TPR_SUB 0x0000000f
984263bc 507
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508/*
509 * lapic.icr_lo -------- ----XXRR TL-SDMMM vvvvvvvv
510 *
511 * The interrupt command register. Generally speaking
512 * writing to ICR_LO initiates a command. All fields
513 * are R/W except the 'S' (delivery status) field, which
514 * is read-only. When
515 *
516 * XX: Destination Shorthand field:
517 *
518 * 00 - Use Destination field
519 * 01 - Self only. Dest field ignored.
520 * 10 - All including self (uses a
521 * destination field of 0x0F)
522 * 11 - All excluding self (uses a
523 * destination field of 0x0F)
524 *
525 * RR: RR mode (? needs documentation)
526 *
527 * T: 1 = Level 0 = Edge Trigger modde, used for
528 * the INIT level de-assert delivery mode only
529 * to de-assert a request.
530 *
531 * L: 0 = De-Assert, 1 = Assert. Always write as
532 * 1 when initiating a new command. Can only
533 * write as 0 for INIT mode de-assertion of
534 * command.
535 *
536 * S: 1 = Send Pending. Interrupt has been injected but the APIC
537 * has not yet accepted it.
538 *
539 * D: 0 = physical 1 = logical. In physical mode only bits 24-27
540 * of the DEST field is used from ICR_HI.
541 *
542 * MMM: Delivery mode
543 *
544 * 000 - Fixed. Deliver to all processors according to the
545 * ICR. Always treated as edge triggered.
546 *
547 * 001 - Lowest Priority. Deliver to just the processor
548 * running at the lowest priority.
549 *
550 * 010 - SMI. The vector must be 00B. Only edge triggered
551 * is allowed. The vector field must be programmed to
552 * 0 (huh?)
553 *
554 * 011 - RR Delivery mode (?? needs documentation).
555 *
556 * 100 - NMI. Deliver as an NMI to all processors listed in
557 * the destination field. The vector is ignored. Always
558 * treated as edge triggered.
559 *
560 * 101 - INIT. Deliver as an INIT signal to all processors
561 * (like FIXED) according to the ICR. The vector is
562 * ignored and delivery is always edge-triggered.
563 *
564 * 110 - Startup. Send a special message between cpus. The
565 * vector contains a startup address for the MP boot
566 * protocol. Always edge triggered. Note: a startup
567 * interrupt is not automatically tried in case of failure.
568 *
569 * 111 - <reserved>
570 */
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571#define APIC_VECTOR_MASK 0x000000ff
572
573#define APIC_DELMODE_MASK 0x00000700
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574#define APIC_DELMODE_FIXED 0x00000000
575#define APIC_DELMODE_LOWPRIO 0x00000100
576#define APIC_DELMODE_SMI 0x00000200
577#define APIC_DELMODE_RR 0x00000300
578#define APIC_DELMODE_NMI 0x00000400
579#define APIC_DELMODE_INIT 0x00000500
580#define APIC_DELMODE_STARTUP 0x00000600
581#define APIC_DELMODE_RESV7 0x00000700
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582
583#define APIC_DESTMODE_MASK 0x00000800
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584#define APIC_DESTMODE_PHY 0x00000000
585#define APIC_DESTMODE_LOG 0x00000800
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586
587#define APIC_DELSTAT_MASK 0x00001000
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588#define APIC_DELSTAT_IDLE 0x00000000
589#define APIC_DELSTAT_PEND 0x00001000
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590
591#define APIC_LEVEL_MASK 0x00004000
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592#define APIC_LEVEL_DEASSERT 0x00000000
593#define APIC_LEVEL_ASSERT 0x00004000
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594
595#define APIC_TRIGMOD_MASK 0x00008000
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596#define APIC_TRIGMOD_EDGE 0x00000000
597#define APIC_TRIGMOD_LEVEL 0x00008000
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598
599#define APIC_RRSTAT_MASK 0x00030000
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600#define APIC_RRSTAT_INVALID 0x00000000
601#define APIC_RRSTAT_INPROG 0x00010000
602#define APIC_RRSTAT_VALID 0x00020000
603#define APIC_RRSTAT_RESV 0x00030000
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604
605#define APIC_DEST_MASK 0x000c0000
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606#define APIC_DEST_DESTFLD 0x00000000
607#define APIC_DEST_SELF 0x00040000
608#define APIC_DEST_ALLISELF 0x00080000
609#define APIC_DEST_ALLESELF 0x000c0000
610
611#define APIC_ICRLO_RESV_MASK 0xfff02000
984263bc 612
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613/*
614 * lapic.icr_hi
615 */
616#define APIC_ICRH_ID_MASK APIC_ID_MASK
617
618/*
619 * lapic.lvt_timer
620 * lapic.lvt_pcint
621 * lapic.lvt_lint0
622 * lapic.lvt_lint1
623 * lapic.lvt_error
624 *
625 * +-----------+--------10-+--FEDCBA98-+-----------+
626 * 0320 LTIMER | | TM | ---S---- | vector |
627 * 0330 | | | | |
628 * +-----------+--------10-+--FEDCBA98-+-----------+
629 * 0340 LVPCINT | | -M | ---S-MMM | vector |
630 * 0350 LVINT0 | | -M | LRPS-MMM | vector |
631 * 0360 LVINT1 | | -M | LRPS-MMM | vector |
632 * 0370 LVERROR | | -M | -------- | vector |
633 * +-----------+-----------+-----------+-----------+
634 *
635 * T: 1 = periodic, 0 = one-shot
636 * (LTIMER only)
637 *
638 * M: 1 = masked
639 *
640 * L: 1 = level, 0 = edge
641 * (LVINT0/1 only)
642 *
643 * R: For level triggered only, set to 1 when a
644 * level int is accepted, cleared by EOI.
645 * (LVINT0/1 only)
646 *
647 * P: Pin Polarity 0 = Active High, 1 = Active Low
648 * (LVINT0/1 only)
649 *
650 * S: 1 = Send Pending. Interrupt has been injected
651 * but APIC has not yet accepted it.
652 *
653 * MMM 000 = Fixed deliver to cpu according to LVT
654 *
655 * MMM 100 = NMI deliver as an NMI. Always edge
656 *
657 * MMM 111 = ExtInt deliver from 8259, routes INTA
658 * bus cycle to external
659 * controller. Controller is
660 * expected to supply vector.
661 * Always level.
662 */
663#define APIC_LVT_VECTOR 0x000000ff
984263bc 664
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665#define APIC_LVT_DM_MASK 0x00000700
666#define APIC_LVT_DM_FIXED 0x00000000
667#define APIC_LVT_DM_NMI 0x00000400
668#define APIC_LVT_DM_EXTINT 0x00000700
984263bc 669
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670#define APIC_LVT_DS 0x00001000 /* (S) Send Pending */
671#define APIC_LVT_POLARITY_MASK 0x00002000
672#define APIC_LVT_POLARITY_LO 0x00002000 /* (P) Pin Polarity */
673#define APIC_LVT_POLARITY_HI 0x00000000
674#define APIC_LVT_LEVELSTATUS 0x00004000 /* (R) level trig status */
675#define APIC_LVT_TRIG_MASK 0x00008000
676#define APIC_LVT_LEVELTRIG 0x00008000 /* (L) 1 = level, 0 = edge */
677#define APIC_LVT_MASKED 0x00010000 /* (M) 1 = masked */
984263bc 678
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679/*
680 * lapic.lvt_timer
681 */
682#define APIC_LVTT_VECTOR APIC_LVT_VECTOR
683#define APIC_LVTT_DS APIC_LVT_DS
684#define APIC_LVTT_MASKED APIC_LVT_MASKED
685#define APIC_LVTT_PERIODIC 0x00020000
984263bc 686
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687#define APIC_TIMER_MAX_COUNT 0xffffffff
688
689/*
690 * lapic.icr_timer - initial count register (32 bits)
691 * lapic.ccr_timer - current count register (32 bits)
692 */
693
694/*
695 * lapic.dcr_timer - timer divider register
696 *
697 * d0dd
698 *
699 * 0000 - divide by 2
700 * 0001 - divide by 4
701 * 0010 - divide by 8
702 * 0011 - divide by 16
703 * 1000 - divide by 32
704 * 1001 - divide by 64
705 * 1010 - divide by 128
706 * 1011 - divide by 1
707 */
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708#define APIC_TDCR_2 0x00
709#define APIC_TDCR_4 0x01
710#define APIC_TDCR_8 0x02
711#define APIC_TDCR_16 0x03
712#define APIC_TDCR_32 0x08
713#define APIC_TDCR_64 0x09
714#define APIC_TDCR_128 0x0a
715#define APIC_TDCR_1 0x0b
716
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717/*
718 * fields in IRR
719 * ISA INTerrupts are in bits 16-31 of the 1st IRR register.
720 * these masks DON'T EQUAL the isa IRQs of the same name.
721 */
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722#define APIC_IRQ0 0
723#define APIC_IRQ1 1
724#define APIC_IRQ2 2
725#define APIC_IRQ3 3
726#define APIC_IRQ4 4
727#define APIC_IRQ5 5
728#define APIC_IRQ6 6
729#define APIC_IRQ7 7
730#define APIC_IRQ8 8
731#define APIC_IRQ9 9
732#define APIC_IRQ10 10
733#define APIC_IRQ11 11
734#define APIC_IRQ12 12
735#define APIC_IRQ13 13
736#define APIC_IRQ14 14
737#define APIC_IRQ15 15
738#define APIC_IRQ16 16
739#define APIC_IRQ17 17
740#define APIC_IRQ18 18
741#define APIC_IRQ19 19
742#define APIC_IRQ20 20
743#define APIC_IRQ21 21
744#define APIC_IRQ22 22
745#define APIC_IRQ23 23
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746
747/******************************************************************************
748 * I/O APIC defines
749 */
750
751/* default physical locations of an IO APIC */
752#define DEFAULT_IO_APIC_BASE 0xfec00000
753
754/* window register offset */
755#define IOAPIC_WINDOW 0x10
756
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757/*
758 * indexes into IO APIC (index into array of 32 bit entities)
759 */
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760#define IOAPIC_ID 0x00
761#define IOAPIC_VER 0x01
762#define IOAPIC_ARB 0x02
763#define IOAPIC_REDTBL 0x10
764#define IOAPIC_REDTBL0 IOAPIC_REDTBL
765#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
766#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
767#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
768#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
769#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
770#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
771#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
772#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
773#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
774#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
775#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
776#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
777#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
778#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
779#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
780#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
781#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
782#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
783#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
784#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
785#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
786#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
787#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
788
789/* fields in VER */
790#define IOART_VER_VERSION 0x000000ff
791#define IOART_VER_MAXREDIR 0x00ff0000
792#define MAXREDIRSHIFT 16
793
794/*
795 * fields in the IO APIC's redirection table entries
796 */
984263bc 797
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798/*
799 * High 32 bit word. The high 8 bits contain the destination field.
800 *
801 * If this entry is set up for Physical Mode, bits 59:56 (the low 4 bits
802 * of the 8 bit destination field) contain an APIC ID.
803 *
804 * If this entry is set up for Logical Mode, the destination field potentially
805 * defines a set of processors. Bits 63:56 (all 8 bits) specify the logical
806 * destination address.
807 *
808 * Current we use IOART_HI_DEST_BROADCAST to broadcast to all LAPICs
809 */
810#define IOART_HI_DEST_MASK APIC_ID_MASK
811#define IOART_HI_DEST_RESV ~APIC_ID_MASK
812#define IOART_HI_DEST_BROADCAST IOART_HI_DEST_MASK
0c8fbc51 813#define IOART_HI_DEST_SHIFT 24
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814
815/*
816 * Low 32 bit word
817 */
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818#define IOART_RESV 0x00fe0000 /* reserved */
819
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820/*
821 * Interrupt mask bit. If 1 the interrupt is masked. An edge sensitive
822 * interrupt which is masked will be lost.
823 */
984263bc 824#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
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825#define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
826#define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
984263bc 827
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828/*
829 * Select trigger mode.
830 */
984263bc 831#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
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832#define IOART_TRGREDG 0x00000000 /* edge */
833#define IOART_TRGRLVL 0x00008000 /* level */
984263bc 834
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835/*
836 * Remote IRR. Only applies to level triggered interrupts, this bit
837 * is set to 1 when the IOAPIC has delivered a level triggered interrupt
838 * to a local APIC. It is cleared when the LAPIC EOI's the interrupt.
839 * This field is read-only.
840 */
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841#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
842
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843/*
844 * Select interrupt pin polarity
845 */
984263bc 846#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
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847#define IOART_INTAHI 0x00000000 /* active high */
848#define IOART_INTALO 0x00002000 /* active low */
984263bc 849
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850/*
851 * Delivery Status (read only). 0 = no interrupt pending, 1 = interrupt
852 * pending for tranmission to an LAPIC. Note that this bit does not
853 * indicate whether the interrupt has been processed or is undergoing
854 * processing by a cpu.
855 */
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856#define IOART_DELIVS 0x00001000 /* RO: delivery status */
857
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858/*
859 * Destination mode.
860 *
861 * In physical mode the destination APIC is identified by its ID.
862 * Bits 56-59 specify the 4 bit APIC ID.
863 *
864 * In logical mode destinations are identified by matching on the logical
865 * destination under the control of the destination format register and
866 * logical destination register in each local APIC.
867 *
868 */
984263bc 869#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
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870#define IOART_DESTPHY 0x00000000 /* physical */
871#define IOART_DESTLOG 0x00000800 /* logical */
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873/*
874 * Delivery mode.
875 *
876 * 000 Fixed Deliver the signal on the INTR signal for
877 * all processor core's LAPICs listed in the
878 * destination. The trigger mode may be
879 * edge or level.
880 *
881 * 001 Lowest Pri Deliver to the processor core whos LAPIC
882 * is operating at the lowest priority (TPR).
883 * The trigger mode may be edge or level.
884 *
885 * 010 SMI System management interrupt. the vector
886 * information is ignored but must be programmed
887 * to all zero's for future compatibility.
888 * Must be edge triggered.
889 *
890 * 011 Reserved
891 *
892 * 100 NMI Deliver on the NMI signal for all cpu cores
893 * listed in the destination. Vector information
894 * is ignored. NMIs are treated as edge triggered
895 * interrupts even if programmed as level
896 * triggered. For proper operation the pin must
897 * be programmed as an edge trigger.
898 *
899 * 101 INIT Deliver to all processor cores listed in
900 * the destination by asserting their INIT signal.
901 * All addressed LAPICs will assume their INIT
902 * state. Always treated as edge-triggered even
903 * if programmed as level. For proper operation
904 * the pin must be programed as an edge trigger.
905 *
906 * 110 Reserved
907 *
908 * 111 ExINT Deliver as an INTR signal to all processor
909 * cores listed in the destination as an
910 * interrupt originating in an externally
911 * connected interrupt controller.
912 * The INTA cycle corresponding to this ExINT
913 * will be routed to the external controller
914 * that is expected to supply the vector.
915 * Must be edge triggered.
916 *
917 */
984263bc 918#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
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919#define IOART_DELFIXED 0x00000000 /* fixed */
920#define IOART_DELLOPRI 0x00000100 /* lowest priority */
921#define IOART_DELSMI 0x00000200 /* System Management INT */
922#define IOART_DELRSV1 0x00000300 /* reserved */
923#define IOART_DELNMI 0x00000400 /* NMI signal */
924#define IOART_DELINIT 0x00000500 /* INIT signal */
925#define IOART_DELRSV2 0x00000600 /* reserved */
926#define IOART_DELEXINT 0x00000700 /* External INTerrupt */
984263bc 927
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928/*
929 * The interrupt vector. Valid values range from 0x10 to 0xFE.
930 */
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931#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
932
933#endif /* _MACHINE_APIC_H_ */