kernel - SMP - "Fix AP #%d (PHY# %d) failed" issues
[dragonfly.git] / sys / platform / pc32 / apic / mpapic.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
0ca0cd25 26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
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27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
b12a1521 31#include <sys/kernel.h>
72740893 32#include <machine/globaldata.h>
984263bc 33#include <machine/smp.h>
90e8a35b 34#include <machine/cputypes.h>
d595a6c0 35#include <machine/md_var.h>
ad52b37b 36#include <machine/pmap.h>
a9295349 37#include <machine_base/apic/mpapic.h>
984263bc 38#include <machine/segments.h>
96728c05 39#include <sys/thread2.h>
984263bc 40
a9295349 41#include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
984263bc 42
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43/* XXX */
44extern pt_entry_t *SMPpt;
45
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46/* EISA Edge/Level trigger control registers */
47#define ELCR0 0x4d0 /* eisa irq 0-7 */
48#define ELCR1 0x4d1 /* eisa irq 8-15 */
49
b52c8db0 50static void lapic_timer_calibrate(void);
086575e9 51static void lapic_timer_set_divisor(int);
a9e511df 52static void lapic_timer_fixup_handler(void *);
76c58571 53static void lapic_timer_restart_handler(void *);
c5b8324c 54
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55void lapic_timer_process(void);
56void lapic_timer_process_frame(struct intrframe *);
c5b8324c 57
ef612539 58static int lapic_timer_enable = 1;
c5b8324c 59TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 60
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61static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
62static void lapic_timer_intr_enable(struct cputimer_intr *);
63static void lapic_timer_intr_restart(struct cputimer_intr *);
64static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65
66static struct cputimer_intr lapic_cputimer_intr = {
67 .freq = 0,
68 .reload = lapic_timer_intr_reload,
69 .enable = lapic_timer_intr_enable,
70 .config = cputimer_intr_default_config,
71 .restart = lapic_timer_intr_restart,
72 .pmfixup = lapic_timer_intr_pmfixup,
73 .initclock = cputimer_intr_default_initclock,
74 .next = SLIST_ENTRY_INITIALIZER,
75 .name = "lapic",
76 .type = CPUTIMER_INTR_LAPIC,
77 .prio = CPUTIMER_INTR_PRIO_LAPIC,
78 .caps = CPUTIMER_INTR_CAP_NONE
79};
80
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81/*
82 * pointers to pmapped apic hardware.
83 */
84
984263bc 85volatile ioapic_t **ioapic;
984263bc 86
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87static int lapic_timer_divisor_idx = -1;
88static const uint32_t lapic_timer_divisors[] = {
89 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
90 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
91};
92#define APIC_TIMER_NDIVISORS \
93 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
94
95
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96/*
97 * Enable APIC, configure interrupts.
98 */
99void
b52c8db0 100apic_initialize(boolean_t bsp)
984263bc 101{
78ea5a2a 102 uint32_t timer;
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103 u_int temp;
104
9d6bf2df 105 /*
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106 * setup LVT1 as ExtINT on the BSP. This is theoretically an
107 * aggregate interrupt input from the 8259. The INTA cycle
108 * will be routed to the external controller (the 8259) which
109 * is expected to supply the vector.
110 *
111 * Must be setup edge triggered, active high.
112 *
113 * Disable LVT1 on the APs. It doesn't matter what delivery
114 * mode we use because we leave it masked.
9d6bf2df 115 */
984263bc 116 temp = lapic.lvt_lint0;
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117 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
118 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
72740893 119 if (mycpu->gd_cpuid == 0)
9d6bf2df 120 temp |= APIC_LVT_DM_EXTINT;
984263bc 121 else
97359a5b 122 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
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123 lapic.lvt_lint0 = temp;
124
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125 /*
126 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
127 */
984263bc 128 temp = lapic.lvt_lint1;
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129 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
130 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
131 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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132 lapic.lvt_lint1 = temp;
133
d9eea1a5 134 /*
c6a1aabe 135 * Mask the apic error interrupt, apic performance counter
78ea5a2a 136 * interrupt.
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137 */
138 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
139 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
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140
141 /* Set apic timer vector and mask the apic timer interrupt. */
142 timer = lapic.lvt_timer;
143 timer &= ~APIC_LVTT_VECTOR;
144 timer |= XTIMER_OFFSET;
145 timer |= APIC_LVTT_MASKED;
146 lapic.lvt_timer = timer;
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147
148 /*
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149 * Set the Task Priority Register as needed. At the moment allow
150 * interrupts on all cpus (the APs will remain CLId until they are
151 * ready to deal). We could disable all but IPIs by setting
152 * temp |= TPR_IPI_ONLY for cpu != 0.
153 */
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154 temp = lapic.tpr;
155 temp &= ~APIC_TPR_PRIO; /* clear priority field */
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156#ifndef APIC_IO
157 /*
158 * If we are NOT running the IO APICs, the LAPIC will only be used
159 * for IPIs. Set the TPR to prevent any unintentional interrupts.
160 */
161 temp |= TPR_IPI_ONLY;
162#endif
8a8d5d85 163
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164 lapic.tpr = temp;
165
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166 /*
167 * enable the local APIC
168 */
984263bc 169 temp = lapic.svr;
9d6bf2df 170 temp |= APIC_SVR_ENABLE; /* enable the APIC */
97359a5b 171 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 172
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173 /*
174 * Set the spurious interrupt vector. The low 4 bits of the vector
175 * must be 1111.
176 */
177 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 178 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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179 temp &= ~APIC_SVR_VECTOR;
180 temp |= XSPURIOUSINT_OFFSET;
984263bc 181
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182 lapic.svr = temp;
183
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184 /*
185 * Pump out a few EOIs to clean out interrupts that got through
186 * before we were able to set the TPR.
187 */
188 lapic.eoi = 0;
189 lapic.eoi = 0;
190 lapic.eoi = 0;
191
c5b8324c 192 if (bsp) {
b52c8db0 193 lapic_timer_calibrate();
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194 if (lapic_timer_enable) {
195 cputimer_intr_register(&lapic_cputimer_intr);
196 cputimer_intr_select(&lapic_cputimer_intr, 0);
197 }
c5b8324c 198 } else {
086575e9 199 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 200 }
b52c8db0 201
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202 if (bootverbose)
203 apic_dump("apic_initialize()");
204}
205
206
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207static void
208lapic_timer_set_divisor(int divisor_idx)
209{
210 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
211 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
212}
213
214static void
215lapic_timer_oneshot(u_int count)
216{
217 uint32_t value;
218
219 value = lapic.lvt_timer;
220 value &= ~APIC_LVTT_PERIODIC;
221 lapic.lvt_timer = value;
222 lapic.icr_timer = count;
223}
224
225static void
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226lapic_timer_oneshot_quick(u_int count)
227{
228 lapic.icr_timer = count;
229}
230
231static void
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232lapic_timer_calibrate(void)
233{
47bdf646 234 sysclock_t value;
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235
236 /* Try to calibrate the local APIC timer. */
237 for (lapic_timer_divisor_idx = 0;
238 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
239 lapic_timer_divisor_idx++) {
240 lapic_timer_set_divisor(lapic_timer_divisor_idx);
241 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
242 DELAY(2000000);
243 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
244 if (value != APIC_TIMER_MAX_COUNT)
245 break;
246 }
247 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
248 panic("lapic: no proper timer divisor?!\n");
ef612539 249 lapic_cputimer_intr.freq = value / 2;
b52c8db0 250
47bdf646 251 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 252 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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253}
254
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255static void
256lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
257{
258 sysclock_t count;
259
260 gd->gd_timer_running = 0;
261
262 count = sys_cputimer->count();
263 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
264 systimer_intr(&count, 0, frame);
265}
266
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267void
268lapic_timer_process(void)
269{
ae48d6cd 270 lapic_timer_process_oncpu(mycpu, NULL);
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271}
272
273void
274lapic_timer_process_frame(struct intrframe *frame)
275{
ae48d6cd 276 lapic_timer_process_oncpu(mycpu, frame);
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277}
278
c5b8324c 279static void
ef612539 280lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
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281{
282 struct globaldata *gd = mycpu;
283
ef612539 284 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
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285 if (reload < 2)
286 reload = 2;
287
288 if (gd->gd_timer_running) {
289 if (reload < lapic.ccr_timer)
290 lapic_timer_oneshot_quick(reload);
291 } else {
292 gd->gd_timer_running = 1;
293 lapic_timer_oneshot_quick(reload);
294 }
295}
296
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297static void
298lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
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299{
300 uint32_t timer;
301
302 timer = lapic.lvt_timer;
303 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
304 lapic.lvt_timer = timer;
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305
306 lapic_timer_fixup_handler(NULL);
307}
308
309static void
76c58571 310lapic_timer_fixup_handler(void *arg)
a9e511df 311{
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312 int *started = arg;
313
314 if (started != NULL)
315 *started = 0;
316
90e8a35b 317 if (cpu_vendor_id == CPU_VENDOR_AMD) {
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318 /*
319 * Detect the presence of C1E capability mostly on latest
320 * dual-cores (or future) k8 family. This feature renders
321 * the local APIC timer dead, so we disable it by reading
322 * the Interrupt Pending Message register and clearing both
323 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
324 *
325 * Reference:
326 * "BIOS and Kernel Developer's Guide for AMD NPT
327 * Family 0Fh Processors"
328 * #32559 revision 3.00
329 */
330 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
331 (cpu_id & 0x0fff0000) >= 0x00040000) {
332 uint64_t msr;
333
334 msr = rdmsr(0xc0010055);
335 if (msr & 0x18000000) {
336 struct globaldata *gd = mycpu;
337
338 kprintf("cpu%d: AMD C1E detected\n",
339 gd->gd_cpuid);
340 wrmsr(0xc0010055, msr & ~0x18000000ULL);
341
342 /*
343 * We are kinda stalled;
344 * kick start again.
345 */
346 gd->gd_timer_running = 1;
347 lapic_timer_oneshot_quick(2);
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348
349 if (started != NULL)
350 *started = 1;
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351 }
352 }
353 }
354}
355
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356static void
357lapic_timer_restart_handler(void *dummy __unused)
358{
359 int started;
360
361 lapic_timer_fixup_handler(&started);
362 if (!started) {
363 struct globaldata *gd = mycpu;
364
365 gd->gd_timer_running = 1;
366 lapic_timer_oneshot_quick(2);
367 }
368}
369
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370/*
371 * This function is called only by ACPI-CA code currently:
372 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
373 * module controls PM. So once ACPI-CA is attached, we try
374 * to apply the fixup to prevent LAPIC timer from hanging.
375 */
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376static void
377lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 378{
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379 lwkt_send_ipiq_mask(smp_active_mask,
380 lapic_timer_fixup_handler, NULL);
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381}
382
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383static void
384lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 385{
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386 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
387}
388
b52c8db0 389
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390/*
391 * dump contents of local APIC registers
392 */
393void
394apic_dump(char* str)
395{
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396 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
397 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
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398 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
399}
400
401
402#if defined(APIC_IO)
403
404/*
405 * IO APIC code,
406 */
407
408#define IOAPIC_ISA_INTS 16
409#define REDIRCNT_IOAPIC(A) \
410 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
411
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412static int trigger (int apic, int pin, u_int32_t * flags);
413static void polarity (int apic, int pin, u_int32_t * flags, int level);
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414
415#define DEFAULT_FLAGS \
416 ((u_int32_t) \
417 (IOART_INTMSET | \
418 IOART_DESTPHY | \
419 IOART_DELLOPRI))
420
421#define DEFAULT_ISA_FLAGS \
422 ((u_int32_t) \
423 (IOART_INTMSET | \
424 IOART_TRGREDG | \
425 IOART_INTAHI | \
426 IOART_DESTPHY | \
427 IOART_DELLOPRI))
428
429void
430io_apic_set_id(int apic, int id)
431{
432 u_int32_t ux;
433
434 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
435 if (((ux & APIC_ID_MASK) >> 24) != id) {
26be20a0 436 kprintf("Changing APIC ID for IO APIC #%d"
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437 " from %d to %d on chip\n",
438 apic, ((ux & APIC_ID_MASK) >> 24), id);
439 ux &= ~APIC_ID_MASK; /* clear the ID field */
440 ux |= (id << 24);
441 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
442 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
443 if (((ux & APIC_ID_MASK) >> 24) != id)
444 panic("can't control IO APIC #%d ID, reg: 0x%08x",
445 apic, ux);
446 }
447}
448
449
450int
451io_apic_get_id(int apic)
452{
453 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
454}
455
456
457
458/*
459 * Setup the IO APIC.
460 */
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461void
462io_apic_setup_intpin(int apic, int pin)
463{
464 int bus, bustype, irq;
465 u_char select; /* the select register is 8 bits */
466 u_int32_t flags; /* the window register is 32 bits */
467 u_int32_t target; /* the window register is 32 bits */
468 u_int32_t vector; /* the window register is 32 bits */
469 int level;
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470 int cpuid;
471 char envpath[32];
984263bc 472
984263bc 473 select = pin * 2 + IOAPIC_REDTBL0; /* register */
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474
475 /*
476 * Always clear an IO APIC pin before [re]programming it. This is
477 * particularly important if the pin is set up for a level interrupt
478 * as the IOART_REM_IRR bit might be set. When we reprogram the
479 * vector any EOI from pending ints on this pin could be lost and
480 * IRR might never get reset.
984263bc 481 *
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482 * To fix this problem, clear the vector and make sure it is
483 * programmed as an edge interrupt. This should theoretically
484 * clear IRR so we can later, safely program it as a level
485 * interrupt.
984263bc 486 */
8a8d5d85 487 imen_lock();
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488
489 flags = io_apic_read(apic, select) & IOART_RESV;
490 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
491 flags |= IOART_DESTPHY | IOART_DELFIXED;
492
493 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
494 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
495
496 vector = 0;
497
498 io_apic_write(apic, select, flags | vector);
499 io_apic_write(apic, select + 1, target);
500
8a8d5d85 501 imen_unlock();
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502
503 /*
504 * We only deal with vectored interrupts here. ? documentation is
505 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
506 * vs ExTINT, etc.
507 *
508 * This test also catches unconfigured pins.
509 */
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510 if (apic_int_type(apic, pin) != 0)
511 return;
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512
513 /*
514 * Leave the pin unprogrammed if it does not correspond to
515 * an IRQ.
516 */
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517 irq = apic_irq(apic, pin);
518 if (irq < 0)
519 return;
520
521 /* determine the bus type for this pin */
522 bus = apic_src_bus_id(apic, pin);
65de6d19 523 if (bus < 0)
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524 return;
525 bustype = apic_bus_type(bus);
526
527 if ((bustype == ISA) &&
528 (pin < IOAPIC_ISA_INTS) &&
529 (irq == pin) &&
530 (apic_polarity(apic, pin) == 0x1) &&
531 (apic_trigger(apic, pin) == 0x3)) {
532 /*
533 * A broken BIOS might describe some ISA
534 * interrupts as active-high level-triggered.
535 * Use default ISA flags for those interrupts.
536 */
537 flags = DEFAULT_ISA_FLAGS;
538 } else {
539 /*
540 * Program polarity and trigger mode according to
541 * interrupt entry.
542 */
543 flags = DEFAULT_FLAGS;
544 level = trigger(apic, pin, &flags);
545 if (level == 1)
0f546930 546 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
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547 polarity(apic, pin, &flags, level);
548 }
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549
550 cpuid = 0;
551 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
552 kgetenv_int(envpath, &cpuid);
553
554 /* ncpus may not be available yet */
555 if (cpuid > mp_naps)
556 cpuid = 0;
557
5737d650 558 if (bootverbose) {
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559 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
560 apic, pin, irq, cpuid);
5737d650 561 }
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562
563 /*
564 * Program the appropriate registers. This routing may be
565 * overridden when an interrupt handler for a device is
9d522d14 566 * actually added (see register_int(), which calls through
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567 * the MACHINTR ABI to set up an interrupt handler/vector).
568 *
569 * The order in which we must program the two registers for
570 * safety is unclear! XXX
571 */
8a8d5d85 572 imen_lock();
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573
574 vector = IDT_OFFSET + irq; /* IDT vec */
575 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
0c8fbc51 576 /* Deliver all interrupts to CPU0 (BSP) */
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577 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
578 IOART_HI_DEST_MASK;
65de6d19 579 flags |= io_apic_read(apic, select) & IOART_RESV;
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580 io_apic_write(apic, select, flags | vector);
581 io_apic_write(apic, select + 1, target);
65de6d19 582
8a8d5d85 583 imen_unlock();
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584}
585
586int
587io_apic_setup(int apic)
588{
589 int maxpin;
590 int pin;
591
984263bc 592 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
26be20a0 593 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
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594
595 for (pin = 0; pin < maxpin; ++pin) {
596 io_apic_setup_intpin(apic, pin);
597 }
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598 while (pin < 32) {
599 if (apic_int_type(apic, pin) >= 0) {
26be20a0 600 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
1f1464ad
MD
601 " cannot program!\n", apic, pin);
602 }
603 ++pin;
604 }
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605
606 /* return GOOD status */
607 return 0;
608}
609#undef DEFAULT_ISA_FLAGS
610#undef DEFAULT_FLAGS
611
612
613#define DEFAULT_EXTINT_FLAGS \
614 ((u_int32_t) \
615 (IOART_INTMSET | \
616 IOART_TRGREDG | \
617 IOART_INTAHI | \
618 IOART_DESTPHY | \
619 IOART_DELLOPRI))
620
621/*
db958607 622 * XXX this function is only used by 8254 setup
984263bc
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623 * Setup the source of External INTerrupts.
624 */
625int
626ext_int_setup(int apic, int intr)
627{
628 u_char select; /* the select register is 8 bits */
629 u_int32_t flags; /* the window register is 32 bits */
630 u_int32_t target; /* the window register is 32 bits */
631 u_int32_t vector; /* the window register is 32 bits */
db958607
SZ
632 int cpuid;
633 char envpath[32];
984263bc
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634
635 if (apic_int_type(apic, intr) != 3)
636 return -1;
637
db958607
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638 cpuid = 0;
639 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
640 kgetenv_int(envpath, &cpuid);
641
642 /* ncpus may not be available yet */
643 if (cpuid > mp_naps)
644 cpuid = 0;
645
0c8fbc51 646 /* Deliver interrupts to CPU0 (BSP) */
db958607
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647 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
648 IOART_HI_DEST_MASK;
984263bc 649 select = IOAPIC_REDTBL0 + (2 * intr);
97359a5b 650 vector = IDT_OFFSET + intr;
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MD
651 flags = DEFAULT_EXTINT_FLAGS;
652
653 io_apic_write(apic, select, flags | vector);
654 io_apic_write(apic, select + 1, target);
655
656 return 0;
657}
658#undef DEFAULT_EXTINT_FLAGS
659
660
661/*
662 * Set the trigger level for an IO APIC pin.
663 */
664static int
665trigger(int apic, int pin, u_int32_t * flags)
666{
667 int id;
668 int eirq;
669 int level;
670 static int intcontrol = -1;
671
672 switch (apic_trigger(apic, pin)) {
673
674 case 0x00:
675 break;
676
677 case 0x01:
678 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
679 return 0;
680
681 case 0x03:
682 *flags |= IOART_TRGRLVL;
683 return 1;
684
685 case -1:
686 default:
687 goto bad;
688 }
689
690 if ((id = apic_src_bus_id(apic, pin)) == -1)
691 goto bad;
692
693 switch (apic_bus_type(id)) {
694 case ISA:
695 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
696 return 0;
697
698 case EISA:
699 eirq = apic_src_bus_irq(apic, pin);
700
701 if (eirq < 0 || eirq > 15) {
26be20a0 702 kprintf("EISA IRQ %d?!?!\n", eirq);
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703 goto bad;
704 }
705
706 if (intcontrol == -1) {
707 intcontrol = inb(ELCR1) << 8;
708 intcontrol |= inb(ELCR0);
26be20a0 709 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
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MD
710 }
711
712 /* Use ELCR settings to determine level or edge mode */
713 level = (intcontrol >> eirq) & 1;
714
715 /*
716 * Note that on older Neptune chipset based systems, any
717 * pci interrupts often show up here and in the ELCR as well
718 * as level sensitive interrupts attributed to the EISA bus.
719 */
720
721 if (level)
722 *flags |= IOART_TRGRLVL;
723 else
724 *flags &= ~IOART_TRGRLVL;
725
726 return level;
727
728 case PCI:
729 *flags |= IOART_TRGRLVL;
730 return 1;
731
732 case -1:
733 default:
734 goto bad;
735 }
736
737bad:
738 panic("bad APIC IO INT flags");
739}
740
741
742/*
743 * Set the polarity value for an IO APIC pin.
744 */
745static void
746polarity(int apic, int pin, u_int32_t * flags, int level)
747{
748 int id;
749
750 switch (apic_polarity(apic, pin)) {
751
752 case 0x00:
753 break;
754
755 case 0x01:
756 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
757 return;
758
759 case 0x03:
760 *flags |= IOART_INTALO;
761 return;
762
763 case -1:
764 default:
765 goto bad;
766 }
767
768 if ((id = apic_src_bus_id(apic, pin)) == -1)
769 goto bad;
770
771 switch (apic_bus_type(id)) {
772 case ISA:
773 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
774 return;
775
776 case EISA:
777 /* polarity converter always gives active high */
778 *flags &= ~IOART_INTALO;
779 return;
780
781 case PCI:
782 *flags |= IOART_INTALO;
783 return;
784
785 case -1:
786 default:
787 goto bad;
788 }
789
790bad:
791 panic("bad APIC IO INT flags");
792}
793
794
795/*
ea689d1c 796 * Print contents of unmasked IRQs.
984263bc 797 */
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798void
799imen_dump(void)
800{
801 int x;
802
26be20a0 803 kprintf("SMP: enabled INTs: ");
ea689d1c
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804 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
805 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
806 kprintf("%d ", x);
807 }
808 kprintf("\n");
984263bc
MD
809}
810
811
812/*
813 * Inter Processor Interrupt functions.
814 */
815
97359a5b 816#endif /* APIC_IO */
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817
818/*
819 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
820 *
821 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
822 * vector is any valid SYSTEM INT vector
823 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
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824 *
825 * A backlog of requests can create a deadlock between cpus. To avoid this
826 * we have to be able to accept IPIs at the same time we are trying to send
827 * them. The critical section prevents us from attempting to send additional
828 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
829 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
830 * to occur but fortunately it does not happen too often.
984263bc 831 */
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832int
833apic_ipi(int dest_type, int vector, int delivery_mode)
834{
835 u_long icr_lo;
836
96728c05
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837 crit_enter();
838 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
839 unsigned int eflags = read_eflags();
840 cpu_enable_intr();
841 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
842 lwkt_process_ipiq();
843 }
844 write_eflags(eflags);
984263bc 845 }
984263bc 846
9d6bf2df 847 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 848 delivery_mode | vector;
984263bc 849 lapic.icr_lo = icr_lo;
96728c05 850 crit_exit();
984263bc
MD
851 return 0;
852}
853
41a01a4d
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854void
855single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
MD
856{
857 u_long icr_lo;
858 u_long icr_hi;
984263bc 859
41a01a4d 860 crit_enter();
96728c05
MD
861 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
862 unsigned int eflags = read_eflags();
863 cpu_enable_intr();
864 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
865 lwkt_process_ipiq();
866 }
867 write_eflags(eflags);
984263bc 868 }
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869 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
870 icr_hi |= (CPU_TO_ID(cpu) << 24);
871 lapic.icr_hi = icr_hi;
872
b2f93ae9 873 /* build ICR_LOW */
9d6bf2df 874 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
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875 | APIC_DEST_DESTFLD | delivery_mode | vector;
876
877 /* write APIC ICR */
878 lapic.icr_lo = icr_lo;
41a01a4d 879 crit_exit();
984263bc
MD
880}
881
41a01a4d
MD
882#if 0
883
884/*
885 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
886 *
887 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
888 * to the target, and the scheduler does not 'poll' for IPI messages.
889 */
890int
891single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
892{
893 u_long icr_lo;
894 u_long icr_hi;
895
896 crit_enter();
897 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
898 crit_exit();
899 return(0);
900 }
901 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
902 icr_hi |= (CPU_TO_ID(cpu) << 24);
903 lapic.icr_hi = icr_hi;
904
905 /* build IRC_LOW */
906 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
907 | APIC_DEST_DESTFLD | delivery_mode | vector;
908
909 /* write APIC ICR */
910 lapic.icr_lo = icr_lo;
911 crit_exit();
912 return(1);
913}
914
915#endif
916
984263bc
MD
917/*
918 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
919 *
96728c05
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920 * target is a bitmask of destination cpus. Vector is any
921 * valid system INT vector. Delivery mode may be either
922 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 923 */
41a01a4d 924void
984263bc
MD
925selected_apic_ipi(u_int target, int vector, int delivery_mode)
926{
96728c05
MD
927 crit_enter();
928 while (target) {
929 int n = bsfl(target);
930 target &= ~(1 << n);
41a01a4d 931 single_apic_ipi(n, vector, delivery_mode);
96728c05
MD
932 }
933 crit_exit();
984263bc 934}
984263bc 935
984263bc
MD
936/*
937 * Timer code, in development...
938 * - suggested by rgrimes@gndrsh.aac.dev.com
939 */
bb467734
MD
940int
941get_apic_timer_frequency(void)
942{
943 return(lapic_cputimer_intr.freq);
944}
984263bc 945
984263bc
MD
946/*
947 * Load a 'downcount time' in uSeconds.
948 */
949void
2942ed63 950set_apic_timer(int us)
984263bc 951{
2942ed63 952 u_int count;
984263bc
MD
953
954 /*
2942ed63
SZ
955 * When we reach here, lapic timer's frequency
956 * must have been calculated as well as the
957 * divisor (lapic.dcr_timer is setup during the
958 * divisor calculation).
984263bc 959 */
ef612539 960 KKASSERT(lapic_cputimer_intr.freq != 0 &&
2942ed63
SZ
961 lapic_timer_divisor_idx >= 0);
962
ef612539 963 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 964 lapic_timer_oneshot(count);
984263bc
MD
965}
966
967
968/*
969 * Read remaining time in timer.
970 */
971int
972read_apic_timer(void)
973{
974#if 0
975 /** XXX FIXME: we need to return the actual remaining time,
976 * for now we just return the remaining count.
977 */
978#else
979 return lapic.ccr_timer;
980#endif
981}
982
983
984/*
985 * Spin-style delay, set delay time in uS, spin till it drains.
986 */
987void
988u_sleep(int count)
989{
990 set_apic_timer(count);
991 while (read_apic_timer())
992 /* spin */ ;
993}
ad52b37b
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994
995void
84cc808b 996lapic_map(vm_offset_t lapic_addr)
ad52b37b
SZ
997{
998 /* Local apic is mapped on last page */
999 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1000 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1001
d557216f 1002 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 1003}
281d9482
SZ
1004
1005static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1006 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1007
1008void
1009lapic_config(void)
1010{
1011 struct lapic_enumerator *e;
1012 int error;
1013
1014 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1015 error = e->lapic_probe(e);
1016 if (!error)
1017 break;
1018 }
1019 if (e == NULL)
1020 panic("can't config lapic\n");
1021
1022 e->lapic_enumerate(e);
1023}
1024
1025void
1026lapic_enumerator_register(struct lapic_enumerator *ne)
1027{
1028 struct lapic_enumerator *e;
1029
1030 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1031 if (e->lapic_prio < ne->lapic_prio) {
1032 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1033 return;
1034 }
1035 }
1036 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1037}