kernel - SMP - "Fix AP #%d (PHY# %d) failed" issues
[dragonfly.git] / sys / platform / pc64 / apic / mpapic.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
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3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
46d4e165 26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
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27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
46d4e165 31#include <sys/kernel.h>
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32#include <machine/globaldata.h>
33#include <machine/smp.h>
46d4e165 34#include <machine/md_var.h>
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35#include <machine_base/apic/mpapic.h>
36#include <machine/segments.h>
37#include <sys/thread2.h>
38
39#include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
40
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41#include "apicvar.h"
42
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43/* EISA Edge/Level trigger control registers */
44#define ELCR0 0x4d0 /* eisa irq 0-7 */
45#define ELCR1 0x4d1 /* eisa irq 8-15 */
46
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47volatile lapic_t *lapic;
48
49static void lapic_timer_calibrate(void);
50static void lapic_timer_set_divisor(int);
51static void lapic_timer_fixup_handler(void *);
52static void lapic_timer_restart_handler(void *);
53
54void lapic_timer_process(void);
55void lapic_timer_process_frame(struct intrframe *);
56
57static int lapic_timer_enable = 1;
58TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
59
60static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61static void lapic_timer_intr_enable(struct cputimer_intr *);
62static void lapic_timer_intr_restart(struct cputimer_intr *);
63static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
64
65static struct cputimer_intr lapic_cputimer_intr = {
66 .freq = 0,
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
74 .name = "lapic",
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
78};
79
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80/*
81 * pointers to pmapped apic hardware.
82 */
83
84volatile ioapic_t **ioapic;
85
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86static int lapic_timer_divisor_idx = -1;
87static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
90};
91#define APIC_TIMER_NDIVISORS \
92 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
93
94
95void
96lapic_eoi(void)
97{
98
99 lapic->eoi = 0;
100}
a9e511df 101
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102/*
103 * Enable APIC, configure interrupts.
104 */
105void
46d4e165 106apic_initialize(boolean_t bsp)
c8fe38ae 107{
46d4e165 108 uint32_t timer;
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109 u_int temp;
110
111 /*
112 * setup LVT1 as ExtINT on the BSP. This is theoretically an
113 * aggregate interrupt input from the 8259. The INTA cycle
114 * will be routed to the external controller (the 8259) which
115 * is expected to supply the vector.
116 *
117 * Must be setup edge triggered, active high.
118 *
119 * Disable LVT1 on the APs. It doesn't matter what delivery
120 * mode we use because we leave it masked.
121 */
46d4e165 122 temp = lapic->lvt_lint0;
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123 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
124 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
125 if (mycpu->gd_cpuid == 0)
126 temp |= APIC_LVT_DM_EXTINT;
127 else
128 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
46d4e165 129 lapic->lvt_lint0 = temp;
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130
131 /*
132 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
133 */
46d4e165 134 temp = lapic->lvt_lint1;
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135 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
136 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
137 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
46d4e165 138 lapic->lvt_lint1 = temp;
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139
140 /*
141 * Mask the apic error interrupt, apic performance counter
46d4e165 142 * interrupt.
c8fe38ae 143 */
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144 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
145 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
146
147 /* Set apic timer vector and mask the apic timer interrupt. */
148 timer = lapic->lvt_timer;
149 timer &= ~APIC_LVTT_VECTOR;
150 timer |= XTIMER_OFFSET;
151 timer |= APIC_LVTT_MASKED;
152 lapic->lvt_timer = timer;
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153
154 /*
155 * Set the Task Priority Register as needed. At the moment allow
156 * interrupts on all cpus (the APs will remain CLId until they are
157 * ready to deal). We could disable all but IPIs by setting
158 * temp |= TPR_IPI_ONLY for cpu != 0.
159 */
46d4e165 160 temp = lapic->tpr;
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161 temp &= ~APIC_TPR_PRIO; /* clear priority field */
162#ifndef APIC_IO
163 /*
164 * If we are NOT running the IO APICs, the LAPIC will only be used
165 * for IPIs. Set the TPR to prevent any unintentional interrupts.
166 */
167 temp |= TPR_IPI_ONLY;
168#endif
169
46d4e165 170 lapic->tpr = temp;
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171
172 /*
173 * enable the local APIC
174 */
46d4e165 175 temp = lapic->svr;
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176 temp |= APIC_SVR_ENABLE; /* enable the APIC */
177 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
178
179 /*
180 * Set the spurious interrupt vector. The low 4 bits of the vector
181 * must be 1111.
182 */
183 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
184 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
185 temp &= ~APIC_SVR_VECTOR;
186 temp |= XSPURIOUSINT_OFFSET;
187
46d4e165 188 lapic->svr = temp;
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189
190 /*
191 * Pump out a few EOIs to clean out interrupts that got through
192 * before we were able to set the TPR.
193 */
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194 lapic_eoi();
195 lapic_eoi();
196 lapic_eoi();
197
198 if (bsp) {
199 lapic_timer_calibrate();
200 if (lapic_timer_enable) {
201 cputimer_intr_register(&lapic_cputimer_intr);
202 cputimer_intr_select(&lapic_cputimer_intr, 0);
203 }
204 } else {
205 lapic_timer_set_divisor(lapic_timer_divisor_idx);
206 }
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207
208 if (bootverbose)
209 apic_dump("apic_initialize()");
210}
211
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212
213static void
214lapic_timer_set_divisor(int divisor_idx)
215{
216 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
217 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
218}
219
220static void
221lapic_timer_oneshot(u_int count)
222{
223 uint32_t value;
224
225 value = lapic->lvt_timer;
226 value &= ~APIC_LVTT_PERIODIC;
227 lapic->lvt_timer = value;
228 lapic->icr_timer = count;
229}
230
231static void
232lapic_timer_oneshot_quick(u_int count)
233{
234 lapic->icr_timer = count;
235}
236
237static void
238lapic_timer_calibrate(void)
239{
240 sysclock_t value;
241
242 /* Try to calibrate the local APIC timer. */
243 for (lapic_timer_divisor_idx = 0;
244 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
245 lapic_timer_divisor_idx++) {
246 lapic_timer_set_divisor(lapic_timer_divisor_idx);
247 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
248 DELAY(2000000);
249 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
250 if (value != APIC_TIMER_MAX_COUNT)
251 break;
252 }
253 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
254 panic("lapic: no proper timer divisor?!\n");
255 lapic_cputimer_intr.freq = value / 2;
256
257 kprintf("lapic: divisor index %d, frequency %u Hz\n",
258 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
259}
260
261static void
262lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
263{
264 sysclock_t count;
265
266 gd->gd_timer_running = 0;
267
268 count = sys_cputimer->count();
269 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
270 systimer_intr(&count, 0, frame);
271}
272
a9e511df 273void
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274lapic_timer_process(void)
275{
276 lapic_timer_process_oncpu(mycpu, NULL);
277}
278
279void
280lapic_timer_process_frame(struct intrframe *frame)
281{
282 lapic_timer_process_oncpu(mycpu, frame);
283}
284
285static void
286lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
287{
288 struct globaldata *gd = mycpu;
289
290 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
291 if (reload < 2)
292 reload = 2;
293
294 if (gd->gd_timer_running) {
295 if (reload < lapic->ccr_timer)
296 lapic_timer_oneshot_quick(reload);
297 } else {
298 gd->gd_timer_running = 1;
299 lapic_timer_oneshot_quick(reload);
300 }
301}
302
303static void
304lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
305{
306 uint32_t timer;
307
308 timer = lapic->lvt_timer;
309 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
310 lapic->lvt_timer = timer;
311
312 lapic_timer_fixup_handler(NULL);
313}
314
315static void
316lapic_timer_fixup_handler(void *arg)
a9e511df 317{
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318 int *started = arg;
319
320 if (started != NULL)
321 *started = 0;
322
323 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
324 /*
325 * Detect the presence of C1E capability mostly on latest
326 * dual-cores (or future) k8 family. This feature renders
327 * the local APIC timer dead, so we disable it by reading
328 * the Interrupt Pending Message register and clearing both
329 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
330 *
331 * Reference:
332 * "BIOS and Kernel Developer's Guide for AMD NPT
333 * Family 0Fh Processors"
334 * #32559 revision 3.00
335 */
336 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
337 (cpu_id & 0x0fff0000) >= 0x00040000) {
338 uint64_t msr;
339
340 msr = rdmsr(0xc0010055);
341 if (msr & 0x18000000) {
342 struct globaldata *gd = mycpu;
343
344 kprintf("cpu%d: AMD C1E detected\n",
345 gd->gd_cpuid);
346 wrmsr(0xc0010055, msr & ~0x18000000ULL);
347
348 /*
349 * We are kinda stalled;
350 * kick start again.
351 */
352 gd->gd_timer_running = 1;
353 lapic_timer_oneshot_quick(2);
354
355 if (started != NULL)
356 *started = 1;
357 }
358 }
359 }
a9e511df 360}
c8fe38ae 361
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362static void
363lapic_timer_restart_handler(void *dummy __unused)
364{
365 int started;
366
367 lapic_timer_fixup_handler(&started);
368 if (!started) {
369 struct globaldata *gd = mycpu;
370
371 gd->gd_timer_running = 1;
372 lapic_timer_oneshot_quick(2);
373 }
374}
375
376/*
377 * This function is called only by ACPI-CA code currently:
378 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
379 * module controls PM. So once ACPI-CA is attached, we try
380 * to apply the fixup to prevent LAPIC timer from hanging.
381 */
382static void
383lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
384{
385 lwkt_send_ipiq_mask(smp_active_mask,
386 lapic_timer_fixup_handler, NULL);
387}
388
389static void
390lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
391{
392 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
393}
394
395
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396/*
397 * dump contents of local APIC registers
398 */
399void
400apic_dump(char* str)
401{
402 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
403 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
46d4e165 404 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
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405}
406
407
408#if defined(APIC_IO)
409
410/*
411 * IO APIC code,
412 */
413
414#define IOAPIC_ISA_INTS 16
415#define REDIRCNT_IOAPIC(A) \
416 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
417
418static int trigger (int apic, int pin, u_int32_t * flags);
419static void polarity (int apic, int pin, u_int32_t * flags, int level);
420
421#define DEFAULT_FLAGS \
422 ((u_int32_t) \
423 (IOART_INTMSET | \
424 IOART_DESTPHY | \
425 IOART_DELLOPRI))
426
427#define DEFAULT_ISA_FLAGS \
428 ((u_int32_t) \
429 (IOART_INTMSET | \
430 IOART_TRGREDG | \
431 IOART_INTAHI | \
432 IOART_DESTPHY | \
433 IOART_DELLOPRI))
434
435void
436io_apic_set_id(int apic, int id)
437{
438 u_int32_t ux;
439
440 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
441 if (((ux & APIC_ID_MASK) >> 24) != id) {
442 kprintf("Changing APIC ID for IO APIC #%d"
443 " from %d to %d on chip\n",
444 apic, ((ux & APIC_ID_MASK) >> 24), id);
445 ux &= ~APIC_ID_MASK; /* clear the ID field */
446 ux |= (id << 24);
447 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
448 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
449 if (((ux & APIC_ID_MASK) >> 24) != id)
450 panic("can't control IO APIC #%d ID, reg: 0x%08x",
451 apic, ux);
452 }
453}
454
455
456int
457io_apic_get_id(int apic)
458{
459 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
460}
461
462
463
464/*
465 * Setup the IO APIC.
466 */
467
468extern int apic_pin_trigger; /* 'opaque' */
469
470void
471io_apic_setup_intpin(int apic, int pin)
472{
473 int bus, bustype, irq;
474 u_char select; /* the select register is 8 bits */
475 u_int32_t flags; /* the window register is 32 bits */
476 u_int32_t target; /* the window register is 32 bits */
477 u_int32_t vector; /* the window register is 32 bits */
478 int level;
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479 int cpuid;
480 char envpath[32];
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481
482 select = pin * 2 + IOAPIC_REDTBL0; /* register */
483
484 /*
485 * Always clear an IO APIC pin before [re]programming it. This is
486 * particularly important if the pin is set up for a level interrupt
487 * as the IOART_REM_IRR bit might be set. When we reprogram the
488 * vector any EOI from pending ints on this pin could be lost and
489 * IRR might never get reset.
490 *
491 * To fix this problem, clear the vector and make sure it is
492 * programmed as an edge interrupt. This should theoretically
493 * clear IRR so we can later, safely program it as a level
494 * interrupt.
495 */
496 imen_lock();
497
498 flags = io_apic_read(apic, select) & IOART_RESV;
499 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
500 flags |= IOART_DESTPHY | IOART_DELFIXED;
501
502 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
503 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
504
505 vector = 0;
506
507 io_apic_write(apic, select, flags | vector);
508 io_apic_write(apic, select + 1, target);
509
510 imen_unlock();
511
512 /*
513 * We only deal with vectored interrupts here. ? documentation is
514 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
515 * vs ExTINT, etc.
516 *
517 * This test also catches unconfigured pins.
518 */
519 if (apic_int_type(apic, pin) != 0)
520 return;
521
522 /*
523 * Leave the pin unprogrammed if it does not correspond to
524 * an IRQ.
525 */
526 irq = apic_irq(apic, pin);
527 if (irq < 0)
528 return;
529
530 /* determine the bus type for this pin */
531 bus = apic_src_bus_id(apic, pin);
532 if (bus < 0)
533 return;
534 bustype = apic_bus_type(bus);
535
536 if ((bustype == ISA) &&
537 (pin < IOAPIC_ISA_INTS) &&
538 (irq == pin) &&
539 (apic_polarity(apic, pin) == 0x1) &&
540 (apic_trigger(apic, pin) == 0x3)) {
541 /*
542 * A broken BIOS might describe some ISA
543 * interrupts as active-high level-triggered.
544 * Use default ISA flags for those interrupts.
545 */
546 flags = DEFAULT_ISA_FLAGS;
547 } else {
548 /*
549 * Program polarity and trigger mode according to
550 * interrupt entry.
551 */
552 flags = DEFAULT_FLAGS;
553 level = trigger(apic, pin, &flags);
554 if (level == 1)
555 apic_pin_trigger |= (1 << irq);
556 polarity(apic, pin, &flags, level);
557 }
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558
559 cpuid = 0;
560 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
561 kgetenv_int(envpath, &cpuid);
562
563 /* ncpus may not be available yet */
564 if (cpuid > mp_naps)
565 cpuid = 0;
566
c8fe38ae 567 if (bootverbose) {
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568 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
569 apic, pin, irq, cpuid);
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570 }
571
572 /*
573 * Program the appropriate registers. This routing may be
574 * overridden when an interrupt handler for a device is
575 * actually added (see register_int(), which calls through
576 * the MACHINTR ABI to set up an interrupt handler/vector).
577 *
578 * The order in which we must program the two registers for
579 * safety is unclear! XXX
580 */
581 imen_lock();
582
583 vector = IDT_OFFSET + irq; /* IDT vec */
584 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
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585 /* Deliver all interrupts to CPU0 (BSP) */
586 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
587 IOART_HI_DEST_MASK;
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588 flags |= io_apic_read(apic, select) & IOART_RESV;
589 io_apic_write(apic, select, flags | vector);
590 io_apic_write(apic, select + 1, target);
591
592 imen_unlock();
593}
594
595int
596io_apic_setup(int apic)
597{
598 int maxpin;
599 int pin;
600
601 if (apic == 0)
602 apic_pin_trigger = 0; /* default to edge-triggered */
603
604 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
605 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
606
607 for (pin = 0; pin < maxpin; ++pin) {
608 io_apic_setup_intpin(apic, pin);
609 }
610 while (pin < 32) {
611 if (apic_int_type(apic, pin) >= 0) {
612 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
613 " cannot program!\n", apic, pin);
614 }
615 ++pin;
616 }
617
618 /* return GOOD status */
619 return 0;
620}
621#undef DEFAULT_ISA_FLAGS
622#undef DEFAULT_FLAGS
623
624
625#define DEFAULT_EXTINT_FLAGS \
626 ((u_int32_t) \
627 (IOART_INTMSET | \
628 IOART_TRGREDG | \
629 IOART_INTAHI | \
630 IOART_DESTPHY | \
631 IOART_DELLOPRI))
632
633/*
46d4e165 634 * XXX this function is only used by 8254 setup
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635 * Setup the source of External INTerrupts.
636 */
637int
638ext_int_setup(int apic, int intr)
639{
640 u_char select; /* the select register is 8 bits */
641 u_int32_t flags; /* the window register is 32 bits */
642 u_int32_t target; /* the window register is 32 bits */
643 u_int32_t vector; /* the window register is 32 bits */
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644 int cpuid;
645 char envpath[32];
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646
647 if (apic_int_type(apic, intr) != 3)
648 return -1;
649
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650 cpuid = 0;
651 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
652 kgetenv_int(envpath, &cpuid);
653
654 /* ncpus may not be available yet */
655 if (cpuid > mp_naps)
656 cpuid = 0;
657
658 /* Deliver interrupts to CPU0 (BSP) */
659 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
660 IOART_HI_DEST_MASK;
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MD
661 select = IOAPIC_REDTBL0 + (2 * intr);
662 vector = IDT_OFFSET + intr;
663 flags = DEFAULT_EXTINT_FLAGS;
664
665 io_apic_write(apic, select, flags | vector);
666 io_apic_write(apic, select + 1, target);
667
668 return 0;
669}
670#undef DEFAULT_EXTINT_FLAGS
671
672
673/*
674 * Set the trigger level for an IO APIC pin.
675 */
676static int
677trigger(int apic, int pin, u_int32_t * flags)
678{
679 int id;
680 int eirq;
681 int level;
682 static int intcontrol = -1;
683
684 switch (apic_trigger(apic, pin)) {
685
686 case 0x00:
687 break;
688
689 case 0x01:
690 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
691 return 0;
692
693 case 0x03:
694 *flags |= IOART_TRGRLVL;
695 return 1;
696
697 case -1:
698 default:
699 goto bad;
700 }
701
702 if ((id = apic_src_bus_id(apic, pin)) == -1)
703 goto bad;
704
705 switch (apic_bus_type(id)) {
706 case ISA:
707 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
708 return 0;
709
710 case EISA:
711 eirq = apic_src_bus_irq(apic, pin);
712
713 if (eirq < 0 || eirq > 15) {
714 kprintf("EISA IRQ %d?!?!\n", eirq);
715 goto bad;
716 }
717
718 if (intcontrol == -1) {
719 intcontrol = inb(ELCR1) << 8;
720 intcontrol |= inb(ELCR0);
721 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
722 }
723
724 /* Use ELCR settings to determine level or edge mode */
725 level = (intcontrol >> eirq) & 1;
726
727 /*
728 * Note that on older Neptune chipset based systems, any
729 * pci interrupts often show up here and in the ELCR as well
730 * as level sensitive interrupts attributed to the EISA bus.
731 */
732
733 if (level)
734 *flags |= IOART_TRGRLVL;
735 else
736 *flags &= ~IOART_TRGRLVL;
737
738 return level;
739
740 case PCI:
741 *flags |= IOART_TRGRLVL;
742 return 1;
743
744 case -1:
745 default:
746 goto bad;
747 }
748
749bad:
750 panic("bad APIC IO INT flags");
751}
752
753
754/*
755 * Set the polarity value for an IO APIC pin.
756 */
757static void
758polarity(int apic, int pin, u_int32_t * flags, int level)
759{
760 int id;
761
762 switch (apic_polarity(apic, pin)) {
763
764 case 0x00:
765 break;
766
767 case 0x01:
768 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
769 return;
770
771 case 0x03:
772 *flags |= IOART_INTALO;
773 return;
774
775 case -1:
776 default:
777 goto bad;
778 }
779
780 if ((id = apic_src_bus_id(apic, pin)) == -1)
781 goto bad;
782
783 switch (apic_bus_type(id)) {
784 case ISA:
785 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
786 return;
787
788 case EISA:
789 /* polarity converter always gives active high */
790 *flags &= ~IOART_INTALO;
791 return;
792
793 case PCI:
794 *flags |= IOART_INTALO;
795 return;
796
797 case -1:
798 default:
799 goto bad;
800 }
801
802bad:
803 panic("bad APIC IO INT flags");
804}
805
806
807/*
808 * Print contents of apic_imen.
809 */
810extern u_int apic_imen; /* keep apic_imen 'opaque' */
811void
812imen_dump(void)
813{
814 int x;
815
816 kprintf("SMP: enabled INTs: ");
817 for (x = 0; x < 24; ++x)
818 if ((apic_imen & (1 << x)) == 0)
819 kprintf("%d, ", x);
820 kprintf("apic_imen: 0x%08x\n", apic_imen);
821}
822
823
824/*
825 * Inter Processor Interrupt functions.
826 */
827
828#endif /* APIC_IO */
829
830/*
831 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
832 *
833 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
834 * vector is any valid SYSTEM INT vector
835 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
836 *
837 * A backlog of requests can create a deadlock between cpus. To avoid this
838 * we have to be able to accept IPIs at the same time we are trying to send
839 * them. The critical section prevents us from attempting to send additional
840 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
841 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
842 * to occur but fortunately it does not happen too often.
843 */
844int
845apic_ipi(int dest_type, int vector, int delivery_mode)
846{
847 u_long icr_lo;
848
849 crit_enter();
46d4e165
JG
850 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
851 unsigned long rflags = read_rflags();
c8fe38ae 852 cpu_enable_intr();
46d4e165 853 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
854 lwkt_process_ipiq();
855 }
46d4e165 856 write_rflags(rflags);
c8fe38ae
MD
857 }
858
46d4e165 859 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
c8fe38ae 860 delivery_mode | vector;
46d4e165 861 lapic->icr_lo = icr_lo;
c8fe38ae
MD
862 crit_exit();
863 return 0;
864}
865
866void
867single_apic_ipi(int cpu, int vector, int delivery_mode)
868{
869 u_long icr_lo;
870 u_long icr_hi;
871
872 crit_enter();
46d4e165
JG
873 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
874 unsigned long rflags = read_rflags();
c8fe38ae 875 cpu_enable_intr();
46d4e165 876 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
877 lwkt_process_ipiq();
878 }
46d4e165 879 write_rflags(rflags);
c8fe38ae 880 }
46d4e165 881 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
c8fe38ae 882 icr_hi |= (CPU_TO_ID(cpu) << 24);
46d4e165 883 lapic->icr_hi = icr_hi;
c8fe38ae 884
b2f93ae9 885 /* build ICR_LOW */
46d4e165 886 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
c8fe38ae
MD
887 | APIC_DEST_DESTFLD | delivery_mode | vector;
888
889 /* write APIC ICR */
46d4e165 890 lapic->icr_lo = icr_lo;
c8fe38ae
MD
891 crit_exit();
892}
893
894#if 0
895
896/*
897 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
898 *
899 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
900 * to the target, and the scheduler does not 'poll' for IPI messages.
901 */
902int
903single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
904{
905 u_long icr_lo;
906 u_long icr_hi;
907
908 crit_enter();
46d4e165 909 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
c8fe38ae
MD
910 crit_exit();
911 return(0);
912 }
46d4e165 913 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
c8fe38ae 914 icr_hi |= (CPU_TO_ID(cpu) << 24);
46d4e165 915 lapic->icr_hi = icr_hi;
c8fe38ae
MD
916
917 /* build IRC_LOW */
46d4e165 918 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
c8fe38ae
MD
919 | APIC_DEST_DESTFLD | delivery_mode | vector;
920
921 /* write APIC ICR */
46d4e165 922 lapic->icr_lo = icr_lo;
c8fe38ae
MD
923 crit_exit();
924 return(1);
925}
926
927#endif
928
929/*
930 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
931 *
932 * target is a bitmask of destination cpus. Vector is any
933 * valid system INT vector. Delivery mode may be either
934 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
935 */
936void
937selected_apic_ipi(u_int target, int vector, int delivery_mode)
938{
939 crit_enter();
940 while (target) {
941 int n = bsfl(target);
942 target &= ~(1 << n);
943 single_apic_ipi(n, vector, delivery_mode);
944 }
945 crit_exit();
946}
947
948/*
949 * Timer code, in development...
950 * - suggested by rgrimes@gndrsh.aac.dev.com
951 */
bb467734
MD
952int
953get_apic_timer_frequency(void)
954{
955 return(lapic_cputimer_intr.freq);
956}
c8fe38ae 957
c8fe38ae
MD
958/*
959 * Load a 'downcount time' in uSeconds.
960 */
961void
46d4e165 962set_apic_timer(int us)
c8fe38ae 963{
46d4e165 964 u_int count;
c8fe38ae
MD
965
966 /*
46d4e165
JG
967 * When we reach here, lapic timer's frequency
968 * must have been calculated as well as the
969 * divisor (lapic->dcr_timer is setup during the
970 * divisor calculation).
c8fe38ae 971 */
46d4e165
JG
972 KKASSERT(lapic_cputimer_intr.freq != 0 &&
973 lapic_timer_divisor_idx >= 0);
974
975 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
976 lapic_timer_oneshot(count);
c8fe38ae
MD
977}
978
979
980/*
981 * Read remaining time in timer.
982 */
983int
984read_apic_timer(void)
985{
986#if 0
987 /** XXX FIXME: we need to return the actual remaining time,
988 * for now we just return the remaining count.
989 */
990#else
46d4e165 991 return lapic->ccr_timer;
c8fe38ae
MD
992#endif
993}
994
995
996/*
997 * Spin-style delay, set delay time in uS, spin till it drains.
998 */
999void
1000u_sleep(int count)
1001{
1002 set_apic_timer(count);
1003 while (read_apic_timer())
1004 /* spin */ ;
1005}