iwn - Clean up memory freeing.
[dragonfly.git] / sys / dev / netif / iwn / if_iwn.c
CommitLineData
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1/*-
2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
4 * Copyright (c) 2008
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/*
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
23 * adapters.
24 */
25
3db796ac 26/* $FreeBSD$ */
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27
28#include <sys/param.h>
29#include <sys/sockio.h>
30#include <sys/sysctl.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>
37#include <sys/rman.h>
38#include <sys/endian.h>
39#include <sys/firmware.h>
40#include <sys/limits.h>
41#include <sys/module.h>
42#include <sys/queue.h>
43#include <sys/taskqueue.h>
3db796ac 44#include <sys/libkern.h>
ffd7c74a 45
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46#include <sys/bus.h>
47#include <sys/resource.h>
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48#include <machine/clock.h>
49
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50#include <bus/pci/pcireg.h>
51#include <bus/pci/pcivar.h>
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52
53#include <net/bpf.h>
54#include <net/if.h>
55#include <net/if_arp.h>
3db796ac 56#include <net/ifq_var.h>
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57#include <net/ethernet.h>
58#include <net/if_dl.h>
59#include <net/if_media.h>
60#include <net/if_types.h>
61
62#include <netinet/in.h>
63#include <netinet/in_systm.h>
64#include <netinet/in_var.h>
65#include <netinet/if_ether.h>
66#include <netinet/ip.h>
67
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68#include <netproto/802_11/ieee80211_var.h>
69#include <netproto/802_11/ieee80211_radiotap.h>
70#include <netproto/802_11/ieee80211_regdomain.h>
71#include <netproto/802_11/ieee80211_ratectl.h>
ffd7c74a 72
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73#include "if_iwnreg.h"
74#include "if_iwnvar.h"
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75
76static int iwn_probe(device_t);
77static int iwn_attach(device_t);
78static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *);
79static void iwn_radiotap_attach(struct iwn_softc *);
80static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
81 const char name[IFNAMSIZ], int unit, int opmode,
82 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
83 const uint8_t mac[IEEE80211_ADDR_LEN]);
84static void iwn_vap_delete(struct ieee80211vap *);
85static int iwn_cleanup(device_t);
86static int iwn_detach(device_t);
87static int iwn_nic_lock(struct iwn_softc *);
88static int iwn_eeprom_lock(struct iwn_softc *);
89static int iwn_init_otprom(struct iwn_softc *);
90static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
91static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
92static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
93 void **, bus_size_t, bus_size_t, int);
94static void iwn_dma_contig_free(struct iwn_dma_info *);
95static int iwn_alloc_sched(struct iwn_softc *);
96static void iwn_free_sched(struct iwn_softc *);
97static int iwn_alloc_kw(struct iwn_softc *);
98static void iwn_free_kw(struct iwn_softc *);
99static int iwn_alloc_ict(struct iwn_softc *);
100static void iwn_free_ict(struct iwn_softc *);
101static int iwn_alloc_fwmem(struct iwn_softc *);
102static void iwn_free_fwmem(struct iwn_softc *);
103static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
104static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
105static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
106static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
107 int);
108static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
109static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
110static void iwn5000_ict_reset(struct iwn_softc *);
111static int iwn_read_eeprom(struct iwn_softc *,
112 uint8_t macaddr[IEEE80211_ADDR_LEN]);
113static void iwn4965_read_eeprom(struct iwn_softc *);
114static void iwn4965_print_power_group(struct iwn_softc *, int);
115static void iwn5000_read_eeprom(struct iwn_softc *);
116static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
117static void iwn_read_eeprom_band(struct iwn_softc *, int);
118#if 0 /* HT */
119static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
120#endif
121static void iwn_read_eeprom_channels(struct iwn_softc *, int,
122 uint32_t);
123static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
124static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
125 const uint8_t mac[IEEE80211_ADDR_LEN]);
126static void iwn_newassoc(struct ieee80211_node *, int);
127static int iwn_media_change(struct ifnet *);
128static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
129static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
130 struct iwn_rx_data *);
131static void iwn_timer_timeout(void *);
132static void iwn_calib_reset(struct iwn_softc *);
133static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
134 struct iwn_rx_data *);
135#if 0 /* HT */
136static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
137 struct iwn_rx_data *);
138#endif
139static void iwn5000_rx_calib_results(struct iwn_softc *,
140 struct iwn_rx_desc *, struct iwn_rx_data *);
141static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
142 struct iwn_rx_data *);
143static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
144 struct iwn_rx_data *);
145static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
146 struct iwn_rx_data *);
147static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
148 uint8_t);
149static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
150static void iwn_notif_intr(struct iwn_softc *);
151static void iwn_wakeup_intr(struct iwn_softc *);
152static void iwn_rftoggle_intr(struct iwn_softc *);
153static void iwn_fatal_intr(struct iwn_softc *);
154static void iwn_intr(void *);
155static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
156 uint16_t);
157static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
158 uint16_t);
159#ifdef notyet
160static void iwn5000_reset_sched(struct iwn_softc *, int, int);
161#endif
162static uint8_t iwn_plcp_signal(int);
163static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
164 struct ieee80211_node *, struct iwn_tx_ring *);
165static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
166 const struct ieee80211_bpf_params *);
167static void iwn_start(struct ifnet *);
168static void iwn_start_locked(struct ifnet *);
169static void iwn_watchdog(struct iwn_softc *sc);
3db796ac 170static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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171static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
172static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
173 int);
174static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
175 int);
176static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int);
177static int iwn_add_broadcast_node(struct iwn_softc *, int);
178static int iwn_wme_update(struct ieee80211com *);
179static void iwn_update_mcast(struct ifnet *);
180static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
181static int iwn_set_critical_temp(struct iwn_softc *);
182static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
183static void iwn4965_power_calibration(struct iwn_softc *, int);
184static int iwn4965_set_txpower(struct iwn_softc *,
185 struct ieee80211_channel *, int);
186static int iwn5000_set_txpower(struct iwn_softc *,
187 struct ieee80211_channel *, int);
188static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
189static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
190static int iwn_get_noise(const struct iwn_rx_general_stats *);
191static int iwn4965_get_temperature(struct iwn_softc *);
192static int iwn5000_get_temperature(struct iwn_softc *);
193static int iwn_init_sensitivity(struct iwn_softc *);
194static void iwn_collect_noise(struct iwn_softc *,
195 const struct iwn_rx_general_stats *);
196static int iwn4965_init_gains(struct iwn_softc *);
197static int iwn5000_init_gains(struct iwn_softc *);
198static int iwn4965_set_gains(struct iwn_softc *);
199static int iwn5000_set_gains(struct iwn_softc *);
200static void iwn_tune_sensitivity(struct iwn_softc *,
201 const struct iwn_rx_stats *);
202static int iwn_send_sensitivity(struct iwn_softc *);
203static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
204static int iwn_config(struct iwn_softc *);
205static int iwn_scan(struct iwn_softc *);
206static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
207static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
208#if 0 /* HT */
209static int iwn_ampdu_rx_start(struct ieee80211com *,
210 struct ieee80211_node *, uint8_t);
211static void iwn_ampdu_rx_stop(struct ieee80211com *,
212 struct ieee80211_node *, uint8_t);
213static int iwn_ampdu_tx_start(struct ieee80211com *,
214 struct ieee80211_node *, uint8_t);
215static void iwn_ampdu_tx_stop(struct ieee80211com *,
216 struct ieee80211_node *, uint8_t);
217static void iwn4965_ampdu_tx_start(struct iwn_softc *,
218 struct ieee80211_node *, uint8_t, uint16_t);
219static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
220static void iwn5000_ampdu_tx_start(struct iwn_softc *,
221 struct ieee80211_node *, uint8_t, uint16_t);
222static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
223#endif
224static int iwn5000_query_calibration(struct iwn_softc *);
225static int iwn5000_send_calibration(struct iwn_softc *);
226static int iwn5000_send_wimax_coex(struct iwn_softc *);
227static int iwn4965_post_alive(struct iwn_softc *);
228static int iwn5000_post_alive(struct iwn_softc *);
229static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
230 int);
231static int iwn4965_load_firmware(struct iwn_softc *);
232static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
233 const uint8_t *, int);
234static int iwn5000_load_firmware(struct iwn_softc *);
235static int iwn_read_firmware(struct iwn_softc *);
236static int iwn_clock_wait(struct iwn_softc *);
237static int iwn_apm_init(struct iwn_softc *);
238static void iwn_apm_stop_master(struct iwn_softc *);
239static void iwn_apm_stop(struct iwn_softc *);
240static int iwn4965_nic_config(struct iwn_softc *);
241static int iwn5000_nic_config(struct iwn_softc *);
242static int iwn_hw_prepare(struct iwn_softc *);
243static int iwn_hw_init(struct iwn_softc *);
244static void iwn_hw_stop(struct iwn_softc *);
245static void iwn_init_locked(struct iwn_softc *);
246static void iwn_init(void *);
247static void iwn_stop_locked(struct iwn_softc *);
248static void iwn_stop(struct iwn_softc *);
249static void iwn_scan_start(struct ieee80211com *);
250static void iwn_scan_end(struct ieee80211com *);
251static void iwn_set_channel(struct ieee80211com *);
252static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
253static void iwn_scan_mindwell(struct ieee80211_scan_state *);
254static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
255 struct ieee80211_channel *);
256static int iwn_setregdomain(struct ieee80211com *,
257 struct ieee80211_regdomain *, int,
258 struct ieee80211_channel []);
259static void iwn_hw_reset(void *, int);
260static void iwn_radio_on(void *, int);
261static void iwn_radio_off(void *, int);
262static void iwn_sysctlattach(struct iwn_softc *);
263static int iwn_shutdown(device_t);
264static int iwn_suspend(device_t);
265static int iwn_resume(device_t);
266
267#define IWN_DEBUG
268#ifdef IWN_DEBUG
269enum {
270 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
271 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
272 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
273 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
274 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
275 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
276 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
277 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
278 IWN_DEBUG_INTR = 0x00000100, /* ISR */
279 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
280 IWN_DEBUG_NODE = 0x00000400, /* node management */
281 IWN_DEBUG_LED = 0x00000800, /* led management */
282 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
283 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
284 IWN_DEBUG_ANY = 0xffffffff
285};
286
287#define DPRINTF(sc, m, fmt, ...) do { \
288 if (sc->sc_debug & (m)) \
3db796ac 289 kprintf(fmt, __VA_ARGS__); \
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290} while (0)
291
292static const char *iwn_intr_str(uint8_t);
293#else
294#define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
295#endif
296
297struct iwn_ident {
298 uint16_t vendor;
299 uint16_t device;
300 const char *name;
301};
302
303static const struct iwn_ident iwn_ident_table [] = {
304 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" },
305 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" },
306 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" },
307 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" },
308 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" },
309 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" },
310 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" },
311 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" },
312 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" },
313 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" },
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314 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" },
315 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" },
316 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" },
317 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" },
318 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" },
319 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" },
320 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" },
321 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" },
322 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" },
323 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" },
324 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" },
325 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" },
326 { 0, 0, NULL }
327};
328
329static const struct iwn_hal iwn4965_hal = {
330 iwn4965_load_firmware,
331 iwn4965_read_eeprom,
332 iwn4965_post_alive,
333 iwn4965_nic_config,
334 iwn4965_update_sched,
335 iwn4965_get_temperature,
336 iwn4965_get_rssi,
337 iwn4965_set_txpower,
338 iwn4965_init_gains,
339 iwn4965_set_gains,
340 iwn4965_add_node,
341 iwn4965_tx_done,
342#if 0 /* HT */
343 iwn4965_ampdu_tx_start,
344 iwn4965_ampdu_tx_stop,
345#endif
346 IWN4965_NTXQUEUES,
347 IWN4965_NDMACHNLS,
348 IWN4965_ID_BROADCAST,
349 IWN4965_RXONSZ,
350 IWN4965_SCHEDSZ,
351 IWN4965_FW_TEXT_MAXSZ,
352 IWN4965_FW_DATA_MAXSZ,
353 IWN4965_FWSZ,
354 IWN4965_SCHED_TXFACT
355};
356
357static const struct iwn_hal iwn5000_hal = {
358 iwn5000_load_firmware,
359 iwn5000_read_eeprom,
360 iwn5000_post_alive,
361 iwn5000_nic_config,
362 iwn5000_update_sched,
363 iwn5000_get_temperature,
364 iwn5000_get_rssi,
365 iwn5000_set_txpower,
366 iwn5000_init_gains,
367 iwn5000_set_gains,
368 iwn5000_add_node,
369 iwn5000_tx_done,
370#if 0 /* HT */
371 iwn5000_ampdu_tx_start,
372 iwn5000_ampdu_tx_stop,
373#endif
374 IWN5000_NTXQUEUES,
375 IWN5000_NDMACHNLS,
376 IWN5000_ID_BROADCAST,
377 IWN5000_RXONSZ,
378 IWN5000_SCHEDSZ,
379 IWN5000_FW_TEXT_MAXSZ,
380 IWN5000_FW_DATA_MAXSZ,
381 IWN5000_FWSZ,
382 IWN5000_SCHED_TXFACT
383};
384
385static int
386iwn_probe(device_t dev)
387{
388 const struct iwn_ident *ident;
389
390 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
391 if (pci_get_vendor(dev) == ident->vendor &&
392 pci_get_device(dev) == ident->device) {
393 device_set_desc(dev, ident->name);
394 return 0;
395 }
396 }
397 return ENXIO;
398}
399
400static int
401iwn_attach(device_t dev)
402{
403 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
404 struct ieee80211com *ic;
405 struct ifnet *ifp;
406 const struct iwn_hal *hal;
407 uint32_t tmp;
408 int i, error, result;
409 uint8_t macaddr[IEEE80211_ADDR_LEN];
410
411 sc->sc_dev = dev;
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412 sc->sc_dmat = NULL;
413
414 if (bus_dma_tag_create(sc->sc_dmat,
415 1, 0,
416 BUS_SPACE_MAXADDR_32BIT,
417 BUS_SPACE_MAXADDR,
418 NULL, NULL,
419 BUS_SPACE_MAXSIZE,
420 IWN_MAX_SCATTER,
421 BUS_SPACE_MAXSIZE,
422 BUS_DMA_ALLOCNOW,
423 &sc->sc_dmat)) {
424 device_printf(dev, "cannot allocate DMA tag\n");
425 error = ENOMEM;
426 goto fail;
427 }
428
429
430
431 /* prepare sysctl tree for use in sub modules */
432 sysctl_ctx_init(&sc->sc_sysctl_ctx);
433 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
434 SYSCTL_STATIC_CHILDREN(_hw),
435 OID_AUTO,
436 device_get_nameunit(sc->sc_dev),
437 CTLFLAG_RD, 0, "");
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438
439 /*
440 * Get the offset of the PCI Express Capability Structure in PCI
441 * Configuration Space.
442 */
443 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
444 if (error != 0) {
445 device_printf(dev, "PCIe capability structure not found!\n");
446 return error;
447 }
448
449 /* Clear device-specific "PCI retry timeout" register (41h). */
450 pci_write_config(dev, 0x41, 0, 1);
451
452 /* Hardware bug workaround. */
453 tmp = pci_read_config(dev, PCIR_COMMAND, 1);
454 if (tmp & PCIM_CMD_INTxDIS) {
455 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
456 __func__);
457 tmp &= ~PCIM_CMD_INTxDIS;
458 pci_write_config(dev, PCIR_COMMAND, tmp, 1);
459 }
460
461 /* Enable bus-mastering. */
462 pci_enable_busmaster(dev);
463
464 sc->mem_rid = PCIR_BAR(0);
465 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
466 RF_ACTIVE);
467 if (sc->mem == NULL ) {
468 device_printf(dev, "could not allocate memory resources\n");
469 error = ENOMEM;
470 return error;
471 }
472
473 sc->sc_st = rman_get_bustag(sc->mem);
474 sc->sc_sh = rman_get_bushandle(sc->mem);
475 sc->irq_rid = 0;
476 if ((result = pci_msi_count(dev)) == 1 &&
477 pci_alloc_msi(dev, &result) == 0)
478 sc->irq_rid = 1;
479 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
480 RF_ACTIVE | RF_SHAREABLE);
481 if (sc->irq == NULL) {
482 device_printf(dev, "could not allocate interrupt resource\n");
483 error = ENOMEM;
484 goto fail;
485 }
486
487 IWN_LOCK_INIT(sc);
3db796ac 488 callout_init(&sc->sc_timer_to);
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489 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc );
490 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc );
491 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc );
492
493 /* Attach Hardware Abstraction Layer. */
494 hal = iwn_hal_attach(sc);
495 if (hal == NULL) {
496 error = ENXIO; /* XXX: Wrong error code? */
497 goto fail;
498 }
499
500 error = iwn_hw_prepare(sc);
501 if (error != 0) {
502 device_printf(dev, "hardware not ready, error %d\n", error);
503 goto fail;
504 }
505
506 /* Allocate DMA memory for firmware transfers. */
507 error = iwn_alloc_fwmem(sc);
508 if (error != 0) {
509 device_printf(dev,
510 "could not allocate memory for firmware, error %d\n",
511 error);
512 goto fail;
513 }
514
515 /* Allocate "Keep Warm" page. */
516 error = iwn_alloc_kw(sc);
517 if (error != 0) {
518 device_printf(dev,
519 "could not allocate \"Keep Warm\" page, error %d\n", error);
520 goto fail;
521 }
522
523 /* Allocate ICT table for 5000 Series. */
524 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
525 (error = iwn_alloc_ict(sc)) != 0) {
526 device_printf(dev,
527 "%s: could not allocate ICT table, error %d\n",
528 __func__, error);
529 goto fail;
530 }
531
532 /* Allocate TX scheduler "rings". */
533 error = iwn_alloc_sched(sc);
534 if (error != 0) {
535 device_printf(dev,
536 "could not allocate TX scheduler rings, error %d\n",
537 error);
538 goto fail;
539 }
540
541 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */
542 for (i = 0; i < hal->ntxqs; i++) {
543 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i);
544 if (error != 0) {
545 device_printf(dev,
546 "could not allocate Tx ring %d, error %d\n",
547 i, error);
548 goto fail;
549 }
550 }
551
552 /* Allocate RX ring. */
553 error = iwn_alloc_rx_ring(sc, &sc->rxq);
554 if (error != 0 ){
555 device_printf(dev,
556 "could not allocate Rx ring, error %d\n", error);
557 goto fail;
558 }
559
560 /* Clear pending interrupts. */
561 IWN_WRITE(sc, IWN_INT, 0xffffffff);
562
563 /* Count the number of available chains. */
564 sc->ntxchains =
565 ((sc->txchainmask >> 2) & 1) +
566 ((sc->txchainmask >> 1) & 1) +
567 ((sc->txchainmask >> 0) & 1);
568 sc->nrxchains =
569 ((sc->rxchainmask >> 2) & 1) +
570 ((sc->rxchainmask >> 1) & 1) +
571 ((sc->rxchainmask >> 0) & 1);
572
573 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
574 if (ifp == NULL) {
575 device_printf(dev, "can not allocate ifnet structure\n");
576 goto fail;
577 }
578 ic = ifp->if_l2com;
579
580 ic->ic_ifp = ifp;
581 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
582 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
583
584 /* Set device capabilities. */
585 ic->ic_caps =
586 IEEE80211_C_STA /* station mode supported */
587 | IEEE80211_C_MONITOR /* monitor mode supported */
588 | IEEE80211_C_TXPMGT /* tx power management */
589 | IEEE80211_C_SHSLOT /* short slot time supported */
590 | IEEE80211_C_WPA
591 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
592 | IEEE80211_C_BGSCAN /* background scanning */
593#if 0
594 | IEEE80211_C_IBSS /* ibss/adhoc mode */
595#endif
596 | IEEE80211_C_WME /* WME */
597 ;
598#if 0 /* HT */
599 /* XXX disable until HT channel setup works */
600 ic->ic_htcaps =
601 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */
602 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */
603 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
604 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
605 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */
606 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
607 /* s/w capabilities */
608 | IEEE80211_HTC_HT /* HT operation */
609 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
610 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
611 ;
612
613 /* Set HT capabilities. */
614 ic->ic_htcaps =
615#if IWN_RBUF_SIZE == 8192
616 IEEE80211_HTCAP_AMSDU7935 |
617#endif
618 IEEE80211_HTCAP_CBW20_40 |
619 IEEE80211_HTCAP_SGI20 |
620 IEEE80211_HTCAP_SGI40;
621 if (sc->hw_type != IWN_HW_REV_TYPE_4965)
622 ic->ic_htcaps |= IEEE80211_HTCAP_GF;
623 if (sc->hw_type == IWN_HW_REV_TYPE_6050)
624 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN;
625 else
626 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS;
627#endif
628
629 /* Read MAC address, channels, etc from EEPROM. */
630 error = iwn_read_eeprom(sc, macaddr);
631 if (error != 0) {
632 device_printf(dev, "could not read EEPROM, error %d\n",
633 error);
634 goto fail;
635 }
636
637 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n",
638 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
639 macaddr, ":");
640
641#if 0 /* HT */
642 /* Set supported HT rates. */
643 ic->ic_sup_mcs[0] = 0xff;
644 if (sc->nrxchains > 1)
645 ic->ic_sup_mcs[1] = 0xff;
646 if (sc->nrxchains > 2)
647 ic->ic_sup_mcs[2] = 0xff;
648#endif
649
650 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
651 ifp->if_softc = sc;
652 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
653 ifp->if_init = iwn_init;
654 ifp->if_ioctl = iwn_ioctl;
655 ifp->if_start = iwn_start;
3db796ac
JT
656 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
657 ifq_set_ready(&ifp->if_snd);
ffd7c74a
JT
658
659 ieee80211_ifattach(ic, macaddr);
660 ic->ic_vap_create = iwn_vap_create;
661 ic->ic_vap_delete = iwn_vap_delete;
662 ic->ic_raw_xmit = iwn_raw_xmit;
663 ic->ic_node_alloc = iwn_node_alloc;
664 ic->ic_newassoc = iwn_newassoc;
665 ic->ic_wme.wme_update = iwn_wme_update;
666 ic->ic_update_mcast = iwn_update_mcast;
667 ic->ic_scan_start = iwn_scan_start;
668 ic->ic_scan_end = iwn_scan_end;
669 ic->ic_set_channel = iwn_set_channel;
670 ic->ic_scan_curchan = iwn_scan_curchan;
671 ic->ic_scan_mindwell = iwn_scan_mindwell;
672 ic->ic_setregdomain = iwn_setregdomain;
673#if 0 /* HT */
674 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
675 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
676 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start;
677 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop;
678#endif
679
680 iwn_radiotap_attach(sc);
681 iwn_sysctlattach(sc);
682
683 /*
684 * Hook our interrupt after all initialization is complete.
685 */
3db796ac 686 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
1fb0473e 687 iwn_intr, sc, &sc->sc_ih, NULL);
ffd7c74a
JT
688 if (error != 0) {
689 device_printf(dev, "could not set up interrupt, error %d\n",
690 error);
691 goto fail;
692 }
693
694 ieee80211_announce(ic);
695 return 0;
696fail:
697 iwn_cleanup(dev);
698 return error;
699}
700
701static const struct iwn_hal *
702iwn_hal_attach(struct iwn_softc *sc)
703{
704 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
705
706 switch (sc->hw_type) {
707 case IWN_HW_REV_TYPE_4965:
708 sc->sc_hal = &iwn4965_hal;
709 sc->limits = &iwn4965_sensitivity_limits;
710 sc->fwname = "iwn4965fw";
711 sc->txchainmask = IWN_ANT_AB;
712 sc->rxchainmask = IWN_ANT_ABC;
713 break;
714 case IWN_HW_REV_TYPE_5100:
715 sc->sc_hal = &iwn5000_hal;
716 sc->limits = &iwn5000_sensitivity_limits;
717 sc->fwname = "iwn5000fw";
718 sc->txchainmask = IWN_ANT_B;
719 sc->rxchainmask = IWN_ANT_AB;
720 break;
721 case IWN_HW_REV_TYPE_5150:
722 sc->sc_hal = &iwn5000_hal;
723 sc->limits = &iwn5150_sensitivity_limits;
724 sc->fwname = "iwn5150fw";
725 sc->txchainmask = IWN_ANT_A;
726 sc->rxchainmask = IWN_ANT_AB;
727 break;
728 case IWN_HW_REV_TYPE_5300:
729 case IWN_HW_REV_TYPE_5350:
730 sc->sc_hal = &iwn5000_hal;
731 sc->limits = &iwn5000_sensitivity_limits;
732 sc->fwname = "iwn5000fw";
733 sc->txchainmask = IWN_ANT_ABC;
734 sc->rxchainmask = IWN_ANT_ABC;
735 break;
736 case IWN_HW_REV_TYPE_1000:
737 sc->sc_hal = &iwn5000_hal;
738 sc->limits = &iwn1000_sensitivity_limits;
739 sc->fwname = "iwn1000fw";
740 sc->txchainmask = IWN_ANT_A;
741 sc->rxchainmask = IWN_ANT_AB;
742 break;
743 case IWN_HW_REV_TYPE_6000:
744 sc->sc_hal = &iwn5000_hal;
745 sc->limits = &iwn6000_sensitivity_limits;
746 sc->fwname = "iwn6000fw";
747 switch (pci_get_device(sc->sc_dev)) {
748 case 0x422C:
749 case 0x4239:
750 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
751 sc->txchainmask = IWN_ANT_BC;
752 sc->rxchainmask = IWN_ANT_BC;
753 break;
754 default:
755 sc->txchainmask = IWN_ANT_ABC;
756 sc->rxchainmask = IWN_ANT_ABC;
757 break;
758 }
759 break;
760 case IWN_HW_REV_TYPE_6050:
761 sc->sc_hal = &iwn5000_hal;
762 sc->limits = &iwn6000_sensitivity_limits;
763 sc->fwname = "iwn6000fw";
764 sc->txchainmask = IWN_ANT_AB;
765 sc->rxchainmask = IWN_ANT_AB;
766 break;
767 default:
768 device_printf(sc->sc_dev, "adapter type %d not supported\n",
769 sc->hw_type);
770 return NULL;
771 }
772 return sc->sc_hal;
773}
774
775/*
776 * Attach the interface to 802.11 radiotap.
777 */
778static void
779iwn_radiotap_attach(struct iwn_softc *sc)
780{
781 struct ifnet *ifp = sc->sc_ifp;
782 struct ieee80211com *ic = ifp->if_l2com;
783
784 ieee80211_radiotap_attach(ic,
785 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
786 IWN_TX_RADIOTAP_PRESENT,
787 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
788 IWN_RX_RADIOTAP_PRESENT);
789}
790
791static struct ieee80211vap *
792iwn_vap_create(struct ieee80211com *ic,
793 const char name[IFNAMSIZ], int unit, int opmode, int flags,
794 const uint8_t bssid[IEEE80211_ADDR_LEN],
795 const uint8_t mac[IEEE80211_ADDR_LEN])
796{
797 struct iwn_vap *ivp;
798 struct ieee80211vap *vap;
799
800 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
801 return NULL;
3db796ac
JT
802 ivp = (struct iwn_vap *) kmalloc(sizeof(struct iwn_vap),
803 M_80211_VAP, M_INTWAIT | M_ZERO);
ffd7c74a
JT
804 if (ivp == NULL)
805 return NULL;
806 vap = &ivp->iv_vap;
807 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
808 vap->iv_bmissthreshold = 10; /* override default */
809 /* Override with driver methods. */
810 ivp->iv_newstate = vap->iv_newstate;
811 vap->iv_newstate = iwn_newstate;
812
813 ieee80211_ratectl_init(vap);
814 /* Complete setup. */
815 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
816 ic->ic_opmode = opmode;
817 return vap;
818}
819
820static void
821iwn_vap_delete(struct ieee80211vap *vap)
822{
823 struct iwn_vap *ivp = IWN_VAP(vap);
824
825 ieee80211_ratectl_deinit(vap);
826 ieee80211_vap_detach(vap);
3db796ac 827 kfree(ivp, M_80211_VAP);
ffd7c74a
JT
828}
829
830static int
831iwn_cleanup(device_t dev)
832{
833 struct iwn_softc *sc = device_get_softc(dev);
834 struct ifnet *ifp = sc->sc_ifp;
835 struct ieee80211com *ic;
836 int i;
837
838 if (ifp != NULL) {
839 ic = ifp->if_l2com;
840
841 ieee80211_draintask(ic, &sc->sc_reinit_task);
842 ieee80211_draintask(ic, &sc->sc_radioon_task);
843 ieee80211_draintask(ic, &sc->sc_radiooff_task);
844
845 iwn_stop(sc);
3db796ac 846 callout_stop(&sc->sc_timer_to);
ffd7c74a
JT
847 ieee80211_ifdetach(ic);
848 }
849
850 /* Free DMA resources. */
851 iwn_free_rx_ring(sc, &sc->rxq);
852 if (sc->sc_hal != NULL)
853 for (i = 0; i < sc->sc_hal->ntxqs; i++)
854 iwn_free_tx_ring(sc, &sc->txq[i]);
855 iwn_free_sched(sc);
856 iwn_free_kw(sc);
bbae4431 857 if (sc->ict != NULL) {
ffd7c74a 858 iwn_free_ict(sc);
bbae4431
JT
859 sc->ict = NULL;
860 }
ffd7c74a
JT
861 iwn_free_fwmem(sc);
862
863 if (sc->irq != NULL) {
864 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
865 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
866 if (sc->irq_rid == 1)
867 pci_release_msi(dev);
bbae4431 868 sc->irq = NULL;
ffd7c74a
JT
869 }
870
bbae4431 871 if (sc->mem != NULL) {
ffd7c74a 872 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
bbae4431
JT
873 sc->mem = NULL;
874 }
ffd7c74a 875
bbae4431 876 if (ifp != NULL) {
ffd7c74a 877 if_free(ifp);
bbae4431
JT
878 sc->sc_ifp = NULL;
879 }
ffd7c74a
JT
880
881 IWN_LOCK_DESTROY(sc);
882 return 0;
883}
884
885static int
886iwn_detach(device_t dev)
887{
3db796ac
JT
888 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
889
ffd7c74a 890 iwn_cleanup(dev);
3db796ac 891 bus_dma_tag_destroy(sc->sc_dmat);
ffd7c74a
JT
892 return 0;
893}
894
895static int
896iwn_nic_lock(struct iwn_softc *sc)
897{
898 int ntries;
899
900 /* Request exclusive access to NIC. */
901 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
902
903 /* Spin until we actually get the lock. */
904 for (ntries = 0; ntries < 1000; ntries++) {
905 if ((IWN_READ(sc, IWN_GP_CNTRL) &
906 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
907 IWN_GP_CNTRL_MAC_ACCESS_ENA)
908 return 0;
909 DELAY(10);
910 }
911 return ETIMEDOUT;
912}
913
914static __inline void
915iwn_nic_unlock(struct iwn_softc *sc)
916{
917 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
918}
919
920static __inline uint32_t
921iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
922{
923 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
924 IWN_BARRIER_READ_WRITE(sc);
925 return IWN_READ(sc, IWN_PRPH_RDATA);
926}
927
928static __inline void
929iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
930{
931 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
932 IWN_BARRIER_WRITE(sc);
933 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
934}
935
936static __inline void
937iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
938{
939 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
940}
941
942static __inline void
943iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
944{
945 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
946}
947
948static __inline void
949iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
950 const uint32_t *data, int count)
951{
952 for (; count > 0; count--, data++, addr += 4)
953 iwn_prph_write(sc, addr, *data);
954}
955
956static __inline uint32_t
957iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
958{
959 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
960 IWN_BARRIER_READ_WRITE(sc);
961 return IWN_READ(sc, IWN_MEM_RDATA);
962}
963
964static __inline void
965iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
966{
967 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
968 IWN_BARRIER_WRITE(sc);
969 IWN_WRITE(sc, IWN_MEM_WDATA, data);
970}
971
972static __inline void
973iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
974{
975 uint32_t tmp;
976
977 tmp = iwn_mem_read(sc, addr & ~3);
978 if (addr & 3)
979 tmp = (tmp & 0x0000ffff) | data << 16;
980 else
981 tmp = (tmp & 0xffff0000) | data;
982 iwn_mem_write(sc, addr & ~3, tmp);
983}
984
985static __inline void
986iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
987 int count)
988{
989 for (; count > 0; count--, addr += 4)
990 *data++ = iwn_mem_read(sc, addr);
991}
992
993static __inline void
994iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
995 int count)
996{
997 for (; count > 0; count--, addr += 4)
998 iwn_mem_write(sc, addr, val);
999}
1000
1001static int
1002iwn_eeprom_lock(struct iwn_softc *sc)
1003{
1004 int i, ntries;
1005
1006 for (i = 0; i < 100; i++) {
1007 /* Request exclusive access to EEPROM. */
1008 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1009 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1010
1011 /* Spin until we actually get the lock. */
1012 for (ntries = 0; ntries < 100; ntries++) {
1013 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1014 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1015 return 0;
1016 DELAY(10);
1017 }
1018 }
1019 return ETIMEDOUT;
1020}
1021
1022static __inline void
1023iwn_eeprom_unlock(struct iwn_softc *sc)
1024{
1025 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1026}
1027
1028/*
1029 * Initialize access by host to One Time Programmable ROM.
1030 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1031 */
1032static int
1033iwn_init_otprom(struct iwn_softc *sc)
1034{
1035 uint16_t prev, base, next;
1036 int count, error;
1037
1038 /* Wait for clock stabilization before accessing prph. */
1039 error = iwn_clock_wait(sc);
1040 if (error != 0)
1041 return error;
1042
1043 error = iwn_nic_lock(sc);
1044 if (error != 0)
1045 return error;
1046 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1047 DELAY(5);
1048 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1049 iwn_nic_unlock(sc);
1050
1051 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1052 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1053 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1054 IWN_RESET_LINK_PWR_MGMT_DIS);
1055 }
1056 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1057 /* Clear ECC status. */
1058 IWN_SETBITS(sc, IWN_OTP_GP,
1059 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1060
1061 /*
1062 * Find the block before last block (contains the EEPROM image)
1063 * for HW without OTP shadow RAM.
1064 */
1065 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1066 /* Switch to absolute addressing mode. */
1067 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1068 base = prev = 0;
1069 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1070 error = iwn_read_prom_data(sc, base, &next, 2);
1071 if (error != 0)
1072 return error;
1073 if (next == 0) /* End of linked-list. */
1074 break;
1075 prev = base;
1076 base = le16toh(next);
1077 }
1078 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1079 return EIO;
1080 /* Skip "next" word. */
1081 sc->prom_base = prev + 1;
1082 }
1083 return 0;
1084}
1085
1086static int
1087iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1088{
1089 uint32_t val, tmp;
1090 int ntries;
1091 uint8_t *out = data;
1092
1093 addr += sc->prom_base;
1094 for (; count > 0; count -= 2, addr++) {
1095 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1096 for (ntries = 0; ntries < 10; ntries++) {
1097 val = IWN_READ(sc, IWN_EEPROM);
1098 if (val & IWN_EEPROM_READ_VALID)
1099 break;
1100 DELAY(5);
1101 }
1102 if (ntries == 10) {
1103 device_printf(sc->sc_dev,
1104 "timeout reading ROM at 0x%x\n", addr);
1105 return ETIMEDOUT;
1106 }
1107 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1108 /* OTPROM, check for ECC errors. */
1109 tmp = IWN_READ(sc, IWN_OTP_GP);
1110 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1111 device_printf(sc->sc_dev,
1112 "OTPROM ECC error at 0x%x\n", addr);
1113 return EIO;
1114 }
1115 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1116 /* Correctable ECC error, clear bit. */
1117 IWN_SETBITS(sc, IWN_OTP_GP,
1118 IWN_OTP_GP_ECC_CORR_STTS);
1119 }
1120 }
1121 *out++ = val >> 16;
1122 if (count > 1)
1123 *out++ = val >> 24;
1124 }
1125 return 0;
1126}
1127
1128static void
1129iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1130{
1131 if (error != 0)
1132 return;
1133 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1134 *(bus_addr_t *)arg = segs[0].ds_addr;
1135}
1136
1137static int
1138iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1139 void **kvap, bus_size_t size, bus_size_t alignment, int flags)
1140{
1141 int error;
1142
1143 dma->size = size;
1144 dma->tag = NULL;
1145
3db796ac 1146 error = bus_dma_tag_create(sc->sc_dmat, alignment,
ffd7c74a 1147 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
3db796ac 1148 1, size, flags, &dma->tag);
ffd7c74a
JT
1149 if (error != 0) {
1150 device_printf(sc->sc_dev,
1151 "%s: bus_dma_tag_create failed, error %d\n",
1152 __func__, error);
1153 goto fail;
1154 }
1155 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1156 flags | BUS_DMA_ZERO, &dma->map);
1157 if (error != 0) {
1158 device_printf(sc->sc_dev,
1159 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error);
1160 goto fail;
1161 }
1162 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr,
1163 size, iwn_dma_map_addr, &dma->paddr, flags);
1164 if (error != 0) {
1165 device_printf(sc->sc_dev,
1166 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
1167 goto fail;
1168 }
1169
1170 if (kvap != NULL)
1171 *kvap = dma->vaddr;
1172 return 0;
1173fail:
1174 iwn_dma_contig_free(dma);
1175 return error;
1176}
1177
1178static void
1179iwn_dma_contig_free(struct iwn_dma_info *dma)
1180{
1181 if (dma->tag != NULL) {
1182 if (dma->map != NULL) {
1183 if (dma->paddr == 0) {
1184 bus_dmamap_sync(dma->tag, dma->map,
1185 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1186 bus_dmamap_unload(dma->tag, dma->map);
1187 }
bbae4431 1188 bus_dmamap_destroy(dma->tag, dma->map);
ffd7c74a 1189 }
bbae4431 1190 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
ffd7c74a
JT
1191 bus_dma_tag_destroy(dma->tag);
1192 }
1193}
1194
1195static int
1196iwn_alloc_sched(struct iwn_softc *sc)
1197{
1198 /* TX scheduler rings must be aligned on a 1KB boundary. */
1199 return iwn_dma_contig_alloc(sc, &sc->sched_dma,
1200 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT);
1201}
1202
1203static void
1204iwn_free_sched(struct iwn_softc *sc)
1205{
1206 iwn_dma_contig_free(&sc->sched_dma);
1207}
1208
1209static int
1210iwn_alloc_kw(struct iwn_softc *sc)
1211{
1212 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1213 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096,
1214 BUS_DMA_NOWAIT);
1215}
1216
1217static void
1218iwn_free_kw(struct iwn_softc *sc)
1219{
1220 iwn_dma_contig_free(&sc->kw_dma);
1221}
1222
1223static int
1224iwn_alloc_ict(struct iwn_softc *sc)
1225{
1226 /* ICT table must be aligned on a 4KB boundary. */
1227 return iwn_dma_contig_alloc(sc, &sc->ict_dma,
1228 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT);
1229}
1230
1231static void
1232iwn_free_ict(struct iwn_softc *sc)
1233{
1234 iwn_dma_contig_free(&sc->ict_dma);
1235}
1236
1237static int
1238iwn_alloc_fwmem(struct iwn_softc *sc)
1239{
1240 /* Must be aligned on a 16-byte boundary. */
1241 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL,
1242 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT);
1243}
1244
1245static void
1246iwn_free_fwmem(struct iwn_softc *sc)
1247{
1248 iwn_dma_contig_free(&sc->fw_dma);
1249}
1250
1251static int
1252iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1253{
1254 bus_size_t size;
1255 int i, error;
1256
1257 ring->cur = 0;
1258
1259 /* Allocate RX descriptors (256-byte aligned). */
1260 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1261 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1262 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1263 if (error != 0) {
1264 device_printf(sc->sc_dev,
1265 "%s: could not allocate Rx ring DMA memory, error %d\n",
1266 __func__, error);
1267 goto fail;
1268 }
1269
3db796ac 1270 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
ffd7c74a 1271 BUS_SPACE_MAXADDR_32BIT,
3db796ac
JT
1272 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1273 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
ffd7c74a
JT
1274 if (error != 0) {
1275 device_printf(sc->sc_dev,
1276 "%s: bus_dma_tag_create_failed, error %d\n",
1277 __func__, error);
1278 goto fail;
1279 }
1280
1281 /* Allocate RX status area (16-byte aligned). */
1282 error = iwn_dma_contig_alloc(sc, &ring->stat_dma,
1283 (void **)&ring->stat, sizeof (struct iwn_rx_status),
1284 16, BUS_DMA_NOWAIT);
1285 if (error != 0) {
1286 device_printf(sc->sc_dev,
1287 "%s: could not allocate Rx status DMA memory, error %d\n",
1288 __func__, error);
1289 goto fail;
1290 }
1291
1292 /*
1293 * Allocate and map RX buffers.
1294 */
1295 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1296 struct iwn_rx_data *data = &ring->data[i];
1297 bus_addr_t paddr;
1298
1299 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1300 if (error != 0) {
1301 device_printf(sc->sc_dev,
1302 "%s: bus_dmamap_create failed, error %d\n",
1303 __func__, error);
1304 goto fail;
1305 }
1306
3db796ac 1307 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT
1308 if (data->m == NULL) {
1309 device_printf(sc->sc_dev,
1310 "%s: could not allocate rx mbuf\n", __func__);
1311 error = ENOMEM;
1312 goto fail;
1313 }
1314
1315 /* Map page. */
1316 error = bus_dmamap_load(ring->data_dmat, data->map,
3db796ac 1317 mtod(data->m, caddr_t), MCLBYTES,
ffd7c74a
JT
1318 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
1319 if (error != 0 && error != EFBIG) {
1320 device_printf(sc->sc_dev,
1321 "%s: bus_dmamap_load failed, error %d\n",
1322 __func__, error);
1323 m_freem(data->m);
1324 error = ENOMEM; /* XXX unique code */
1325 goto fail;
1326 }
1327 bus_dmamap_sync(ring->data_dmat, data->map,
1328 BUS_DMASYNC_PREWRITE);
1329
1330 /* Set physical address of RX buffer (256-byte aligned). */
1331 ring->desc[i] = htole32(paddr >> 8);
1332 }
1333 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1334 BUS_DMASYNC_PREWRITE);
1335 return 0;
1336fail:
1337 iwn_free_rx_ring(sc, ring);
1338 return error;
1339}
1340
1341static void
1342iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1343{
1344 int ntries;
1345
1346 if (iwn_nic_lock(sc) == 0) {
1347 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1348 for (ntries = 0; ntries < 1000; ntries++) {
1349 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1350 IWN_FH_RX_STATUS_IDLE)
1351 break;
1352 DELAY(10);
1353 }
1354 iwn_nic_unlock(sc);
1355#ifdef IWN_DEBUG
1356 if (ntries == 1000)
1357 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
1358 "timeout resetting Rx ring");
1359#endif
1360 }
1361 ring->cur = 0;
1362 sc->last_rx_valid = 0;
1363}
1364
1365static void
1366iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1367{
1368 int i;
1369
1370 iwn_dma_contig_free(&ring->desc_dma);
1371 iwn_dma_contig_free(&ring->stat_dma);
1372
1373 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1374 struct iwn_rx_data *data = &ring->data[i];
1375
1376 if (data->m != NULL) {
1377 bus_dmamap_sync(ring->data_dmat, data->map,
1378 BUS_DMASYNC_POSTREAD);
1379 bus_dmamap_unload(ring->data_dmat, data->map);
1380 m_freem(data->m);
1381 }
1382 if (data->map != NULL)
1383 bus_dmamap_destroy(ring->data_dmat, data->map);
1384 }
1385}
1386
1387static int
1388iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1389{
1390 bus_size_t size;
1391 bus_addr_t paddr;
1392 int i, error;
1393
1394 ring->qid = qid;
1395 ring->queued = 0;
1396 ring->cur = 0;
1397
1398 /* Allocate TX descriptors (256-byte aligned.) */
1399 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc);
1400 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1401 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1402 if (error != 0) {
1403 device_printf(sc->sc_dev,
1404 "%s: could not allocate TX ring DMA memory, error %d\n",
1405 __func__, error);
1406 goto fail;
1407 }
1408
1409 /*
1410 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
1411 * to allocate commands space for other rings.
1412 */
1413 if (qid > 4)
1414 return 0;
1415
1416 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd);
1417 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma,
1418 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT);
1419 if (error != 0) {
1420 device_printf(sc->sc_dev,
1421 "%s: could not allocate TX cmd DMA memory, error %d\n",
1422 __func__, error);
1423 goto fail;
1424 }
1425
3db796ac 1426 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
ffd7c74a
JT
1427 BUS_SPACE_MAXADDR_32BIT,
1428 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
3db796ac 1429 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
ffd7c74a
JT
1430 if (error != 0) {
1431 device_printf(sc->sc_dev,
1432 "%s: bus_dma_tag_create_failed, error %d\n",
1433 __func__, error);
1434 goto fail;
1435 }
1436
1437 paddr = ring->cmd_dma.paddr;
1438 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1439 struct iwn_tx_data *data = &ring->data[i];
1440
1441 data->cmd_paddr = paddr;
1442 data->scratch_paddr = paddr + 12;
1443 paddr += sizeof (struct iwn_tx_cmd);
1444
1445 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1446 if (error != 0) {
1447 device_printf(sc->sc_dev,
1448 "%s: bus_dmamap_create failed, error %d\n",
1449 __func__, error);
1450 goto fail;
1451 }
1452 bus_dmamap_sync(ring->data_dmat, data->map,
1453 BUS_DMASYNC_PREWRITE);
1454 }
1455 return 0;
1456fail:
1457 iwn_free_tx_ring(sc, ring);
1458 return error;
1459}
1460
1461static void
1462iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1463{
1464 int i;
1465
1466 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1467 struct iwn_tx_data *data = &ring->data[i];
1468
1469 if (data->m != NULL) {
1470 bus_dmamap_unload(ring->data_dmat, data->map);
1471 m_freem(data->m);
1472 data->m = NULL;
1473 }
1474 }
1475 /* Clear TX descriptors. */
1476 memset(ring->desc, 0, ring->desc_dma.size);
1477 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1478 BUS_DMASYNC_PREWRITE);
1479 sc->qfullmsk &= ~(1 << ring->qid);
1480 ring->queued = 0;
1481 ring->cur = 0;
1482}
1483
1484static void
1485iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1486{
1487 int i;
1488
1489 iwn_dma_contig_free(&ring->desc_dma);
1490 iwn_dma_contig_free(&ring->cmd_dma);
1491
1492 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1493 struct iwn_tx_data *data = &ring->data[i];
1494
1495 if (data->m != NULL) {
1496 bus_dmamap_sync(ring->data_dmat, data->map,
1497 BUS_DMASYNC_POSTWRITE);
1498 bus_dmamap_unload(ring->data_dmat, data->map);
1499 m_freem(data->m);
1500 }
1501 if (data->map != NULL)
1502 bus_dmamap_destroy(ring->data_dmat, data->map);
1503 }
1504}
1505
1506static void
1507iwn5000_ict_reset(struct iwn_softc *sc)
1508{
1509 /* Disable interrupts. */
1510 IWN_WRITE(sc, IWN_INT_MASK, 0);
1511
1512 /* Reset ICT table. */
1513 memset(sc->ict, 0, IWN_ICT_SIZE);
1514 sc->ict_cur = 0;
1515
1516 /* Set physical address of ICT table (4KB aligned.) */
1517 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1518 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1519 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1520
1521 /* Enable periodic RX interrupt. */
1522 sc->int_mask |= IWN_INT_RX_PERIODIC;
1523 /* Switch to ICT interrupt mode in driver. */
1524 sc->sc_flags |= IWN_FLAG_USE_ICT;
1525
1526 /* Re-enable interrupts. */
1527 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1528 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1529}
1530
1531static int
1532iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1533{
1534 const struct iwn_hal *hal = sc->sc_hal;
1535 int error;
1536 uint16_t val;
1537
1538 /* Check whether adapter has an EEPROM or an OTPROM. */
1539 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1540 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1541 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1542 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1543 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1544
1545 /* Adapter has to be powered on for EEPROM access to work. */
1546 error = iwn_apm_init(sc);
1547 if (error != 0) {
1548 device_printf(sc->sc_dev,
1549 "%s: could not power ON adapter, error %d\n",
1550 __func__, error);
1551 return error;
1552 }
1553
1554 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1555 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1556 return EIO;
1557 }
1558 error = iwn_eeprom_lock(sc);
1559 if (error != 0) {
1560 device_printf(sc->sc_dev,
1561 "%s: could not lock ROM, error %d\n",
1562 __func__, error);
1563 return error;
1564 }
1565
1566 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1567 error = iwn_init_otprom(sc);
1568 if (error != 0) {
1569 device_printf(sc->sc_dev,
1570 "%s: could not initialize OTPROM, error %d\n",
1571 __func__, error);
1572 return error;
1573 }
1574 }
1575
1576 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1577 sc->rfcfg = le16toh(val);
1578 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1579
1580 /* Read MAC address. */
1581 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1582
1583 /* Read adapter-specific information from EEPROM. */
1584 hal->read_eeprom(sc);
1585
1586 iwn_apm_stop(sc); /* Power OFF adapter. */
1587
1588 iwn_eeprom_unlock(sc);
1589 return 0;
1590}
1591
1592static void
1593iwn4965_read_eeprom(struct iwn_softc *sc)
1594{
1595 uint32_t addr;
1596 int i;
1597 uint16_t val;
1598
1599 /* Read regulatory domain (4 ASCII characters.) */
1600 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1601
1602 /* Read the list of authorized channels (20MHz ones only.) */
1603 for (i = 0; i < 5; i++) {
1604 addr = iwn4965_regulatory_bands[i];
1605 iwn_read_eeprom_channels(sc, i, addr);
1606 }
1607
1608 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1609 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1610 sc->maxpwr2GHz = val & 0xff;
1611 sc->maxpwr5GHz = val >> 8;
1612 /* Check that EEPROM values are within valid range. */
1613 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1614 sc->maxpwr5GHz = 38;
1615 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1616 sc->maxpwr2GHz = 38;
1617 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1618 sc->maxpwr2GHz, sc->maxpwr5GHz);
1619
1620 /* Read samples for each TX power group. */
1621 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1622 sizeof sc->bands);
1623
1624 /* Read voltage at which samples were taken. */
1625 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1626 sc->eeprom_voltage = (int16_t)le16toh(val);
1627 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1628 sc->eeprom_voltage);
1629
1630#ifdef IWN_DEBUG
1631 /* Print samples. */
1632 if (sc->sc_debug & IWN_DEBUG_ANY) {
1633 for (i = 0; i < IWN_NBANDS; i++)
1634 iwn4965_print_power_group(sc, i);
1635 }
1636#endif
1637}
1638
1639#ifdef IWN_DEBUG
1640static void
1641iwn4965_print_power_group(struct iwn_softc *sc, int i)
1642{
1643 struct iwn4965_eeprom_band *band = &sc->bands[i];
1644 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1645 int j, c;
1646
3db796ac
JT
1647 kprintf("===band %d===\n", i);
1648 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1649 kprintf("chan1 num=%d\n", chans[0].num);
ffd7c74a
JT
1650 for (c = 0; c < 2; c++) {
1651 for (j = 0; j < IWN_NSAMPLES; j++) {
3db796ac 1652 kprintf("chain %d, sample %d: temp=%d gain=%d "
ffd7c74a
JT
1653 "power=%d pa_det=%d\n", c, j,
1654 chans[0].samples[c][j].temp,
1655 chans[0].samples[c][j].gain,
1656 chans[0].samples[c][j].power,
1657 chans[0].samples[c][j].pa_det);
1658 }
1659 }
3db796ac 1660 kprintf("chan2 num=%d\n", chans[1].num);
ffd7c74a
JT
1661 for (c = 0; c < 2; c++) {
1662 for (j = 0; j < IWN_NSAMPLES; j++) {
3db796ac 1663 kprintf("chain %d, sample %d: temp=%d gain=%d "
ffd7c74a
JT
1664 "power=%d pa_det=%d\n", c, j,
1665 chans[1].samples[c][j].temp,
1666 chans[1].samples[c][j].gain,
1667 chans[1].samples[c][j].power,
1668 chans[1].samples[c][j].pa_det);
1669 }
1670 }
1671}
1672#endif
1673
1674static void
1675iwn5000_read_eeprom(struct iwn_softc *sc)
1676{
1677 struct iwn5000_eeprom_calib_hdr hdr;
1678 int32_t temp, volt;
1679 uint32_t addr, base;
1680 int i;
1681 uint16_t val;
1682
1683 /* Read regulatory domain (4 ASCII characters.) */
1684 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1685 base = le16toh(val);
1686 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1687 sc->eeprom_domain, 4);
1688
1689 /* Read the list of authorized channels (20MHz ones only.) */
1690 for (i = 0; i < 5; i++) {
1691 addr = base + iwn5000_regulatory_bands[i];
1692 iwn_read_eeprom_channels(sc, i, addr);
1693 }
1694
1695 /* Read enhanced TX power information for 6000 Series. */
1696 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1697 iwn_read_eeprom_enhinfo(sc);
1698
1699 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1700 base = le16toh(val);
1701 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1702 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1703 "%s: calib version=%u pa type=%u voltage=%u\n",
1704 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt));
1705 sc->calib_ver = hdr.version;
1706
1707 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1708 /* Compute temperature offset. */
1709 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1710 temp = le16toh(val);
1711 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1712 volt = le16toh(val);
1713 sc->temp_off = temp - (volt / -5);
1714 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1715 temp, volt, sc->temp_off);
1716 } else {
1717 /* Read crystal calibration. */
1718 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1719 &sc->eeprom_crystal, sizeof (uint32_t));
1720 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1721 le32toh(sc->eeprom_crystal));
1722 }
1723}
1724
1725/*
1726 * Translate EEPROM flags to net80211.
1727 */
1728static uint32_t
1729iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1730{
1731 uint32_t nflags;
1732
1733 nflags = 0;
1734 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1735 nflags |= IEEE80211_CHAN_PASSIVE;
1736 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1737 nflags |= IEEE80211_CHAN_NOADHOC;
1738 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1739 nflags |= IEEE80211_CHAN_DFS;
1740 /* XXX apparently IBSS may still be marked */
1741 nflags |= IEEE80211_CHAN_NOADHOC;
1742 }
1743
1744 return nflags;
1745}
1746
1747static void
1748iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1749{
1750 struct ifnet *ifp = sc->sc_ifp;
1751 struct ieee80211com *ic = ifp->if_l2com;
1752 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1753 const struct iwn_chan_band *band = &iwn_bands[n];
1754 struct ieee80211_channel *c;
1755 int i, chan, nflags;
1756
1757 for (i = 0; i < band->nchan; i++) {
1758 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1759 DPRINTF(sc, IWN_DEBUG_RESET,
1760 "skip chan %d flags 0x%x maxpwr %d\n",
1761 band->chan[i], channels[i].flags,
1762 channels[i].maxpwr);
1763 continue;
1764 }
1765 chan = band->chan[i];
1766 nflags = iwn_eeprom_channel_flags(&channels[i]);
1767
1768 DPRINTF(sc, IWN_DEBUG_RESET,
1769 "add chan %d flags 0x%x maxpwr %d\n",
1770 chan, channels[i].flags, channels[i].maxpwr);
1771
1772 c = &ic->ic_channels[ic->ic_nchans++];
1773 c->ic_ieee = chan;
1774 c->ic_maxregpower = channels[i].maxpwr;
1775 c->ic_maxpower = 2*c->ic_maxregpower;
1776
1777 /* Save maximum allowed TX power for this channel. */
1778 sc->maxpwr[chan] = channels[i].maxpwr;
1779
1780 if (n == 0) { /* 2GHz band */
1781 c->ic_freq = ieee80211_ieee2mhz(chan,
1782 IEEE80211_CHAN_G);
1783
1784 /* G =>'s B is supported */
1785 c->ic_flags = IEEE80211_CHAN_B | nflags;
1786
1787 c = &ic->ic_channels[ic->ic_nchans++];
1788 c[0] = c[-1];
1789 c->ic_flags = IEEE80211_CHAN_G | nflags;
1790 } else { /* 5GHz band */
1791 c->ic_freq = ieee80211_ieee2mhz(chan,
1792 IEEE80211_CHAN_A);
1793 c->ic_flags = IEEE80211_CHAN_A | nflags;
1794 sc->sc_flags |= IWN_FLAG_HAS_5GHZ;
1795 }
1796#if 0 /* HT */
1797 /* XXX no constraints on using HT20 */
1798 /* add HT20, HT40 added separately */
1799 c = &ic->ic_channels[ic->ic_nchans++];
1800 c[0] = c[-1];
1801 c->ic_flags |= IEEE80211_CHAN_HT20;
1802 /* XXX NARROW =>'s 1/2 and 1/4 width? */
1803#endif
1804 }
1805}
1806
1807#if 0 /* HT */
1808static void
1809iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1810{
1811 struct ifnet *ifp = sc->sc_ifp;
1812 struct ieee80211com *ic = ifp->if_l2com;
1813 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1814 const struct iwn_chan_band *band = &iwn_bands[n];
1815 struct ieee80211_channel *c, *cent, *extc;
1816 int i;
1817
1818 for (i = 0; i < band->nchan; i++) {
1819 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) ||
1820 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) {
1821 DPRINTF(sc, IWN_DEBUG_RESET,
1822 "skip chan %d flags 0x%x maxpwr %d\n",
1823 band->chan[i], channels[i].flags,
1824 channels[i].maxpwr);
1825 continue;
1826 }
1827 /*
1828 * Each entry defines an HT40 channel pair; find the
1829 * center channel, then the extension channel above.
1830 */
1831 cent = ieee80211_find_channel_byieee(ic, band->chan[i],
1832 band->flags & ~IEEE80211_CHAN_HT);
1833 if (cent == NULL) { /* XXX shouldn't happen */
1834 device_printf(sc->sc_dev,
1835 "%s: no entry for channel %d\n",
1836 __func__, band->chan[i]);
1837 continue;
1838 }
1839 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1840 band->flags & ~IEEE80211_CHAN_HT);
1841 if (extc == NULL) {
1842 DPRINTF(sc, IWN_DEBUG_RESET,
1843 "skip chan %d, extension channel not found\n",
1844 band->chan[i]);
1845 continue;
1846 }
1847
1848 DPRINTF(sc, IWN_DEBUG_RESET,
1849 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1850 band->chan[i], channels[i].flags, channels[i].maxpwr);
1851
1852 c = &ic->ic_channels[ic->ic_nchans++];
1853 c[0] = cent[0];
1854 c->ic_extieee = extc->ic_ieee;
1855 c->ic_flags &= ~IEEE80211_CHAN_HT;
1856 c->ic_flags |= IEEE80211_CHAN_HT40U;
1857 c = &ic->ic_channels[ic->ic_nchans++];
1858 c[0] = extc[0];
1859 c->ic_extieee = cent->ic_ieee;
1860 c->ic_flags &= ~IEEE80211_CHAN_HT;
1861 c->ic_flags |= IEEE80211_CHAN_HT40D;
1862 }
1863}
1864#endif
1865
1866static void
1867iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1868{
1869 struct ifnet *ifp = sc->sc_ifp;
1870 struct ieee80211com *ic = ifp->if_l2com;
1871
1872 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1873 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1874
1875 if (n < 5)
1876 iwn_read_eeprom_band(sc, n);
1877#if 0 /* HT */
1878 else
1879 iwn_read_eeprom_ht40(sc, n);
1880#endif
1881 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1882}
1883
1884#define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
1885
1886static void
1887iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
1888{
1889 struct iwn_eeprom_enhinfo enhinfo[35];
1890 uint16_t val, base;
1891 int8_t maxpwr;
1892 int i;
1893
1894 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1895 base = le16toh(val);
1896 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
1897 enhinfo, sizeof enhinfo);
1898
1899 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr);
1900 for (i = 0; i < nitems(enhinfo); i++) {
1901 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0)
1902 continue; /* Skip invalid entries. */
1903
1904 maxpwr = 0;
1905 if (sc->txchainmask & IWN_ANT_A)
1906 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
1907 if (sc->txchainmask & IWN_ANT_B)
1908 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
1909 if (sc->txchainmask & IWN_ANT_C)
1910 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
1911 if (sc->ntxchains == 2)
1912 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
1913 else if (sc->ntxchains == 3)
1914 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
1915 maxpwr /= 2; /* Convert half-dBm to dBm. */
1916
1917 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i,
1918 maxpwr);
1919 sc->enh_maxpwr[i] = maxpwr;
1920 }
1921}
1922
1923static struct ieee80211_node *
1924iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
1925{
3db796ac 1926 return kmalloc(sizeof (struct iwn_node), M_80211_NODE,M_INTWAIT | M_ZERO);
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1927}
1928
1929static void
1930iwn_newassoc(struct ieee80211_node *ni, int isnew)
1931{
1932 /* XXX move */
3db796ac
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1933 //if (!isnew) {
1934 ieee80211_ratectl_node_deinit(ni);
1935 //}
1936
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1937 ieee80211_ratectl_node_init(ni);
1938}
1939
1940static int
1941iwn_media_change(struct ifnet *ifp)
1942{
1943 int error = ieee80211_media_change(ifp);
1944 /* NB: only the fixed rate can change and that doesn't need a reset */
1945 return (error == ENETRESET ? 0 : error);
1946}
1947
1948static int
1949iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1950{
1951 struct iwn_vap *ivp = IWN_VAP(vap);
1952 struct ieee80211com *ic = vap->iv_ic;
1953 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1954 int error;
1955
1956 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1957 ieee80211_state_name[vap->iv_state],
1958 ieee80211_state_name[nstate]);
1959
1960 IEEE80211_UNLOCK(ic);
1961 IWN_LOCK(sc);
1962 callout_stop(&sc->sc_timer_to);
1963
1964 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) {
1965 /* !AUTH -> AUTH requires adapter config */
1966 /* Reset state to handle reassociations correctly. */
1967 sc->rxon.associd = 0;
1968 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
1969 iwn_calib_reset(sc);
1970 error = iwn_auth(sc, vap);
1971 }
1972 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) {
1973 /*
1974 * !RUN -> RUN requires setting the association id
1975 * which is done with a firmware cmd. We also defer
1976 * starting the timers until that work is done.
1977 */
1978 error = iwn_run(sc, vap);
1979 }
1980 if (nstate == IEEE80211_S_RUN) {
1981 /*
1982 * RUN -> RUN transition; just restart the timers.
1983 */
1984 iwn_calib_reset(sc);
1985 }
1986 IWN_UNLOCK(sc);
1987 IEEE80211_LOCK(ic);
1988 return ivp->iv_newstate(vap, nstate, arg);
1989}
1990
1991/*
1992 * Process an RX_PHY firmware notification. This is usually immediately
1993 * followed by an MPDU_RX_DONE notification.
1994 */
1995static void
1996iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
1997 struct iwn_rx_data *data)
1998{
1999 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
2000
2001 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
2002 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2003
2004 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
2005 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
2006 sc->last_rx_valid = 1;
2007}
2008
2009static void
2010iwn_timer_timeout(void *arg)
2011{
2012 struct iwn_softc *sc = arg;
2013 uint32_t flags = 0;
2014
5b54eab3 2015 IWN_LOCK(sc);
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2016
2017 if (sc->calib_cnt && --sc->calib_cnt == 0) {
2018 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2019 "send statistics request");
2020 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2021 sizeof flags, 1);
2022 sc->calib_cnt = 60; /* do calibration every 60s */
2023 }
2024 iwn_watchdog(sc); /* NB: piggyback tx watchdog */
2025 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
5b54eab3 2026 IWN_UNLOCK(sc);
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JT
2027}
2028
2029static void
2030iwn_calib_reset(struct iwn_softc *sc)
2031{
2032 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
2033 sc->calib_cnt = 60; /* do calibration every 60s */
2034}
2035
2036/*
2037 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2038 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2039 */
2040static void
2041iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2042 struct iwn_rx_data *data)
2043{
2044 const struct iwn_hal *hal = sc->sc_hal;
2045 struct ifnet *ifp = sc->sc_ifp;
2046 struct ieee80211com *ic = ifp->if_l2com;
2047 struct iwn_rx_ring *ring = &sc->rxq;
2048 struct ieee80211_frame *wh;
2049 struct ieee80211_node *ni;
2050 struct mbuf *m, *m1;
2051 struct iwn_rx_stat *stat;
2052 caddr_t head;
2053 bus_addr_t paddr;
2054 uint32_t flags;
2055 int error, len, rssi, nf;
2056
2057 if (desc->type == IWN_MPDU_RX_DONE) {
2058 /* Check for prior RX_PHY notification. */
2059 if (!sc->last_rx_valid) {
2060 DPRINTF(sc, IWN_DEBUG_ANY,
2061 "%s: missing RX_PHY\n", __func__);
2062 ifp->if_ierrors++;
2063 return;
2064 }
2065 sc->last_rx_valid = 0;
2066 stat = &sc->last_rx_stat;
2067 } else
2068 stat = (struct iwn_rx_stat *)(desc + 1);
2069
2070 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2071
2072 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2073 device_printf(sc->sc_dev,
2074 "%s: invalid rx statistic header, len %d\n",
2075 __func__, stat->cfg_phy_len);
2076 ifp->if_ierrors++;
2077 return;
2078 }
2079 if (desc->type == IWN_MPDU_RX_DONE) {
2080 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2081 head = (caddr_t)(mpdu + 1);
2082 len = le16toh(mpdu->len);
2083 } else {
2084 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2085 len = le16toh(stat->len);
2086 }
2087
2088 flags = le32toh(*(uint32_t *)(head + len));
2089
2090 /* Discard frames with a bad FCS early. */
2091 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2092 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n",
2093 __func__, flags);
2094 ifp->if_ierrors++;
2095 return;
2096 }
2097 /* Discard frames that are too short. */
2098 if (len < sizeof (*wh)) {
2099 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2100 __func__, len);
2101 ifp->if_ierrors++;
2102 return;
2103 }
2104
2105 /* XXX don't need mbuf, just dma buffer */
3db796ac 2106 m1 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT
2107 if (m1 == NULL) {
2108 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2109 __func__);
2110 ifp->if_ierrors++;
2111 return;
2112 }
2113 bus_dmamap_unload(ring->data_dmat, data->map);
2114
2115 error = bus_dmamap_load(ring->data_dmat, data->map,
3db796ac 2116 mtod(m1, caddr_t), MCLBYTES,
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JT
2117 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2118 if (error != 0 && error != EFBIG) {
2119 device_printf(sc->sc_dev,
2120 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2121 m_freem(m1);
2122 ifp->if_ierrors++;
2123 return;
2124 }
2125
2126 m = data->m;
2127 data->m = m1;
2128 /* Update RX descriptor. */
2129 ring->desc[ring->cur] = htole32(paddr >> 8);
2130 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2131 BUS_DMASYNC_PREWRITE);
2132
2133 /* Finalize mbuf. */
2134 m->m_pkthdr.rcvif = ifp;
2135 m->m_data = head;
2136 m->m_pkthdr.len = m->m_len = len;
2137
2138 rssi = hal->get_rssi(sc, stat);
2139
2140 /* Grab a reference to the source node. */
2141 wh = mtod(m, struct ieee80211_frame *);
2142 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2143 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2144 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2145
2146 if (ieee80211_radiotap_active(ic)) {
2147 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2148
2149 tap->wr_tsft = htole64(stat->tstamp);
2150 tap->wr_flags = 0;
2151 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2152 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2153 switch (stat->rate) {
2154 /* CCK rates. */
2155 case 10: tap->wr_rate = 2; break;
2156 case 20: tap->wr_rate = 4; break;
2157 case 55: tap->wr_rate = 11; break;
2158 case 110: tap->wr_rate = 22; break;
2159 /* OFDM rates. */
2160 case 0xd: tap->wr_rate = 12; break;
2161 case 0xf: tap->wr_rate = 18; break;
2162 case 0x5: tap->wr_rate = 24; break;
2163 case 0x7: tap->wr_rate = 36; break;
2164 case 0x9: tap->wr_rate = 48; break;
2165 case 0xb: tap->wr_rate = 72; break;
2166 case 0x1: tap->wr_rate = 96; break;
2167 case 0x3: tap->wr_rate = 108; break;
2168 /* Unknown rate: should not happen. */
2169 default: tap->wr_rate = 0;
2170 }
2171 tap->wr_dbm_antsignal = rssi;
2172 tap->wr_dbm_antnoise = nf;
2173 }
2174
2175 IWN_UNLOCK(sc);
2176
2177 /* Send the frame to the 802.11 layer. */
2178 if (ni != NULL) {
2179 (void) ieee80211_input(ni, m, rssi - nf, nf);
2180 /* Node is no longer needed. */
2181 ieee80211_free_node(ni);
2182 } else
2183 (void) ieee80211_input_all(ic, m, rssi - nf, nf);
2184
2185 IWN_LOCK(sc);
2186}
2187
2188#if 0 /* HT */
2189/* Process an incoming Compressed BlockAck. */
2190static void
2191iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2192 struct iwn_rx_data *data)
2193{
2194 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2195 struct iwn_tx_ring *txq;
2196
2197 txq = &sc->txq[letoh16(ba->qid)];
2198 /* XXX TBD */
2199}
2200#endif
2201
2202/*
2203 * Process a CALIBRATION_RESULT notification sent by the initialization
2204 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.)
2205 */
2206static void
2207iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2208 struct iwn_rx_data *data)
2209{
2210 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2211 int len, idx = -1;
2212
2213 /* Runtime firmware should not send such a notification. */
2214 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2215 return;
2216
2217 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2218 len = (le32toh(desc->len) & 0x3fff) - 4;
2219
2220 switch (calib->code) {
2221 case IWN5000_PHY_CALIB_DC:
2222 if (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2223 sc->hw_type == IWN_HW_REV_TYPE_6050)
2224 idx = 0;
2225 break;
2226 case IWN5000_PHY_CALIB_LO:
2227 idx = 1;
2228 break;
2229 case IWN5000_PHY_CALIB_TX_IQ:
2230 idx = 2;
2231 break;
2232 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2233 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2234 sc->hw_type != IWN_HW_REV_TYPE_5150)
2235 idx = 3;
2236 break;
2237 case IWN5000_PHY_CALIB_BASE_BAND:
2238 idx = 4;
2239 break;
2240 }
2241 if (idx == -1) /* Ignore other results. */
2242 return;
2243
2244 /* Save calibration result. */
2245 if (sc->calibcmd[idx].buf != NULL)
3db796ac
JT
2246 kfree(sc->calibcmd[idx].buf, M_DEVBUF);
2247 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT);
ffd7c74a
JT
2248 if (sc->calibcmd[idx].buf == NULL) {
2249 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2250 "not enough memory for calibration result %d\n",
2251 calib->code);
2252 return;
2253 }
2254 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2255 "saving calibration result code=%d len=%d\n", calib->code, len);
2256 sc->calibcmd[idx].len = len;
2257 memcpy(sc->calibcmd[idx].buf, calib, len);
2258}
2259
2260/*
2261 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2262 * The latter is sent by the firmware after each received beacon.
2263 */
2264static void
2265iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2266 struct iwn_rx_data *data)
2267{
2268 const struct iwn_hal *hal = sc->sc_hal;
2269 struct ifnet *ifp = sc->sc_ifp;
2270 struct ieee80211com *ic = ifp->if_l2com;
2271 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2272 struct iwn_calib_state *calib = &sc->calib;
2273 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2274 int temp;
2275
2276 /* Beacon stats are meaningful only when associated and not scanning. */
2277 if (vap->iv_state != IEEE80211_S_RUN ||
2278 (ic->ic_flags & IEEE80211_F_SCAN))
2279 return;
2280
2281 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2282 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type);
2283 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */
2284
2285 /* Test if temperature has changed. */
2286 if (stats->general.temp != sc->rawtemp) {
2287 /* Convert "raw" temperature to degC. */
2288 sc->rawtemp = stats->general.temp;
2289 temp = hal->get_temperature(sc);
2290 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2291 __func__, temp);
2292
2293 /* Update TX power if need be (4965AGN only.) */
2294 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2295 iwn4965_power_calibration(sc, temp);
2296 }
2297
2298 if (desc->type != IWN_BEACON_STATISTICS)
2299 return; /* Reply to a statistics request. */
2300
2301 sc->noise = iwn_get_noise(&stats->rx.general);
2302 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2303
2304 /* Test that RSSI and noise are present in stats report. */
2305 if (le32toh(stats->rx.general.flags) != 1) {
2306 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2307 "received statistics without RSSI");
2308 return;
2309 }
2310
2311 if (calib->state == IWN_CALIB_STATE_ASSOC)
2312 iwn_collect_noise(sc, &stats->rx.general);
2313 else if (calib->state == IWN_CALIB_STATE_RUN)
2314 iwn_tune_sensitivity(sc, &stats->rx);
2315}
2316
2317/*
2318 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2319 * and 5000 adapters have different incompatible TX status formats.
2320 */
2321static void
2322iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2323 struct iwn_rx_data *data)
2324{
2325 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2326 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2327
2328 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2329 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2330 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2331 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2332 le32toh(stat->status));
2333
2334 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2335 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff);
2336}
2337
2338static void
2339iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2340 struct iwn_rx_data *data)
2341{
2342 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2343 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2344
2345 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2346 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2347 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2348 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2349 le32toh(stat->status));
2350
2351#ifdef notyet
2352 /* Reset TX scheduler slot. */
2353 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2354#endif
2355
2356 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2357 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff);
2358}
2359
2360/*
2361 * Adapter-independent backend for TX_DONE firmware notifications.
2362 */
2363static void
2364iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2365 uint8_t status)
2366{
2367 struct ifnet *ifp = sc->sc_ifp;
2368 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2369 struct iwn_tx_data *data = &ring->data[desc->idx];
2370 struct mbuf *m;
2371 struct ieee80211_node *ni;
2372 struct ieee80211vap *vap;
2373
2374 KASSERT(data->ni != NULL, ("no node"));
2375
2376 /* Unmap and free mbuf. */
2377 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2378 bus_dmamap_unload(ring->data_dmat, data->map);
2379 m = data->m, data->m = NULL;
2380 ni = data->ni, data->ni = NULL;
2381 vap = ni->ni_vap;
2382
2383 if (m->m_flags & M_TXCB) {
2384 /*
2385 * Channels marked for "radar" require traffic to be received
2386 * to unlock before we can transmit. Until traffic is seen
2387 * any attempt to transmit is returned immediately with status
2388 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2389 * happen on first authenticate after scanning. To workaround
2390 * this we ignore a failure of this sort in AUTH state so the
2391 * 802.11 layer will fall back to using a timeout to wait for
2392 * the AUTH reply. This allows the firmware time to see
2393 * traffic so a subsequent retry of AUTH succeeds. It's
2394 * unclear why the firmware does not maintain state for
2395 * channels recently visited as this would allow immediate
2396 * use of the channel after a scan (where we see traffic).
2397 */
2398 if (status == IWN_TX_FAIL_TX_LOCKED &&
2399 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2400 ieee80211_process_callback(ni, m, 0);
2401 else
2402 ieee80211_process_callback(ni, m,
2403 (status & IWN_TX_FAIL) != 0);
2404 }
2405
2406 /*
2407 * Update rate control statistics for the node.
2408 */
2409 if (status & 0x80) {
2410 ifp->if_oerrors++;
2411 ieee80211_ratectl_tx_complete(vap, ni,
2412 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2413 } else {
2414 ieee80211_ratectl_tx_complete(vap, ni,
2415 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2416 }
2417 m_freem(m);
2418 ieee80211_free_node(ni);
2419
2420 sc->sc_tx_timer = 0;
2421 if (--ring->queued < IWN_TX_RING_LOMARK) {
2422 sc->qfullmsk &= ~(1 << ring->qid);
2423 if (sc->qfullmsk == 0 &&
3db796ac
JT
2424 (ifp->if_flags & IFF_OACTIVE)) {
2425 ifp->if_flags &= ~IFF_OACTIVE;
ffd7c74a
JT
2426 iwn_start_locked(ifp);
2427 }
2428 }
2429}
2430
2431/*
2432 * Process a "command done" firmware notification. This is where we wakeup
2433 * processes waiting for a synchronous command completion.
2434 */
2435static void
2436iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2437{
2438 struct iwn_tx_ring *ring = &sc->txq[4];
2439 struct iwn_tx_data *data;
2440
2441 if ((desc->qid & 0xf) != 4)
2442 return; /* Not a command ack. */
2443
2444 data = &ring->data[desc->idx];
2445
2446 /* If the command was mapped in an mbuf, free it. */
2447 if (data->m != NULL) {
2448 bus_dmamap_unload(ring->data_dmat, data->map);
2449 m_freem(data->m);
2450 data->m = NULL;
2451 }
2452 wakeup(&ring->desc[desc->idx]);
2453}
2454
2455/*
2456 * Process an INT_FH_RX or INT_SW_RX interrupt.
2457 */
2458static void
2459iwn_notif_intr(struct iwn_softc *sc)
2460{
2461 struct ifnet *ifp = sc->sc_ifp;
2462 struct ieee80211com *ic = ifp->if_l2com;
2463 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2464 uint16_t hw;
2465
2466 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2467 BUS_DMASYNC_POSTREAD);
2468
2469 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2470 while (sc->rxq.cur != hw) {
2471 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2472 struct iwn_rx_desc *desc;
2473
2474 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2475 BUS_DMASYNC_POSTREAD);
2476 desc = mtod(data->m, struct iwn_rx_desc *);
2477
2478 DPRINTF(sc, IWN_DEBUG_RECV,
2479 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2480 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2481 desc->type, iwn_intr_str(desc->type),
2482 le16toh(desc->len));
2483
2484 if (!(desc->qid & 0x80)) /* Reply to a command. */
2485 iwn_cmd_done(sc, desc);
2486
2487 switch (desc->type) {
2488 case IWN_RX_PHY:
2489 iwn_rx_phy(sc, desc, data);
2490 break;
2491
2492 case IWN_RX_DONE: /* 4965AGN only. */
2493 case IWN_MPDU_RX_DONE:
2494 /* An 802.11 frame has been received. */
2495 iwn_rx_done(sc, desc, data);
2496 break;
2497
2498#if 0 /* HT */
2499 case IWN_RX_COMPRESSED_BA:
2500 /* A Compressed BlockAck has been received. */
2501 iwn_rx_compressed_ba(sc, desc, data);
2502 break;
2503#endif
2504
2505 case IWN_TX_DONE:
2506 /* An 802.11 frame has been transmitted. */
2507 sc->sc_hal->tx_done(sc, desc, data);
2508 break;
2509
2510 case IWN_RX_STATISTICS:
2511 case IWN_BEACON_STATISTICS:
2512 iwn_rx_statistics(sc, desc, data);
2513 break;
2514
2515 case IWN_BEACON_MISSED:
2516 {
2517 struct iwn_beacon_missed *miss =
2518 (struct iwn_beacon_missed *)(desc + 1);
2519 int misses;
2520
2521 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2522 BUS_DMASYNC_POSTREAD);
2523 misses = le32toh(miss->consecutive);
2524
2525 /* XXX not sure why we're notified w/ zero */
2526 if (misses == 0)
2527 break;
2528 DPRINTF(sc, IWN_DEBUG_STATE,
2529 "%s: beacons missed %d/%d\n", __func__,
2530 misses, le32toh(miss->total));
2531
2532 /*
2533 * If more than 5 consecutive beacons are missed,
2534 * reinitialize the sensitivity state machine.
2535 */
2536 if (vap->iv_state == IEEE80211_S_RUN && misses > 5)
2537 (void) iwn_init_sensitivity(sc);
2538 if (misses >= vap->iv_bmissthreshold) {
2539 IWN_UNLOCK(sc);
2540 ieee80211_beacon_miss(ic);
2541 IWN_LOCK(sc);
2542 }
2543 break;
2544 }
2545 case IWN_UC_READY:
2546 {
2547 struct iwn_ucode_info *uc =
2548 (struct iwn_ucode_info *)(desc + 1);
2549
2550 /* The microcontroller is ready. */
2551 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2552 BUS_DMASYNC_POSTREAD);
2553 DPRINTF(sc, IWN_DEBUG_RESET,
2554 "microcode alive notification version=%d.%d "
2555 "subtype=%x alive=%x\n", uc->major, uc->minor,
2556 uc->subtype, le32toh(uc->valid));
2557
2558 if (le32toh(uc->valid) != 1) {
2559 device_printf(sc->sc_dev,
2560 "microcontroller initialization failed");
2561 break;
2562 }
2563 if (uc->subtype == IWN_UCODE_INIT) {
2564 /* Save microcontroller report. */
2565 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2566 }
2567 /* Save the address of the error log in SRAM. */
2568 sc->errptr = le32toh(uc->errptr);
2569 break;
2570 }
2571 case IWN_STATE_CHANGED:
2572 {
2573 uint32_t *status = (uint32_t *)(desc + 1);
2574
2575 /*
2576 * State change allows hardware switch change to be
2577 * noted. However, we handle this in iwn_intr as we
2578 * get both the enable/disble intr.
2579 */
2580 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2581 BUS_DMASYNC_POSTREAD);
2582 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
2583 le32toh(*status));
2584 break;
2585 }
2586 case IWN_START_SCAN:
2587 {
2588 struct iwn_start_scan *scan =
2589 (struct iwn_start_scan *)(desc + 1);
2590
2591 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2592 BUS_DMASYNC_POSTREAD);
2593 DPRINTF(sc, IWN_DEBUG_ANY,
2594 "%s: scanning channel %d status %x\n",
2595 __func__, scan->chan, le32toh(scan->status));
2596 break;
2597 }
2598 case IWN_STOP_SCAN:
2599 {
2600 struct iwn_stop_scan *scan =
2601 (struct iwn_stop_scan *)(desc + 1);
2602
2603 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2604 BUS_DMASYNC_POSTREAD);
2605 DPRINTF(sc, IWN_DEBUG_STATE,
2606 "scan finished nchan=%d status=%d chan=%d\n",
2607 scan->nchan, scan->status, scan->chan);
2608
2609 IWN_UNLOCK(sc);
2610 ieee80211_scan_next(vap);
2611 IWN_LOCK(sc);
2612 break;
2613 }
2614 case IWN5000_CALIBRATION_RESULT:
2615 iwn5000_rx_calib_results(sc, desc, data);
2616 break;
2617
2618 case IWN5000_CALIBRATION_DONE:
2619 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
2620 wakeup(sc);
2621 break;
2622 }
2623
2624 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
2625 }
2626
2627 /* Tell the firmware what we have processed. */
2628 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
2629 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
2630}
2631
2632/*
2633 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
2634 * from power-down sleep mode.
2635 */
2636static void
2637iwn_wakeup_intr(struct iwn_softc *sc)
2638{
2639 int qid;
2640
2641 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
2642 __func__);
2643
2644 /* Wakeup RX and TX rings. */
2645 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
2646 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) {
2647 struct iwn_tx_ring *ring = &sc->txq[qid];
2648 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
2649 }
2650}
2651
2652static void
2653iwn_rftoggle_intr(struct iwn_softc *sc)
2654{
2655 struct ifnet *ifp = sc->sc_ifp;
2656 struct ieee80211com *ic = ifp->if_l2com;
2657 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
2658
2659 IWN_LOCK_ASSERT(sc);
2660
2661 device_printf(sc->sc_dev, "RF switch: radio %s\n",
2662 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
2663 if (tmp & IWN_GP_CNTRL_RFKILL)
2664 ieee80211_runtask(ic, &sc->sc_radioon_task);
2665 else
2666 ieee80211_runtask(ic, &sc->sc_radiooff_task);
2667}
2668
2669/*
2670 * Dump the error log of the firmware when a firmware panic occurs. Although
2671 * we can't debug the firmware because it is neither open source nor free, it
2672 * can help us to identify certain classes of problems.
2673 */
2674static void
2675iwn_fatal_intr(struct iwn_softc *sc)
2676{
2677 const struct iwn_hal *hal = sc->sc_hal;
2678 struct iwn_fw_dump dump;
2679 int i;
2680
2681 IWN_LOCK_ASSERT(sc);
2682
2683 /* Force a complete recalibration on next init. */
2684 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
2685
2686 /* Check that the error log address is valid. */
2687 if (sc->errptr < IWN_FW_DATA_BASE ||
2688 sc->errptr + sizeof (dump) >
2689 IWN_FW_DATA_BASE + hal->fw_data_maxsz) {
3db796ac 2690 kprintf("%s: bad firmware error log address 0x%08x\n",
ffd7c74a
JT
2691 __func__, sc->errptr);
2692 return;
2693 }
2694 if (iwn_nic_lock(sc) != 0) {
3db796ac 2695 kprintf("%s: could not read firmware error log\n",
ffd7c74a
JT
2696 __func__);
2697 return;
2698 }
2699 /* Read firmware error log from SRAM. */
2700 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
2701 sizeof (dump) / sizeof (uint32_t));
2702 iwn_nic_unlock(sc);
2703
2704 if (dump.valid == 0) {
3db796ac 2705 kprintf("%s: firmware error log is empty\n",
ffd7c74a
JT
2706 __func__);
2707 return;
2708 }
3db796ac
JT
2709 kprintf("firmware error log:\n");
2710 kprintf(" error type = \"%s\" (0x%08X)\n",
ffd7c74a
JT
2711 (dump.id < nitems(iwn_fw_errmsg)) ?
2712 iwn_fw_errmsg[dump.id] : "UNKNOWN",
2713 dump.id);
3db796ac
JT
2714 kprintf(" program counter = 0x%08X\n", dump.pc);
2715 kprintf(" source line = 0x%08X\n", dump.src_line);
2716 kprintf(" error data = 0x%08X%08X\n",
ffd7c74a 2717 dump.error_data[0], dump.error_data[1]);
3db796ac 2718 kprintf(" branch link = 0x%08X%08X\n",
ffd7c74a 2719 dump.branch_link[0], dump.branch_link[1]);
3db796ac 2720 kprintf(" interrupt link = 0x%08X%08X\n",
ffd7c74a 2721 dump.interrupt_link[0], dump.interrupt_link[1]);
3db796ac 2722 kprintf(" time = %u\n", dump.time[0]);
ffd7c74a
JT
2723
2724 /* Dump driver status (TX and RX rings) while we're here. */
3db796ac 2725 kprintf("driver status:\n");
ffd7c74a
JT
2726 for (i = 0; i < hal->ntxqs; i++) {
2727 struct iwn_tx_ring *ring = &sc->txq[i];
3db796ac 2728 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
ffd7c74a
JT
2729 i, ring->qid, ring->cur, ring->queued);
2730 }
3db796ac 2731 kprintf(" rx ring: cur=%d\n", sc->rxq.cur);
ffd7c74a
JT
2732}
2733
2734static void
2735iwn_intr(void *arg)
2736{
2737 struct iwn_softc *sc = arg;
2738 struct ifnet *ifp = sc->sc_ifp;
2739 uint32_t r1, r2, tmp;
2740
1fb0473e
JT
2741 IWN_LOCK(sc);
2742
ffd7c74a
JT
2743 /* Disable interrupts. */
2744 IWN_WRITE(sc, IWN_INT_MASK, 0);
2745
2746 /* Read interrupts from ICT (fast) or from registers (slow). */
2747 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2748 tmp = 0;
2749 while (sc->ict[sc->ict_cur] != 0) {
2750 tmp |= sc->ict[sc->ict_cur];
2751 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
2752 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
2753 }
2754 tmp = le32toh(tmp);
2755 if (tmp == 0xffffffff) /* Shouldn't happen. */
2756 tmp = 0;
2757 else if (tmp & 0xc0000) /* Workaround a HW bug. */
2758 tmp |= 0x8000;
2759 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
2760 r2 = 0; /* Unused. */
2761 } else {
2762 r1 = IWN_READ(sc, IWN_INT);
2763 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
2764 return; /* Hardware gone! */
2765 r2 = IWN_READ(sc, IWN_FH_INT);
2766 }
2767
2768 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
2769
2770 if (r1 == 0 && r2 == 0)
2771 goto done; /* Interrupt not for us. */
2772
2773 /* Acknowledge interrupts. */
2774 IWN_WRITE(sc, IWN_INT, r1);
2775 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
2776 IWN_WRITE(sc, IWN_FH_INT, r2);
2777
2778 if (r1 & IWN_INT_RF_TOGGLED) {
2779 iwn_rftoggle_intr(sc);
2780 goto done;
2781 }
2782 if (r1 & IWN_INT_CT_REACHED) {
2783 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
2784 __func__);
2785 }
2786 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
2787 iwn_fatal_intr(sc);
2788 ifp->if_flags &= ~IFF_UP;
2789 iwn_stop_locked(sc);
2790 goto done;
2791 }
2792 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
2793 (r2 & IWN_FH_INT_RX)) {
2794 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2795 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
2796 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
2797 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2798 IWN_INT_PERIODIC_DIS);
2799 iwn_notif_intr(sc);
2800 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
2801 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2802 IWN_INT_PERIODIC_ENA);
2803 }
2804 } else
2805 iwn_notif_intr(sc);
2806 }
2807
2808 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
2809 if (sc->sc_flags & IWN_FLAG_USE_ICT)
2810 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
2811 wakeup(sc); /* FH DMA transfer completed. */
2812 }
2813
2814 if (r1 & IWN_INT_ALIVE)
2815 wakeup(sc); /* Firmware is alive. */
2816
2817 if (r1 & IWN_INT_WAKEUP)
2818 iwn_wakeup_intr(sc);
2819
2820done:
2821 /* Re-enable interrupts. */
2822 if (ifp->if_flags & IFF_UP)
2823 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2824
1fb0473e
JT
2825 IWN_UNLOCK(sc);
2826
ffd7c74a
JT
2827}
2828
2829/*
2830 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
2831 * 5000 adapters use a slightly different format.)
2832 */
2833static void
2834iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2835 uint16_t len)
2836{
2837 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
2838
2839 *w = htole16(len + 8);
2840 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2841 BUS_DMASYNC_PREWRITE);
2842 if (idx < IWN_SCHED_WINSZ) {
2843 *(w + IWN_TX_RING_COUNT) = *w;
2844 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2845 BUS_DMASYNC_PREWRITE);
2846 }
2847}
2848
2849static void
2850iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2851 uint16_t len)
2852{
2853 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2854
2855 *w = htole16(id << 12 | (len + 8));
2856
2857 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2858 BUS_DMASYNC_PREWRITE);
2859 if (idx < IWN_SCHED_WINSZ) {
2860 *(w + IWN_TX_RING_COUNT) = *w;
2861 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2862 BUS_DMASYNC_PREWRITE);
2863 }
2864}
2865
2866#ifdef notyet
2867static void
2868iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
2869{
2870 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2871
2872 *w = (*w & htole16(0xf000)) | htole16(1);
2873 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2874 BUS_DMASYNC_PREWRITE);
2875 if (idx < IWN_SCHED_WINSZ) {
2876 *(w + IWN_TX_RING_COUNT) = *w;
2877 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2878 BUS_DMASYNC_PREWRITE);
2879 }
2880}
2881#endif
2882
2883static uint8_t
2884iwn_plcp_signal(int rate) {
2885 int i;
2886
2887 for (i = 0; i < IWN_RIDX_MAX + 1; i++) {
2888 if (rate == iwn_rates[i].rate)
2889 return i;
2890 }
2891
2892 return 0;
2893}
2894
2895static int
2896iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
2897 struct iwn_tx_ring *ring)
2898{
2899 const struct iwn_hal *hal = sc->sc_hal;
2900 const struct ieee80211_txparam *tp;
2901 const struct iwn_rate *rinfo;
2902 struct ieee80211vap *vap = ni->ni_vap;
2903 struct ieee80211com *ic = ni->ni_ic;
2904 struct iwn_node *wn = (void *)ni;
2905 struct iwn_tx_desc *desc;
2906 struct iwn_tx_data *data;
2907 struct iwn_tx_cmd *cmd;
2908 struct iwn_cmd_data *tx;
2909 struct ieee80211_frame *wh;
2910 struct ieee80211_key *k = NULL;
2911 struct mbuf *mnew;
2912 bus_dma_segment_t segs[IWN_MAX_SCATTER];
2913 uint32_t flags;
2914 u_int hdrlen;
2915 int totlen, error, pad, nsegs = 0, i, rate;
2916 uint8_t ridx, type, txant;
2917
2918 IWN_LOCK_ASSERT(sc);
2919
2920 wh = mtod(m, struct ieee80211_frame *);
2921 hdrlen = ieee80211_anyhdrsize(wh);
2922 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2923
2924 desc = &ring->desc[ring->cur];
2925 data = &ring->data[ring->cur];
2926
2927 /* Choose a TX rate index. */
2928 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
2929 if (type == IEEE80211_FC0_TYPE_MGT)
2930 rate = tp->mgmtrate;
2931 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
2932 rate = tp->mcastrate;
2933 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
2934 rate = tp->ucastrate;
2935 else {
2936 /* XXX pass pktlen */
3db796ac
JT
2937 ieee80211_ratectl_rate(ni, NULL, 0);
2938
ffd7c74a
JT
2939 rate = ni->ni_txrate;
2940 }
2941 ridx = iwn_plcp_signal(rate);
2942 rinfo = &iwn_rates[ridx];
2943
2944 /* Encrypt the frame if need be. */
2945 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2946 k = ieee80211_crypto_encap(ni, m);
2947 if (k == NULL) {
2948 m_freem(m);
2949 return ENOBUFS;
2950 }
2951 /* Packet header may have moved, reset our local pointer. */
2952 wh = mtod(m, struct ieee80211_frame *);
2953 }
2954 totlen = m->m_pkthdr.len;
2955
2956 if (ieee80211_radiotap_active_vap(vap)) {
2957 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
2958
2959 tap->wt_flags = 0;
2960 tap->wt_rate = rinfo->rate;
2961 if (k != NULL)
2962 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2963
2964 ieee80211_radiotap_tx(vap, m);
2965 }
2966
2967 /* Prepare TX firmware command. */
2968 cmd = &ring->cmd[ring->cur];
2969 cmd->code = IWN_CMD_TX_DATA;
2970 cmd->flags = 0;
2971 cmd->qid = ring->qid;
2972 cmd->idx = ring->cur;
2973
2974 tx = (struct iwn_cmd_data *)cmd->data;
2975 /* NB: No need to clear tx, all fields are reinitialized here. */
2976 tx->scratch = 0; /* clear "scratch" area */
2977
2978 flags = 0;
2979 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
2980 flags |= IWN_TX_NEED_ACK;
2981 if ((wh->i_fc[0] &
2982 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
2983 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
2984 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
2985
2986 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
2987 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
2988
2989 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
2990 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2991 /* NB: Group frames are sent using CCK in 802.11b/g. */
2992 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
2993 flags |= IWN_TX_NEED_RTS;
2994 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
2995 ridx >= IWN_RIDX_OFDM6) {
2996 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2997 flags |= IWN_TX_NEED_CTS;
2998 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2999 flags |= IWN_TX_NEED_RTS;
3000 }
3001 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
3002 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3003 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3004 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
3005 flags |= IWN_TX_NEED_PROTECTION;
3006 } else
3007 flags |= IWN_TX_FULL_TXOP;
3008 }
3009 }
3010
3011 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3012 type != IEEE80211_FC0_TYPE_DATA)
3013 tx->id = hal->broadcast_id;
3014 else
3015 tx->id = wn->id;
3016
3017 if (type == IEEE80211_FC0_TYPE_MGT) {
3018 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3019
3020 /* Tell HW to set timestamp in probe responses. */
3021 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3022 flags |= IWN_TX_INSERT_TSTAMP;
3023
3024 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3025 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3026 tx->timeout = htole16(3);
3027 else
3028 tx->timeout = htole16(2);
3029 } else
3030 tx->timeout = htole16(0);
3031
3032 if (hdrlen & 3) {
3033 /* First segment length must be a multiple of 4. */
3034 flags |= IWN_TX_NEED_PADDING;
3035 pad = 4 - (hdrlen & 3);
3036 } else
3037 pad = 0;
3038
3039 tx->len = htole16(totlen);
3040 tx->tid = 0;
3041 tx->rts_ntries = 60;
3042 tx->data_ntries = 15;
3043 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3044 tx->plcp = rinfo->plcp;
3045 tx->rflags = rinfo->flags;
3046 if (tx->id == hal->broadcast_id) {
3047 /* Group or management frame. */
3048 tx->linkq = 0;
3049 /* XXX Alternate between antenna A and B? */
3050 txant = IWN_LSB(sc->txchainmask);
3051 tx->rflags |= IWN_RFLAG_ANT(txant);
3052 } else {
d50981ca 3053 tx->linkq = IWN_RIDX_OFDM54 - ridx;
ffd7c74a
JT
3054 flags |= IWN_TX_LINKQ; /* enable MRR */
3055 }
3056
3057 /* Set physical address of "scratch area". */
3058 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3059 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3060
3061 /* Copy 802.11 header in TX command. */
3062 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3063
3064 /* Trim 802.11 header. */
3065 m_adj(m, hdrlen);
3066 tx->security = 0;
3067 tx->flags = htole32(flags);
3068
3069 if (m->m_len > 0) {
3db796ac
JT
3070 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3071 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT
3072 if (error == EFBIG) {
3073 /* too many fragments, linearize */
3db796ac 3074 mnew = m_defrag(m, MB_DONTWAIT);
ffd7c74a
JT
3075 if (mnew == NULL) {
3076 device_printf(sc->sc_dev,
3077 "%s: could not defrag mbuf\n", __func__);
3078 m_freem(m);
3079 return ENOBUFS;
3080 }
3081 m = mnew;
3db796ac
JT
3082 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3083 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT
3084 }
3085 if (error != 0) {
3086 device_printf(sc->sc_dev,
3db796ac 3087 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
ffd7c74a
JT
3088 __func__, error);
3089 m_freem(m);
3090 return error;
3091 }
3092 }
3093
3094 data->m = m;
3095 data->ni = ni;
3096
3097 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3098 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3099
3100 /* Fill TX descriptor. */
3101 desc->nsegs = 1 + nsegs;
3102 /* First DMA segment is used by the TX command. */
3103 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3104 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3105 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3106 /* Other DMA segments are for data payload. */
3107 for (i = 1; i <= nsegs; i++) {
3108 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3109 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3110 segs[i - 1].ds_len << 4);
3111 }
3112
3113 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3114 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3115 BUS_DMASYNC_PREWRITE);
3116 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3117 BUS_DMASYNC_PREWRITE);
3118
3119#ifdef notyet
3120 /* Update TX scheduler. */
3121 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3122#endif
3123
3124 /* Kick TX ring. */
3125 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3126 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3127
3128 /* Mark TX ring as full if we reach a certain threshold. */
3129 if (++ring->queued > IWN_TX_RING_HIMARK)
3130 sc->qfullmsk |= 1 << ring->qid;
3131
3132 return 0;
3133}
3134
3135static int
3136iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3137 struct ieee80211_node *ni, struct iwn_tx_ring *ring,
3138 const struct ieee80211_bpf_params *params)
3139{
3140 const struct iwn_hal *hal = sc->sc_hal;
3141 const struct iwn_rate *rinfo;
3142 struct ifnet *ifp = sc->sc_ifp;
3143 struct ieee80211vap *vap = ni->ni_vap;
3144 struct ieee80211com *ic = ifp->if_l2com;
3145 struct iwn_tx_cmd *cmd;
3146 struct iwn_cmd_data *tx;
3147 struct ieee80211_frame *wh;
3148 struct iwn_tx_desc *desc;
3149 struct iwn_tx_data *data;
3150 struct mbuf *mnew;
3151 bus_addr_t paddr;
3152 bus_dma_segment_t segs[IWN_MAX_SCATTER];
3153 uint32_t flags;
3154 u_int hdrlen;
3155 int totlen, error, pad, nsegs = 0, i, rate;
3156 uint8_t ridx, type, txant;
3157
3158 IWN_LOCK_ASSERT(sc);
3159
3160 wh = mtod(m, struct ieee80211_frame *);
3161 hdrlen = ieee80211_anyhdrsize(wh);
3162 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3163
3164 desc = &ring->desc[ring->cur];
3165 data = &ring->data[ring->cur];
3166
3167 /* Choose a TX rate index. */
3168 rate = params->ibp_rate0;
3169 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3170 /* XXX fall back to mcast/mgmt rate? */
3171 m_freem(m);
3172 return EINVAL;
3173 }
3174 ridx = iwn_plcp_signal(rate);
3175 rinfo = &iwn_rates[ridx];
3176
3177 totlen = m->m_pkthdr.len;
3178
3179 /* Prepare TX firmware command. */
3180 cmd = &ring->cmd[ring->cur];
3181 cmd->code = IWN_CMD_TX_DATA;
3182 cmd->flags = 0;
3183 cmd->qid = ring->qid;
3184 cmd->idx = ring->cur;
3185
3186 tx = (struct iwn_cmd_data *)cmd->data;
3187 /* NB: No need to clear tx, all fields are reinitialized here. */
3188 tx->scratch = 0; /* clear "scratch" area */
3189
3190 flags = 0;
3191 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3192 flags |= IWN_TX_NEED_ACK;
3193 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3194 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3195 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3196 flags &= ~IWN_TX_NEED_RTS;
3197 flags |= IWN_TX_NEED_PROTECTION;
3198 } else
3199 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3200 }
3201 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3202 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3203 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3204 flags &= ~IWN_TX_NEED_CTS;
3205 flags |= IWN_TX_NEED_PROTECTION;
3206 } else
3207 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3208 }
3209 if (type == IEEE80211_FC0_TYPE_MGT) {
3210 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3211
3212 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3213 flags |= IWN_TX_INSERT_TSTAMP;
3214
3215 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3216 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3217 tx->timeout = htole16(3);
3218 else
3219 tx->timeout = htole16(2);
3220 } else
3221 tx->timeout = htole16(0);
3222
3223 if (hdrlen & 3) {
3224 /* First segment length must be a multiple of 4. */
3225 flags |= IWN_TX_NEED_PADDING;
3226 pad = 4 - (hdrlen & 3);
3227 } else
3228 pad = 0;
3229
3230 if (ieee80211_radiotap_active_vap(vap)) {
3231 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3232
3233 tap->wt_flags = 0;
3234 tap->wt_rate = rate;
3235
3236 ieee80211_radiotap_tx(vap, m);
3237 }
3238
3239 tx->len = htole16(totlen);
3240 tx->tid = 0;
3241 tx->id = hal->broadcast_id;
3242 tx->rts_ntries = params->ibp_try1;
3243 tx->data_ntries = params->ibp_try0;
3244 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3245 tx->plcp = rinfo->plcp;
3246 tx->rflags = rinfo->flags;
3247 /* Group or management frame. */
3248 tx->linkq = 0;
3249 txant = IWN_LSB(sc->txchainmask);
3250 tx->rflags |= IWN_RFLAG_ANT(txant);
3251 /* Set physical address of "scratch area". */
3252 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd);
3253 tx->loaddr = htole32(IWN_LOADDR(paddr));
3254 tx->hiaddr = IWN_HIADDR(paddr);
3255
3256 /* Copy 802.11 header in TX command. */
3257 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3258
3259 /* Trim 802.11 header. */
3260 m_adj(m, hdrlen);
3261 tx->security = 0;
3262 tx->flags = htole32(flags);
3263
3264 if (m->m_len > 0) {
3db796ac
JT
3265 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3266 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT
3267 if (error == EFBIG) {
3268 /* Too many fragments, linearize. */
3db796ac 3269 mnew = m_defrag(m, MB_DONTWAIT);
ffd7c74a
JT
3270 if (mnew == NULL) {
3271 device_printf(sc->sc_dev,
3272 "%s: could not defrag mbuf\n", __func__);
3273 m_freem(m);
3274 return ENOBUFS;
3275 }
3276 m = mnew;
3db796ac
JT
3277 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3278 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT
3279 }
3280 if (error != 0) {
3281 device_printf(sc->sc_dev,
3db796ac 3282 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
ffd7c74a
JT
3283 __func__, error);
3284 m_freem(m);
3285 return error;
3286 }
3287 }
3288
3289 data->m = m;
3290 data->ni = ni;
3291
3292 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3293 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3294
3295 /* Fill TX descriptor. */
3296 desc->nsegs = 1 + nsegs;
3297 /* First DMA segment is used by the TX command. */
3298 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3299 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3300 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3301 /* Other DMA segments are for data payload. */
3302 for (i = 1; i <= nsegs; i++) {
3303 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3304 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3305 segs[i - 1].ds_len << 4);
3306 }
3307
3308 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3309 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3310 BUS_DMASYNC_PREWRITE);
3311 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3312 BUS_DMASYNC_PREWRITE);
3313
3314#ifdef notyet
3315 /* Update TX scheduler. */
3316 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3317#endif
3318
3319 /* Kick TX ring. */
3320 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3321 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3322
3323 /* Mark TX ring as full if we reach a certain threshold. */
3324 if (++ring->queued > IWN_TX_RING_HIMARK)
3325 sc->qfullmsk |= 1 << ring->qid;
3326
3327 return 0;
3328}
3329
3330static int
3331iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3332 const struct ieee80211_bpf_params *params)
3333{
3334 struct ieee80211com *ic = ni->ni_ic;
3335 struct ifnet *ifp = ic->ic_ifp;
3336 struct iwn_softc *sc = ifp->if_softc;
3337 struct iwn_tx_ring *txq;
3338 int error = 0;
3339
3db796ac 3340 if ((ifp->if_flags & IFF_RUNNING) == 0) {
ffd7c74a
JT
3341 ieee80211_free_node(ni);
3342 m_freem(m);
3343 return ENETDOWN;
3344 }
3345
3346 IWN_LOCK(sc);
3347 if (params == NULL)
3348 txq = &sc->txq[M_WME_GETAC(m)];
3349 else
3350 txq = &sc->txq[params->ibp_pri & 3];
3351
3352 if (params == NULL) {
3353 /*
3354 * Legacy path; interpret frame contents to decide
3355 * precisely how to send the frame.
3356 */
3357 error = iwn_tx_data(sc, m, ni, txq);
3358 } else {
3359 /*
3360 * Caller supplied explicit parameters to use in
3361 * sending the frame.
3362 */
3363 error = iwn_tx_data_raw(sc, m, ni, txq, params);
3364 }
3365 if (error != 0) {
3366 /* NB: m is reclaimed on tx failure */
3367 ieee80211_free_node(ni);
3368 ifp->if_oerrors++;
3369 }
3370 IWN_UNLOCK(sc);
3371 return error;
3372}
3373
3374static void
3375iwn_start(struct ifnet *ifp)
3376{
3377 struct iwn_softc *sc = ifp->if_softc;
3378
1fb0473e 3379 IWN_LOCK(sc);
ffd7c74a 3380 iwn_start_locked(ifp);
1fb0473e 3381 IWN_UNLOCK(sc);
ffd7c74a
JT
3382}
3383
3384static void
3385iwn_start_locked(struct ifnet *ifp)
3386{
3387 struct iwn_softc *sc = ifp->if_softc;
3388 struct ieee80211_node *ni;
3389 struct iwn_tx_ring *txq;
3390 struct mbuf *m;
3391 int pri;
3392
3393 IWN_LOCK_ASSERT(sc);
3394
3395 for (;;) {
3396 if (sc->qfullmsk != 0) {
3db796ac 3397 ifp->if_flags |= IFF_OACTIVE;
ffd7c74a
JT
3398 break;
3399 }
3db796ac 3400 m = ifq_dequeue(&ifp->if_snd, NULL);
ffd7c74a
JT
3401 if (m == NULL)
3402 break;
3403 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3404 pri = M_WME_GETAC(m);
3405 txq = &sc->txq[pri];
3406 if (iwn_tx_data(sc, m, ni, txq) != 0) {
3407 ifp->if_oerrors++;
3408 ieee80211_free_node(ni);
3409 break;
3410 }
3411 sc->sc_tx_timer = 5;
3412 }
3413}
3414
3415static void
3416iwn_watchdog(struct iwn_softc *sc)
3417{
3418 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
3419 struct ifnet *ifp = sc->sc_ifp;
3420 struct ieee80211com *ic = ifp->if_l2com;
3421
3422 if_printf(ifp, "device timeout\n");
3423 ieee80211_runtask(ic, &sc->sc_reinit_task);
3424 }
3425}
3426
3427static int
3db796ac 3428iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
ffd7c74a
JT
3429{
3430 struct iwn_softc *sc = ifp->if_softc;
3431 struct ieee80211com *ic = ifp->if_l2com;
3432 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3433 struct ifreq *ifr = (struct ifreq *) data;
3434 int error = 0, startall = 0, stop = 0;
3435
3436 switch (cmd) {
3437 case SIOCSIFFLAGS:
3438 IWN_LOCK(sc);
3439 if (ifp->if_flags & IFF_UP) {
3db796ac 3440 if (!(ifp->if_flags & IFF_RUNNING)) {
ffd7c74a
JT
3441 iwn_init_locked(sc);
3442 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3443 startall = 1;
3444 else
3445 stop = 1;
3446 }
3447 } else {
3db796ac 3448 if (ifp->if_flags & IFF_RUNNING)
ffd7c74a
JT
3449 iwn_stop_locked(sc);
3450 }
3451 IWN_UNLOCK(sc);
3452 if (startall)
3453 ieee80211_start_all(ic);
3454 else if (vap != NULL && stop)
3455 ieee80211_stop(vap);
3456 break;
3457 case SIOCGIFMEDIA:
3458 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3459 break;
3460 case SIOCGIFADDR:
3461 error = ether_ioctl(ifp, cmd, data);
3462 break;
3463 default:
3464 error = EINVAL;
3465 break;
3466 }
3467 return error;
3468}
3469
3470/*
3471 * Send a command to the firmware.
3472 */
3473static int
3474iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3475{
3476 struct iwn_tx_ring *ring = &sc->txq[4];
3477 struct iwn_tx_desc *desc;
3478 struct iwn_tx_data *data;
3479 struct iwn_tx_cmd *cmd;
3480 struct mbuf *m;
3481 bus_addr_t paddr;
3482 int totlen, error;
3483
3484 IWN_LOCK_ASSERT(sc);
3485
3486 desc = &ring->desc[ring->cur];
3487 data = &ring->data[ring->cur];
3488 totlen = 4 + size;
3489
3490 if (size > sizeof cmd->data) {
3491 /* Command is too large to fit in a descriptor. */
3492 if (totlen > MCLBYTES)
3493 return EINVAL;
3db796ac 3494 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT
3495 if (m == NULL)
3496 return ENOMEM;
3497 cmd = mtod(m, struct iwn_tx_cmd *);
3498 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3499 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3500 if (error != 0) {
3501 m_freem(m);
3502 return error;
3503 }
3504 data->m = m;
3505 } else {
3506 cmd = &ring->cmd[ring->cur];
3507 paddr = data->cmd_paddr;
3508 }
3509
3510 cmd->code = code;
3511 cmd->flags = 0;
3512 cmd->qid = ring->qid;
3513 cmd->idx = ring->cur;
3514 memcpy(cmd->data, buf, size);
3515
3516 desc->nsegs = 1;
3517 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3518 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3519
3520 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
3521 __func__, iwn_intr_str(cmd->code), cmd->code,
3522 cmd->flags, cmd->qid, cmd->idx);
3523
3524 if (size > sizeof cmd->data) {
3525 bus_dmamap_sync(ring->data_dmat, data->map,
3526 BUS_DMASYNC_PREWRITE);
3527 } else {
3528 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3529 BUS_DMASYNC_PREWRITE);
3530 }
3531 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3532 BUS_DMASYNC_PREWRITE);
3533
3534#ifdef notyet
3535 /* Update TX scheduler. */
3536 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0);
3537#endif
3538
3539 /* Kick command ring. */
3540 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3541 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3542
a945833d 3543 return async ? 0 : tsleep(desc, 0, "iwncmd", hz);
ffd7c74a
JT
3544}
3545
3546static int
3547iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3548{
3549 struct iwn4965_node_info hnode;
3550 caddr_t src, dst;
3551
3552 /*
3553 * We use the node structure for 5000 Series internally (it is
3554 * a superset of the one for 4965AGN). We thus copy the common
3555 * fields before sending the command.
3556 */
3557 src = (caddr_t)node;
3558 dst = (caddr_t)&hnode;
3559 memcpy(dst, src, 48);
3560 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3561 memcpy(dst + 48, src + 72, 20);
3562 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3563}
3564
3565static int
3566iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3567{
3568 /* Direct mapping. */
3569 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3570}
3571
3572#if 0 /* HT */
3573static const uint8_t iwn_ridx_to_plcp[] = {
3574 10, 20, 55, 110, /* CCK */
3575 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */
3576};
3577static const uint8_t iwn_siso_mcs_to_plcp[] = {
3578 0, 0, 0, 0, /* CCK */
3579 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */
3580};
3581static const uint8_t iwn_mimo_mcs_to_plcp[] = {
3582 0, 0, 0, 0, /* CCK */
3583 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */
3584};
3585#endif
3586static const uint8_t iwn_prev_ridx[] = {
3587 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */
3588 0, 0, 1, 5, /* CCK */
3589 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */
3590};
3591
3592/*
3593 * Configure hardware link parameters for the specified
3594 * node operating on the specified channel.
3595 */
3596static int
3597iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async)
3598{
3599 struct ifnet *ifp = sc->sc_ifp;
3600 struct ieee80211com *ic = ifp->if_l2com;
3601 struct iwn_cmd_link_quality linkq;
3602 const struct iwn_rate *rinfo;
3603 int i;
3604 uint8_t txant, ridx;
3605
3606 /* Use the first valid TX antenna. */
3607 txant = IWN_LSB(sc->txchainmask);
3608
3609 memset(&linkq, 0, sizeof linkq);
3610 linkq.id = id;
3611 linkq.antmsk_1stream = txant;
3612 linkq.antmsk_2stream = IWN_ANT_AB;
3613 linkq.ampdu_max = 31;
3614 linkq.ampdu_threshold = 3;
3615 linkq.ampdu_limit = htole16(4000); /* 4ms */
3616
3617#if 0 /* HT */
3618 if (IEEE80211_IS_CHAN_HT(c))
3619 linkq.mimo = 1;
3620#endif
3621
3622 if (id == IWN_ID_BSS)
3623 ridx = IWN_RIDX_OFDM54;
3624 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan))
3625 ridx = IWN_RIDX_OFDM6;
3626 else
3627 ridx = IWN_RIDX_CCK1;
3628
3629 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
3630 rinfo = &iwn_rates[ridx];
3631#if 0 /* HT */
3632 if (IEEE80211_IS_CHAN_HT40(c)) {
3633 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx]
3634 | IWN_RIDX_MCS;
3635 linkq.retry[i].rflags = IWN_RFLAG_HT
3636 | IWN_RFLAG_HT40;
3637 /* XXX shortGI */
3638 } else if (IEEE80211_IS_CHAN_HT(c)) {
3639 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx]
3640 | IWN_RIDX_MCS;
3641 linkq.retry[i].rflags = IWN_RFLAG_HT;
3642 /* XXX shortGI */
3643 } else
3644#endif
3645 {
3646 linkq.retry[i].plcp = rinfo->plcp;
3647 linkq.retry[i].rflags = rinfo->flags;
3648 }
3649 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant);
3650 ridx = iwn_prev_ridx[ridx];
3651 }
3652#ifdef IWN_DEBUG
3653 if (sc->sc_debug & IWN_DEBUG_STATE) {
3db796ac 3654 kprintf("%s: set link quality for node %d, mimo %d ssmask %d\n",
ffd7c74a 3655 __func__, id, linkq.mimo, linkq.antmsk_1stream);
3db796ac 3656 kprintf("%s:", __func__);
ffd7c74a 3657 for (i = 0; i < IWN_MAX_TX_RETRIES; i++)
3db796ac 3658 kprintf(" %d:%x", linkq.retry[i].plcp,
ffd7c74a 3659 linkq.retry[i].rflags);
3db796ac 3660 kprintf("\n");
ffd7c74a
JT
3661 }
3662#endif
3663 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
3664}
3665
3666/*
3667 * Broadcast node is used to send group-addressed and management frames.
3668 */
3669static int
3670iwn_add_broadcast_node(struct iwn_softc *sc, int async)
3671{
3672 const struct iwn_hal *hal = sc->sc_hal;
3673 struct ifnet *ifp = sc->sc_ifp;
3674 struct iwn_node_info node;
3675 int error;
3676
3677 memset(&node, 0, sizeof node);
3678 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
3679 node.id = hal->broadcast_id;
3680 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
3681 error = hal->add_node(sc, &node, async);
3682 if (error != 0)
3683 return error;
3684
3685 error = iwn_set_link_quality(sc, hal->broadcast_id, async);
3686 return error;
3687}
3688
3689static int
3690iwn_wme_update(struct ieee80211com *ic)
3691{
3692#define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
3693#define IWN_TXOP_TO_US(v) (v<<5)
3694 struct iwn_softc *sc = ic->ic_ifp->if_softc;
3695 struct iwn_edca_params cmd;
3696 int i;
3697
3698 memset(&cmd, 0, sizeof cmd);
3699 cmd.flags = htole32(IWN_EDCA_UPDATE);
3700 for (i = 0; i < WME_NUM_AC; i++) {
3701 const struct wmeParams *wmep =
3702 &ic->ic_wme.wme_chanParams.cap_wmeParams[i];
3703 cmd.ac[i].aifsn = wmep->wmep_aifsn;
3704 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin));
3705 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax));
3706 cmd.ac[i].txoplimit =
3707 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit));
3708 }
3709 IEEE80211_UNLOCK(ic);
3710 IWN_LOCK(sc);
3711 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/);
3712 IWN_UNLOCK(sc);
3713 IEEE80211_LOCK(ic);
3714 return 0;
3715#undef IWN_TXOP_TO_US
3716#undef IWN_EXP2
3717}
3718
3719static void
3720iwn_update_mcast(struct ifnet *ifp)
3721{
3722 /* Ignore */
3723}
3724
3725static void
3726iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
3727{
3728 struct iwn_cmd_led led;
3729
3730 /* Clear microcode LED ownership. */
3731 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
3732
3733 led.which = which;
3734 led.unit = htole32(10000); /* on/off in unit of 100ms */
3735 led.off = off;
3736 led.on = on;
3737 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
3738}
3739
3740/*
3741 * Set the critical temperature at which the firmware will stop the radio
3742 * and notify us.
3743 */
3744static int
3745iwn_set_critical_temp(struct iwn_softc *sc)
3746{
3747 struct iwn_critical_temp crit;
3748 int32_t temp;
3749
3750 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
3751
3752 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
3753 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
3754 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3755 temp = IWN_CTOK(110);
3756 else
3757 temp = 110;
3758 memset(&crit, 0, sizeof crit);
3759 crit.tempR = htole32(temp);
3760 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n",
3761 temp);
3762 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
3763}
3764
3765static int
3766iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
3767{
3768 struct iwn_cmd_timing cmd;
3769 uint64_t val, mod;
3770
3771 memset(&cmd, 0, sizeof cmd);
3772 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
3773 cmd.bintval = htole16(ni->ni_intval);
3774 cmd.lintval = htole16(10);
3775
3776 /* Compute remaining time until next beacon. */
3777 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
3778 mod = le64toh(cmd.tstamp) % val;
3779 cmd.binitval = htole32((uint32_t)(val - mod));
3780
3781 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
3782 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
3783
3784 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
3785}
3786
3787static void
3788iwn4965_power_calibration(struct iwn_softc *sc, int temp)
3789{
3790 struct ifnet *ifp = sc->sc_ifp;
3791 struct ieee80211com *ic = ifp->if_l2com;
3792
3793 /* Adjust TX power if need be (delta >= 3 degC.) */
3794 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
3795 __func__, sc->temp, temp);
3796 if (abs(temp - sc->temp) >= 3) {
3797 /* Record temperature of last calibration. */
3798 sc->temp = temp;
3799 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
3800 }
3801}
3802
3803/*
3804 * Set TX power for current channel (each rate has its own power settings).
3805 * This function takes into account the regulatory information from EEPROM,
3806 * the current temperature and the current voltage.
3807 */
3808static int
3809iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3810 int async)
3811{
3812/* Fixed-point arithmetic division using a n-bit fractional part. */
3813#define fdivround(a, b, n) \
3814 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
3815/* Linear interpolation. */
3816#define interpolate(x, x1, y1, x2, y2, n) \
3817 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
3818
3819 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
3820 struct ifnet *ifp = sc->sc_ifp;
3821 struct ieee80211com *ic = ifp->if_l2com;
3822 struct iwn_ucode_info *uc = &sc->ucode_info;
3823 struct iwn4965_cmd_txpower cmd;
3824 struct iwn4965_eeprom_chan_samples *chans;
3825 int32_t vdiff, tdiff;
3826 int i, c, grp, maxpwr;
3827 const uint8_t *rf_gain, *dsp_gain;
3828 uint8_t chan;
3829
3830 /* Retrieve channel number. */
3831 chan = ieee80211_chan2ieee(ic, ch);
3832 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
3833 chan);
3834
3835 memset(&cmd, 0, sizeof cmd);
3836 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
3837 cmd.chan = chan;
3838
3839 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
3840 maxpwr = sc->maxpwr5GHz;
3841 rf_gain = iwn4965_rf_gain_5ghz;
3842 dsp_gain = iwn4965_dsp_gain_5ghz;
3843 } else {
3844 maxpwr = sc->maxpwr2GHz;
3845 rf_gain = iwn4965_rf_gain_2ghz;
3846 dsp_gain = iwn4965_dsp_gain_2ghz;
3847 }
3848
3849 /* Compute voltage compensation. */
3850 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
3851 if (vdiff > 0)
3852 vdiff *= 2;
3853 if (abs(vdiff) > 2)
3854 vdiff = 0;
3855 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3856 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
3857 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
3858
3859 /* Get channel attenuation group. */
3860 if (chan <= 20) /* 1-20 */
3861 grp = 4;
3862 else if (chan <= 43) /* 34-43 */
3863 grp = 0;
3864 else if (chan <= 70) /* 44-70 */
3865 grp = 1;
3866 else if (chan <= 124) /* 71-124 */
3867 grp = 2;
3868 else /* 125-200 */
3869 grp = 3;
3870 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3871 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
3872
3873 /* Get channel sub-band. */
3874 for (i = 0; i < IWN_NBANDS; i++)
3875 if (sc->bands[i].lo != 0 &&
3876 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
3877 break;
3878 if (i == IWN_NBANDS) /* Can't happen in real-life. */
3879 return EINVAL;
3880 chans = sc->bands[i].chans;
3881 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3882 "%s: chan %d sub-band=%d\n", __func__, chan, i);
3883
3884 for (c = 0; c < 2; c++) {
3885 uint8_t power, gain, temp;
3886 int maxchpwr, pwr, ridx, idx;
3887
3888 power = interpolate(chan,
3889 chans[0].num, chans[0].samples[c][1].power,
3890 chans[1].num, chans[1].samples[c][1].power, 1);
3891 gain = interpolate(chan,
3892 chans[0].num, chans[0].samples[c][1].gain,
3893 chans[1].num, chans[1].samples[c][1].gain, 1);
3894 temp = interpolate(chan,
3895 chans[0].num, chans[0].samples[c][1].temp,
3896 chans[1].num, chans[1].samples[c][1].temp, 1);
3897 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3898 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
3899 __func__, c, power, gain, temp);
3900
3901 /* Compute temperature compensation. */
3902 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
3903 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3904 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
3905 __func__, tdiff, sc->temp, temp);
3906
3907 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
3908 /* Convert dBm to half-dBm. */
3909 maxchpwr = sc->maxpwr[chan] * 2;
3910 if ((ridx / 8) & 1)
3911 maxchpwr -= 6; /* MIMO 2T: -3dB */
3912
3913 pwr = maxpwr;
3914
3915 /* Adjust TX power based on rate. */
3916 if ((ridx % 8) == 5)
3917 pwr -= 15; /* OFDM48: -7.5dB */
3918 else if ((ridx % 8) == 6)
3919 pwr -= 17; /* OFDM54: -8.5dB */
3920 else if ((ridx % 8) == 7)
3921 pwr -= 20; /* OFDM60: -10dB */
3922 else
3923 pwr -= 10; /* Others: -5dB */
3924
3925 /* Do not exceed channel max TX power. */
3926 if (pwr > maxchpwr)
3927 pwr = maxchpwr;
3928
3929 idx = gain - (pwr - power) - tdiff - vdiff;
3930 if ((ridx / 8) & 1) /* MIMO */
3931 idx += (int32_t)le32toh(uc->atten[grp][c]);
3932
3933 if (cmd.band == 0)
3934 idx += 9; /* 5GHz */
3935 if (ridx == IWN_RIDX_MAX)
3936 idx += 5; /* CCK */
3937
3938 /* Make sure idx stays in a valid range. */
3939 if (idx < 0)
3940 idx = 0;
3941 else if (idx > IWN4965_MAX_PWR_INDEX)
3942 idx = IWN4965_MAX_PWR_INDEX;
3943
3944 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3945 "%s: Tx chain %d, rate idx %d: power=%d\n",
3946 __func__, c, ridx, idx);
3947 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
3948 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
3949 }
3950 }
3951
3952 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3953 "%s: set tx power for chan %d\n", __func__, chan);
3954 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
3955
3956#undef interpolate
3957#undef fdivround
3958}
3959
3960static int
3961iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3962 int async)
3963{
3964 struct iwn5000_cmd_txpower cmd;
3965
3966 /*
3967 * TX power calibration is handled automatically by the firmware
3968 * for 5000 Series.
3969 */
3970 memset(&cmd, 0, sizeof cmd);
3971 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
3972 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
3973 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
3974 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
3975 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
3976}
3977
3978/*
3979 * Retrieve the maximum RSSI (in dBm) among receivers.
3980 */
3981static int
3982iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
3983{
3984 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
3985 uint8_t mask, agc;
3986 int rssi;
3987
3988 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
3989 agc = (le16toh(phy->agc) >> 7) & 0x7f;
3990
3991 rssi = 0;
3992#if 0
3993 if (mask & IWN_ANT_A) /* Ant A */
3994 rssi = max(rssi, phy->rssi[0]);
3995 if (mask & IWN_ATH_B) /* Ant B */
3996 rssi = max(rssi, phy->rssi[2]);
3997 if (mask & IWN_ANT_C) /* Ant C */
3998 rssi = max(rssi, phy->rssi[4]);
3999#else
4000 rssi = max(rssi, phy->rssi[0]);
4001 rssi = max(rssi, phy->rssi[2]);
4002 rssi = max(rssi, phy->rssi[4]);
4003#endif
4004
4005 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d "
4006 "result %d\n", __func__, agc, mask,
4007 phy->rssi[0], phy->rssi[2], phy->rssi[4],
4008 rssi - agc - IWN_RSSI_TO_DBM);
4009 return rssi - agc - IWN_RSSI_TO_DBM;
4010}
4011
4012static int
4013iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4014{
4015 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4016 int rssi;
4017 uint8_t agc;
4018
4019 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4020
4021 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4022 le16toh(phy->rssi[1]) & 0xff);
4023 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4024
4025 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d "
4026 "result %d\n", __func__, agc,
4027 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4028 rssi - agc - IWN_RSSI_TO_DBM);
4029 return rssi - agc - IWN_RSSI_TO_DBM;
4030}
4031
4032/*
4033 * Retrieve the average noise (in dBm) among receivers.
4034 */
4035static int
4036iwn_get_noise(const struct iwn_rx_general_stats *stats)
4037{
4038 int i, total, nbant, noise;
4039
4040 total = nbant = 0;
4041 for (i = 0; i < 3; i++) {
4042 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4043 continue;
4044 total += noise;
4045 nbant++;
4046 }
4047 /*