ioapic_abi/x86_64: Record the max line based IRQ
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
CommitLineData
c8fe38ae
MD
1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41 */
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/kernel.h>
46#include <sys/machintr.h>
47#include <sys/interrupt.h>
48#include <sys/bus.h>
95874ffd 49#include <sys/thread2.h>
c8fe38ae
MD
50
51#include <machine/smp.h>
52#include <machine/segments.h>
53#include <machine/md_var.h>
57a9c56b 54#include <machine/intr_machdep.h>
c8fe38ae
MD
55#include <machine/globaldata.h>
56
104463f2 57#include <machine_base/isa/isa_intr.h>
61452645 58#include <machine_base/icu/icu.h>
6b809ec7 59#include <machine_base/icu/icu_var.h>
61452645 60#include <machine_base/apic/ioapic.h>
929c940f 61#include <machine_base/apic/ioapic_abi.h>
77f86d14 62#include <machine_base/apic/ioapic_ipl.h>
9a4bd8f3 63#include <machine_base/apic/apicreg.h>
c8fe38ae 64
95874ffd
SZ
65#include <dev/acpica5/acpi_sci_var.h>
66
451af8d9
SZ
67#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
68
c8fe38ae 69extern inthand_t
9e0e3f85
SZ
70 IDTVEC(ioapic_intr0),
71 IDTVEC(ioapic_intr1),
72 IDTVEC(ioapic_intr2),
73 IDTVEC(ioapic_intr3),
74 IDTVEC(ioapic_intr4),
75 IDTVEC(ioapic_intr5),
76 IDTVEC(ioapic_intr6),
77 IDTVEC(ioapic_intr7),
78 IDTVEC(ioapic_intr8),
79 IDTVEC(ioapic_intr9),
80 IDTVEC(ioapic_intr10),
81 IDTVEC(ioapic_intr11),
82 IDTVEC(ioapic_intr12),
83 IDTVEC(ioapic_intr13),
84 IDTVEC(ioapic_intr14),
85 IDTVEC(ioapic_intr15),
86 IDTVEC(ioapic_intr16),
87 IDTVEC(ioapic_intr17),
88 IDTVEC(ioapic_intr18),
89 IDTVEC(ioapic_intr19),
90 IDTVEC(ioapic_intr20),
91 IDTVEC(ioapic_intr21),
92 IDTVEC(ioapic_intr22),
93 IDTVEC(ioapic_intr23),
94 IDTVEC(ioapic_intr24),
95 IDTVEC(ioapic_intr25),
96 IDTVEC(ioapic_intr26),
97 IDTVEC(ioapic_intr27),
98 IDTVEC(ioapic_intr28),
99 IDTVEC(ioapic_intr29),
100 IDTVEC(ioapic_intr30),
101 IDTVEC(ioapic_intr31),
102 IDTVEC(ioapic_intr32),
103 IDTVEC(ioapic_intr33),
104 IDTVEC(ioapic_intr34),
105 IDTVEC(ioapic_intr35),
106 IDTVEC(ioapic_intr36),
107 IDTVEC(ioapic_intr37),
108 IDTVEC(ioapic_intr38),
109 IDTVEC(ioapic_intr39),
110 IDTVEC(ioapic_intr40),
111 IDTVEC(ioapic_intr41),
112 IDTVEC(ioapic_intr42),
113 IDTVEC(ioapic_intr43),
114 IDTVEC(ioapic_intr44),
115 IDTVEC(ioapic_intr45),
116 IDTVEC(ioapic_intr46),
117 IDTVEC(ioapic_intr47),
118 IDTVEC(ioapic_intr48),
119 IDTVEC(ioapic_intr49),
120 IDTVEC(ioapic_intr50),
121 IDTVEC(ioapic_intr51),
122 IDTVEC(ioapic_intr52),
123 IDTVEC(ioapic_intr53),
124 IDTVEC(ioapic_intr54),
125 IDTVEC(ioapic_intr55),
126 IDTVEC(ioapic_intr56),
127 IDTVEC(ioapic_intr57),
128 IDTVEC(ioapic_intr58),
129 IDTVEC(ioapic_intr59),
130 IDTVEC(ioapic_intr60),
131 IDTVEC(ioapic_intr61),
132 IDTVEC(ioapic_intr62),
133 IDTVEC(ioapic_intr63),
134 IDTVEC(ioapic_intr64),
135 IDTVEC(ioapic_intr65),
136 IDTVEC(ioapic_intr66),
137 IDTVEC(ioapic_intr67),
138 IDTVEC(ioapic_intr68),
139 IDTVEC(ioapic_intr69),
140 IDTVEC(ioapic_intr70),
141 IDTVEC(ioapic_intr71),
142 IDTVEC(ioapic_intr72),
143 IDTVEC(ioapic_intr73),
144 IDTVEC(ioapic_intr74),
145 IDTVEC(ioapic_intr75),
146 IDTVEC(ioapic_intr76),
147 IDTVEC(ioapic_intr77),
148 IDTVEC(ioapic_intr78),
149 IDTVEC(ioapic_intr79),
150 IDTVEC(ioapic_intr80),
151 IDTVEC(ioapic_intr81),
152 IDTVEC(ioapic_intr82),
153 IDTVEC(ioapic_intr83),
154 IDTVEC(ioapic_intr84),
155 IDTVEC(ioapic_intr85),
156 IDTVEC(ioapic_intr86),
157 IDTVEC(ioapic_intr87),
158 IDTVEC(ioapic_intr88),
159 IDTVEC(ioapic_intr89),
160 IDTVEC(ioapic_intr90),
161 IDTVEC(ioapic_intr91),
162 IDTVEC(ioapic_intr92),
163 IDTVEC(ioapic_intr93),
164 IDTVEC(ioapic_intr94),
165 IDTVEC(ioapic_intr95),
166 IDTVEC(ioapic_intr96),
167 IDTVEC(ioapic_intr97),
168 IDTVEC(ioapic_intr98),
169 IDTVEC(ioapic_intr99),
170 IDTVEC(ioapic_intr100),
171 IDTVEC(ioapic_intr101),
172 IDTVEC(ioapic_intr102),
173 IDTVEC(ioapic_intr103),
174 IDTVEC(ioapic_intr104),
175 IDTVEC(ioapic_intr105),
176 IDTVEC(ioapic_intr106),
177 IDTVEC(ioapic_intr107),
178 IDTVEC(ioapic_intr108),
179 IDTVEC(ioapic_intr109),
180 IDTVEC(ioapic_intr110),
181 IDTVEC(ioapic_intr111),
182 IDTVEC(ioapic_intr112),
183 IDTVEC(ioapic_intr113),
184 IDTVEC(ioapic_intr114),
185 IDTVEC(ioapic_intr115),
186 IDTVEC(ioapic_intr116),
187 IDTVEC(ioapic_intr117),
188 IDTVEC(ioapic_intr118),
189 IDTVEC(ioapic_intr119),
190 IDTVEC(ioapic_intr120),
191 IDTVEC(ioapic_intr121),
192 IDTVEC(ioapic_intr122),
193 IDTVEC(ioapic_intr123),
194 IDTVEC(ioapic_intr124),
195 IDTVEC(ioapic_intr125),
196 IDTVEC(ioapic_intr126),
197 IDTVEC(ioapic_intr127),
198 IDTVEC(ioapic_intr128),
199 IDTVEC(ioapic_intr129),
200 IDTVEC(ioapic_intr130),
201 IDTVEC(ioapic_intr131),
202 IDTVEC(ioapic_intr132),
203 IDTVEC(ioapic_intr133),
204 IDTVEC(ioapic_intr134),
205 IDTVEC(ioapic_intr135),
206 IDTVEC(ioapic_intr136),
207 IDTVEC(ioapic_intr137),
208 IDTVEC(ioapic_intr138),
209 IDTVEC(ioapic_intr139),
210 IDTVEC(ioapic_intr140),
211 IDTVEC(ioapic_intr141),
212 IDTVEC(ioapic_intr142),
213 IDTVEC(ioapic_intr143),
214 IDTVEC(ioapic_intr144),
215 IDTVEC(ioapic_intr145),
216 IDTVEC(ioapic_intr146),
217 IDTVEC(ioapic_intr147),
218 IDTVEC(ioapic_intr148),
219 IDTVEC(ioapic_intr149),
220 IDTVEC(ioapic_intr150),
221 IDTVEC(ioapic_intr151),
222 IDTVEC(ioapic_intr152),
223 IDTVEC(ioapic_intr153),
224 IDTVEC(ioapic_intr154),
225 IDTVEC(ioapic_intr155),
226 IDTVEC(ioapic_intr156),
227 IDTVEC(ioapic_intr157),
228 IDTVEC(ioapic_intr158),
229 IDTVEC(ioapic_intr159),
230 IDTVEC(ioapic_intr160),
231 IDTVEC(ioapic_intr161),
232 IDTVEC(ioapic_intr162),
233 IDTVEC(ioapic_intr163),
234 IDTVEC(ioapic_intr164),
235 IDTVEC(ioapic_intr165),
236 IDTVEC(ioapic_intr166),
237 IDTVEC(ioapic_intr167),
238 IDTVEC(ioapic_intr168),
239 IDTVEC(ioapic_intr169),
240 IDTVEC(ioapic_intr170),
241 IDTVEC(ioapic_intr171),
242 IDTVEC(ioapic_intr172),
243 IDTVEC(ioapic_intr173),
244 IDTVEC(ioapic_intr174),
245 IDTVEC(ioapic_intr175),
246 IDTVEC(ioapic_intr176),
247 IDTVEC(ioapic_intr177),
248 IDTVEC(ioapic_intr178),
249 IDTVEC(ioapic_intr179),
250 IDTVEC(ioapic_intr180),
251 IDTVEC(ioapic_intr181),
252 IDTVEC(ioapic_intr182),
253 IDTVEC(ioapic_intr183),
254 IDTVEC(ioapic_intr184),
255 IDTVEC(ioapic_intr185),
256 IDTVEC(ioapic_intr186),
257 IDTVEC(ioapic_intr187),
258 IDTVEC(ioapic_intr188),
259 IDTVEC(ioapic_intr189),
260 IDTVEC(ioapic_intr190),
261 IDTVEC(ioapic_intr191);
262
263static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
264 &IDTVEC(ioapic_intr0),
265 &IDTVEC(ioapic_intr1),
266 &IDTVEC(ioapic_intr2),
267 &IDTVEC(ioapic_intr3),
268 &IDTVEC(ioapic_intr4),
269 &IDTVEC(ioapic_intr5),
270 &IDTVEC(ioapic_intr6),
271 &IDTVEC(ioapic_intr7),
272 &IDTVEC(ioapic_intr8),
273 &IDTVEC(ioapic_intr9),
274 &IDTVEC(ioapic_intr10),
275 &IDTVEC(ioapic_intr11),
276 &IDTVEC(ioapic_intr12),
277 &IDTVEC(ioapic_intr13),
278 &IDTVEC(ioapic_intr14),
279 &IDTVEC(ioapic_intr15),
280 &IDTVEC(ioapic_intr16),
281 &IDTVEC(ioapic_intr17),
282 &IDTVEC(ioapic_intr18),
283 &IDTVEC(ioapic_intr19),
284 &IDTVEC(ioapic_intr20),
285 &IDTVEC(ioapic_intr21),
286 &IDTVEC(ioapic_intr22),
287 &IDTVEC(ioapic_intr23),
288 &IDTVEC(ioapic_intr24),
289 &IDTVEC(ioapic_intr25),
290 &IDTVEC(ioapic_intr26),
291 &IDTVEC(ioapic_intr27),
292 &IDTVEC(ioapic_intr28),
293 &IDTVEC(ioapic_intr29),
294 &IDTVEC(ioapic_intr30),
295 &IDTVEC(ioapic_intr31),
296 &IDTVEC(ioapic_intr32),
297 &IDTVEC(ioapic_intr33),
298 &IDTVEC(ioapic_intr34),
299 &IDTVEC(ioapic_intr35),
300 &IDTVEC(ioapic_intr36),
301 &IDTVEC(ioapic_intr37),
302 &IDTVEC(ioapic_intr38),
303 &IDTVEC(ioapic_intr39),
304 &IDTVEC(ioapic_intr40),
305 &IDTVEC(ioapic_intr41),
306 &IDTVEC(ioapic_intr42),
307 &IDTVEC(ioapic_intr43),
308 &IDTVEC(ioapic_intr44),
309 &IDTVEC(ioapic_intr45),
310 &IDTVEC(ioapic_intr46),
311 &IDTVEC(ioapic_intr47),
312 &IDTVEC(ioapic_intr48),
313 &IDTVEC(ioapic_intr49),
314 &IDTVEC(ioapic_intr50),
315 &IDTVEC(ioapic_intr51),
316 &IDTVEC(ioapic_intr52),
317 &IDTVEC(ioapic_intr53),
318 &IDTVEC(ioapic_intr54),
319 &IDTVEC(ioapic_intr55),
320 &IDTVEC(ioapic_intr56),
321 &IDTVEC(ioapic_intr57),
322 &IDTVEC(ioapic_intr58),
323 &IDTVEC(ioapic_intr59),
324 &IDTVEC(ioapic_intr60),
325 &IDTVEC(ioapic_intr61),
326 &IDTVEC(ioapic_intr62),
327 &IDTVEC(ioapic_intr63),
328 &IDTVEC(ioapic_intr64),
329 &IDTVEC(ioapic_intr65),
330 &IDTVEC(ioapic_intr66),
331 &IDTVEC(ioapic_intr67),
332 &IDTVEC(ioapic_intr68),
333 &IDTVEC(ioapic_intr69),
334 &IDTVEC(ioapic_intr70),
335 &IDTVEC(ioapic_intr71),
336 &IDTVEC(ioapic_intr72),
337 &IDTVEC(ioapic_intr73),
338 &IDTVEC(ioapic_intr74),
339 &IDTVEC(ioapic_intr75),
340 &IDTVEC(ioapic_intr76),
341 &IDTVEC(ioapic_intr77),
342 &IDTVEC(ioapic_intr78),
343 &IDTVEC(ioapic_intr79),
344 &IDTVEC(ioapic_intr80),
345 &IDTVEC(ioapic_intr81),
346 &IDTVEC(ioapic_intr82),
347 &IDTVEC(ioapic_intr83),
348 &IDTVEC(ioapic_intr84),
349 &IDTVEC(ioapic_intr85),
350 &IDTVEC(ioapic_intr86),
351 &IDTVEC(ioapic_intr87),
352 &IDTVEC(ioapic_intr88),
353 &IDTVEC(ioapic_intr89),
354 &IDTVEC(ioapic_intr90),
355 &IDTVEC(ioapic_intr91),
356 &IDTVEC(ioapic_intr92),
357 &IDTVEC(ioapic_intr93),
358 &IDTVEC(ioapic_intr94),
359 &IDTVEC(ioapic_intr95),
360 &IDTVEC(ioapic_intr96),
361 &IDTVEC(ioapic_intr97),
362 &IDTVEC(ioapic_intr98),
363 &IDTVEC(ioapic_intr99),
364 &IDTVEC(ioapic_intr100),
365 &IDTVEC(ioapic_intr101),
366 &IDTVEC(ioapic_intr102),
367 &IDTVEC(ioapic_intr103),
368 &IDTVEC(ioapic_intr104),
369 &IDTVEC(ioapic_intr105),
370 &IDTVEC(ioapic_intr106),
371 &IDTVEC(ioapic_intr107),
372 &IDTVEC(ioapic_intr108),
373 &IDTVEC(ioapic_intr109),
374 &IDTVEC(ioapic_intr110),
375 &IDTVEC(ioapic_intr111),
376 &IDTVEC(ioapic_intr112),
377 &IDTVEC(ioapic_intr113),
378 &IDTVEC(ioapic_intr114),
379 &IDTVEC(ioapic_intr115),
380 &IDTVEC(ioapic_intr116),
381 &IDTVEC(ioapic_intr117),
382 &IDTVEC(ioapic_intr118),
383 &IDTVEC(ioapic_intr119),
384 &IDTVEC(ioapic_intr120),
385 &IDTVEC(ioapic_intr121),
386 &IDTVEC(ioapic_intr122),
387 &IDTVEC(ioapic_intr123),
388 &IDTVEC(ioapic_intr124),
389 &IDTVEC(ioapic_intr125),
390 &IDTVEC(ioapic_intr126),
391 &IDTVEC(ioapic_intr127),
392 &IDTVEC(ioapic_intr128),
393 &IDTVEC(ioapic_intr129),
394 &IDTVEC(ioapic_intr130),
395 &IDTVEC(ioapic_intr131),
396 &IDTVEC(ioapic_intr132),
397 &IDTVEC(ioapic_intr133),
398 &IDTVEC(ioapic_intr134),
399 &IDTVEC(ioapic_intr135),
400 &IDTVEC(ioapic_intr136),
401 &IDTVEC(ioapic_intr137),
402 &IDTVEC(ioapic_intr138),
403 &IDTVEC(ioapic_intr139),
404 &IDTVEC(ioapic_intr140),
405 &IDTVEC(ioapic_intr141),
406 &IDTVEC(ioapic_intr142),
407 &IDTVEC(ioapic_intr143),
408 &IDTVEC(ioapic_intr144),
409 &IDTVEC(ioapic_intr145),
410 &IDTVEC(ioapic_intr146),
411 &IDTVEC(ioapic_intr147),
412 &IDTVEC(ioapic_intr148),
413 &IDTVEC(ioapic_intr149),
414 &IDTVEC(ioapic_intr150),
415 &IDTVEC(ioapic_intr151),
416 &IDTVEC(ioapic_intr152),
417 &IDTVEC(ioapic_intr153),
418 &IDTVEC(ioapic_intr154),
419 &IDTVEC(ioapic_intr155),
420 &IDTVEC(ioapic_intr156),
421 &IDTVEC(ioapic_intr157),
422 &IDTVEC(ioapic_intr158),
423 &IDTVEC(ioapic_intr159),
424 &IDTVEC(ioapic_intr160),
425 &IDTVEC(ioapic_intr161),
426 &IDTVEC(ioapic_intr162),
427 &IDTVEC(ioapic_intr163),
428 &IDTVEC(ioapic_intr164),
429 &IDTVEC(ioapic_intr165),
430 &IDTVEC(ioapic_intr166),
431 &IDTVEC(ioapic_intr167),
432 &IDTVEC(ioapic_intr168),
433 &IDTVEC(ioapic_intr169),
434 &IDTVEC(ioapic_intr170),
435 &IDTVEC(ioapic_intr171),
436 &IDTVEC(ioapic_intr172),
437 &IDTVEC(ioapic_intr173),
438 &IDTVEC(ioapic_intr174),
439 &IDTVEC(ioapic_intr175),
440 &IDTVEC(ioapic_intr176),
441 &IDTVEC(ioapic_intr177),
442 &IDTVEC(ioapic_intr178),
443 &IDTVEC(ioapic_intr179),
444 &IDTVEC(ioapic_intr180),
445 &IDTVEC(ioapic_intr181),
446 &IDTVEC(ioapic_intr182),
447 &IDTVEC(ioapic_intr183),
448 &IDTVEC(ioapic_intr184),
449 &IDTVEC(ioapic_intr185),
450 &IDTVEC(ioapic_intr186),
451 &IDTVEC(ioapic_intr187),
452 &IDTVEC(ioapic_intr188),
453 &IDTVEC(ioapic_intr189),
454 &IDTVEC(ioapic_intr190),
455 &IDTVEC(ioapic_intr191)
c571da4a 456};
c8fe38ae 457
474ba684
SZ
458#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
459
a3dd9120
SZ
460static struct ioapic_irqmap {
461 int im_type; /* IOAPIC_IMT_ */
462 enum intr_trigger im_trig;
f6915355 463 enum intr_polarity im_pola;
a3dd9120 464 int im_gsi;
d1ae7328 465 uint32_t im_flags; /* IOAPIC_IMF_ */
451af8d9 466} ioapic_irqmaps[IOAPIC_HWI_VECTORS];
a3dd9120
SZ
467
468#define IOAPIC_IMT_UNUSED 0
469#define IOAPIC_IMT_RESERVED 1
470#define IOAPIC_IMT_LINE 2
474ba684 471#define IOAPIC_IMT_SYSCALL 3
a3dd9120 472
d1ae7328
SZ
473#define IOAPIC_IMF_CONF 0x1
474
9e0e3f85
SZ
475extern void IOAPIC_INTREN(int);
476extern void IOAPIC_INTRDIS(int);
477
85bcaa51
SZ
478extern int imcr_present;
479
35b2edcb
SZ
480static void ioapic_abi_intr_enable(int);
481static void ioapic_abi_intr_disable(int);
f416026e
SZ
482static void ioapic_abi_intr_setup(int, int);
483static void ioapic_abi_intr_teardown(int);
aea76754
SZ
484static void ioapic_abi_intr_config(int,
485 enum intr_trigger, enum intr_polarity);
a05c798c 486static int ioapic_abi_intr_cpuid(int);
35b2edcb 487
aea76754
SZ
488static void ioapic_abi_finalize(void);
489static void ioapic_abi_cleanup(void);
490static void ioapic_abi_setdefault(void);
491static void ioapic_abi_stabilize(void);
492static void ioapic_abi_initmap(void);
9e0e3f85 493
95874ffd
SZ
494static int ioapic_abi_gsi_cpuid(int, int);
495
9e0e3f85
SZ
496struct machintr_abi MachIntrABI_IOAPIC = {
497 MACHINTR_IOAPIC,
35b2edcb
SZ
498 .intr_disable = ioapic_abi_intr_disable,
499 .intr_enable = ioapic_abi_intr_enable,
f416026e
SZ
500 .intr_setup = ioapic_abi_intr_setup,
501 .intr_teardown = ioapic_abi_intr_teardown,
aea76754 502 .intr_config = ioapic_abi_intr_config,
a05c798c 503 .intr_cpuid = ioapic_abi_intr_cpuid,
35b2edcb 504
aea76754
SZ
505 .finalize = ioapic_abi_finalize,
506 .cleanup = ioapic_abi_cleanup,
507 .setdefault = ioapic_abi_setdefault,
508 .stabilize = ioapic_abi_stabilize,
509 .initmap = ioapic_abi_initmap
c8fe38ae
MD
510};
511
6b809ec7 512static int ioapic_abi_extint_irq = -1;
bf2e6ffb 513static int ioapic_abi_line_irq_max;
6b809ec7 514
5ac5ccd2 515struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
566d27d4
SZ
516
517static void
35b2edcb 518ioapic_abi_intr_enable(int irq)
566d27d4
SZ
519{
520 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 521 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
566d27d4
SZ
522 return;
523 }
524 IOAPIC_INTREN(irq);
525}
526
527static void
35b2edcb 528ioapic_abi_intr_disable(int irq)
566d27d4
SZ
529{
530 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
35b2edcb 531 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
566d27d4
SZ
532 return;
533 }
534 IOAPIC_INTRDIS(irq);
535}
536
c8fe38ae 537static void
aea76754 538ioapic_abi_finalize(void)
c8fe38ae 539{
e0918665 540 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 541 KKASSERT(ioapic_enable);
10db3cc6 542
339478ac
SZ
543 /*
544 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 545 * from the BSP.
339478ac 546 */
9d758cc4 547 if (imcr_present) {
339478ac
SZ
548 outb(0x22, 0x70); /* select IMCR */
549 outb(0x23, 0x01); /* disconnect 8259 */
550 }
c8fe38ae
MD
551}
552
553/*
554 * This routine is called after physical interrupts are enabled but before
555 * the critical section is released. We need to clean out any interrupts
556 * that had already been posted to the cpu.
557 */
558static void
aea76754 559ioapic_abi_cleanup(void)
c8fe38ae 560{
9611ff20 561 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
c8fe38ae
MD
562}
563
7bf5fa56
SZ
564/* Must never be called */
565static void
aea76754 566ioapic_abi_stabilize(void)
7bf5fa56
SZ
567{
568 panic("ioapic_stabilize is called\n");
569}
570
f416026e
SZ
571static void
572ioapic_abi_intr_setup(int intr, int flags)
c8fe38ae 573{
f416026e 574 int vector, select;
339478ac 575 uint32_t value;
7bf5fa56 576 register_t ef;
c8fe38ae 577
f416026e
SZ
578 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
579 intr != IOAPIC_HWI_SYSCALL);
580 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
581
582 ef = read_rflags();
583 cpu_disable_intr();
584
585 vector = IDT_OFFSET + intr;
586 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
587
588 /*
589 * Now reprogram the vector in the IO APIC. In order to avoid
590 * losing an EOI for a level interrupt, which is vector based,
591 * make sure that the IO APIC is programmed for edge-triggering
592 * first, then reprogrammed with the new vector. This should
593 * clear the IRR bit.
594 */
595 imen_lock();
596
597 select = ioapic_irqs[intr].io_idx;
598 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
599 value |= IOART_INTMSET;
600
601 ioapic_write(ioapic_irqs[intr].io_addr, select,
602 (value & ~APIC_TRIGMOD_MASK));
603 ioapic_write(ioapic_irqs[intr].io_addr, select,
604 (value & ~IOART_INTVEC) | vector);
605
606 imen_unlock();
607
35b2edcb 608 machintr_intr_enable(intr);
c8fe38ae 609
f416026e
SZ
610 write_rflags(ef);
611}
612
613static void
614ioapic_abi_intr_teardown(int intr)
615{
616 int vector, select;
617 uint32_t value;
618 register_t ef;
619
620 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
621 intr != IOAPIC_HWI_SYSCALL);
622 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
5ac5ccd2 623
339478ac
SZ
624 ef = read_rflags();
625 cpu_disable_intr();
f416026e
SZ
626
627 /*
628 * Teardown an interrupt vector. The vector should already be
629 * installed in the cpu's IDT, but make sure.
630 */
35b2edcb 631 machintr_intr_disable(intr);
f416026e
SZ
632
633 vector = IDT_OFFSET + intr;
634 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
635
636 /*
637 * In order to avoid losing an EOI for a level interrupt, which
638 * is vector based, make sure that the IO APIC is programmed for
639 * edge-triggering first, then reprogrammed with the new vector.
640 * This should clear the IRR bit.
641 */
642 imen_lock();
643
644 select = ioapic_irqs[intr].io_idx;
645 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
646
647 ioapic_write(ioapic_irqs[intr].io_addr, select,
648 (value & ~APIC_TRIGMOD_MASK));
649 ioapic_write(ioapic_irqs[intr].io_addr, select,
650 (value & ~IOART_INTVEC) | vector);
651
652 imen_unlock();
c8fe38ae 653
339478ac 654 write_rflags(ef);
339478ac 655}
c8fe38ae 656
10db3cc6 657static void
aea76754 658ioapic_abi_setdefault(void)
10db3cc6
SZ
659{
660 int intr;
661
9e0e3f85 662 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 663 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 664 continue;
9e0e3f85 665 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
10db3cc6
SZ
666 SEL_KPL, 0);
667 }
668}
669
a3dd9120 670static void
aea76754 671ioapic_abi_initmap(void)
a3dd9120
SZ
672{
673 int i;
674
c36b581c
SZ
675 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
676 ioapic_irqmaps[i].im_gsi = -1;
474ba684 677 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
a3dd9120
SZ
678}
679
929c940f
SZ
680void
681ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
682 enum intr_polarity pola)
683{
5ac5ccd2 684 struct ioapic_irqinfo *info;
929c940f
SZ
685 struct ioapic_irqmap *map;
686 void *ioaddr;
95874ffd 687 int pin, cpuid;
929c940f
SZ
688
689 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
690 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f
SZ
691
692 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
bf2e6ffb
SZ
693 if (irq > ioapic_abi_line_irq_max)
694 ioapic_abi_line_irq_max = irq;
695
929c940f
SZ
696 map = &ioapic_irqmaps[irq];
697
698 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
699 map->im_type = IOAPIC_IMT_LINE;
700
701 map->im_gsi = gsi;
702 map->im_trig = trig;
703 map->im_pola = pola;
704
705 if (bootverbose) {
4ecd5d4d
SZ
706 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
707 irq, map->im_gsi,
708 intr_str_trigger(map->im_trig),
709 intr_str_polarity(map->im_pola));
929c940f
SZ
710 }
711
d1ae7328
SZ
712 pin = ioapic_gsi_pin(map->im_gsi);
713 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 714
95874ffd
SZ
715 cpuid = ioapic_abi_gsi_cpuid(irq, map->im_gsi);
716
5ac5ccd2 717 info = &ioapic_irqs[irq];
929c940f 718
7bceaa10
SZ
719 imen_lock();
720
5ac5ccd2
SZ
721 info->io_addr = ioaddr;
722 info->io_idx = IOAPIC_REDTBL + (2 * pin);
723 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 724 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 725 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ
726
727 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 728 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
729
730 imen_unlock();
d1ae7328
SZ
731}
732
4a913811
SZ
733void
734ioapic_abi_fixup_irqmap(void)
735{
736 int i;
737
104463f2 738 for (i = 0; i < ISA_IRQ_CNT; ++i) {
4a913811
SZ
739 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
740
741 if (map->im_type == IOAPIC_IMT_UNUSED) {
742 map->im_type = IOAPIC_IMT_RESERVED;
743 if (bootverbose)
744 kprintf("IOAPIC: irq %d reserved\n", i);
745 }
746 }
bf2e6ffb
SZ
747 ioapic_abi_line_irq_max += 1;
748 if (bootverbose)
749 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
4a913811
SZ
750}
751
e90e7ac4
SZ
752int
753ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
754{
755 int irq;
756
757 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
758 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
759
760 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
761 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
762
763 if (map->im_gsi == gsi) {
764 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
765
766 if (map->im_flags & IOAPIC_IMF_CONF) {
767 if (map->im_trig != trig ||
768 map->im_pola != pola)
769 return -1;
770 }
771 return irq;
772 }
773 }
774 return -1;
775}
776
777int
778ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
779{
780 const struct ioapic_irqmap *map;
781
782 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
783 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
e90e7ac4
SZ
784
785 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
786 return -1;
787 map = &ioapic_irqmaps[irq];
788
789 if (map->im_type != IOAPIC_IMT_LINE)
790 return -1;
791
792 if (map->im_flags & IOAPIC_IMF_CONF) {
793 if (map->im_trig != trig || map->im_pola != pola)
794 return -1;
795 }
796 return irq;
797}
798
d1ae7328 799static void
aea76754 800ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
d1ae7328 801{
5ac5ccd2 802 struct ioapic_irqinfo *info;
d1ae7328
SZ
803 struct ioapic_irqmap *map;
804 void *ioaddr;
95874ffd 805 int pin, cpuid;
d1ae7328 806
d1ae7328
SZ
807 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
808 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328
SZ
809
810 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
811 map = &ioapic_irqmaps[irq];
812
813 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
814
7962296e 815#ifdef notyet
d1ae7328
SZ
816 if (map->im_flags & IOAPIC_IMF_CONF) {
817 if (trig != map->im_trig) {
4ecd5d4d
SZ
818 panic("ioapic_intr_config: trig %s -> %s\n",
819 intr_str_trigger(map->im_trig),
820 intr_str_trigger(trig));
d1ae7328
SZ
821 }
822 if (pola != map->im_pola) {
823 panic("ioapic_intr_config: pola %s -> %s\n",
4ecd5d4d
SZ
824 intr_str_polarity(map->im_pola),
825 intr_str_polarity(pola));
d1ae7328
SZ
826 }
827 return;
828 }
7962296e 829#endif
d1ae7328
SZ
830 map->im_flags |= IOAPIC_IMF_CONF;
831
832 if (trig == map->im_trig && pola == map->im_pola)
833 return;
834
835 if (bootverbose) {
4ecd5d4d
SZ
836 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
837 irq, map->im_gsi,
838 intr_str_trigger(map->im_trig),
839 intr_str_polarity(map->im_pola),
840 intr_str_trigger(trig),
841 intr_str_polarity(pola));
d1ae7328 842 }
d1ae7328
SZ
843 map->im_trig = trig;
844 map->im_pola = pola;
845
846 pin = ioapic_gsi_pin(map->im_gsi);
847 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
848
95874ffd
SZ
849 cpuid = ioapic_abi_gsi_cpuid(irq, map->im_gsi);
850
5ac5ccd2 851 info = &ioapic_irqs[irq];
d1ae7328 852
7bceaa10
SZ
853 imen_lock();
854
5ac5ccd2 855 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 856 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 857 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 858
ecec8ddc 859 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 860 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
861
862 imen_unlock();
929c940f
SZ
863}
864
6b809ec7
SZ
865int
866ioapic_abi_extint_irqmap(int irq)
867{
5ac5ccd2 868 struct ioapic_irqinfo *info;
6b809ec7
SZ
869 struct ioapic_irqmap *map;
870 void *ioaddr;
871 int pin, error, vec;
872
95874ffd
SZ
873 /* XXX only irq0 is allowed */
874 KKASSERT(irq == 0);
875
6b809ec7
SZ
876 vec = IDT_OFFSET + irq;
877
878 if (ioapic_abi_extint_irq == irq)
879 return 0;
880 else if (ioapic_abi_extint_irq >= 0)
881 return EEXIST;
882
883 error = icu_ioapic_extint(irq, vec);
884 if (error)
885 return error;
886
887 map = &ioapic_irqmaps[irq];
888
889 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
890 map->im_type == IOAPIC_IMT_LINE);
891 if (map->im_type == IOAPIC_IMT_LINE) {
892 if (map->im_flags & IOAPIC_IMF_CONF)
893 return EEXIST;
894 }
895 ioapic_abi_extint_irq = irq;
896
897 map->im_type = IOAPIC_IMT_LINE;
898 map->im_trig = INTR_TRIGGER_EDGE;
899 map->im_pola = INTR_POLARITY_HIGH;
900 map->im_flags = IOAPIC_IMF_CONF;
901
902 map->im_gsi = ioapic_extpin_gsi();
903 KKASSERT(map->im_gsi >= 0);
904
905 if (bootverbose) {
4ecd5d4d
SZ
906 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
907 irq, map->im_gsi,
908 intr_str_trigger(map->im_trig),
909 intr_str_polarity(map->im_pola));
6b809ec7
SZ
910 }
911
912 pin = ioapic_gsi_pin(map->im_gsi);
913 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
914
5ac5ccd2 915 info = &ioapic_irqs[irq];
6b809ec7
SZ
916
917 imen_lock();
918
5ac5ccd2
SZ
919 info->io_addr = ioaddr;
920 info->io_idx = IOAPIC_REDTBL + (2 * pin);
921 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
922
923 ioapic_extpin_setup(ioaddr, pin, vec);
924
925 imen_unlock();
926
927 return 0;
928}
a05c798c
SZ
929
930static int
95874ffd 931ioapic_abi_intr_cpuid(int irq)
a05c798c 932{
95874ffd
SZ
933 const struct ioapic_irqmap *map;
934
935 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
936 map = &ioapic_irqmaps[irq];
937
938 if (map->im_type == IOAPIC_IMT_RESERVED) {
939 /* XXX some drivers tries to peek at IRQ 2 */
940 return 0;
941 }
942
943 KASSERT(map->im_type == IOAPIC_IMT_LINE,
944 ("invalid irq %d, type %d\n", irq, map->im_type));
945 KKASSERT(map->im_gsi >= 0);
946
947 return ioapic_abi_gsi_cpuid(irq, map->im_gsi);
948}
949
950static int
951ioapic_abi_gsi_cpuid(int irq, int gsi)
952{
953 char envpath[32];
954 int cpuid = -1;
955
956 KKASSERT(gsi >= 0);
957
958 if (irq == 0 || gsi == 0) {
621d2ccf
SZ
959 if (bootverbose) {
960 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
961 irq, gsi);
962 }
95874ffd
SZ
963 return 0;
964 }
965
966 if (irq == acpi_sci_irqno()) {
621d2ccf
SZ
967 if (bootverbose) {
968 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
969 irq, gsi);
970 }
95874ffd
SZ
971 return 0;
972 }
973
974 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
975 kgetenv_int(envpath, &cpuid);
976
977 if (cpuid < 0) {
978 cpuid = gsi % ncpus;
621d2ccf
SZ
979 if (bootverbose) {
980 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
981 irq, gsi, cpuid);
982 }
95874ffd
SZ
983 } else if (cpuid >= ncpus) {
984 cpuid = ncpus - 1;
621d2ccf
SZ
985 if (bootverbose) {
986 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
987 irq, gsi, cpuid);
988 }
95874ffd 989 } else {
621d2ccf
SZ
990 if (bootverbose) {
991 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
992 irq, gsi, cpuid);
993 }
95874ffd
SZ
994 }
995 return cpuid;
a05c798c 996}