nge: Switch from device_polling to ifpoll
[dragonfly.git] / sys / dev / netif / nge / if_nge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 */
35
36/*
37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
38 * for FreeBSD. Datasheets are available from:
39 *
40 * http://www.national.com/ds/DP/DP83820.pdf
41 * http://www.national.com/ds/DP/DP83821.pdf
42 *
43 * These chips are used on several low cost gigabit ethernet NICs
44 * sold by D-Link, Addtron, SMC and Asante. Both parts are
45 * virtually the same, except the 83820 is a 64-bit/32-bit part,
46 * while the 83821 is 32-bit only.
47 *
48 * Many cards also use National gigE transceivers, such as the
49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
50 * contains a full register description that applies to all of these
51 * components:
52 *
53 * http://www.national.com/ds/DP/DP83861.pdf
54 *
55 * Written by Bill Paul <wpaul@bsdi.com>
56 * BSDi Open Source Solutions
57 */
58
59/*
60 * The NatSemi DP83820 and 83821 controllers are enhanced versions
61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
66 * matching buffers, one perfect address filter buffer and interrupt
67 * moderation. The 83820 supports both 64-bit and 32-bit addressing
68 * and data transfers: the 64-bit support can be toggled on or off
69 * via software. This affects the size of certain fields in the DMA
70 * descriptors.
71 *
72 * There are two bugs/misfeatures in the 83820/83821 that I have
73 * discovered so far:
74 *
75 * - Receive buffers must be aligned on 64-bit boundaries, which means
76 * you must resort to copying data in order to fix up the payload
77 * alignment.
78 *
79 * - In order to transmit jumbo frames larger than 8170 bytes, you have
80 * to turn off transmit checksum offloading, because the chip can't
81 * compute the checksum on an outgoing frame unless it fits entirely
82 * within the TX FIFO, which is only 8192 bytes in size. If you have
83 * TX checksum offload enabled and you transmit attempt to transmit a
84 * frame larger than 8170 bytes, the transmitter will wedge.
85 *
86 * To work around the latter problem, TX checksum offload is disabled
87 * if the user selects an MTU larger than 8152 (8170 - 18).
88 */
89
bf58d756 90#include "opt_ifpoll.h"
2b71c8f1 91
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92#include <sys/param.h>
93#include <sys/systm.h>
94#include <sys/sockio.h>
95#include <sys/mbuf.h>
96#include <sys/malloc.h>
97#include <sys/kernel.h>
9db4b353 98#include <sys/interrupt.h>
984263bc 99#include <sys/socket.h>
78195a76 100#include <sys/serialize.h>
1f7ab7c9
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101#include <sys/bus.h>
102#include <sys/rman.h>
88e7510c 103#include <sys/thread2.h>
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104
105#include <net/if.h>
0b193118 106#include <net/ifq_var.h>
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107#include <net/if_arp.h>
108#include <net/ethernet.h>
109#include <net/if_dl.h>
110#include <net/if_media.h>
bf58d756 111#include <net/if_poll.h>
984263bc 112#include <net/if_types.h>
1f2de5d4 113#include <net/vlan/if_vlan_var.h>
b637f170 114#include <net/vlan/if_vlan_ether.h>
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115
116#include <net/bpf.h>
117
118#include <vm/vm.h> /* for vtophys */
119#include <vm/pmap.h> /* for vtophys */
984263bc 120
22bf5b21
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121#include <dev/netif/mii_layer/mii.h>
122#include <dev/netif/mii_layer/miivar.h>
984263bc 123
cf908797 124#include <bus/pci/pcidevs.h>
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125#include <bus/pci/pcireg.h>
126#include <bus/pci/pcivar.h>
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127
128#define NGE_USEIOSPACE
129
1f2de5d4 130#include "if_ngereg.h"
984263bc 131
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132
133/* "controller miibus0" required. See GENERIC if you get errors here. */
134#include "miibus_if.h"
135
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136#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138/*
139 * Various supported device vendors/types and their names.
140 */
141static struct nge_type nge_devs[] = {
cf908797 142 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
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143 "National Semiconductor Gigabit Ethernet" },
144 { 0, 0, NULL }
145};
146
22bf5b21
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147static int nge_probe(device_t);
148static int nge_attach(device_t);
149static int nge_detach(device_t);
984263bc 150
22bf5b21 151static int nge_alloc_jumbo_mem(struct nge_softc *);
368e791d
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152static struct nge_jslot
153 *nge_jalloc(struct nge_softc *);
154static void nge_jfree(void *);
155static void nge_jref(void *);
156
157static int nge_newbuf(struct nge_softc *, struct nge_desc *,
158 struct mbuf *);
159static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
22bf5b21
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160static void nge_rxeof(struct nge_softc *);
161static void nge_txeof(struct nge_softc *);
162static void nge_intr(void *);
163static void nge_tick(void *);
164static void nge_start(struct ifnet *);
368e791d 165static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
22bf5b21
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166static void nge_init(void *);
167static void nge_stop(struct nge_softc *);
168static void nge_watchdog(struct ifnet *);
169static void nge_shutdown(device_t);
170static int nge_ifmedia_upd(struct ifnet *);
171static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
172
173static void nge_delay(struct nge_softc *);
174static void nge_eeprom_idle(struct nge_softc *);
175static void nge_eeprom_putbyte(struct nge_softc *, int);
176static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
177static void nge_read_eeprom(struct nge_softc *, void *, int, int);
178
179static void nge_mii_sync(struct nge_softc *);
180static void nge_mii_send(struct nge_softc *, uint32_t, int);
181static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
182static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
183
184static int nge_miibus_readreg(device_t, int, int);
185static int nge_miibus_writereg(device_t, int, int, int);
186static void nge_miibus_statchg(device_t);
187
188static void nge_setmulti(struct nge_softc *);
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189static void nge_reset(struct nge_softc *);
190static int nge_list_rx_init(struct nge_softc *);
191static int nge_list_tx_init(struct nge_softc *);
bf58d756
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192#ifdef IFPOLL_ENABLE
193static void nge_npoll(struct ifnet *, struct ifpoll_info *);
194static void nge_npoll_compat(struct ifnet *, void *, int);
9c095379 195#endif
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196
197#ifdef NGE_USEIOSPACE
198#define NGE_RES SYS_RES_IOPORT
199#define NGE_RID NGE_PCI_LOIO
200#else
201#define NGE_RES SYS_RES_MEMORY
202#define NGE_RID NGE_PCI_LOMEM
203#endif
204
205static device_method_t nge_methods[] = {
206 /* Device interface */
207 DEVMETHOD(device_probe, nge_probe),
208 DEVMETHOD(device_attach, nge_attach),
209 DEVMETHOD(device_detach, nge_detach),
210 DEVMETHOD(device_shutdown, nge_shutdown),
211
212 /* bus interface */
213 DEVMETHOD(bus_print_child, bus_generic_print_child),
214 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215
216 /* MII interface */
217 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
218 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
219 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
220
221 { 0, 0 }
222};
223
22bf5b21 224static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
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225static devclass_t nge_devclass;
226
32832096
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227DECLARE_DUMMY_MODULE(if_nge);
228MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
aa2b9d05
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229DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, NULL, NULL);
230DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, NULL, NULL);
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231
232#define NGE_SETBIT(sc, reg, x) \
22bf5b21 233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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234
235#define NGE_CLRBIT(sc, reg, x) \
22bf5b21 236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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237
238#define SIO_SET(x) \
22bf5b21 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
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240
241#define SIO_CLR(x) \
22bf5b21 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
984263bc 243
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244static void
245nge_delay(struct nge_softc *sc)
984263bc 246{
22bf5b21 247 int idx;
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248
249 for (idx = (300 / 33) + 1; idx > 0; idx--)
250 CSR_READ_4(sc, NGE_CSR);
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251}
252
22bf5b21
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253static void
254nge_eeprom_idle(struct nge_softc *sc)
984263bc 255{
22bf5b21 256 int i;
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257
258 SIO_SET(NGE_MEAR_EE_CSEL);
259 nge_delay(sc);
260 SIO_SET(NGE_MEAR_EE_CLK);
261 nge_delay(sc);
262
263 for (i = 0; i < 25; i++) {
264 SIO_CLR(NGE_MEAR_EE_CLK);
265 nge_delay(sc);
266 SIO_SET(NGE_MEAR_EE_CLK);
267 nge_delay(sc);
268 }
269
270 SIO_CLR(NGE_MEAR_EE_CLK);
271 nge_delay(sc);
272 SIO_CLR(NGE_MEAR_EE_CSEL);
273 nge_delay(sc);
274 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
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275}
276
277/*
278 * Send a read command and address to the EEPROM, check for ACK.
279 */
22bf5b21
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280static void
281nge_eeprom_putbyte(struct nge_softc *sc, int addr)
984263bc 282{
22bf5b21 283 int d, i;
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284
285 d = addr | NGE_EECMD_READ;
286
287 /*
288 * Feed in each bit and stobe the clock.
289 */
290 for (i = 0x400; i; i >>= 1) {
22bf5b21 291 if (d & i)
984263bc 292 SIO_SET(NGE_MEAR_EE_DIN);
22bf5b21 293 else
984263bc 294 SIO_CLR(NGE_MEAR_EE_DIN);
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295 nge_delay(sc);
296 SIO_SET(NGE_MEAR_EE_CLK);
297 nge_delay(sc);
298 SIO_CLR(NGE_MEAR_EE_CLK);
299 nge_delay(sc);
300 }
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301}
302
303/*
304 * Read a word of data stored in the EEPROM at address 'addr.'
305 */
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306static void
307nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
984263bc 308{
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309 int i;
310 uint16_t word = 0;
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311
312 /* Force EEPROM to idle state. */
313 nge_eeprom_idle(sc);
314
315 /* Enter EEPROM access mode. */
316 nge_delay(sc);
317 SIO_CLR(NGE_MEAR_EE_CLK);
318 nge_delay(sc);
319 SIO_SET(NGE_MEAR_EE_CSEL);
320 nge_delay(sc);
321
322 /*
323 * Send address of word we want to read.
324 */
325 nge_eeprom_putbyte(sc, addr);
326
327 /*
328 * Start reading bits from EEPROM.
329 */
330 for (i = 0x8000; i; i >>= 1) {
331 SIO_SET(NGE_MEAR_EE_CLK);
332 nge_delay(sc);
333 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
334 word |= i;
335 nge_delay(sc);
336 SIO_CLR(NGE_MEAR_EE_CLK);
337 nge_delay(sc);
338 }
339
340 /* Turn off EEPROM access mode. */
341 nge_eeprom_idle(sc);
342
343 *dest = word;
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344}
345
346/*
347 * Read a sequence of words from the EEPROM.
348 */
22bf5b21
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349static void
350nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
984263bc 351{
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352 int i;
353 uint16_t word = 0, *ptr;
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354
355 for (i = 0; i < cnt; i++) {
356 nge_eeprom_getword(sc, off + i, &word);
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357 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
358 *ptr = word;
984263bc 359 }
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360}
361
362/*
363 * Sync the PHYs by setting data bit and strobing the clock 32 times.
364 */
22bf5b21
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365static void
366nge_mii_sync(struct nge_softc *sc)
984263bc 367{
22bf5b21 368 int i;
984263bc 369
22bf5b21 370 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
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MD
371
372 for (i = 0; i < 32; i++) {
373 SIO_SET(NGE_MEAR_MII_CLK);
374 DELAY(1);
375 SIO_CLR(NGE_MEAR_MII_CLK);
376 DELAY(1);
377 }
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378}
379
380/*
381 * Clock a series of bits through the MII.
382 */
22bf5b21
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383static void
384nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
984263bc 385{
22bf5b21 386 int i;
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387
388 SIO_CLR(NGE_MEAR_MII_CLK);
389
390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
22bf5b21 391 if (bits & i)
984263bc 392 SIO_SET(NGE_MEAR_MII_DATA);
22bf5b21 393 else
984263bc 394 SIO_CLR(NGE_MEAR_MII_DATA);
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395 DELAY(1);
396 SIO_CLR(NGE_MEAR_MII_CLK);
397 DELAY(1);
398 SIO_SET(NGE_MEAR_MII_CLK);
399 }
400}
401
402/*
403 * Read an PHY register through the MII.
404 */
22bf5b21
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405static int
406nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 407{
88e7510c 408 int ack, i;
984263bc 409
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410 /*
411 * Set up frame for RX.
412 */
413 frame->mii_stdelim = NGE_MII_STARTDELIM;
414 frame->mii_opcode = NGE_MII_READOP;
415 frame->mii_turnaround = 0;
416 frame->mii_data = 0;
22bf5b21 417
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418 CSR_WRITE_4(sc, NGE_MEAR, 0);
419
420 /*
421 * Turn on data xmit.
422 */
423 SIO_SET(NGE_MEAR_MII_DIR);
424
425 nge_mii_sync(sc);
426
427 /*
428 * Send command/address info.
429 */
430 nge_mii_send(sc, frame->mii_stdelim, 2);
431 nge_mii_send(sc, frame->mii_opcode, 2);
432 nge_mii_send(sc, frame->mii_phyaddr, 5);
433 nge_mii_send(sc, frame->mii_regaddr, 5);
434
435 /* Idle bit */
22bf5b21 436 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
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437 DELAY(1);
438 SIO_SET(NGE_MEAR_MII_CLK);
439 DELAY(1);
440
441 /* Turn off xmit. */
442 SIO_CLR(NGE_MEAR_MII_DIR);
443 /* Check for ack */
444 SIO_CLR(NGE_MEAR_MII_CLK);
445 DELAY(1);
446 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
447 SIO_SET(NGE_MEAR_MII_CLK);
448 DELAY(1);
449
450 /*
451 * Now try reading data bits. If the ack failed, we still
452 * need to clock through 16 cycles to keep the PHY(s) in sync.
453 */
454 if (ack) {
455 for(i = 0; i < 16; i++) {
456 SIO_CLR(NGE_MEAR_MII_CLK);
457 DELAY(1);
458 SIO_SET(NGE_MEAR_MII_CLK);
459 DELAY(1);
460 }
461 goto fail;
462 }
463
464 for (i = 0x8000; i; i >>= 1) {
465 SIO_CLR(NGE_MEAR_MII_CLK);
466 DELAY(1);
467 if (!ack) {
468 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
469 frame->mii_data |= i;
470 DELAY(1);
471 }
472 SIO_SET(NGE_MEAR_MII_CLK);
473 DELAY(1);
474 }
475
476fail:
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477 SIO_CLR(NGE_MEAR_MII_CLK);
478 DELAY(1);
479 SIO_SET(NGE_MEAR_MII_CLK);
480 DELAY(1);
481
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482 if (ack)
483 return(1);
484 return(0);
485}
486
487/*
488 * Write to a PHY register through the MII.
489 */
22bf5b21
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490static int
491nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 492{
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493 /*
494 * Set up frame for TX.
495 */
496
497 frame->mii_stdelim = NGE_MII_STARTDELIM;
498 frame->mii_opcode = NGE_MII_WRITEOP;
499 frame->mii_turnaround = NGE_MII_TURNAROUND;
500
501 /*
502 * Turn on data output.
503 */
504 SIO_SET(NGE_MEAR_MII_DIR);
505
506 nge_mii_sync(sc);
507
508 nge_mii_send(sc, frame->mii_stdelim, 2);
509 nge_mii_send(sc, frame->mii_opcode, 2);
510 nge_mii_send(sc, frame->mii_phyaddr, 5);
511 nge_mii_send(sc, frame->mii_regaddr, 5);
512 nge_mii_send(sc, frame->mii_turnaround, 2);
513 nge_mii_send(sc, frame->mii_data, 16);
514
515 /* Idle bit. */
516 SIO_SET(NGE_MEAR_MII_CLK);
517 DELAY(1);
518 SIO_CLR(NGE_MEAR_MII_CLK);
519 DELAY(1);
520
521 /*
522 * Turn off xmit.
523 */
524 SIO_CLR(NGE_MEAR_MII_DIR);
525
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526 return(0);
527}
528
22bf5b21
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529static int
530nge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 531{
22bf5b21
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532 struct nge_softc *sc = device_get_softc(dev);
533 struct nge_mii_frame frame;
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534
535 bzero((char *)&frame, sizeof(frame));
536
537 frame.mii_phyaddr = phy;
538 frame.mii_regaddr = reg;
539 nge_mii_readreg(sc, &frame);
540
541 return(frame.mii_data);
542}
543
22bf5b21
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544static int
545nge_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 546{
22bf5b21
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547 struct nge_softc *sc = device_get_softc(dev);
548 struct nge_mii_frame frame;
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549
550 bzero((char *)&frame, sizeof(frame));
551
552 frame.mii_phyaddr = phy;
553 frame.mii_regaddr = reg;
554 frame.mii_data = data;
555 nge_mii_writereg(sc, &frame);
556
557 return(0);
558}
559
22bf5b21
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560static void
561nge_miibus_statchg(device_t dev)
984263bc 562{
22bf5b21
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563 struct nge_softc *sc = device_get_softc(dev);
564 struct mii_data *mii;
565 int status;
984263bc 566
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567 if (sc->nge_tbi) {
568 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
569 == IFM_AUTO) {
570 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
571 if (status == 0 || status & NGE_TBIANAR_FDX) {
572 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 573 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
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574 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
575 } else {
576 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 577 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
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578 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
579 }
984263bc
MD
580 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
581 != IFM_FDX) {
582 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
585 } else {
586 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
588 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
589 }
590 } else {
591 mii = device_get_softc(sc->nge_miibus);
592
593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
594 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 595 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
596 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
597 } else {
598 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 599 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
600 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
601 }
602
603 /* If we have a 1000Mbps link, set the mode_1000 bit. */
7f259627 604 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
984263bc
MD
605 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
606 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
607 } else {
608 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
609 }
610 }
984263bc
MD
611}
612
22bf5b21
JS
613static void
614nge_setmulti(struct nge_softc *sc)
984263bc 615{
22bf5b21
JS
616 struct ifnet *ifp = &sc->arpcom.ac_if;
617 struct ifmultiaddr *ifma;
618 uint32_t filtsave, h = 0, i;
619 int bit, index;
984263bc
MD
620
621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
622 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 623 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
984263bc
MD
624 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
625 return;
626 }
627
628 /*
629 * We have to explicitly enable the multicast hash table
630 * on the NatSemi chip if we want to use it, which we do.
631 * We also have to tell it that we don't want to use the
632 * hash table for matching unicast addresses.
633 */
634 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
635 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 636 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
984263bc
MD
637
638 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
639
640 /* first, zot all the existing hash bits */
641 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
642 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
643 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
644 }
645
646 /*
647 * From the 11 bits returned by the crc routine, the top 7
648 * bits represent the 16-bit word in the mcast hash table
649 * that needs to be updated, and the lower 4 bits represent
650 * which bit within that byte needs to be set.
651 */
441d34b2 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
653 if (ifma->ifma_addr->sa_family != AF_LINK)
654 continue;
4c6f5f4c
JS
655 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
656 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
984263bc
MD
657 index = (h >> 4) & 0x7F;
658 bit = h & 0xF;
659 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
660 NGE_FILTADDR_MCAST_LO + (index * 2));
661 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
662 }
663
664 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
984263bc
MD
665}
666
22bf5b21
JS
667static void
668nge_reset(struct nge_softc *sc)
984263bc 669{
22bf5b21 670 int i;
984263bc
MD
671
672 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
673
674 for (i = 0; i < NGE_TIMEOUT; i++) {
22bf5b21 675 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
984263bc
MD
676 break;
677 }
678
679 if (i == NGE_TIMEOUT)
e3869ec7 680 kprintf("nge%d: reset never completed\n", sc->nge_unit);
984263bc
MD
681
682 /* Wait a little while for the chip to get its brains in order. */
683 DELAY(1000);
684
685 /*
686 * If this is a NetSemi chip, make sure to clear
687 * PME mode.
688 */
689 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
690 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
984263bc
MD
691}
692
693/*
694 * Probe for an NatSemi chip. Check the PCI vendor and device
695 * IDs against our list and return a device name if we find a match.
696 */
22bf5b21
JS
697static int
698nge_probe(device_t dev)
984263bc 699{
22bf5b21
JS
700 struct nge_type *t;
701 uint16_t vendor, product;
984263bc 702
22bf5b21
JS
703 vendor = pci_get_vendor(dev);
704 product = pci_get_device(dev);
984263bc 705
22bf5b21
JS
706 for (t = nge_devs; t->nge_name != NULL; t++) {
707 if (vendor == t->nge_vid && product == t->nge_did) {
984263bc
MD
708 device_set_desc(dev, t->nge_name);
709 return(0);
710 }
984263bc
MD
711 }
712
713 return(ENXIO);
714}
715
716/*
717 * Attach the interface. Allocate softc structures, do ifmedia
718 * setup and ethernet/BPF attach.
719 */
22bf5b21
JS
720static int
721nge_attach(device_t dev)
984263bc 722{
22bf5b21
JS
723 struct nge_softc *sc;
724 struct ifnet *ifp;
725 uint8_t eaddr[ETHER_ADDR_LEN];
726 uint32_t command;
88e7510c 727 int error = 0, rid, unit;
984263bc
MD
728 const char *sep = "";
729
984263bc
MD
730 sc = device_get_softc(dev);
731 unit = device_get_unit(dev);
43c4cb7e 732 callout_init(&sc->nge_stat_timer);
16dca0df 733 lwkt_serialize_init(&sc->nge_jslot_serializer);
984263bc
MD
734
735 /*
736 * Handle power management nonsense.
737 */
984263bc
MD
738 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
739 if (command == 0x01) {
984263bc
MD
740 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
741 if (command & NGE_PSTATE_MASK) {
22bf5b21 742 uint32_t iobase, membase, irq;
984263bc
MD
743
744 /* Save important PCI config data. */
745 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
746 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
747 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
748
749 /* Reset the power state. */
e3869ec7 750 kprintf("nge%d: chip is in D%d power mode "
984263bc
MD
751 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
752 command &= 0xFFFFFFFC;
753 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
754
755 /* Restore PCI config data. */
756 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
757 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
758 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
759 }
760 }
761
762 /*
763 * Map control/status registers.
764 */
765 command = pci_read_config(dev, PCIR_COMMAND, 4);
766 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
767 pci_write_config(dev, PCIR_COMMAND, command, 4);
768 command = pci_read_config(dev, PCIR_COMMAND, 4);
769
770#ifdef NGE_USEIOSPACE
771 if (!(command & PCIM_CMD_PORTEN)) {
e3869ec7 772 kprintf("nge%d: failed to enable I/O ports!\n", unit);
88e7510c
JS
773 error = ENXIO;
774 return(error);
984263bc
MD
775 }
776#else
777 if (!(command & PCIM_CMD_MEMEN)) {
e3869ec7 778 kprintf("nge%d: failed to enable memory mapping!\n", unit);
88e7510c
JS
779 error = ENXIO;
780 return(error);
984263bc
MD
781 }
782#endif
783
784 rid = NGE_RID;
4e6d744d 785 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
984263bc
MD
786
787 if (sc->nge_res == NULL) {
e3869ec7 788 kprintf("nge%d: couldn't map ports/memory\n", unit);
984263bc 789 error = ENXIO;
88e7510c 790 return(error);
984263bc
MD
791 }
792
793 sc->nge_btag = rman_get_bustag(sc->nge_res);
794 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
795
796 /* Allocate interrupt */
797 rid = 0;
4e6d744d 798 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
799 RF_SHAREABLE | RF_ACTIVE);
800
801 if (sc->nge_irq == NULL) {
e3869ec7 802 kprintf("nge%d: couldn't map interrupt\n", unit);
984263bc
MD
803 error = ENXIO;
804 goto fail;
805 }
806
984263bc
MD
807 /* Reset the adapter. */
808 nge_reset(sc);
809
810 /*
811 * Get station address from the EEPROM.
812 */
22bf5b21
JS
813 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
814 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
815 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
984263bc 816
984263bc 817 sc->nge_unit = unit;
984263bc
MD
818
819 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
e7b4468c 820 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
821
822 if (sc->nge_ldata == NULL) {
e3869ec7 823 kprintf("nge%d: no memory for list buffers!\n", unit);
984263bc
MD
824 error = ENXIO;
825 goto fail;
826 }
984263bc
MD
827
828 /* Try to allocate memory for jumbo buffers. */
829 if (nge_alloc_jumbo_mem(sc)) {
e3869ec7 830 kprintf("nge%d: jumbo buffer allocation failed\n",
984263bc 831 sc->nge_unit);
984263bc
MD
832 error = ENXIO;
833 goto fail;
834 }
835
836 ifp = &sc->arpcom.ac_if;
837 ifp->if_softc = sc;
cdb7d804 838 if_initname(ifp, "nge", unit);
984263bc
MD
839 ifp->if_mtu = ETHERMTU;
840 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
841 ifp->if_ioctl = nge_ioctl;
984263bc 842 ifp->if_start = nge_start;
bf58d756
SZ
843#ifdef IFPOLL_ENABLE
844 ifp->if_npoll = nge_npoll;
9c095379 845#endif
984263bc
MD
846 ifp->if_watchdog = nge_watchdog;
847 ifp->if_init = nge_init;
848 ifp->if_baudrate = 1000000000;
0b193118
JS
849 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
850 ifq_set_ready(&ifp->if_snd);
984263bc 851 ifp->if_hwassist = NGE_CSUM_FEATURES;
26a4e3b9 852 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
984263bc
MD
853 ifp->if_capenable = ifp->if_capabilities;
854
855 /*
856 * Do MII setup.
857 */
858 if (mii_phy_probe(dev, &sc->nge_miibus,
859 nge_ifmedia_upd, nge_ifmedia_sts)) {
860 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
861 sc->nge_tbi = 1;
862 device_printf(dev, "Using TBI\n");
863
864 sc->nge_miibus = dev;
865
866 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
867 nge_ifmedia_sts);
868#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
e3869ec7 869#define PRINT(s) kprintf("%s%s", sep, s); sep = ", "
984263bc
MD
870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
871 device_printf(dev, " ");
872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
873 PRINT("1000baseSX");
874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
875 PRINT("1000baseSX-FDX");
876 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
877 PRINT("auto");
878
e3869ec7 879 kprintf("\n");
984263bc
MD
880#undef ADD
881#undef PRINT
882 ifmedia_set(&sc->nge_ifmedia,
883 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
884
885 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
886 | NGE_GPIO_GP4_OUT
887 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
888 | NGE_GPIO_GP3_OUTENB
889 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
890
891 } else {
e3869ec7 892 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
984263bc
MD
893 error = ENXIO;
894 goto fail;
895 }
896 }
897
898 /*
899 * Call MI attach routine.
900 */
78195a76 901 ether_ifattach(ifp, eaddr, NULL);
984263bc 902
bf58d756
SZ
903#ifdef IFPOLL_ENABLE
904 ifpoll_compat_setup(&sc->nge_npoll, NULL, NULL, device_get_unit(dev),
905 ifp->if_serializer);
906#endif
907
95893fe4 908 error = bus_setup_intr(dev, sc->nge_irq, INTR_MPSAFE,
78195a76
MD
909 nge_intr, sc, &sc->nge_intrhand,
910 ifp->if_serializer);
88e7510c
JS
911 if (error) {
912 ether_ifdetach(ifp);
913 device_printf(dev, "couldn't set up irq\n");
914 goto fail;
915 }
984263bc 916
28e81a28 917 ifp->if_cpuid = rman_get_cpuid(sc->nge_irq);
9db4b353
SZ
918 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
919
88e7510c
JS
920 return(0);
921fail:
922 nge_detach(dev);
984263bc
MD
923 return(error);
924}
925
22bf5b21
JS
926static int
927nge_detach(device_t dev)
984263bc 928{
88e7510c
JS
929 struct nge_softc *sc = device_get_softc(dev);
930 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 931
88e7510c 932 if (device_is_attached(dev)) {
cdf89432 933 lwkt_serialize_enter(ifp->if_serializer);
88e7510c
JS
934 nge_reset(sc);
935 nge_stop(sc);
cdf89432
SZ
936 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
937 lwkt_serialize_exit(ifp->if_serializer);
938
88e7510c
JS
939 ether_ifdetach(ifp);
940 }
984263bc 941
88e7510c 942 if (sc->nge_miibus)
984263bc 943 device_delete_child(dev, sc->nge_miibus);
88e7510c 944 bus_generic_detach(dev);
22bf5b21 945
88e7510c
JS
946 if (sc->nge_irq)
947 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
948 if (sc->nge_res)
949 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
950 if (sc->nge_ldata) {
951 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
952 M_DEVBUF);
953 }
954 if (sc->nge_cdata.nge_jumbo_buf)
955 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
984263bc
MD
956
957 return(0);
958}
959
960/*
961 * Initialize the transmit descriptors.
962 */
22bf5b21
JS
963static int
964nge_list_tx_init(struct nge_softc *sc)
984263bc 965{
22bf5b21
JS
966 struct nge_list_data *ld;
967 struct nge_ring_data *cd;
968 int i;
984263bc
MD
969
970 cd = &sc->nge_cdata;
971 ld = sc->nge_ldata;
972
973 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
974 if (i == (NGE_TX_LIST_CNT - 1)) {
975 ld->nge_tx_list[i].nge_nextdesc =
976 &ld->nge_tx_list[0];
977 ld->nge_tx_list[i].nge_next =
978 vtophys(&ld->nge_tx_list[0]);
979 } else {
980 ld->nge_tx_list[i].nge_nextdesc =
981 &ld->nge_tx_list[i + 1];
982 ld->nge_tx_list[i].nge_next =
983 vtophys(&ld->nge_tx_list[i + 1]);
984 }
985 ld->nge_tx_list[i].nge_mbuf = NULL;
986 ld->nge_tx_list[i].nge_ptr = 0;
987 ld->nge_tx_list[i].nge_ctl = 0;
988 }
989
990 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
991
992 return(0);
993}
994
995
996/*
997 * Initialize the RX descriptors and allocate mbufs for them. Note that
998 * we arrange the descriptors in a closed ring, so that the last descriptor
999 * points back to the first.
1000 */
22bf5b21
JS
1001static int
1002nge_list_rx_init(struct nge_softc *sc)
984263bc 1003{
22bf5b21
JS
1004 struct nge_list_data *ld;
1005 struct nge_ring_data *cd;
1006 int i;
984263bc
MD
1007
1008 ld = sc->nge_ldata;
1009 cd = &sc->nge_cdata;
1010
1011 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1012 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1013 return(ENOBUFS);
1014 if (i == (NGE_RX_LIST_CNT - 1)) {
1015 ld->nge_rx_list[i].nge_nextdesc =
1016 &ld->nge_rx_list[0];
1017 ld->nge_rx_list[i].nge_next =
1018 vtophys(&ld->nge_rx_list[0]);
1019 } else {
1020 ld->nge_rx_list[i].nge_nextdesc =
1021 &ld->nge_rx_list[i + 1];
1022 ld->nge_rx_list[i].nge_next =
1023 vtophys(&ld->nge_rx_list[i + 1]);
1024 }
1025 }
1026
1027 cd->nge_rx_prod = 0;
1028
1029 return(0);
1030}
1031
1032/*
1033 * Initialize an RX descriptor and attach an MBUF cluster.
1034 */
22bf5b21
JS
1035static int
1036nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
984263bc 1037{
22bf5b21 1038 struct mbuf *m_new = NULL;
368e791d 1039 struct nge_jslot *buf;
984263bc
MD
1040
1041 if (m == NULL) {
74f1caca 1042 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc 1043 if (m_new == NULL) {
e3869ec7 1044 kprintf("nge%d: no memory for rx list "
984263bc
MD
1045 "-- packet dropped!\n", sc->nge_unit);
1046 return(ENOBUFS);
1047 }
1048
1049 /* Allocate the jumbo buffer */
1050 buf = nge_jalloc(sc);
1051 if (buf == NULL) {
1052#ifdef NGE_VERBOSE
e3869ec7 1053 kprintf("nge%d: jumbo allocation failed "
984263bc
MD
1054 "-- packet dropped!\n", sc->nge_unit);
1055#endif
1056 m_freem(m_new);
1057 return(ENOBUFS);
1058 }
1059 /* Attach the buffer to the mbuf */
368e791d
JS
1060 m_new->m_ext.ext_arg = buf;
1061 m_new->m_ext.ext_buf = buf->nge_buf;
b542cd49
JS
1062 m_new->m_ext.ext_free = nge_jfree;
1063 m_new->m_ext.ext_ref = nge_jref;
368e791d
JS
1064 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1065
1066 m_new->m_data = m_new->m_ext.ext_buf;
1067 m_new->m_flags |= M_EXT;
1068 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc
MD
1069 } else {
1070 m_new = m;
368e791d 1071 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
984263bc
MD
1072 m_new->m_data = m_new->m_ext.ext_buf;
1073 }
1074
22bf5b21 1075 m_adj(m_new, sizeof(uint64_t));
984263bc
MD
1076
1077 c->nge_mbuf = m_new;
1078 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1079 c->nge_ctl = m_new->m_len;
1080 c->nge_extsts = 0;
1081
1082 return(0);
1083}
1084
22bf5b21
JS
1085static int
1086nge_alloc_jumbo_mem(struct nge_softc *sc)
984263bc 1087{
22bf5b21
JS
1088 caddr_t ptr;
1089 int i;
368e791d 1090 struct nge_jslot *entry;
984263bc
MD
1091
1092 /* Grab a big chunk o' storage. */
1093 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
56ae9d75 1094 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
1095
1096 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
e3869ec7 1097 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
984263bc
MD
1098 return(ENOBUFS);
1099 }
1100
1101 SLIST_INIT(&sc->nge_jfree_listhead);
984263bc
MD
1102
1103 /*
1104 * Now divide it up into 9K pieces and save the addresses
1105 * in an array.
1106 */
1107 ptr = sc->nge_cdata.nge_jumbo_buf;
1108 for (i = 0; i < NGE_JSLOTS; i++) {
368e791d
JS
1109 entry = &sc->nge_cdata.nge_jslots[i];
1110 entry->nge_sc = sc;
1111 entry->nge_buf = ptr;
1112 entry->nge_inuse = 0;
1113 entry->nge_slot = i;
1114 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1115 ptr += NGE_JLEN;
984263bc
MD
1116 }
1117
1118 return(0);
1119}
1120
984263bc
MD
1121
1122/*
1123 * Allocate a jumbo buffer.
1124 */
368e791d 1125static struct nge_jslot *
22bf5b21 1126nge_jalloc(struct nge_softc *sc)
984263bc 1127{
368e791d 1128 struct nge_jslot *entry;
22bf5b21 1129
16dca0df 1130 lwkt_serialize_enter(&sc->nge_jslot_serializer);
984263bc 1131 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
16dca0df
MD
1132 if (entry) {
1133 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1134 entry->nge_inuse = 1;
1135 } else {
984263bc 1136#ifdef NGE_VERBOSE
e3869ec7 1137 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
984263bc 1138#endif
984263bc 1139 }
16dca0df 1140 lwkt_serialize_exit(&sc->nge_jslot_serializer);
368e791d 1141 return(entry);
984263bc
MD
1142}
1143
1144/*
1145 * Adjust usage count on a jumbo buffer. In general this doesn't
1146 * get used much because our jumbo buffers don't get passed around
1147 * a lot, but it's implemented for correctness.
1148 */
22bf5b21 1149static void
368e791d 1150nge_jref(void *arg)
984263bc 1151{
368e791d
JS
1152 struct nge_jslot *entry = (struct nge_jslot *)arg;
1153 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1154
1155 if (sc == NULL)
1156 panic("nge_jref: can't find softc pointer!");
1157
368e791d 1158 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
984263bc
MD
1159 panic("nge_jref: asked to reference buffer "
1160 "that we don't manage!");
368e791d 1161 else if (entry->nge_inuse == 0)
984263bc
MD
1162 panic("nge_jref: buffer already free!");
1163 else
16dca0df 1164 atomic_add_int(&entry->nge_inuse, 1);
984263bc
MD
1165}
1166
1167/*
1168 * Release a jumbo buffer.
1169 */
22bf5b21 1170static void
368e791d 1171nge_jfree(void *arg)
984263bc 1172{
368e791d
JS
1173 struct nge_jslot *entry = (struct nge_jslot *)arg;
1174 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1175
1176 if (sc == NULL)
368e791d
JS
1177 panic("nge_jref: can't find softc pointer!");
1178
16dca0df 1179 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
368e791d
JS
1180 panic("nge_jref: asked to reference buffer "
1181 "that we don't manage!");
16dca0df 1182 } else if (entry->nge_inuse == 0) {
368e791d 1183 panic("nge_jref: buffer already free!");
16dca0df
MD
1184 } else {
1185 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1186 atomic_subtract_int(&entry->nge_inuse, 1);
1187 if (entry->nge_inuse == 0) {
1188 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1189 entry, jslot_link);
1190 }
1191 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1192 }
984263bc
MD
1193}
1194/*
1195 * A frame has been uploaded: pass the resulting mbuf chain up to
1196 * the higher level protocols.
1197 */
22bf5b21
JS
1198static void
1199nge_rxeof(struct nge_softc *sc)
984263bc 1200{
22bf5b21
JS
1201 struct mbuf *m;
1202 struct ifnet *ifp = &sc->arpcom.ac_if;
1203 struct nge_desc *cur_rx;
1204 int i, total_len = 0;
1205 uint32_t rxstat;
984263bc 1206
984263bc
MD
1207 i = sc->nge_cdata.nge_rx_prod;
1208
1209 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
22bf5b21
JS
1210 struct mbuf *m0 = NULL;
1211 uint32_t extsts;
984263bc 1212
bf58d756
SZ
1213#ifdef IFPOLL_ENABLE
1214 if (ifp->if_flags & IFF_NPOLLING) {
984263bc
MD
1215 if (sc->rxcycles <= 0)
1216 break;
1217 sc->rxcycles--;
1218 }
bf58d756 1219#endif /* IFPOLL_ENABLE */
984263bc
MD
1220
1221 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1222 rxstat = cur_rx->nge_rxstat;
1223 extsts = cur_rx->nge_extsts;
1224 m = cur_rx->nge_mbuf;
1225 cur_rx->nge_mbuf = NULL;
1226 total_len = NGE_RXBYTES(cur_rx);
1227 NGE_INC(i, NGE_RX_LIST_CNT);
1228 /*
1229 * If an error occurs, update stats, clear the
1230 * status word and leave the mbuf cluster in place:
1231 * it should simply get re-used next time this descriptor
1232 * comes up in the ring.
1233 */
22bf5b21 1234 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
984263bc
MD
1235 ifp->if_ierrors++;
1236 nge_newbuf(sc, cur_rx, m);
1237 continue;
1238 }
1239
1240 /*
1241 * Ok. NatSemi really screwed up here. This is the
1242 * only gigE chip I know of with alignment constraints
1243 * on receive buffers. RX buffers must be 64-bit aligned.
1244 */
1245#ifdef __i386__
1246 /*
1247 * By popular demand, ignore the alignment problems
1248 * on the Intel x86 platform. The performance hit
1249 * incurred due to unaligned accesses is much smaller
1250 * than the hit produced by forcing buffer copies all
1251 * the time, especially with jumbo frames. We still
1252 * need to fix up the alignment everywhere else though.
1253 */
1254 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1255#endif
1256 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1257 total_len + ETHER_ALIGN, 0, ifp, NULL);
1258 nge_newbuf(sc, cur_rx, m);
1259 if (m0 == NULL) {
e3869ec7 1260 kprintf("nge%d: no receive buffers "
984263bc
MD
1261 "available -- packet dropped!\n",
1262 sc->nge_unit);
1263 ifp->if_ierrors++;
1264 continue;
1265 }
1266 m_adj(m0, ETHER_ALIGN);
1267 m = m0;
1268#ifdef __i386__
1269 } else {
1270 m->m_pkthdr.rcvif = ifp;
1271 m->m_pkthdr.len = m->m_len = total_len;
1272 }
1273#endif
1274
1275 ifp->if_ipackets++;
984263bc
MD
1276
1277 /* Do IP checksum checking. */
1278 if (extsts & NGE_RXEXTSTS_IPPKT)
1279 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1280 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1281 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1282 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
22bf5b21 1283 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
984263bc 1284 (extsts & NGE_RXEXTSTS_UDPPKT &&
22bf5b21 1285 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
984263bc 1286 m->m_pkthdr.csum_flags |=
fbb35ef0
SZ
1287 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1288 CSUM_FRAG_NOT_CHECKED;
984263bc
MD
1289 m->m_pkthdr.csum_data = 0xffff;
1290 }
1291
1292 /*
1293 * If we received a packet with a vlan tag, pass it
1294 * to vlan_input() instead of ether_input().
1295 */
e6b5847c
SZ
1296 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1297 m->m_flags |= M_VLANTAG;
1298 m->m_pkthdr.ether_vlantag =
1299 (extsts & NGE_RXEXTSTS_VTCI);
1300 }
1301 ifp->if_input(ifp, m);
984263bc
MD
1302 }
1303
1304 sc->nge_cdata.nge_rx_prod = i;
984263bc
MD
1305}
1306
1307/*
1308 * A frame was downloaded to the chip. It's safe for us to clean up
1309 * the list buffers.
1310 */
22bf5b21
JS
1311static void
1312nge_txeof(struct nge_softc *sc)
984263bc 1313{
22bf5b21
JS
1314 struct ifnet *ifp = &sc->arpcom.ac_if;
1315 struct nge_desc *cur_tx = NULL;
1316 uint32_t idx;
984263bc
MD
1317
1318 /* Clear the timeout timer. */
1319 ifp->if_timer = 0;
1320
1321 /*
1322 * Go through our tx list and free mbufs for those
1323 * frames that have been transmitted.
1324 */
1325 idx = sc->nge_cdata.nge_tx_cons;
1326 while (idx != sc->nge_cdata.nge_tx_prod) {
1327 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1328
1329 if (NGE_OWNDESC(cur_tx))
1330 break;
1331
1332 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1333 sc->nge_cdata.nge_tx_cnt--;
1334 NGE_INC(idx, NGE_TX_LIST_CNT);
1335 continue;
1336 }
1337
1338 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1339 ifp->if_oerrors++;
1340 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1341 ifp->if_collisions++;
1342 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1343 ifp->if_collisions++;
1344 }
1345
1346 ifp->if_collisions +=
1347 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1348
1349 ifp->if_opackets++;
1350 if (cur_tx->nge_mbuf != NULL) {
1351 m_freem(cur_tx->nge_mbuf);
1352 cur_tx->nge_mbuf = NULL;
1353 }
1354
1355 sc->nge_cdata.nge_tx_cnt--;
1356 NGE_INC(idx, NGE_TX_LIST_CNT);
1357 ifp->if_timer = 0;
1358 }
1359
1360 sc->nge_cdata.nge_tx_cons = idx;
1361
1362 if (cur_tx != NULL)
1363 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1364}
1365
22bf5b21
JS
1366static void
1367nge_tick(void *xsc)
984263bc 1368{
22bf5b21
JS
1369 struct nge_softc *sc = xsc;
1370 struct ifnet *ifp = &sc->arpcom.ac_if;
1371 struct mii_data *mii;
984263bc 1372
78195a76 1373 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1374
984263bc 1375 if (sc->nge_tbi) {
22bf5b21 1376 if (sc->nge_link == 0) {
984263bc
MD
1377 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1378 & NGE_TBIBMSR_ANEG_DONE) {
e3869ec7 1379 kprintf("nge%d: gigabit link up\n",
984263bc
MD
1380 sc->nge_unit);
1381 nge_miibus_statchg(sc->nge_miibus);
1382 sc->nge_link++;
0b193118 1383 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1384 if_devstart(ifp);
984263bc
MD
1385 }
1386 }
1387 } else {
1388 mii = device_get_softc(sc->nge_miibus);
1389 mii_tick(mii);
1390
22bf5b21 1391 if (sc->nge_link == 0) {
984263bc
MD
1392 if (mii->mii_media_status & IFM_ACTIVE &&
1393 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1394 sc->nge_link++;
1395 if (IFM_SUBTYPE(mii->mii_media_active)
7f259627 1396 == IFM_1000_T)
e3869ec7 1397 kprintf("nge%d: gigabit link up\n",
984263bc 1398 sc->nge_unit);
0b193118 1399 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1400 if_devstart(ifp);
984263bc
MD
1401 }
1402 }
1403 }
43c4cb7e 1404 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1405
78195a76 1406 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1407}
1408
bf58d756 1409#ifdef IFPOLL_ENABLE
984263bc
MD
1410
1411static void
bf58d756 1412nge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
984263bc 1413{
22bf5b21 1414 struct nge_softc *sc = ifp->if_softc;
984263bc 1415
bf58d756 1416 ASSERT_SERIALIZED(ifp->if_serializer);
984263bc 1417
bf58d756
SZ
1418 /*
1419 * On the nge, reading the status register also clears it.
1420 * So before returning to intr mode we must make sure that all
1421 * possible pending sources of interrupts have been served.
1422 * In practice this means run to completion the *eof routines,
1423 * and then call the interrupt routine
1424 */
1425 sc->rxcycles = count;
1426 nge_rxeof(sc);
1427 nge_txeof(sc);
1428 if (!ifq_is_empty(&ifp->if_snd))
1429 if_devstart(ifp);
984263bc 1430
bf58d756
SZ
1431 if (sc->nge_npoll.ifpc_stcount-- == 0) {
1432 uint32_t status;
984263bc 1433
bf58d756 1434 sc->nge_npoll.ifpc_stcount = sc->nge_npoll.ifpc_stfrac;
984263bc 1435
bf58d756
SZ
1436 /* Reading the ISR register clears all interrupts. */
1437 status = CSR_READ_4(sc, NGE_ISR);
984263bc 1438
bf58d756
SZ
1439 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1440 nge_rxeof(sc);
1441
1442 if (status & (NGE_ISR_RX_IDLE))
1443 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1444
1445 if (status & NGE_ISR_SYSERR) {
1446 nge_reset(sc);
1447 nge_init(sc);
1448 }
1449 }
1450}
1451
1452static void
1453nge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1454{
1455 struct nge_softc *sc = ifp->if_softc;
1456
1457 ASSERT_SERIALIZED(ifp->if_serializer);
1458
1459 if (info != NULL) {
1460 int cpuid = sc->nge_npoll.ifpc_cpuid;
1461
1462 info->ifpi_rx[cpuid].poll_func = nge_npoll_compat;
1463 info->ifpi_rx[cpuid].arg = NULL;
1464 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1465
1466 if (ifp->if_flags & IFF_RUNNING) {
1467 /* disable interrupts */
1468 CSR_WRITE_4(sc, NGE_IER, 0);
1469 sc->nge_npoll.ifpc_stcount = 0;
1470 }
1471 ifp->if_npoll_cpuid = cpuid;
1472 } else {
1473 if (ifp->if_flags & IFF_RUNNING) {
1474 /* enable interrupts */
1475 CSR_WRITE_4(sc, NGE_IER, 1);
984263bc 1476 }
bf58d756 1477 ifp->if_npoll_cpuid = -1;
984263bc
MD
1478 }
1479}
9c095379 1480
bf58d756 1481#endif /* IFPOLL_ENABLE */
984263bc 1482
22bf5b21
JS
1483static void
1484nge_intr(void *arg)
984263bc 1485{
22bf5b21
JS
1486 struct nge_softc *sc = arg;
1487 struct ifnet *ifp = &sc->arpcom.ac_if;
1488 uint32_t status;
984263bc 1489
984263bc
MD
1490 /* Supress unwanted interrupts */
1491 if (!(ifp->if_flags & IFF_UP)) {
1492 nge_stop(sc);
1493 return;
1494 }
1495
1496 /* Disable interrupts. */
1497 CSR_WRITE_4(sc, NGE_IER, 0);
1498
1499 /* Data LED on for TBI mode */
1500 if(sc->nge_tbi)
1501 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1502 | NGE_GPIO_GP3_OUT);
1503
1504 for (;;) {
1505 /* Reading the ISR register clears all interrupts. */
1506 status = CSR_READ_4(sc, NGE_ISR);
1507
1508 if ((status & NGE_INTRS) == 0)
1509 break;
1510
1511 if ((status & NGE_ISR_TX_DESC_OK) ||
1512 (status & NGE_ISR_TX_ERR) ||
1513 (status & NGE_ISR_TX_OK) ||
1514 (status & NGE_ISR_TX_IDLE))
1515 nge_txeof(sc);
1516
1517 if ((status & NGE_ISR_RX_DESC_OK) ||
1518 (status & NGE_ISR_RX_ERR) ||
1519 (status & NGE_ISR_RX_OFLOW) ||
1520 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1521 (status & NGE_ISR_RX_IDLE) ||
1522 (status & NGE_ISR_RX_OK))
1523 nge_rxeof(sc);
1524
1525 if ((status & NGE_ISR_RX_IDLE))
1526 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1527
1528 if (status & NGE_ISR_SYSERR) {
1529 nge_reset(sc);
1530 ifp->if_flags &= ~IFF_RUNNING;
1531 nge_init(sc);
1532 }
1533
1534#ifdef notyet
1535 /* mii_tick should only be called once per second */
1536 if (status & NGE_ISR_PHY_INTR) {
1537 sc->nge_link = 0;
78195a76 1538 nge_tick_serialized(sc);
984263bc
MD
1539 }
1540#endif
1541 }
1542
1543 /* Re-enable interrupts. */
1544 CSR_WRITE_4(sc, NGE_IER, 1);
1545
0b193118 1546 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1547 if_devstart(ifp);
984263bc
MD
1548
1549 /* Data LED off for TBI mode */
1550
1551 if(sc->nge_tbi)
1552 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1553 & ~NGE_GPIO_GP3_OUT);
984263bc
MD
1554}
1555
1556/*
1557 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1558 * pointers to the fragment pointers.
1559 */
22bf5b21
JS
1560static int
1561nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1562{
22bf5b21
JS
1563 struct nge_desc *f = NULL;
1564 struct mbuf *m;
1565 int frag, cur, cnt = 0;
984263bc
MD
1566
1567 /*
1568 * Start packing the mbufs in this chain into
1569 * the fragment pointers. Stop when we run out
1570 * of fragments or hit the end of the mbuf chain.
1571 */
984263bc
MD
1572 cur = frag = *txidx;
1573
1574 for (m = m_head; m != NULL; m = m->m_next) {
1575 if (m->m_len != 0) {
1576 if ((NGE_TX_LIST_CNT -
1577 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
9db4b353 1578 break;
984263bc
MD
1579 f = &sc->nge_ldata->nge_tx_list[frag];
1580 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1581 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1582 if (cnt != 0)
1583 f->nge_ctl |= NGE_CMDSTS_OWN;
1584 cur = frag;
1585 NGE_INC(frag, NGE_TX_LIST_CNT);
1586 cnt++;
1587 }
1588 }
9db4b353 1589 /* Caller should make sure that 'm_head' is not excessive fragmented */
ed20d0e3 1590 KASSERT(m == NULL, ("too many fragments"));
984263bc
MD
1591
1592 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1593 if (m_head->m_pkthdr.csum_flags) {
1594 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1595 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1596 NGE_TXEXTSTS_IPCSUM;
1597 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1598 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1599 NGE_TXEXTSTS_TCPCSUM;
1600 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1601 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1602 NGE_TXEXTSTS_UDPCSUM;
1603 }
1604
83790f85 1605 if (m_head->m_flags & M_VLANTAG) {
984263bc 1606 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
83790f85 1607 (NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag);
984263bc
MD
1608 }
1609
1610 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1611 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1612 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1613 sc->nge_cdata.nge_tx_cnt += cnt;
1614 *txidx = frag;
1615
1616 return(0);
1617}
1618
1619/*
1620 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1621 * to the mbuf data regions directly in the transmit lists. We also save a
1622 * copy of the pointers since the transmit list fragment pointers are
1623 * physical addresses.
1624 */
1625
22bf5b21
JS
1626static void
1627nge_start(struct ifnet *ifp)
984263bc 1628{
22bf5b21 1629 struct nge_softc *sc = ifp->if_softc;
9db4b353 1630 struct mbuf *m_head = NULL, *m_defragged;
22bf5b21 1631 uint32_t idx;
2f54d1d2 1632 int need_trans;
984263bc 1633
9db4b353
SZ
1634 if (!sc->nge_link) {
1635 ifq_purge(&ifp->if_snd);
984263bc 1636 return;
9db4b353 1637 }
984263bc
MD
1638
1639 idx = sc->nge_cdata.nge_tx_prod;
1640
9db4b353 1641 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
984263bc
MD
1642 return;
1643
2f54d1d2 1644 need_trans = 0;
9db4b353
SZ
1645 while (sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1646 struct mbuf *m;
1647 int cnt;
1648
1649 m_defragged = NULL;
1650 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1651 if (m_head == NULL)
1652 break;
1653
9db4b353
SZ
1654again:
1655 cnt = 0;
1656 for (m = m_head; m != NULL; m = m->m_next)
1657 ++cnt;
1658 if ((NGE_TX_LIST_CNT -
1659 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) {
1660 if (m_defragged != NULL) {
1661 /*
1662 * Even after defragmentation, there
1663 * are still too many fragments, so
1664 * drop this packet.
1665 */
1666 m_freem(m_head);
1667 ifp->if_flags |= IFF_OACTIVE;
1668 break;
1669 }
1670
1671 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1672 if (m_defragged == NULL) {
1673 m_freem(m_head);
1674 continue;
1675 }
1676 m_head = m_defragged;
1677
1678 /* Recount # of fragments */
1679 goto again;
984263bc 1680 }
9db4b353
SZ
1681
1682 nge_encap(sc, m_head, &idx);
2f54d1d2 1683 need_trans = 1;
984263bc 1684
b637f170 1685 ETHER_BPF_MTAP(ifp, m_head);
984263bc
MD
1686 }
1687
2f54d1d2
SZ
1688 if (!need_trans)
1689 return;
1690
984263bc
MD
1691 /* Transmit */
1692 sc->nge_cdata.nge_tx_prod = idx;
1693 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1694
1695 /*
1696 * Set a timeout in case the chip goes out to lunch.
1697 */
1698 ifp->if_timer = 5;
984263bc
MD
1699}
1700
22bf5b21
JS
1701static void
1702nge_init(void *xsc)
984263bc 1703{
22bf5b21
JS
1704 struct nge_softc *sc = xsc;
1705 struct ifnet *ifp = &sc->arpcom.ac_if;
1706 struct mii_data *mii;
984263bc 1707
88e7510c 1708 if (ifp->if_flags & IFF_RUNNING) {
88e7510c
JS
1709 return;
1710 }
984263bc
MD
1711
1712 /*
1713 * Cancel pending I/O and free all RX/TX buffers.
1714 */
1715 nge_stop(sc);
43c4cb7e 1716 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1717
22bf5b21 1718 if (sc->nge_tbi)
984263bc 1719 mii = NULL;
22bf5b21 1720 else
984263bc 1721 mii = device_get_softc(sc->nge_miibus);
984263bc
MD
1722
1723 /* Set MAC address */
1724 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1725 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1726 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1727 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1728 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1729 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1730 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1731 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1732 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1733
1734 /* Init circular RX list. */
1735 if (nge_list_rx_init(sc) == ENOBUFS) {
e3869ec7 1736 kprintf("nge%d: initialization failed: no "
984263bc
MD
1737 "memory for rx buffers\n", sc->nge_unit);
1738 nge_stop(sc);
984263bc
MD
1739 return;
1740 }
1741
1742 /*
1743 * Init tx descriptors.
1744 */
1745 nge_list_tx_init(sc);
1746
1747 /*
1748 * For the NatSemi chip, we have to explicitly enable the
1749 * reception of ARP frames, as well as turn on the 'perfect
1750 * match' filter where we store the station address, otherwise
1751 * we won't receive unicasts meant for this host.
1752 */
1753 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1754 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1755
1756 /* If we want promiscuous mode, set the allframes bit. */
22bf5b21 1757 if (ifp->if_flags & IFF_PROMISC)
984263bc 1758 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
22bf5b21 1759 else
984263bc 1760 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
984263bc
MD
1761
1762 /*
1763 * Set the capture broadcast bit to capture broadcast frames.
1764 */
22bf5b21 1765 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1766 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
22bf5b21 1767 else
984263bc 1768 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
984263bc
MD
1769
1770 /*
1771 * Load the multicast filter.
1772 */
1773 nge_setmulti(sc);
1774
1775 /* Turn the receive filter on */
1776 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1777
1778 /*
1779 * Load the address of the RX and TX lists.
1780 */
1781 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1782 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1783 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1784 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1785
1786 /* Set RX configuration */
1787 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1788 /*
1789 * Enable hardware checksum validation for all IPv4
1790 * packets, do not reject packets with bad checksums.
1791 */
1792 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1793
1794 /*
1795 * Tell the chip to detect and strip VLAN tag info from
1796 * received frames. The tag will be provided in the extsts
1797 * field in the RX descriptors.
1798 */
1799 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1800 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1801
1802 /* Set TX configuration */
1803 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1804
1805 /*
1806 * Enable TX IPv4 checksumming on a per-packet basis.
1807 */
1808 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1809
1810 /*
1811 * Tell the chip to insert VLAN tags on a per-packet basis as
1812 * dictated by the code in the frame encapsulation routine.
1813 */
1814 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1815
1816 /* Set full/half duplex mode. */
1817 if (sc->nge_tbi) {
1818 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1819 == IFM_FDX) {
1820 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1821 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1822 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1823 } else {
1824 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1825 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1826 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1827 }
1828 } else {
1829 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1830 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1831 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1832 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1833 } else {
1834 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1835 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1836 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1837 }
1838 }
1839
1840 /*
1841 * Enable the delivery of PHY interrupts based on
1842 * link/speed/duplex status changes. Also enable the
1843 * extsts field in the DMA descriptors (needed for
1844 * TCP/IP checksum offload on transmit).
1845 */
22bf5b21
JS
1846 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1847 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
984263bc
MD
1848
1849 /*
1850 * Configure interrupt holdoff (moderation). We can
1851 * have the chip delay interrupt delivery for a certain
1852 * period. Units are in 100us, and the max setting
1853 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1854 */
1855 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1856
1857 /*
1858 * Enable interrupts.
1859 */
1860 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
bf58d756 1861#ifdef IFPOLL_ENABLE
984263bc
MD
1862 /*
1863 * ... only enable interrupts if we are not polling, make sure
1864 * they are off otherwise.
1865 */
bf58d756 1866 if (ifp->if_flags & IFF_NPOLLING) {
984263bc 1867 CSR_WRITE_4(sc, NGE_IER, 0);
bf58d756
SZ
1868 sc->nge_npoll.ifpc_stcount = 0;
1869 } else
1870#endif /* IFPOLL_ENABLE */
984263bc
MD
1871 CSR_WRITE_4(sc, NGE_IER, 1);
1872
1873 /* Enable receiver and transmitter. */
22bf5b21 1874 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
984263bc
MD
1875 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1876
1877 nge_ifmedia_upd(ifp);
1878
1879 ifp->if_flags |= IFF_RUNNING;
1880 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1881}
1882
1883/*
1884 * Set media options.
1885 */
22bf5b21
JS
1886static int
1887nge_ifmedia_upd(struct ifnet *ifp)
984263bc 1888{
22bf5b21
JS
1889 struct nge_softc *sc = ifp->if_softc;
1890 struct mii_data *mii;
984263bc
MD
1891
1892 if (sc->nge_tbi) {
1893 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1894 == IFM_AUTO) {
1895 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1896 CSR_READ_4(sc, NGE_TBI_ANAR)
1897 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1898 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1899 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1900 | NGE_TBIBMCR_RESTART_ANEG);
1901 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1902 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1903 & IFM_GMASK) == IFM_FDX) {
1904 NGE_SETBIT(sc, NGE_TX_CFG,
1905 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1906 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1907
1908 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1909 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1910 } else {
1911 NGE_CLRBIT(sc, NGE_TX_CFG,
1912 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1913 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1914
1915 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1916 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1917 }
1918
1919 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1920 & ~NGE_GPIO_GP3_OUT);
1921 } else {
1922 mii = device_get_softc(sc->nge_miibus);
1923 sc->nge_link = 0;
1924 if (mii->mii_instance) {
1925 struct mii_softc *miisc;
1926 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1927 miisc = LIST_NEXT(miisc, mii_list))
1928 mii_phy_reset(miisc);
1929 }
1930 mii_mediachg(mii);
1931 }
1932
1933 return(0);
1934}
1935
1936/*
1937 * Report current media status.
1938 */
22bf5b21
JS
1939static void
1940nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1941{
22bf5b21
JS
1942 struct nge_softc *sc = ifp->if_softc;
1943 struct mii_data *mii;
984263bc
MD
1944
1945 if (sc->nge_tbi) {
1946 ifmr->ifm_status = IFM_AVALID;
1947 ifmr->ifm_active = IFM_ETHER;
1948
22bf5b21 1949 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
984263bc 1950 ifmr->ifm_status |= IFM_ACTIVE;
984263bc
MD
1951 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1952 ifmr->ifm_active |= IFM_LOOP;
9ba8519f 1953 if (!(CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)) {
984263bc
MD
1954 ifmr->ifm_active |= IFM_NONE;
1955 ifmr->ifm_status = 0;
1956 return;
1957 }
1958 ifmr->ifm_active |= IFM_1000_SX;
1959 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1960 == IFM_AUTO) {
1961 ifmr->ifm_active |= IFM_AUTO;
1962 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1963 & NGE_TBIANAR_FDX) {
1964 ifmr->ifm_active |= IFM_FDX;
1965 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1966 & NGE_TBIANAR_HDX) {
1967 ifmr->ifm_active |= IFM_HDX;
1968 }
1969 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1970 == IFM_FDX)
1971 ifmr->ifm_active |= IFM_FDX;
1972 else
1973 ifmr->ifm_active |= IFM_HDX;
1974
1975 } else {
1976 mii = device_get_softc(sc->nge_miibus);
1977 mii_pollstat(mii);
1978 ifmr->ifm_active = mii->mii_media_active;
1979 ifmr->ifm_status = mii->mii_media_status;
1980 }
984263bc
MD
1981}
1982
22bf5b21
JS
1983static int
1984nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1985{
22bf5b21
JS
1986 struct nge_softc *sc = ifp->if_softc;
1987 struct ifreq *ifr = (struct ifreq *) data;
1988 struct mii_data *mii;
88e7510c 1989 int error = 0;
984263bc 1990
984263bc 1991 switch(command) {
984263bc 1992 case SIOCSIFMTU:
22bf5b21 1993 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
984263bc 1994 error = EINVAL;
22bf5b21 1995 } else {
984263bc
MD
1996 ifp->if_mtu = ifr->ifr_mtu;
1997 /*
1998 * Workaround: if the MTU is larger than
1999 * 8152 (TX FIFO size minus 64 minus 18), turn off
2000 * TX checksum offloading.
2001 */
2002 if (ifr->ifr_mtu >= 8152)
2003 ifp->if_hwassist = 0;
2004 else
2005 ifp->if_hwassist = NGE_CSUM_FEATURES;
2006 }
2007 break;
2008 case SIOCSIFFLAGS:
2009 if (ifp->if_flags & IFF_UP) {
2010 if (ifp->if_flags & IFF_RUNNING &&
2011 ifp->if_flags & IFF_PROMISC &&
2012 !(sc->nge_if_flags & IFF_PROMISC)) {
2013 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2014 NGE_RXFILTCTL_ALLPHYS|
2015 NGE_RXFILTCTL_ALLMULTI);
2016 } else if (ifp->if_flags & IFF_RUNNING &&
2017 !(ifp->if_flags & IFF_PROMISC) &&
2018 sc->nge_if_flags & IFF_PROMISC) {
2019 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2020 NGE_RXFILTCTL_ALLPHYS);
2021 if (!(ifp->if_flags & IFF_ALLMULTI))
2022 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2023 NGE_RXFILTCTL_ALLMULTI);
2024 } else {
2025 ifp->if_flags &= ~IFF_RUNNING;
2026 nge_init(sc);
2027 }
2028 } else {
2029 if (ifp->if_flags & IFF_RUNNING)
2030 nge_stop(sc);
2031 }
2032 sc->nge_if_flags = ifp->if_flags;
2033 error = 0;
2034 break;
2035 case SIOCADDMULTI:
2036 case SIOCDELMULTI:
2037 nge_setmulti(sc);
2038 error = 0;
2039 break;
2040 case SIOCGIFMEDIA:
2041 case SIOCSIFMEDIA:
2042 if (sc->nge_tbi) {
2043 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2044 command);
2045 } else {
2046 mii = device_get_softc(sc->nge_miibus);
2047 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2048 command);
2049 }
2050 break;
2051 default:
c1484ba2 2052 error = ether_ioctl(ifp, command, data);
984263bc
MD
2053 break;
2054 }
984263bc
MD
2055 return(error);
2056}
2057
22bf5b21
JS
2058static void
2059nge_watchdog(struct ifnet *ifp)
984263bc 2060{
22bf5b21 2061 struct nge_softc *sc = ifp->if_softc;
984263bc
MD
2062
2063 ifp->if_oerrors++;
e3869ec7 2064 kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
984263bc
MD
2065
2066 nge_stop(sc);
2067 nge_reset(sc);
2068 ifp->if_flags &= ~IFF_RUNNING;
2069 nge_init(sc);
2070
0b193118 2071 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2072 if_devstart(ifp);
984263bc
MD
2073}
2074
2075/*
2076 * Stop the adapter and free any mbufs allocated to the
2077 * RX and TX lists.
2078 */
22bf5b21
JS
2079static void
2080nge_stop(struct nge_softc *sc)
984263bc 2081{
22bf5b21
JS
2082 struct ifnet *ifp = &sc->arpcom.ac_if;
2083 struct ifmedia_entry *ifm;
2084 struct mii_data *mii;
08bec554 2085 int i, itmp, mtmp, dtmp;
984263bc 2086
984263bc 2087 ifp->if_timer = 0;
22bf5b21 2088 if (sc->nge_tbi)
984263bc 2089 mii = NULL;
22bf5b21 2090 else
984263bc 2091 mii = device_get_softc(sc->nge_miibus);
984263bc 2092
43c4cb7e 2093 callout_stop(&sc->nge_stat_timer);
984263bc
MD
2094 CSR_WRITE_4(sc, NGE_IER, 0);
2095 CSR_WRITE_4(sc, NGE_IMR, 0);
2096 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2097 DELAY(1000);
2098 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2099 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2100
2101 /*
2102 * Isolate/power down the PHY, but leave the media selection
2103 * unchanged so that things will be put back to normal when
2104 * we bring the interface back up.
2105 */
2106 itmp = ifp->if_flags;
2107 ifp->if_flags |= IFF_UP;
2108
2109 if (sc->nge_tbi)
2110 ifm = sc->nge_ifmedia.ifm_cur;
2111 else
2112 ifm = mii->mii_media.ifm_cur;
08bec554 2113
984263bc 2114 mtmp = ifm->ifm_media;
08bec554 2115 dtmp = ifm->ifm_data;
984263bc 2116 ifm->ifm_media = IFM_ETHER|IFM_NONE;
08bec554
SZ
2117 ifm->ifm_data = MII_MEDIA_NONE;
2118
984263bc
MD
2119 if (!sc->nge_tbi)
2120 mii_mediachg(mii);
2121 ifm->ifm_media = mtmp;
08bec554 2122 ifm->ifm_data = dtmp;
984263bc
MD
2123 ifp->if_flags = itmp;
2124
2125 sc->nge_link = 0;
2126
2127 /*
2128 * Free data in the RX lists.
2129 */
2130 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2131 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2132 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2133 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2134 }
2135 }
22bf5b21 2136 bzero(&sc->nge_ldata->nge_rx_list,
984263bc
MD
2137 sizeof(sc->nge_ldata->nge_rx_list));
2138
2139 /*
2140 * Free the TX list buffers.
2141 */
2142 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2143 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2144 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2145 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2146 }
2147 }
2148
22bf5b21 2149 bzero(&sc->nge_ldata->nge_tx_list,
984263bc
MD
2150 sizeof(sc->nge_ldata->nge_tx_list));
2151
2152 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
2153}
2154
2155/*
2156 * Stop all chip I/O so that the kernel's probe routines don't
2157 * get confused by errant DMAs when rebooting.
2158 */
22bf5b21
JS
2159static void
2160nge_shutdown(device_t dev)
984263bc 2161{
22bf5b21 2162 struct nge_softc *sc = device_get_softc(dev);
78195a76 2163 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 2164
78195a76 2165 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
2166 nge_reset(sc);
2167 nge_stop(sc);
78195a76 2168 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2169}
78195a76 2170