rename amd64 architecture to x86_64
[dragonfly.git] / sys / cpu / i386 / include / ieee.h
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dc3d60d3 1/* $NetBSD: ieee.h,v 1.7 2003/10/26 21:46:46 kleink Exp $ */
88181b08 2/* $DragonFly: src/sys/cpu/i386/include/ieee.h,v 1.2 2006/11/07 17:51:21 dillon Exp $ */
dc3d60d3
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3
4/*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
11 *
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)ieee.h 8.1 (Berkeley) 6/11/93
42 */
43
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44#ifndef _CPU_IEEE_H_
45#define _CPU_IEEE_H_
46
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47/*
48 * ieee.h defines the machine-dependent layout of the machine's IEEE
49 * floating point. It does *not* define (yet?) any of the rounding
50 * mode bits, exceptions, and so forth.
51 */
52
53#include <sys/ieee754.h>
54
55#define EXT_EXPBITS 15
56#define EXT_FRACBITS 64
57
58/*
59 * struct ieee_ext is the raw storage layout of the 80-bit
60 * extended-precision type as implemented by the FPU. Per the
61 * respective ABI specifications, it is followed by a tail padding of
62 *
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63 * x86_64: 48 bits,
64 * i386: 16 bits.
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65 */
66struct ieee_ext {
67 u_int ext_fracl;
68 u_int ext_frach:31;
69 u_int ext_int:1;
70 u_int ext_exp:15;
71 u_int ext_sign:1;
72};
73
74/*
75 * Floats whose exponent is in [1..INFNAN) (of whatever type) are
76 * `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
77 * Floats whose exponent is zero are either zero (iff all fraction
78 * bits are zero) or subnormal values.
79 *
80 * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
81 * high fraction; if the bit is set, it is a `quiet NaN'.
82 */
83#define EXT_EXP_INFNAN 32767
84
85#if 0
86#define EXT_QUIETNAN (1 << 30)
87#endif
88
89/*
90 * Exponent biases.
91 */
92#define EXT_EXP_BIAS 16383
93
94/*
95 * Convenience data structures.
96 */
97union ieee_ext_u {
98 long double extu_ld;
99 struct ieee_ext extu_ext;
100};
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101
102#endif