Use mptable_iterate_entries() in mptable_pass2()
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
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27 */
28
29#include "opt_cpu.h"
984263bc 30
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31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
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34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
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39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
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45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
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51
52#include <machine/smp.h>
a9295349 53#include <machine_base/apic/apicreg.h>
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54#include <machine/atomic.h>
55#include <machine/cpufunc.h>
a9295349 56#include <machine_base/apic/mpapic.h>
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57#include <machine/psl.h>
58#include <machine/segments.h>
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59#include <machine/tss.h>
60#include <machine/specialreg.h>
61#include <machine/globaldata.h>
62
984263bc 63#include <machine/md_var.h> /* setidt() */
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64#include <machine_base/icu/icu.h> /* IPIs */
65#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 66
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67#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
68
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69#define WARMBOOT_TARGET 0
70#define WARMBOOT_OFF (KERNBASE + 0x0467)
71#define WARMBOOT_SEG (KERNBASE + 0x0469)
72
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73#define BIOS_BASE (0xf0000)
74#define BIOS_SIZE (0x10000)
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75#define BIOS_COUNT (BIOS_SIZE/4)
76
77#define CMOS_REG (0x70)
78#define CMOS_DATA (0x71)
79#define BIOS_RESET (0x0f)
80#define BIOS_WARM (0x0a)
81
82#define PROCENTRY_FLAG_EN 0x01
83#define PROCENTRY_FLAG_BP 0x02
84#define IOAPICENTRY_FLAG_EN 0x01
85
86
87/* MP Floating Pointer Structure */
88typedef struct MPFPS {
89 char signature[4];
981bebd1 90 u_int32_t pap;
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91 u_char length;
92 u_char spec_rev;
93 u_char checksum;
94 u_char mpfb1;
95 u_char mpfb2;
96 u_char mpfb3;
97 u_char mpfb4;
98 u_char mpfb5;
99} *mpfps_t;
100
101/* MP Configuration Table Header */
102typedef struct MPCTH {
103 char signature[4];
104 u_short base_table_length;
105 u_char spec_rev;
106 u_char checksum;
107 u_char oem_id[8];
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
111 u_short entry_count;
112 void *apic_address;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
115 u_char reserved;
116} *mpcth_t;
117
118
119typedef struct PROCENTRY {
120 u_char type;
121 u_char apic_id;
122 u_char apic_version;
123 u_char cpu_flags;
124 u_long cpu_signature;
125 u_long feature_flags;
126 u_long reserved1;
127 u_long reserved2;
128} *proc_entry_ptr;
129
130typedef struct BUSENTRY {
131 u_char type;
132 u_char bus_id;
133 char bus_type[6];
134} *bus_entry_ptr;
135
136typedef struct IOAPICENTRY {
137 u_char type;
138 u_char apic_id;
139 u_char apic_version;
140 u_char apic_flags;
141 void *apic_address;
142} *io_apic_entry_ptr;
143
144typedef struct INTENTRY {
145 u_char type;
146 u_char int_type;
147 u_short int_flags;
148 u_char src_bus_id;
149 u_char src_bus_irq;
150 u_char dst_apic_id;
151 u_char dst_apic_int;
152} *int_entry_ptr;
153
154/* descriptions of MP basetable entries */
155typedef struct BASETABLE_ENTRY {
156 u_char type;
157 u_char length;
158 char name[16];
159} basetable_entry;
160
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161struct mptable_pos {
162 mpfps_t mp_fps;
163 mpcth_t mp_cth;
164 vm_size_t mp_cth_mapsz;
165};
166
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167typedef int (*mptable_iter_func)(void *, const void *, int);
168
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169/*
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
173 *
984263bc 174 */
7d34994c 175#if defined(CHECK_POINTS)
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176#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178
179#define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
186
187#define CHECK_PRINT(S); \
26be20a0 188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
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189 (S), \
190 CHECK_READ(0x34), \
191 CHECK_READ(0x35), \
192 CHECK_READ(0x36), \
193 CHECK_READ(0x37), \
194 CHECK_READ(0x38), \
195 CHECK_READ(0x39));
196
197#else /* CHECK_POINTS */
198
199#define CHECK_INIT(D)
200#define CHECK_PRINT(S)
201
202#endif /* CHECK_POINTS */
203
204/*
205 * Values to send to the POST hardware.
206 */
207#define MP_BOOTADDRESS_POST 0x10
208#define MP_PROBE_POST 0x11
209#define MPTABLE_PASS1_POST 0x12
210
211#define MP_START_POST 0x13
212#define MP_ENABLE_POST 0x14
213#define MPTABLE_PASS2_POST 0x15
214
215#define START_ALL_APS_POST 0x16
216#define INSTALL_AP_TRAMP_POST 0x17
217#define START_AP_POST 0x18
218
219#define MP_ANNOUNCE_POST 0x19
220
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221static int madt_probe_test;
222TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
223
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224/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225int current_postcode;
226
227/** XXX FIXME: what system files declare these??? */
228extern struct region_descriptor r_gdt, r_idt;
229
984263bc 230int mp_naps; /* # of Applications processors */
97359a5b 231#ifdef APIC_IO
4f6a8b30 232static int mp_nbusses; /* # of busses */
984263bc 233int mp_napics; /* # of IO APICs */
97359a5b 234#endif
5a16ccc3 235static vm_offset_t cpu_apic_address;
97359a5b 236#ifdef APIC_IO
984263bc 237vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
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238u_int32_t *io_apic_versions;
239#endif
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240extern int nkpt;
241
242u_int32_t cpu_apic_versions[MAXCPU];
374133e3 243int64_t tsc0_offset;
0b698dca 244extern int64_t tsc_offsets[];
984263bc 245
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246extern u_long ebda_addr;
247
97359a5b 248#ifdef APIC_IO
8a8d5d85 249struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 250#endif
984263bc 251
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252/*
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
255 */
256int cpu_num_to_apic_id[NAPICID];
97359a5b 257#ifdef APIC_IO
984263bc 258int io_num_to_apic_id[NAPICID];
97359a5b 259#endif
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260int apic_id_to_logical[NAPICID];
261
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262/* AP uses this during bootstrap. Do not staticize. */
263char *bootSTK;
264static int bootAP;
265
266/* Hotwire a 0->4MB V==P mapping */
267extern pt_entry_t *KPTphys;
268
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269/*
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
272 * and so forth.
273 */
274
275#define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277
984263bc 278extern pt_entry_t *SMPpt;
f13b5eec 279static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
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280
281struct pcb stoppcbs[MAXCPU];
282
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283static basetable_entry basetable_entry_types[] =
284{
285 {0, 20, "Processor"},
286 {1, 8, "Bus"},
287 {2, 8, "I/O APIC"},
288 {3, 8, "I/O INT"},
289 {4, 8, "Local INT"}
290};
291
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292/*
293 * Local data and functions.
294 */
295
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296static u_int boot_address;
297static u_int base_memory;
41a01a4d 298static int mp_finish;
984263bc 299
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300static void mp_enable(u_int boot_addr);
301
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302static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
cb00b5c4 304static int mptable_probe(void);
fa058384 305static int mptable_check(vm_paddr_t);
3aba8f73 306static int mptable_search_sig(u_int32_t target, int count);
44c36320 307static int mptable_hyperthread_fixup(u_int, int);
981bebd1 308static void mptable_pass1(struct mptable_pos *);
390b18b0 309static void mptable_pass2(struct mptable_pos *);
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310static void mptable_default(int type);
311static void mptable_fix(void);
fa058384 312static int mptable_map(struct mptable_pos *, vm_paddr_t);
981bebd1 313static void mptable_unmap(struct mptable_pos *);
a0873f07 314static void mptable_lapic_enumerate(struct mptable_pos *);
322abba7 315static void mptable_lapic_default(void);
a0eaef71 316static void mptable_imcr(struct mptable_pos *);
3aba8f73 317
97359a5b 318#ifdef APIC_IO
984263bc 319static void setup_apic_irq_mapping(void);
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320static int apic_int_is_bus_type(int intr, int bus_type);
321#endif
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322static int start_all_aps(u_int boot_addr);
323static void install_ap_tramp(u_int boot_addr);
0f7a3396 324static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
5a16ccc3 325static void lapic_init(vm_offset_t);
984263bc 326
41a01a4d 327static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
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328cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
329SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
330
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331/*
332 * Calculate usable address in base memory for AP trampoline code.
333 */
334u_int
335mp_bootaddress(u_int basemem)
336{
337 POSTCODE(MP_BOOTADDRESS_POST);
338
c0c5de70 339 base_memory = basemem;
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340
341 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
342 if ((base_memory - boot_address) < bootMP_size)
343 boot_address -= 4096; /* not enough, lower by 4k */
344
345 return boot_address;
346}
347
348
349/*
350 * Look for an Intel MP spec table (ie, SMP capable hardware).
351 */
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352static int
353mptable_probe(void)
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354{
355 int x;
984263bc 356 u_int32_t target;
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357
358 /*
359 * Make sure our SMPpt[] page table is big enough to hold all the
360 * mappings we need.
361 */
362 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
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363
364 POSTCODE(MP_PROBE_POST);
365
366 /* see if EBDA exists */
1876681a 367 if (ebda_addr != 0) {
984263bc 368 /* search first 1K of EBDA */
1876681a 369 target = (u_int32_t)ebda_addr;
3aba8f73 370 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 371 return x;
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372 } else {
373 /* last 1K of base memory, effective 'top of base' passed in */
aeb48299 374 target = (u_int32_t)(base_memory - 0x400);
3aba8f73 375 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 376 return x;
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377 }
378
379 /* search the BIOS */
aeb48299 380 target = (u_int32_t)BIOS_BASE;
3aba8f73 381 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
aeb48299 382 return x;
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383
384 /* nothing found */
984263bc 385 return 0;
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386}
387
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388struct mptable_check_cbarg {
389 int cpu_count;
390 int found_bsp;
391};
392
393static int
394mptable_check_callback(void *xarg, const void *pos, int type)
395{
396 const struct PROCENTRY *ent;
397 struct mptable_check_cbarg *arg = xarg;
398
399 if (type != 0)
400 return 0;
401 ent = pos;
402
403 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
404 return 0;
405 arg->cpu_count++;
406
407 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
408 if (arg->found_bsp) {
409 kprintf("more than one BSP in base MP table\n");
410 return EINVAL;
411 }
412 arg->found_bsp = 1;
413 }
414 return 0;
415}
416
417static int
418mptable_check(vm_paddr_t mpfps_paddr)
419{
420 struct mptable_pos mpt;
421 struct mptable_check_cbarg arg;
422 mpcth_t cth;
423 int error;
424
425 if (mpfps_paddr == 0)
426 return EOPNOTSUPP;
427
428 error = mptable_map(&mpt, mpfps_paddr);
429 if (error)
430 return error;
431
432 if (mpt.mp_fps->mpfb1 != 0)
433 goto done;
434
435 error = EINVAL;
436
437 cth = mpt.mp_cth;
438 if (cth == NULL)
439 goto done;
440 if (cth->apic_address == 0)
441 goto done;
442
443 bzero(&arg, sizeof(arg));
444 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
445 if (!error) {
446 if (arg.cpu_count == 0) {
447 kprintf("MP table contains no processor entries\n");
448 error = EINVAL;
449 } else if (!arg.found_bsp) {
450 kprintf("MP table does not contains BSP entry\n");
451 error = EINVAL;
452 }
453 }
454done:
455 mptable_unmap(&mpt);
456 return error;
457}
458
459static int
460mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
461{
462 int count, total_size;
463 const void *position;
464
465 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
466 total_size = cth->base_table_length - sizeof(struct MPCTH);
467 position = (const uint8_t *)cth + sizeof(struct MPCTH);
468 count = cth->entry_count;
469
470 while (count--) {
471 int type, error;
472
473 KKASSERT(total_size >= 0);
474 if (total_size == 0) {
475 kprintf("invalid base MP table, "
476 "entry count and length mismatch\n");
477 return EINVAL;
478 }
479
480 type = *(const uint8_t *)position;
481 switch (type) {
482 case 0: /* processor_entry */
483 case 1: /* bus_entry */
484 case 2: /* io_apic_entry */
485 case 3: /* int_entry */
486 case 4: /* int_entry */
487 break;
488 default:
489 kprintf("unknown base MP table entry type %d\n", type);
490 return EINVAL;
491 }
492
493 if (total_size < basetable_entry_types[type].length) {
494 kprintf("invalid base MP table length, "
495 "does not contain all entries\n");
496 return EINVAL;
497 }
498 total_size -= basetable_entry_types[type].length;
499
500 error = func(arg, position, type);
501 if (error)
502 return error;
503
504 position = (const uint8_t *)position +
505 basetable_entry_types[type].length;
506 }
507 return 0;
508}
509
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510
511/*
512 * Startup the SMP processors.
513 */
514void
515mp_start(void)
516{
517 POSTCODE(MP_START_POST);
50bc991e 518 mp_enable(boot_address);
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519}
520
521
522/*
523 * Print various information about the SMP system hardware and setup.
524 */
525void
526mp_announce(void)
527{
528 int x;
529
530 POSTCODE(MP_ANNOUNCE_POST);
531
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532 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
533 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
534 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
535 kprintf(", at 0x%08x\n", cpu_apic_address);
984263bc 536 for (x = 1; x <= mp_naps; ++x) {
26be20a0
SW
537 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
538 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
539 kprintf(", at 0x%08x\n", cpu_apic_address);
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540 }
541
542#if defined(APIC_IO)
543 for (x = 0; x < mp_napics; ++x) {
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544 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
545 kprintf(", version: 0x%08x", io_apic_versions[x]);
546 kprintf(", at 0x%08x\n", io_apic_address[x]);
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547 }
548#else
26be20a0 549 kprintf(" Warning: APIC I/O disabled\n");
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550#endif /* APIC_IO */
551}
552
553/*
554 * AP cpu's call this to sync up protected mode.
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555 *
556 * WARNING! We must ensure that the cpu is sufficiently initialized to
557 * be able to use to the FP for our optimized bzero/bcopy code before
558 * we enter more mainstream C code.
a44bdeec
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559 *
560 * WARNING! %fs is not set up on entry. This routine sets up %fs.
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561 */
562void
563init_secondary(void)
564{
565 int gsel_tss;
566 int x, myid = bootAP;
567 u_int cr0;
8a8d5d85 568 struct mdglobaldata *md;
0f7a3396 569 struct privatespace *ps;
984263bc 570
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571 ps = &CPU_prvspace[myid];
572
573 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 574 gdt_segs[GPROC0_SEL].ssd_base =
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575 (int) &ps->mdglobaldata.gd_common_tss;
576 ps->mdglobaldata.mi.gd_prvspace = ps;
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577
578 for (x = 0; x < NGDT; x++) {
579 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
580 }
581
582 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
583 r_gdt.rd_base = (int) &gdt[myid * NGDT];
584 lgdt(&r_gdt); /* does magic intra-segment return */
585
586 lidt(&r_idt);
587
588 lldt(_default_ldt);
7b95be2a 589 mdcpu->gd_currentldt = _default_ldt;
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590
591 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
592 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 593
0f7a3396 594 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
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595
596 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
597 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
598 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
599 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
600 md->gd_common_tssd = *md->gd_tss_gdt;
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601 ltr(gsel_tss);
602
603 /*
604 * Set to a known state:
605 * Set by mpboot.s: CR0_PG, CR0_PE
606 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
607 */
608 cr0 = rcr0();
609 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
610 load_cr0(cr0);
7160572f 611 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 612
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613 /* set up CPU registers and state */
614 cpu_setregs();
615
616 /* set up FPU state on the AP */
617 npxinit(__INITIAL_NPXCW__);
618
619 /* set up SSE registers */
620 enable_sse();
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621}
622
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623/*******************************************************************
624 * local functions and data
625 */
626
627/*
628 * start the SMP system
629 */
630static void
631mp_enable(u_int boot_addr)
632{
984263bc
MD
633#if defined(APIC_IO)
634 int apic;
635 u_int ux;
636#endif /* APIC_IO */
981bebd1 637 vm_paddr_t mpfps_paddr;
984263bc
MD
638
639 POSTCODE(MP_ENABLE_POST);
640
fa058384 641 if (madt_probe_test) {
a26bbcd5 642 mpfps_paddr = 0;
fa058384 643 } else {
a26bbcd5 644 mpfps_paddr = mptable_probe();
fa058384
SZ
645 if (mptable_check(mpfps_paddr))
646 mpfps_paddr = 0;
647 }
85fd9f87 648
a26bbcd5 649 if (mpfps_paddr) {
223bf214
SZ
650 struct mptable_pos mpt;
651
a26bbcd5 652 mptable_map(&mpt, mpfps_paddr);
0f85efa2 653
a0873f07
SZ
654 mptable_lapic_enumerate(&mpt);
655
a0eaef71
SZ
656 mptable_imcr(&mpt);
657
a26bbcd5 658 /*
a26bbcd5
SZ
659 * Examine the MP table for needed info
660 */
c4717d5c 661 mptable_pass1(&mpt);
390b18b0 662 mptable_pass2(&mpt);
f9c3b04f 663
a26bbcd5 664 mptable_unmap(&mpt);
984263bc 665
a26bbcd5
SZ
666 /* Post scan cleanup */
667 mptable_fix();
668 } else {
223bf214 669 vm_paddr_t madt_paddr;
5a16ccc3 670 vm_offset_t lapic_addr;
223bf214
SZ
671 int bsp_apic_id;
672
673 madt_paddr = madt_probe();
674 if (madt_paddr == 0)
a26bbcd5
SZ
675 panic("mp_enable: madt_probe failed\n");
676
5a16ccc3
SZ
677 lapic_addr = madt_pass1(madt_paddr);
678 if (lapic_addr == 0)
a26bbcd5 679 panic("mp_enable: no local apic (madt)!\n");
984263bc 680
5a16ccc3 681 lapic_init(lapic_addr);
223bf214 682
bc021528 683 bsp_apic_id = APIC_ID(lapic.id);
223bf214
SZ
684 if (madt_pass2(madt_paddr, bsp_apic_id))
685 panic("mp_enable: madt_pass2 failed\n");
a26bbcd5 686 }
984263bc
MD
687
688#if defined(APIC_IO)
689
97359a5b
MD
690 setup_apic_irq_mapping();
691
984263bc
MD
692 /* fill the LOGICAL io_apic_versions table */
693 for (apic = 0; apic < mp_napics; ++apic) {
694 ux = io_apic_read(apic, IOAPIC_VER);
695 io_apic_versions[apic] = ux;
696 io_apic_set_id(apic, IO_TO_ID(apic));
697 }
698
699 /* program each IO APIC in the system */
700 for (apic = 0; apic < mp_napics; ++apic)
701 if (io_apic_setup(apic) < 0)
702 panic("IO APIC setup failure");
703
97359a5b
MD
704#endif /* APIC_IO */
705
706 /*
707 * These are required for SMP operation
708 */
709
984263bc
MD
710 /* install a 'Spurious INTerrupt' vector */
711 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
712 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
713
714 /* install an inter-CPU IPI for TLB invalidation */
715 setidt(XINVLTLB_OFFSET, Xinvltlb,
716 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
717
96728c05
MD
718 /* install an inter-CPU IPI for IPIQ messaging */
719 setidt(XIPIQ_OFFSET, Xipiq,
720 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ
721
722 /* install a timer vector */
723 setidt(XTIMER_OFFSET, Xtimer,
724 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 725
984263bc
MD
726 /* install an inter-CPU IPI for CPU stop/restart */
727 setidt(XCPUSTOP_OFFSET, Xcpustop,
728 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
729
984263bc
MD
730 /* start each Application Processor */
731 start_all_aps(boot_addr);
732}
733
734
735/*
736 * look for the MP spec signature
737 */
738
739/* string defined by the Intel MP Spec as identifying the MP table */
740#define MP_SIG 0x5f504d5f /* _MP_ */
741#define NEXT(X) ((X) += 4)
742static int
3aba8f73 743mptable_search_sig(u_int32_t target, int count)
984263bc 744{
0f85efa2
SZ
745 vm_size_t map_size;
746 u_int32_t *addr;
747 int x, ret;
984263bc 748
aeb48299
SZ
749 KKASSERT(target != 0);
750
0f85efa2
SZ
751 map_size = count * sizeof(u_int32_t);
752 addr = pmap_mapdev((vm_paddr_t)target, map_size);
984263bc 753
aeb48299 754 ret = 0;
0f85efa2
SZ
755 for (x = 0; x < count; NEXT(x)) {
756 if (addr[x] == MP_SIG) {
757 /* make array index a byte index */
758 ret = target + (x * sizeof(u_int32_t));
759 break;
760 }
761 }
aeb48299 762
0f85efa2
SZ
763 pmap_unmapdev((vm_offset_t)addr, map_size);
764 return ret;
984263bc
MD
765}
766
767
984263bc
MD
768typedef struct BUSDATA {
769 u_char bus_id;
770 enum busTypes bus_type;
771} bus_datum;
772
773typedef struct INTDATA {
774 u_char int_type;
775 u_short int_flags;
776 u_char src_bus_id;
777 u_char src_bus_irq;
778 u_char dst_apic_id;
779 u_char dst_apic_int;
780 u_char int_vector;
781} io_int, local_int;
782
783typedef struct BUSTYPENAME {
784 u_char type;
785 char name[7];
786} bus_type_name;
787
788static bus_type_name bus_type_table[] =
789{
790 {CBUS, "CBUS"},
791 {CBUSII, "CBUSII"},
792 {EISA, "EISA"},
793 {MCA, "MCA"},
794 {UNKNOWN_BUSTYPE, "---"},
795 {ISA, "ISA"},
796 {MCA, "MCA"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
802 {PCI, "PCI"},
803 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {XPRESS, "XPRESS"},
808 {UNKNOWN_BUSTYPE, "---"}
809};
810/* from MP spec v1.4, table 5-1 */
811static int default_data[7][5] =
812{
813/* nbus, id0, type0, id1, type1 */
814 {1, 0, ISA, 255, 255},
815 {1, 0, EISA, 255, 255},
816 {1, 0, EISA, 255, 255},
817 {1, 0, MCA, 255, 255},
818 {2, 0, ISA, 1, PCI},
819 {2, 0, EISA, 1, PCI},
820 {2, 0, MCA, 1, PCI}
821};
822
823
4f6a8b30
SZ
824#ifdef APIC_IO
825
984263bc
MD
826/* the bus data */
827static bus_datum *bus_data;
828
829/* the IO INT data, one entry per possible APIC INTerrupt */
830static io_int *io_apic_ints;
984263bc 831static int nintrs;
4f6a8b30 832
97359a5b 833#endif
984263bc 834
a0873f07 835static int processor_entry (const struct PROCENTRY *entry, int cpu);
97359a5b 836#ifdef APIC_IO
c4717d5c
SZ
837static int bus_entry (const struct BUSENTRY *entry, int bus);
838static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
839static int int_entry (const struct INTENTRY *entry, int intr);
97359a5b 840#endif
3ae0cd58 841static int lookup_bus_type (char *name);
984263bc 842
8658b5be
SZ
843#ifdef APIC_IO
844
845static int
846mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
847{
848 const struct IOAPICENTRY *ioapic_ent;
849
850 switch (type) {
851 case 1: /* bus_entry */
852 ++mp_nbusses;
853 break;
854
855 case 2: /* io_apic_entry */
856 ioapic_ent = pos;
857 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
858 io_apic_address[mp_napics++] =
859 (vm_offset_t)ioapic_ent->apic_address;
860 }
861 break;
862
863 case 3: /* int_entry */
864 ++nintrs;
865 break;
866 }
867 return 0;
868}
869
870#endif /* APIC_IO */
984263bc
MD
871
872/*
873 * 1st pass on motherboard's Intel MP specification table.
874 *
984263bc 875 * determines:
984263bc 876 * io_apic_address[N]
984263bc
MD
877 * mp_nbusses
878 * mp_napics
879 * nintrs
880 */
881static void
981bebd1 882mptable_pass1(struct mptable_pos *mpt)
984263bc 883{
97359a5b 884#ifdef APIC_IO
981bebd1 885 mpfps_t fps;
8658b5be 886 int x;
984263bc
MD
887
888 POSTCODE(MPTABLE_PASS1_POST);
889
981bebd1
SZ
890 fps = mpt->mp_fps;
891 KKASSERT(fps != NULL);
f9c3b04f 892
984263bc 893 /* clear various tables */
8658b5be 894 for (x = 0; x < NAPICID; ++x)
984263bc 895 io_apic_address[x] = ~0; /* IO APIC address table */
984263bc 896
4f6a8b30 897 mp_nbusses = 0;
984263bc
MD
898 mp_napics = 0;
899 nintrs = 0;
984263bc
MD
900
901 /* check for use of 'default' configuration */
981bebd1 902 if (fps->mpfb1 != 0) {
984263bc 903 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
4f6a8b30 904 mp_nbusses = default_data[fps->mpfb1 - 1][0];
984263bc
MD
905 mp_napics = 1;
906 nintrs = 16;
8658b5be
SZ
907 } else {
908 int error;
909
910 error = mptable_iterate_entries(mpt->mp_cth,
911 mptable_ioapic_pass1_callback, NULL);
912 if (error)
913 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
984263bc 914 }
8658b5be 915#endif /* APIC_IO */
984263bc
MD
916}
917
c4717d5c
SZ
918#ifdef APIC_IO
919
920struct mptable_ioapic2_cbarg {
921 int bus;
922 int apic;
923 int intr;
924};
925
926static int
927mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
928{
929 struct mptable_ioapic2_cbarg *arg = xarg;
930
931 switch (type) {
932 case 1:
933 if (bus_entry(pos, arg->bus))
934 ++arg->bus;
935 break;
936
937 case 2:
938 if (io_apic_entry(pos, arg->apic))
939 ++arg->apic;
940 break;
941
942 case 3:
943 if (int_entry(pos, arg->intr))
944 ++arg->intr;
945 break;
946 }
947 return 0;
948}
949
950#endif /* APIC_IO */
984263bc
MD
951
952/*
953 * 2nd pass on motherboard's Intel MP specification table.
954 *
955 * sets:
984263bc 956 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
984263bc
MD
957 * IO_TO_ID(N), logical IO to APIC ID table
958 * bus_data[N]
959 * io_apic_ints[N]
960 */
390b18b0 961static void
981bebd1 962mptable_pass2(struct mptable_pos *mpt)
984263bc 963{
c4717d5c
SZ
964#ifdef APIC_IO
965 struct mptable_ioapic2_cbarg arg;
981bebd1 966 mpfps_t fps;
c4717d5c 967 int error, x;
984263bc
MD
968
969 POSTCODE(MPTABLE_PASS2_POST);
970
981bebd1
SZ
971 fps = mpt->mp_fps;
972 KKASSERT(fps != NULL);
973
984263bc
MD
974 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
975 M_DEVBUF, M_WAITOK);
976 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 977 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 978 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc
MD
979 M_DEVBUF, M_WAITOK);
980 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
981 M_DEVBUF, M_WAITOK);
982
c4717d5c
SZ
983 for (x = 0; x < mp_napics; x++)
984 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
984263bc
MD
985
986 /* clear various tables */
987 for (x = 0; x < NAPICID; ++x) {
97359a5b 988 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc
MD
989 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
990 }
991
992 /* clear bus data table */
993 for (x = 0; x < mp_nbusses; ++x)
994 bus_data[x].bus_id = 0xff;
995
996 /* clear IO APIC INT table */
997 for (x = 0; x < (nintrs + 1); ++x) {
998 io_apic_ints[x].int_type = 0xff;
999 io_apic_ints[x].int_vector = 0xff;
1000 }
1001
984263bc 1002 /* check for use of 'default' configuration */
390b18b0
SZ
1003 if (fps->mpfb1 != 0) {
1004 mptable_default(fps->mpfb1);
1005 return;
1006 }
984263bc 1007
c4717d5c
SZ
1008 bzero(&arg, sizeof(arg));
1009 error = mptable_iterate_entries(mpt->mp_cth,
1010 mptable_ioapic_pass2_callback, &arg);
1011 if (error)
1012 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
97359a5b 1013#endif
984263bc
MD
1014}
1015
984263bc
MD
1016/*
1017 * Check if we should perform a hyperthreading "fix-up" to
1018 * enumerate any logical CPU's that aren't already listed
1019 * in the table.
1020 *
1021 * XXX: We assume that all of the physical CPUs in the
1022 * system have the same number of logical CPUs.
1023 *
1024 * XXX: We assume that APIC ID's are allocated such that
1025 * the APIC ID's for a physical processor are aligned
1026 * with the number of logical CPU's in the processor.
1027 */
44c36320
SZ
1028static int
1029mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
984263bc 1030{
44c36320 1031 int i, id, lcpus_max, logical_cpus;
984263bc 1032
984263bc 1033 if ((cpu_feature & CPUID_HTT) == 0)
44c36320 1034 return 0;
7ea07fd2
SZ
1035
1036 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1037 if (lcpus_max <= 1)
44c36320 1038 return 0;
984263bc 1039
7ea07fd2
SZ
1040 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1041 /*
1042 * INSTRUCTION SET REFERENCE, A-M (#253666)
1043 * Page 3-181, Table 3-20
1044 * "The nearest power-of-2 integer that is not smaller
1045 * than EBX[23:16] is the number of unique initial APIC
1046 * IDs reserved for addressing different logical
1047 * processors in a physical package."
1048 */
1049 for (i = 0; ; ++i) {
1050 if ((1 << i) >= lcpus_max) {
1051 lcpus_max = 1 << i;
1052 break;
1053 }
1054 }
1055 }
1056
44c36320
SZ
1057 KKASSERT(cpu_count != 0);
1058 if (cpu_count == lcpus_max) {
7ea07fd2 1059 /* We have nothing to fix */
44c36320
SZ
1060 return 0;
1061 } else if (cpu_count == 1) {
7ea07fd2
SZ
1062 /* XXX this may be incorrect */
1063 logical_cpus = lcpus_max;
1064 } else {
1065 int cur, prev, dist;
1066
1067 /*
1068 * Calculate the distances between two nearest
1069 * APIC IDs. If all such distances are same,
1070 * then it is the number of missing cpus that
1071 * we are going to fill later.
1072 */
1073 dist = cur = prev = -1;
1074 for (id = 0; id < MAXCPU; ++id) {
1075 if ((id_mask & 1 << id) == 0)
1076 continue;
1077
1078 cur = id;
1079 if (prev >= 0) {
1080 int new_dist = cur - prev;
1081
1082 if (dist < 0)
1083 dist = new_dist;
1084
1085 /*
1086 * Make sure that all distances
1087 * between two nearest APIC IDs
1088 * are same.
1089 */
1090 if (dist != new_dist)
44c36320 1091 return 0;
7ea07fd2
SZ
1092 }
1093 prev = cur;
1094 }
1095 if (dist == 1)
44c36320 1096 return 0;
7ea07fd2
SZ
1097
1098 /* Must be power of 2 */
1099 if (dist & (dist - 1))
44c36320 1100 return 0;
7ea07fd2
SZ
1101
1102 /* Can't exceed CPU package capacity */
1103 if (dist > lcpus_max)
1104 logical_cpus = lcpus_max;
1105 else
1106 logical_cpus = dist;
1107 }
1108
984263bc
MD
1109 /*
1110 * For each APIC ID of a CPU that is set in the mask,
1111 * scan the other candidate APIC ID's for this
1112 * physical processor. If any of those ID's are
1113 * already in the table, then kill the fixup.
1114 */
7ea07fd2 1115 for (id = 0; id < MAXCPU; id++) {
984263bc
MD
1116 if ((id_mask & 1 << id) == 0)
1117 continue;
1118 /* First, make sure we are on a logical_cpus boundary. */
1119 if (id % logical_cpus != 0)
44c36320 1120 return 0;
984263bc
MD
1121 for (i = id + 1; i < id + logical_cpus; i++)
1122 if ((id_mask & 1 << i) != 0)
44c36320 1123 return 0;
984263bc 1124 }
44c36320 1125 return logical_cpus;
984263bc 1126}
984263bc 1127
fa058384 1128static int
981bebd1
SZ
1129mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1130{
1131 mpfps_t fps = NULL;
1132 mpcth_t cth = NULL;
1133 vm_size_t cth_mapsz = 0;
1134
fa058384
SZ
1135 bzero(mpt, sizeof(*mpt));
1136
981bebd1
SZ
1137 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1138 if (fps->pap != 0) {
1139 /*
1140 * Map configuration table header to get
1141 * the base table size
1142 */
1143 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1144 cth_mapsz = cth->base_table_length;
1145 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1146
fa058384
SZ
1147 if (cth_mapsz < sizeof(*cth)) {
1148 kprintf("invalid base MP table length %d\n",
1149 (int)cth_mapsz);
1150 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1151 return EINVAL;
1152 }
1153
981bebd1
SZ
1154 /*
1155 * Map the base table
1156 */
1157 cth = pmap_mapdev(fps->pap, cth_mapsz);
1158 }
1159
1160 mpt->mp_fps = fps;
1161 mpt->mp_cth = cth;
1162 mpt->mp_cth_mapsz = cth_mapsz;
fa058384
SZ
1163
1164 return 0;
981bebd1
SZ
1165}
1166
1167static void
1168mptable_unmap(struct mptable_pos *mpt)
1169{
1170 if (mpt->mp_cth != NULL) {
1171 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1172 mpt->mp_cth = NULL;
1173 mpt->mp_cth_mapsz = 0;
1174 }
1175 if (mpt->mp_fps != NULL) {
1176 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1177 mpt->mp_fps = NULL;
1178 }
1179}
1180
97359a5b
MD
1181#ifdef APIC_IO
1182
984263bc
MD
1183void
1184assign_apic_irq(int apic, int intpin, int irq)
1185{
1186 int x;
1187
1188 if (int_to_apicintpin[irq].ioapic != -1)
1189 panic("assign_apic_irq: inconsistent table");
1190
1191 int_to_apicintpin[irq].ioapic = apic;
1192 int_to_apicintpin[irq].int_pin = intpin;
1193 int_to_apicintpin[irq].apic_address = ioapic[apic];
1194 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1195
1196 for (x = 0; x < nintrs; x++) {
1197 if ((io_apic_ints[x].int_type == 0 ||
1198 io_apic_ints[x].int_type == 3) &&
1199 io_apic_ints[x].int_vector == 0xff &&
1200 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1201 io_apic_ints[x].dst_apic_int == intpin)
1202 io_apic_ints[x].int_vector = irq;
1203 }
1204}
1205
1206void
1207revoke_apic_irq(int irq)
1208{
1209 int x;
1210 int oldapic;
1211 int oldintpin;
1212
1213 if (int_to_apicintpin[irq].ioapic == -1)
1214 panic("revoke_apic_irq: inconsistent table");
1215
1216 oldapic = int_to_apicintpin[irq].ioapic;
1217 oldintpin = int_to_apicintpin[irq].int_pin;
1218
1219 int_to_apicintpin[irq].ioapic = -1;
1220 int_to_apicintpin[irq].int_pin = 0;
1221 int_to_apicintpin[irq].apic_address = NULL;
1222 int_to_apicintpin[irq].redirindex = 0;
1223
1224 for (x = 0; x < nintrs; x++) {
1225 if ((io_apic_ints[x].int_type == 0 ||
1226 io_apic_ints[x].int_type == 3) &&
1227 io_apic_ints[x].int_vector != 0xff &&
1228 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1229 io_apic_ints[x].dst_apic_int == oldintpin)
1230 io_apic_ints[x].int_vector = 0xff;
1231 }
1232}
1233
1439c090
MD
1234/*
1235 * Allocate an IRQ
1236 */
984263bc
MD
1237static void
1238allocate_apic_irq(int intr)
1239{
1240 int apic;
1241 int intpin;
1242 int irq;
1243
1244 if (io_apic_ints[intr].int_vector != 0xff)
1245 return; /* Interrupt handler already assigned */
1246
1247 if (io_apic_ints[intr].int_type != 0 &&
1248 (io_apic_ints[intr].int_type != 3 ||
1249 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1250 io_apic_ints[intr].dst_apic_int == 0)))
1251 return; /* Not INT or ExtInt on != (0, 0) */
1252
1253 irq = 0;
1254 while (irq < APIC_INTMAPSIZE &&
1255 int_to_apicintpin[irq].ioapic != -1)
1256 irq++;
1257
1258 if (irq >= APIC_INTMAPSIZE)
1259 return; /* No free interrupt handlers */
1260
1261 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1262 intpin = io_apic_ints[intr].dst_apic_int;
1263
1264 assign_apic_irq(apic, intpin, irq);
1265 io_apic_setup_intpin(apic, intpin);
1266}
1267
1268
1269static void
1270swap_apic_id(int apic, int oldid, int newid)
1271{
1272 int x;
1273 int oapic;
1274
1275
1276 if (oldid == newid)
1277 return; /* Nothing to do */
1278
26be20a0 1279 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD
1280 apic, oldid, newid);
1281
1282 /* Swap physical APIC IDs in interrupt entries */
1283 for (x = 0; x < nintrs; x++) {
1284 if (io_apic_ints[x].dst_apic_id == oldid)
1285 io_apic_ints[x].dst_apic_id = newid;
1286 else if (io_apic_ints[x].dst_apic_id == newid)
1287 io_apic_ints[x].dst_apic_id = oldid;
1288 }
1289
1290 /* Swap physical APIC IDs in IO_TO_ID mappings */
1291 for (oapic = 0; oapic < mp_napics; oapic++)
1292 if (IO_TO_ID(oapic) == newid)
1293 break;
1294
1295 if (oapic < mp_napics) {
26be20a0 1296 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD
1297 "%d to %d in MP table\n",
1298 oapic, newid, oldid);
1299 IO_TO_ID(oapic) = oldid;
1300 }
1301 IO_TO_ID(apic) = newid;
1302}
1303
1304
1305static void
1306fix_id_to_io_mapping(void)
1307{
1308 int x;
1309
1310 for (x = 0; x < NAPICID; x++)
1311 ID_TO_IO(x) = -1;
1312
1313 for (x = 0; x <= mp_naps; x++)
1314 if (CPU_TO_ID(x) < NAPICID)
1315 ID_TO_IO(CPU_TO_ID(x)) = x;
1316
1317 for (x = 0; x < mp_napics; x++)
1318 if (IO_TO_ID(x) < NAPICID)
1319 ID_TO_IO(IO_TO_ID(x)) = x;
1320}
1321
1322
1323static int
1324first_free_apic_id(void)
1325{
1326 int freeid, x;
1327
1328 for (freeid = 0; freeid < NAPICID; freeid++) {
1329 for (x = 0; x <= mp_naps; x++)
1330 if (CPU_TO_ID(x) == freeid)
1331 break;
1332 if (x <= mp_naps)
1333 continue;
1334 for (x = 0; x < mp_napics; x++)
1335 if (IO_TO_ID(x) == freeid)
1336 break;
1337 if (x < mp_napics)
1338 continue;
1339 return freeid;
1340 }
1341 return freeid;
1342}
1343
1344
1345static int
1346io_apic_id_acceptable(int apic, int id)
1347{
1348 int cpu; /* Logical CPU number */
1349 int oapic; /* Logical IO APIC number for other IO APIC */
1350
1351 if (id >= NAPICID)
1352 return 0; /* Out of range */
1353
1354 for (cpu = 0; cpu <= mp_naps; cpu++)
1355 if (CPU_TO_ID(cpu) == id)
1356 return 0; /* Conflict with CPU */
1357
1358 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1359 if (IO_TO_ID(oapic) == id)
1360 return 0; /* Conflict with other APIC */
1361
1362 return 1; /* ID is acceptable for IO APIC */
1363}
1364
1439c090
MD
1365static
1366io_int *
1367io_apic_find_int_entry(int apic, int pin)
1368{
1369 int x;
1370
1371 /* search each of the possible INTerrupt sources */
1372 for (x = 0; x < nintrs; ++x) {
1373 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1374 (pin == io_apic_ints[x].dst_apic_int))
1375 return (&io_apic_ints[x]);
1376 }
1377 return NULL;
1378}
1379
97359a5b 1380#endif
984263bc
MD
1381
1382/*
1383 * parse an Intel MP specification table
1384 */
1385static void
3aba8f73 1386mptable_fix(void)
984263bc 1387{
97359a5b 1388#ifdef APIC_IO
4f6a8b30 1389 int x;
984263bc 1390 int id;
984263bc
MD
1391 int apic; /* IO APIC unit number */
1392 int freeid; /* Free physical APIC ID */
1393 int physid; /* Current physical IO APIC ID */
1439c090 1394 io_int *io14;
97359a5b
MD
1395 int bus_0 = 0; /* Stop GCC warning */
1396 int bus_pci = 0; /* Stop GCC warning */
1397 int num_pci_bus;
984263bc
MD
1398
1399 /*
1400 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1401 * did it wrong. The MP spec says that when more than 1 PCI bus
1402 * exists the BIOS must begin with bus entries for the PCI bus and use
1403 * actual PCI bus numbering. This implies that when only 1 PCI bus
1404 * exists the BIOS can choose to ignore this ordering, and indeed many
1405 * MP motherboards do ignore it. This causes a problem when the PCI
1406 * sub-system makes requests of the MP sub-system based on PCI bus
1407 * numbers. So here we look for the situation and renumber the
1408 * busses and associated INTs in an effort to "make it right".
1409 */
1410
1411 /* find bus 0, PCI bus, count the number of PCI busses */
1412 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1413 if (bus_data[x].bus_id == 0) {
1414 bus_0 = x;
1415 }
1416 if (bus_data[x].bus_type == PCI) {
1417 ++num_pci_bus;
1418 bus_pci = x;
1419 }
1420 }
1421 /*
1422 * bus_0 == slot of bus with ID of 0
1423 * bus_pci == slot of last PCI bus encountered
1424 */
1425
1426 /* check the 1 PCI bus case for sanity */
1427 /* if it is number 0 all is well */
1428 if (num_pci_bus == 1 &&
1429 bus_data[bus_pci].bus_id != 0) {
1430
1431 /* mis-numbered, swap with whichever bus uses slot 0 */
1432
1433 /* swap the bus entry types */
1434 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1435 bus_data[bus_0].bus_type = PCI;
1436
1437 /* swap each relavant INTerrupt entry */
1438 id = bus_data[bus_pci].bus_id;
1439 for (x = 0; x < nintrs; ++x) {
1440 if (io_apic_ints[x].src_bus_id == id) {
1441 io_apic_ints[x].src_bus_id = 0;
1442 }
1443 else if (io_apic_ints[x].src_bus_id == 0) {
1444 io_apic_ints[x].src_bus_id = id;
1445 }
1446 }
1447 }
1448
1449 /* Assign IO APIC IDs.
1450 *
1451 * First try the existing ID. If a conflict is detected, try
1452 * the ID in the MP table. If a conflict is still detected, find
1453 * a free id.
1454 *
1455 * We cannot use the ID_TO_IO table before all conflicts has been
1456 * resolved and the table has been corrected.
1457 */
1458 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1459
1460 /* First try to use the value set by the BIOS */
1461 physid = io_apic_get_id(apic);
1462 if (io_apic_id_acceptable(apic, physid)) {
1463 if (IO_TO_ID(apic) != physid)
1464 swap_apic_id(apic, IO_TO_ID(apic), physid);
1465 continue;
1466 }
1467
1468 /* Then check if the value in the MP table is acceptable */
1469 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1470 continue;
1471
1472 /* Last resort, find a free APIC ID and use it */
1473 freeid = first_free_apic_id();
1474 if (freeid >= NAPICID)
1475 panic("No free physical APIC IDs found");
1476
1477 if (io_apic_id_acceptable(apic, freeid)) {
1478 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1479 continue;
1480 }
1481 panic("Free physical APIC ID not usable");
1482 }
1483 fix_id_to_io_mapping();
1484
1485 /* detect and fix broken Compaq MP table */
1486 if (apic_int_type(0, 0) == -1) {
26be20a0 1487 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD
1488 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1489 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1490 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1491 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1492 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1493 nintrs++;
ad12f88c 1494 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1495 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP
1496 for (x = 0; x < nintrs; ++x)
1497 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1498 (0 == io_apic_ints[x].dst_apic_int)) {
1499 io_apic_ints[x].int_type = 3;
1500 io_apic_ints[x].int_vector = 0xff;
1501 break;
1502 }
984263bc 1503 }
1439c090
MD
1504
1505 /*
1506 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1507 * controllers universally come in pairs. If IRQ 14 is specified
1508 * as an ISA interrupt, then IRQ 15 had better be too.
1509 *
1510 * [ Shuttle XPC / AMD Athlon X2 ]
1511 * The MPTable is missing an entry for IRQ 15. Note that the
1512 * ACPI table has an entry for both 14 and 15.
1513 */
1514 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1515 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD
1516 io14 = io_apic_find_int_entry(0, 14);
1517 io_apic_ints[nintrs] = *io14;
1518 io_apic_ints[nintrs].src_bus_irq = 15;
1519 io_apic_ints[nintrs].dst_apic_int = 15;
1520 nintrs++;
1521 }
97359a5b 1522#endif
984263bc
MD
1523}
1524
97359a5b 1525#ifdef APIC_IO
984263bc
MD
1526
1527/* Assign low level interrupt handlers */
1528static void
1529setup_apic_irq_mapping(void)
1530{
1531 int x;
1532 int int_vector;
1533
1534 /* Clear array */
1535 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1536 int_to_apicintpin[x].ioapic = -1;
1537 int_to_apicintpin[x].int_pin = 0;
1538 int_to_apicintpin[x].apic_address = NULL;
1539 int_to_apicintpin[x].redirindex = 0;
1540 }
1541
1542 /* First assign ISA/EISA interrupts */
1543 for (x = 0; x < nintrs; x++) {
1544 int_vector = io_apic_ints[x].src_bus_irq;
1545 if (int_vector < APIC_INTMAPSIZE &&
1546 io_apic_ints[x].int_vector == 0xff &&
1547 int_to_apicintpin[int_vector].ioapic == -1 &&
1548 (apic_int_is_bus_type(x, ISA) ||
1549 apic_int_is_bus_type(x, EISA)) &&
1550 io_apic_ints[x].int_type == 0) {
1551 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1552 io_apic_ints[x].dst_apic_int,
1553 int_vector);
1554 }
1555 }
1556
1557 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1558 for (x = 0; x < nintrs; x++) {
1559 if (io_apic_ints[x].dst_apic_int == 0 &&
1560 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1561 io_apic_ints[x].int_vector == 0xff &&
1562 int_to_apicintpin[0].ioapic == -1 &&
1563 io_apic_ints[x].int_type == 3) {
1564 assign_apic_irq(0, 0, 0);
1565 break;
1566 }
1567 }
1568 /* PCI interrupt assignment is deferred */
1569}
1570
97359a5b 1571#endif
984263bc 1572
a9112655
SZ
1573void
1574mp_set_cpuids(int cpu_id, int apic_id)
1575{
1576 CPU_TO_ID(cpu_id) = apic_id;
1577 ID_TO_CPU(apic_id) = cpu_id;
1578}
1579
984263bc 1580static int
a0873f07 1581processor_entry(const struct PROCENTRY *entry, int cpu)
984263bc 1582{
bd8aa7e2
SZ
1583 KKASSERT(cpu > 0);
1584
984263bc
MD
1585 /* check for usability */
1586 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1587 return 0;
1588
984263bc
MD
1589 /* check for BSP flag */
1590 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
a9112655 1591 mp_set_cpuids(0, entry->apic_id);
984263bc
MD
1592 return 0; /* its already been counted */
1593 }
1594
1595 /* add another AP to list, if less than max number of CPUs */
1596 else if (cpu < MAXCPU) {
a9112655 1597 mp_set_cpuids(cpu, entry->apic_id);
984263bc
MD
1598 return 1;
1599 }
1600
1601 return 0;
1602}
1603
4f6a8b30 1604#ifdef APIC_IO
984263bc
MD
1605
1606static int
c4717d5c 1607bus_entry(const struct BUSENTRY *entry, int bus)
984263bc
MD
1608{
1609 int x;
1610 char c, name[8];
1611
1612 /* encode the name into an index */
1613 for (x = 0; x < 6; ++x) {
1614 if ((c = entry->bus_type[x]) == ' ')
1615 break;
1616 name[x] = c;
1617 }
1618 name[x] = '\0';
1619
1620 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1621 panic("unknown bus type: '%s'", name);
1622
1623 bus_data[bus].bus_id = entry->bus_id;
1624 bus_data[bus].bus_type = x;
1625
1626 return 1;
1627}
1628
984263bc 1629static int
c4717d5c 1630io_apic_entry(const struct IOAPICENTRY *entry, int apic)
984263bc
MD
1631{
1632 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1633 return 0;
1634
1635 IO_TO_ID(apic) = entry->apic_id;
c163176b 1636 ID_TO_IO(entry->apic_id) = apic;
984263bc
MD
1637
1638 return 1;
1639}
1640
97359a5b 1641#endif
984263bc
MD
1642
1643static int
1644lookup_bus_type(char *name)
1645{
1646 int x;
1647
1648 for (x = 0; x < MAX_BUSTYPE; ++x)
1649 if (strcmp(bus_type_table[x].name, name) == 0)
1650 return bus_type_table[x].type;
1651
1652 return UNKNOWN_BUSTYPE;
1653}
1654
97359a5b 1655#ifdef APIC_IO
984263bc
MD
1656
1657static int
c4717d5c 1658int_entry(const struct INTENTRY *entry, int intr)
984263bc
MD
1659{
1660 int apic;
1661
1662 io_apic_ints[intr].int_type = entry->int_type;
1663 io_apic_ints[intr].int_flags = entry->int_flags;
1664 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1665 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1666 if (entry->dst_apic_id == 255) {
1667 /* This signal goes to all IO APICS. Select an IO APIC
1668 with sufficient number of interrupt pins */
1669 for (apic = 0; apic < mp_napics; apic++)
1670 if (((io_apic_read(apic, IOAPIC_VER) &
1671 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1672 entry->dst_apic_int)
1673 break;
1674 if (apic < mp_napics)
1675 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1676 else
1677 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1678 } else
1679 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1680 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1681
1682 return 1;
1683}
1684
984263bc
MD
1685static int
1686apic_int_is_bus_type(int intr, int bus_type)
1687{
1688 int bus;
1689
1690 for (bus = 0; bus < mp_nbusses; ++bus)
1691 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1692 && ((int) bus_data[bus].bus_type == bus_type))
1693 return 1;
1694
1695 return 0;
1696}
1697
984263bc
MD
1698/*
1699 * Given a traditional ISA INT mask, return an APIC mask.
1700 */
1701u_int
1702isa_apic_mask(u_int isa_mask)
1703{
1704 int isa_irq;
1705 int apic_pin;
1706
1707#if defined(SKIP_IRQ15_REDIRECT)
1708 if (isa_mask == (1 << 15)) {
26be20a0 1709 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD
1710 return isa_mask;
1711 }
1712#endif /* SKIP_IRQ15_REDIRECT */
1713
1714 isa_irq = ffs(isa_mask); /* find its bit position */
1715 if (isa_irq == 0) /* doesn't exist */
1716 return 0;
1717 --isa_irq; /* make it zero based */
1718
1719 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1720 if (apic_pin == -1)
1721 return 0;
1722
1723 return (1 << apic_pin); /* convert pin# to a mask */
1724}
1725
984263bc
MD
1726/*
1727 * Determine which APIC pin an ISA/EISA INT is attached to.
1728 */
1729#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1730#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1731#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1732#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1733
1734#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1735int
1736isa_apic_irq(int isa_irq)
1737{
1738 int intr;
1739
1740 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1741 if (INTTYPE(intr) == 0) { /* standard INT */
1742 if (SRCBUSIRQ(intr) == isa_irq) {
1743 if (apic_int_is_bus_type(intr, ISA) ||
1744 apic_int_is_bus_type(intr, EISA)) {
1745 if (INTIRQ(intr) == 0xff)
1746 return -1; /* unassigned */
1747 return INTIRQ(intr); /* found */
1748 }
1749 }
1750 }
1751 }
1752 return -1; /* NOT found */
1753}
1754
1755
1756/*
1757 * Determine which APIC pin a PCI INT is attached to.
1758 */
1759#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1760#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1761#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1762int
1763pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1764{
1765 int intr;
1766
1767 --pciInt; /* zero based */
1768
1439c090 1769 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD
1770 if ((INTTYPE(intr) == 0) /* standard INT */
1771 && (SRCBUSID(intr) == pciBus)
1772 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1773 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc
MD
1774 if (apic_int_is_bus_type(intr, PCI)) {
1775 if (INTIRQ(intr) == 0xff)
1776 allocate_apic_irq(intr);
1777 if (INTIRQ(intr) == 0xff)
1778 return -1; /* unassigned */
1779 return INTIRQ(intr); /* exact match */
1780 }
1439c090
MD
1781 }
1782 }
984263bc
MD
1783
1784 return -1; /* NOT found */
1785}
1786
1787int
1788next_apic_irq(int irq)
1789{
1790 int intr, ointr;
1791 int bus, bustype;
1792
1793 bus = 0;
1794 bustype = 0;
1795 for (intr = 0; intr < nintrs; intr++) {
1796 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1797 continue;
1798 bus = SRCBUSID(intr);
1799 bustype = apic_bus_type(bus);
1800 if (bustype != ISA &&
1801 bustype != EISA &&
1802 bustype != PCI)
1803 continue;
1804 break;
1805 }
1806 if (intr >= nintrs) {
1807 return -1;
1808 }
1809 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1810 if (INTTYPE(ointr) != 0)
1811 continue;
1812 if (bus != SRCBUSID(ointr))
1813 continue;
1814 if (bustype == PCI) {
1815 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1816 continue;
1817 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1818 continue;
1819 }
1820 if (bustype == ISA || bustype == EISA) {
1821 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1822 continue;
1823 }
1824 if (INTPIN(intr) == INTPIN(ointr))
1825 continue;
1826 break;
1827 }
1828 if (ointr >= nintrs) {
1829 return -1;
1830 }
1831 return INTIRQ(ointr);
1832}
1833#undef SRCBUSLINE
1834#undef SRCBUSDEVICE
1835#undef SRCBUSID
1836#undef SRCBUSIRQ
1837
1838#undef INTPIN
1839#undef INTIRQ
1840#undef INTAPIC
1841#undef INTTYPE
1842
97359a5b 1843#endif
984263bc
MD
1844
1845/*
1846 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1847 *
1848 * XXX FIXME:
1849 * Exactly what this means is unclear at this point. It is a solution
1850 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1851 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1852 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1853 * option.
1854 */
1855int
1856undirect_isa_irq(int rirq)
1857{
1858#if defined(READY)
1859 if (bootverbose)
26be20a0 1860 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1861 /** FIXME: tickle the MB redirector chip */
c044141b 1862 return /* XXX */;
984263bc
MD
1863#else
1864 if (bootverbose)
26be20a0 1865 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
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MD
1866 return 0;
1867#endif /* READY */
1868}
1869
1870
1871/*
1872 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1873 */
1874int
1875undirect_pci_irq(int rirq)
1876{
1877#if defined(READY)
1878 if (bootverbose)
26be20a0 1879 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD
1880
1881 /** FIXME: tickle the MB redirector chip */
c044141b 1882 return /* XXX */;
984263bc
MD
1883#else
1884 if (bootverbose)
26be20a0 1885 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD
1886 rirq);
1887 return 0;
1888#endif /* READY */
1889}
1890
1891
4f6a8b30
SZ
1892#ifdef APIC_IO
1893
984263bc
MD
1894/*
1895 * given a bus ID, return:
1896 * the bus type if found
1897 * -1 if NOT found
1898 */
1899int
1900apic_bus_type(int id)
1901{
1902 int x;
1903
1904 for (x = 0; x < mp_nbusses; ++x)
1905 if (bus_data[x].bus_id == id)
1906 return bus_data[x].bus_type;
1907
1908 return -1;
1909}
1910
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MD
1911/*
1912 * given a LOGICAL APIC# and pin#, return:
1913 * the associated src bus ID if found
1914 * -1 if NOT found
1915 */
1916int
1917apic_src_bus_id(int apic, int pin)
1918{
1919 int x;
1920
1921 /* search each of the possible INTerrupt sources */
1922 for (x = 0; x < nintrs; ++x)
1923 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1924 (pin == io_apic_ints[x].dst_apic_int))
1925 return (io_apic_ints[x].src_bus_id);
1926
1927 return -1; /* NOT found */
1928}
1929
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1930/*
1931 * given a LOGICAL APIC# and pin#, return:
1932 * the associated src bus IRQ if found
1933 * -1 if NOT found
1934 */
1935int
1936apic_src_bus_irq(int apic, int pin)
1937{
1938 int x;
1939
1940 for (x = 0; x < nintrs; x++)
1941 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1942 (pin == io_apic_ints[x].dst_apic_int))
1943 return (io_apic_ints[x].src_bus_irq);
1944
1945 return -1; /* NOT found */
1946}
1947
1948
1949/*
1950 * given a LOGICAL APIC# and pin#, return:
1951 * the associated INTerrupt type if found
1952 * -1 if NOT found
1953 */
1954int
1955apic_int_type(int apic, int pin)
1956{
1957 int x;
1958
1959 /* search each of the possible INTerrupt sources */
1439c090 1960 for (x = 0; x < nintrs; ++x) {
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MD
1961 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1962 (pin == io_apic_ints[x].dst_apic_int))
1963 return (io_apic_ints[x].int_type);
1439c090 1964 }
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MD
1965 return -1; /* NOT found */
1966}
1967
1439c090
MD
1968/*
1969 * Return the IRQ associated with an APIC pin
1970 */
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MD
1971int
1972apic_irq(int apic, int pin)
1973{
1974 int x;
1975 int res;
1976
1439c090 1977 for (x = 0; x < nintrs; ++x) {
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MD
1978 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1979 (pin == io_apic_ints[x].dst_apic_int)) {
1980 res = io_apic_ints[x].int_vector;
1981 if (res == 0xff)
1982 return -1;
1983 if (apic != int_to_apicintpin[res].ioapic)
1439c090 1984 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
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MD
1985 if (pin != int_to_apicintpin[res].int_pin)
1986 panic("apic_irq inconsistent table (2)");
1987 return res;
1988 }
1439c090 1989 }
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MD
1990 return -1;
1991}
1992
1993
1994/*
1995 * given a LOGICAL APIC# and pin#, return:
1996 * the associated trigger mode if found
1997 * -1 if NOT found
1998 */
1999int
2000apic_trigger(int apic, int pin)
2001{
2002 int x;
2003
2004 /* search each of the possible INTerrupt sources */
2005 for (x = 0; x < nintrs; ++x)
2006 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2007 (pin == io_apic_ints[x].dst_apic_int))
2008 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2009
2010 return -1; /* NOT found */
2011}
2012
2013
2014/*
2015 * given a LOGICAL APIC# and pin#, return:
2016 * the associated 'active' level if found
2017 * -1 if NOT found
2018 */
2019int
2020apic_polarity(int apic, int pin)
2021{
2022 int x;
2023
2024 /* search each of the possible INTerrupt sources */
2025 for (x = 0; x < nintrs; ++x)
2026 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2027 (pin == io_apic_ints[x].dst_apic_int))
2028 return (io_apic_ints[x].int_flags & 0x03);
2029
2030 return -1; /* NOT found */
2031}
2032
97359a5b 2033#endif
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MD
2034
2035/*
2036 * set data according to MP defaults
2037 * FIXME: probably not complete yet...
2038 */
2039static void
3aba8f73 2040mptable_default(int type)
984263bc 2041{
984263bc
MD
2042#if defined(APIC_IO)
2043 int io_apic_id;
2044 int pin;
984263bc
MD
2045
2046#if 0
26be20a0 2047 kprintf(" MP default config type: %d\n", type);
984263bc
MD
2048 switch (type) {
2049 case 1:
26be20a0 2050 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD
2051 break;
2052 case 2:
26be20a0 2053 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2054 break;
2055 case 3:
26be20a0 2056 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2057 break;
2058 case 4:
26be20a0 2059 kprintf(" bus: MCA, APIC: 82489DX\n");
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MD
2060 break;
2061 case 5:
26be20a0 2062 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD
2063 break;
2064 case 6:
26be20a0 2065 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD
2066 break;
2067 case 7:
26be20a0 2068 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD
2069 break;
2070 default:
26be20a0 2071 kprintf(" future type\n");
984263bc
MD
2072 break;
2073 /* NOTREACHED */
2074 }
2075#endif /* 0 */
2076
984263bc
MD
2077 /* one and only IO APIC */
2078 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2079
2080 /*
2081 * sanity check, refer to MP spec section 3.6.6, last paragraph
2082 * necessary as some hardware isn't properly setting up the IO APIC
2083 */
2084#if defined(REALLY_ANAL_IOAPICID_VALUE)
2085 if (io_apic_id != 2) {
2086#else
2087 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2088#endif /* REALLY_ANAL_IOAPICID_VALUE */
2089 io_apic_set_id(0, 2);
2090 io_apic_id = 2;
2091 }
2092 IO_TO_ID(0) = io_apic_id;
2093 ID_TO_IO(io_apic_id) = 0;
984263bc
MD
2094
2095 /* fill out bus entries */
2096 switch (type) {
2097 case 1:
2098 case 2:
2099 case 3:
2100 case 4:
2101 case 5:
2102 case 6:
2103 case 7:
2104 bus_data[0].bus_id = default_data[type - 1][1];
2105 bus_data[0].bus_type = default_data[type - 1][2];
2106 bus_data[1].bus_id = default_data[type - 1][3];
2107 bus_data[1].bus_type = default_data[type - 1][4];
2108 break;
2109
2110 /* case 4: case 7: MCA NOT supported */
2111 default: /* illegal/reserved */
2112 panic("BAD default MP config: %d", type);
2113 /* NOTREACHED */
2114 }
2115
984263bc
MD
2116 /* general cases from MP v1.4, table 5-2 */
2117 for (pin = 0; pin < 16; ++pin) {
2118 io_apic_ints[pin].int_type = 0;
2119 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2120 io_apic_ints[pin].src_bus_id = 0;
2121 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2122 io_apic_ints[pin].dst_apic_id = io_apic_id;
2123 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2124 }
2125
2126 /* special cases from MP v1.4, table 5-2 */
2127 if (type == 2) {
2128 io_apic_ints[2].int_type = 0xff; /* N/C */
2129 io_apic_ints[13].int_type = 0xff; /* N/C */
2130#if !defined(APIC_MIXED_MODE)
2131 /** FIXME: ??? */
2132 panic("sorry, can't support type 2 default yet");
2133#endif /* APIC_MIXED_MODE */
2134 }
2135 else
2136 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2137
2138 if (type == 7)
2139 io_apic_ints[0].int_type = 0xff; /* N/C */
2140 else
2141 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2142#endif /* APIC_IO */
2143}
2144
984263bc 2145/*
f13b5eec
MD
2146 * Map a physical memory address representing I/O into KVA. The I/O
2147 * block is assumed not to cross a page boundary.
2148 */
2149void *
2150permanent_io_mapping(vm_paddr_t pa)
2151{
2152 vm_offset_t vaddr;
2153 int pgeflag;
2154 int i;
2155
2156 KKASSERT(pa < 0x100000000LL);
2157
2158 pgeflag = 0; /* not used for SMP yet */
2159
2160 /*
2161 * If the requested physical address has already been incidently
2162 * mapped, just use the existing mapping. Otherwise create a new
2163 * mapping.
2164 */
2165 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2166 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2167 ((vm_offset_t)pa & PG_FRAME)) {
2168 break;
2169 }
2170 }
2171 if (i == SMPpt_alloc_index) {
2172 if (i == NPTEPG - 2) {
2173 panic("permanent_io_mapping: We ran out of space"
2174 " in SMPpt[]!");
2175 }
2176 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2177 ((vm_offset_t)pa & PG_FRAME));
2178 ++SMPpt_alloc_index;
2179 }
2180 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2181 ((vm_offset_t)pa & PAGE_MASK);
2182 return ((void *)vaddr);
2183}
2184
2185/*
984263bc
MD
2186 * start each AP in our list
2187 */
2188static int
2189start_all_aps(u_int boot_addr)
2190{
b45759e1
MD
2191 int x, i, pg;
2192 int shift;
984263bc
MD
2193 u_char mpbiosreason;
2194 u_long mpbioswarmvec;
8a8d5d85 2195 struct mdglobaldata *gd;
0f7a3396 2196 struct privatespace *ps;
984263bc
MD
2197 char *stack;
2198 uintptr_t kptbase;
2199
2200 POSTCODE(START_ALL_APS_POST);
2201
b52c8db0
SZ
2202 /* Initialize BSP's local APIC */
2203 apic_initialize(TRUE);
984263bc
MD
2204
2205 /* install the AP 1st level boot code */
2206 install_ap_tramp(boot_addr);
2207
2208
2209 /* save the current value of the warm-start vector */
2210 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
2211 outb(CMOS_REG, BIOS_RESET);
2212 mpbiosreason = inb(CMOS_DATA);
984263bc 2213
984263bc
MD
2214 /* set up temporary P==V mapping for AP boot */
2215 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2216 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2217 for (x = 0; x < NKPT; x++) {
984263bc
MD
2218 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2219 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2220 }
0f7a3396 2221 cpu_invltlb();
984263bc
MD
2222
2223 /* start each AP */
2224 for (x = 1; x <= mp_naps; ++x) {
2225
2226 /* This is a bit verbose, it will go away soon. */
2227
2228 /* first page of AP's private space */
2229 pg = x * i386_btop(sizeof(struct privatespace));
2230
81c04d07 2231 /* allocate new private data page(s) */
e4846942 2232 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2233 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2234 /* wire it into the private page table page */
81c04d07
MD
2235 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2236 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2237 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2238 }
2239 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2240
2241 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2242 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2243 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2244 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
2245
2246 /* allocate and set up an idle stack data page */
e4846942 2247 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2248 for (i = 0; i < UPAGES; i++) {
81c04d07 2249 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2250 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2251 }
984263bc 2252
8a8d5d85
MD
2253 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2254 bzero(gd, sizeof(*gd));
0f7a3396 2255 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2256
984263bc 2257 /* prime data page for it to use */
8a8d5d85 2258 mi_gdinit(&gd->mi, x);
8ad65e08 2259 cpu_gdinit(gd, x);
81c04d07
MD
2260 gd->gd_CMAP1 = &SMPpt[pg + 0];
2261 gd->gd_CMAP2 = &SMPpt[pg + 1];
2262 gd->gd_CMAP3 = &SMPpt[pg + 2];
2263 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
2264 gd->gd_CADDR1 = ps->CPAGE1;
2265 gd->gd_CADDR2 = ps->CPAGE2;
2266 gd->gd_CADDR3 = ps->CPAGE3;
2267 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
e4846942 2268 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2269 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc
MD
2270
2271 /* setup a vector to our boot code */
2272 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2273 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
984263bc
MD
2274 outb(CMOS_REG, BIOS_RESET);
2275 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
984263bc 2276
8a8d5d85
MD
2277 /*
2278 * Setup the AP boot stack
2279 */
0f7a3396 2280 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2281 bootAP = x;
2282
2283 /* attempt to start the Application Processor */
2284 CHECK_INIT(99); /* setup checkpoints */
0f7a3396 2285 if (!start_ap(gd, boot_addr)) {
26be20a0 2286 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
2287 CHECK_PRINT("trace"); /* show checkpoints */
2288 /* better panic as the AP may be running loose */
26be20a0 2289 kprintf("panic y/n? [y] ");
984263bc
MD
2290 if (cngetc() != 'n')
2291 panic("bye-bye");
2292 }
2293 CHECK_PRINT("trace"); /* show checkpoints */
2294
2295 /* record its version info */
2296 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD
2297 }
2298
0f7a3396
MD
2299 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2300 ncpus = x;
2301
b45759e1
MD
2302 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2303 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2304 ;
2305 --shift;
2306 ncpus2_shift = shift;
2307 ncpus2 = 1 << shift;
90100055
JH
2308 ncpus2_mask = ncpus2 - 1;
2309
b45759e1
MD
2310 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2311 if ((1 << shift) < ncpus)
2312 ++shift;
2313 ncpus_fit = 1 << shift;
2314 ncpus_fit_mask = ncpus_fit - 1;
2315
984263bc 2316 /* build our map of 'other' CPUs */
0f7a3396 2317 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2318 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2319 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2320
2321 /* fill in our (BSP) APIC version */
2322 cpu_apic_versions[0] = lapic.version;
2323
2324 /* restore the warmstart vector */
2325 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
2326 outb(CMOS_REG, BIOS_RESET);
2327 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
2328
2329 /*
8a8d5d85
MD
2330 * NOTE! The idlestack for the BSP was setup by locore. Finish
2331 * up, clean out the P==V mapping we did earlier.
984263bc 2332 */
984263bc
MD
2333 for (x = 0; x < NKPT; x++)
2334 PTD[x] = 0;
2335 pmap_set_opt();
2336
2337 /* number of APs actually started */
8a8d5d85 2338 return ncpus - 1;
984263bc
MD
2339}
2340
2341
2342/*
2343 * load the 1st level AP boot code into base memory.
2344 */
2345
2346/* targets for relocation */
2347extern void bigJump(void);
2348extern void bootCodeSeg(void);
2349extern void bootDataSeg(void);
2350extern void MPentry(void);
2351extern u_int MP_GDT;
2352extern u_int mp_gdtbase;
2353
2354static void
2355install_ap_tramp(u_int boot_addr)
2356{
2357 int x;
2358 int size = *(int *) ((u_long) & bootMP_size);
2359 u_char *src = (u_char *) ((u_long) bootMP);
2360 u_char *dst = (u_char *) boot_addr + KERNBASE;
2361 u_int boot_base = (u_int) bootMP;
2362 u_int8_t *dst8;
2363 u_int16_t *dst16;
2364 u_int32_t *dst32;
2365
2366 POSTCODE(INSTALL_AP_TRAMP_POST);
2367
2368 for (x = 0; x < size; ++x)
2369 *dst++ = *src++;
2370
2371 /*
2372 * modify addresses in code we just moved to basemem. unfortunately we
2373 * need fairly detailed info about mpboot.s for this to work. changes
2374 * to mpboot.s might require changes here.
2375 */
2376
2377 /* boot code is located in KERNEL space */
2378 dst = (u_char *) boot_addr + KERNBASE;
2379
2380 /* modify the lgdt arg */
2381 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2382 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2383
2384 /* modify the ljmp target for MPentry() */
2385 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2386 *dst32 = ((u_int) MPentry - KERNBASE);
2387
2388 /* modify the target for boot code segment */
2389 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2390 dst8 = (u_int8_t *) (dst16 + 1);
2391 *dst16 = (u_int) boot_addr & 0xffff;
2392 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2393
2394 /* modify the target for boot data segment */
2395 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2396 dst8 = (u_int8_t *) (dst16 + 1);
2397 *dst16 = (u_int) boot_addr & 0xffff;
2398 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2399}
2400
2401
2402/*
2403 * this function starts the AP (application processor) identified
2404 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2405 * to accomplish this. This is necessary because of the nuances
2406 * of the different hardware we might encounter. It ain't pretty,
2407 * but it seems to work.
a108bf71
MD
2408 *
2409 * NOTE: eventually an AP gets to ap_init(), which is called just
2410 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
2411 */
2412static int
0f7a3396 2413start_ap(struct mdglobaldata *gd, u_int boot_addr)
984263bc
MD
2414{
2415 int physical_cpu;
2416 int vector;
984263bc
MD
2417 u_long icr_lo, icr_hi;
2418
2419 POSTCODE(START_AP_POST);
2420
2421 /* get the PHYSICAL APIC ID# */
0f7a3396 2422 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
2423
2424 /* calculate the vector */
2425 vector = (boot_addr >> 12) & 0xff;
2426
8a8d5d85
MD
2427 /* Make sure the target cpu sees everything */
2428 wbinvd();
984263bc
MD
2429
2430 /*
2431 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2432 * and running the target CPU. OR this INIT IPI might be latched (P5
2433 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2434 * ignored.
2435 */
2436
2437 /* setup the address for the target AP */
2438 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2439 icr_hi |= (physical_cpu << 24);
2440 lapic.icr_hi = icr_hi;
2441
2442 /* do an INIT IPI: assert RESET */
2443 icr_lo = lapic.icr_lo & 0xfff00000;
2444 lapic.icr_lo = icr_lo | 0x0000c500;
2445
2446 /* wait for pending status end */
2447 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2448 /* spin */ ;
2449
2450 /* do an INIT IPI: deassert RESET */
2451 lapic.icr_lo = icr_lo | 0x00008500;
2452
2453 /* wait for pending status end */
2454 u_sleep(10000); /* wait ~10mS */
2455 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2456 /* spin */ ;
2457
2458 /*
2459 * next we do a STARTUP IPI: the previous INIT IPI might still be
2460 * latched, (P5 bug) this 1st STARTUP would then terminate
2461 * immediately, and the previously started INIT IPI would continue. OR
2462 * the previous INIT IPI has already run. and this STARTUP IPI will
2463 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2464 * will run.
2465 */
2466
2467 /* do a STARTUP IPI */
2468 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2469 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2470 /* spin */ ;
2471 u_sleep(200); /* wait ~200uS */
2472
2473 /*
2474 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2475 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2476 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2477 * recognized after hardware RESET or INIT IPI.
2478 */
2479
2480 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2481 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2482 /* spin */ ;
2483 u_sleep(200); /* wait ~200uS */
2484
8a8d5d85 2485 /* wait for it to start, see ap_init() */
984263bc 2486 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2487 while (read_apic_timer()) {
0f7a3396 2488 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2489 return 1; /* return SUCCESS */
8a8d5d85 2490 }
984263bc
MD
2491 return 0; /* return FAILURE */
2492}
2493
2494
2495/*
0f7a3396 2496 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2497 *
0f7a3396
MD
2498 * If for some reason we were unable to start all cpus we cannot safely
2499 * use broadcast IPIs.
984263bc
MD
2500 */
2501void
2502smp_invltlb(void)
2503{
97359a5b 2504#ifdef SMP
0f7a3396 2505 if (smp_startup_mask == smp_active_mask) {
984263bc 2506 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396
MD
2507 } else {
2508 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2509 APIC_DELMODE_FIXED);
2510 }
97359a5b 2511#endif
984263bc
MD
2512}
2513
984263bc
MD
2514/*
2515 * When called the executing CPU will send an IPI to all other CPUs
2516 * requesting that they halt execution.
2517 *
2518 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2519 *
2520 * - Signals all CPUs in map to stop.
2521 * - Waits for each to stop.
2522 *
2523 * Returns:
2524 * -1: error
2525 * 0: NA
2526 * 1: ok
2527 *
2528 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2529 * from executing at same time.
2530 */
2531int
2532stop_cpus(u_int map)
2533{
0f7a3396 2534 map &= smp_active_mask;
984263bc
MD
2535
2536 /* send the Xcpustop IPI to all CPUs in map */
2537 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2538
2539 while ((stopped_cpus & map) != map)
2540 /* spin */ ;
2541
2542 return 1;
2543}
2544
2545
2546/*
2547 * Called by a CPU to restart stopped CPUs.
2548 *
2549 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2550 *
2551 * - Signals all CPUs in map to restart.
2552 * - Waits for each to restart.
2553 *
2554 * Returns:
2555 * -1: error
2556 * 0: NA
2557 * 1: ok
2558 */
2559int
2560restart_cpus(u_int map)
2561{
0f7a3396
MD
2562 /* signal other cpus to restart */
2563 started_cpus = map & smp_active_mask;
984263bc
MD
2564
2565 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2566 /* spin */ ;
2567
2568 return 1;
2569}
2570
984263bc 2571/*
8a8d5d85
MD
2572 * This is called once the mpboot code has gotten us properly relocated
2573 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2574 * and when it returns the scheduler will call the real cpu_idle() main
2575 * loop for the idlethread. Interrupts are disabled on entry and should
2576 * remain disabled at return.
984263bc 2577 */
984263bc 2578void
8a8d5d85 2579ap_init(void)
984263bc
MD
2580{
2581 u_int apic_id;
2582
8a8d5d85 2583 /*
0f7a3396
MD
2584 * Adjust smp_startup_mask to signal the BSP that we have started
2585 * up successfully. Note that we do not yet hold the BGL. The BSP
2586 * is waiting for our signal.
2587 *
2588 * We can't set our bit in smp_active_mask yet because we are holding
2589 * interrupts physically disabled and remote cpus could deadlock
2590 * trying to send us an IPI.
8a8d5d85 2591 */
0f7a3396 2592 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2593 cpu_mfence();
8a8d5d85
MD
2594
2595 /*
41a01a4d
MD
2596 * Interlock for finalization. Wait until mp_finish is non-zero,
2597 * then get the MP lock.
2598 *
2599 * Note: We are in a critical section.
2600 *
2601 * Note: We have to synchronize td_mpcount to our desired MP state
2602 * before calling cpu_try_mplock().
2603 *
2604 * Note: we are the idle thread, we can only spin.
2605 *
35238fa5
MD
2606 * Note: The load fence is memory volatile and prevents the compiler
2607 * from improperly caching mp_finish, and the cpu from improperly
2608 * caching it.
8a8d5d85 2609 */
41a01a4d 2610 while (mp_finish == 0)
35238fa5 2611 cpu_lfence();
d9ebdce5 2612 ++curthread->td_mpcount;
8a8d5d85
MD
2613 while (cpu_try_mplock() == 0)
2614 ;
2615
374133e3
MD
2616 if (cpu_feature & CPUID_TSC) {
2617 /*
2618 * The BSP is constantly updating tsc0_offset, figure out the
2619 * relative difference to synchronize ktrdump.
2620 */
2621 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2622 }
2623
984263bc
MD
2624 /* BSP may have changed PTD while we're waiting for the lock */
2625 cpu_invltlb();
2626
984263bc
MD
2627#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2628 lidt(&r_idt);
2629#endif
2630
2631 /* Build our map of 'other' CPUs. */
0f7a3396 2632 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2633
26be20a0 2634 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2635
984263bc
MD
2636 /* A quick check from sanity claus */
2637 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2638 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
2639 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2640 kprintf("SMP: apic_id = %d\n", apic_id);
2641 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
2642 panic("cpuid mismatch! boom!!");
2643 }
2644
b52c8db0
SZ
2645 /* Initialize AP's local APIC for irq's */
2646 apic_initialize(FALSE);
984263bc
MD
2647
2648 /* Set memory range attributes for this CPU to match the BSP */
2649 mem_range_AP_init();
2650
a2a5ad0d 2651 /*
4c9f5a7f
MD
2652 * Once we go active we must process any IPIQ messages that may
2653 * have been queued, because no actual IPI will occur until we
2654 * set our bit in the smp_active_mask. If we don't the IPI
2655 * message interlock could be left set which would also prevent
2656 * further IPIs.
2657 *
8a8d5d85
MD
2658 * The idle loop doesn't expect the BGL to be held and while
2659 * lwkt_switch() normally cleans things up this is a special case
2660 * because we returning almost directly into the idle loop.
41a01a4d
MD
2661 *
2662 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2663 * nothing we've done put it there.
8a8d5d85 2664 */
96728c05 2665 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2666 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD
2667
2668 /*
2669 * Enable interrupts here. idle_restore will also do it, but
2670 * doing it here lets us clean up any strays that got posted to
2671 * the CPU during the AP boot while we are still in a critical
2672 * section.
2673 */
2674 __asm __volatile("sti; pause; pause"::);
2675 mdcpu->gd_fpending = 0;
2676 mdcpu->gd_ipending = 0;
2677
4a19580d 2678 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2679 lwkt_process_ipiq();
d19f6edf
MD
2680
2681 /*
2682 * Releasing the mp lock lets the BSP finish up the SMP init
2683 */
96728c05 2684 rel_mplock();
41a01a4d 2685 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
2686}
2687
41a01a4d
MD
2688/*
2689 * Get SMP fully working before we start initializing devices.
2690 */
2691static
2692void
2693ap_finish(void)
2694{
2695 mp_finish = 1;
2696 if (bootverbose)
26be20a0 2697 kprintf("Finish MP startup\n");
374133e3
MD
2698 if (cpu_feature & CPUID_TSC)
2699 tsc0_offset = rdtsc();
2700 tsc_offsets[0] = 0;
41a01a4d 2701 rel_mplock();
374133e3 2702 while (smp_active_mask != smp_startup_mask) {
35238fa5 2703 cpu_lfence();
374133e3
MD
2704 if (cpu_feature & CPUID_TSC)
2705 tsc0_offset = rdtsc();
2706 }
4da43e1f 2707 while (try_mplock() == 0)
41a01a4d
MD
2708 ;
2709 if (bootverbose)
26be20a0 2710 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
2711}
2712
ba39e2e0 2713SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2714
96728c05
MD
2715void
2716cpu_send_ipiq(int dcpu)
2717{
41a01a4d
MD
2718 if ((1 << dcpu) & smp_active_mask)
2719 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2720}
41a01a4d
MD
2721
2722#if 0 /* single_apic_ipi_passive() not working yet */
2723/*
2724 * Returns 0 on failure, 1 on success
2725 */
2726int
2727cpu_send_ipiq_passive(int dcpu)
2728{
2729 int r = 0;
2730 if ((1 << dcpu) & smp_active_mask) {
2731 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2732 APIC_DELMODE_FIXED);
2733 }
2734 return(r);
2735}
2736#endif
2737
a0873f07
SZ
2738struct mptable_lapic_cbarg1 {
2739 int cpu_count;
44c36320
SZ
2740 int ht_fixup;
2741 u_int ht_apicid_mask;
a0873f07
SZ
2742};
2743
2744static int
2745mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2746{
2747 const struct PROCENTRY *ent;
2748 struct mptable_lapic_cbarg1 *arg = xarg;
2749
2750 if (type != 0)
2751 return 0;
2752 ent = pos;
2753
2754 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2755 return 0;
2756
2757 arg->cpu_count++;
44c36320
SZ
2758 if (ent->apic_id < 32) {
2759 arg->ht_apicid_mask |= 1 << ent->apic_id;
2760 } else if (arg->ht_fixup) {
2761 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2762 arg->ht_fixup = 0;
2763 }
a0873f07
SZ
2764 return 0;
2765}
2766
2767struct mptable_lapic_cbarg2 {
2768 int cpu;
44c36320 2769 int logical_cpus;
a0873f07
SZ
2770 int found_bsp;
2771};
2772
2773static int
2774mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2775{
2776 const struct PROCENTRY *ent;
2777 struct mptable_lapic_cbarg2 *arg = xarg;
2778
2779 if (type != 0)
2780 return 0;
2781 ent = pos;
2782
2783 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2784 KKASSERT(!arg->found_bsp);
2785 arg->found_bsp = 1;
2786 }
2787
2788 if (processor_entry(ent, arg->cpu))
2789 arg->cpu++;
2790
44c36320 2791 if (arg->logical_cpus) {
a0873f07
SZ
2792 struct PROCENTRY proc;
2793 int i;
2794
2795 /*
2796 * Create fake mptable processor entries
2797 * and feed them to processor_entry() to
2798 * enumerate the logical CPUs.
2799 */
2800 bzero(&proc, sizeof(proc));
2801 proc.type = 0;
2802 proc.cpu_flags = PROCENTRY_FLAG_EN;
2803 proc.apic_id = ent->apic_id;
2804
44c36320 2805 for (i = 1; i < arg->logical_cpus; i++) {
a0873f07
SZ
2806 proc.apic_id++;
2807 processor_entry(&proc, arg->cpu);
a0873f07
SZ
2808 arg->cpu++;
2809 }
2810 }
2811 return 0;
2812}
2813
322abba7
SZ
2814static void
2815mptable_lapic_default(void)
2816{
2817 int ap_apicid, bsp_apicid;
2818
2819 mp_naps = 1; /* exclude BSP */
2820
2821 /* Map local apic before the id field is accessed */
2822 lapic_init(DEFAULT_APIC_BASE);
2823
2824 bsp_apicid = APIC_ID(lapic.id);
2825 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2826
2827 /* BSP */
2828 mp_set_cpuids(0, bsp_apicid);
2829 /* one and only AP */
2830 mp_set_cpuids(1, ap_apicid);
2831}
2832
a0873f07
SZ
2833/*
2834 * Configure:
2835 * cpu_apic_address (common to all CPUs)
2836 * mp_naps
d787e80c 2837 * ID_TO_CPU(N), APIC ID to logical CPU table
a0873f07
SZ
2838 * CPU_TO_ID(N), logical CPU to APIC ID table
2839 */
2840static void
2841mptable_lapic_enumerate(struct mptable_pos *mpt)
2842{
322abba7
SZ
2843 struct mptable_lapic_cbarg1 arg1;
2844 struct mptable_lapic_cbarg2 arg2;
2845 mpcth_t cth;
44c36320 2846 int error, logical_cpus = 0;
5a16ccc3 2847 vm_offset_t lapic_addr;
a0873f07 2848
322abba7 2849 KKASSERT(mpt->mp_fps != NULL);
a0873f07 2850
322abba7
SZ
2851 /*
2852 * Check for use of 'default' configuration
2853 */
2854 if (mpt->mp_fps->mpfb1 != 0) {
2855 mptable_lapic_default();
2856 return;
2857 }
a0873f07 2858
322abba7
SZ
2859 cth = mpt->mp_cth;
2860 KKASSERT(cth != NULL);
a0873f07 2861
322abba7
SZ
2862 /* Save local apic address */
2863 lapic_addr = (vm_offset_t)cth->apic_address;
2864 KKASSERT(lapic_addr != 0);
a0873f07 2865
322abba7
SZ
2866 /*
2867 * Find out how many CPUs do we have
2868 */
2869 bzero(&arg1, sizeof(arg1));
44c36320
SZ
2870 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2871
322abba7
SZ
2872 error = mptable_iterate_entries(cth,
2873 mptable_lapic_pass1_callback, &arg1);
2874 if (error)
2875 panic("mptable_iterate_entries(lapic_pass1) failed\n");
322abba7 2876 KKASSERT(arg1.cpu_count != 0);
a0873f07 2877
322abba7 2878 /* See if we need to fixup HT logical CPUs. */
44c36320
SZ
2879 if (arg1.ht_fixup) {
2880 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2881 arg1.cpu_count);
2882 if (logical_cpus != 0)
2883 arg1.cpu_count *= logical_cpus;
2884 }
2885 mp_naps = arg1.cpu_count;
a0873f07 2886
44c36320 2887 /* Qualify the numbers again, after possible HT fixup */
322abba7
SZ
2888 if (mp_naps > MAXCPU) {
2889 kprintf("Warning: only using %d of %d available CPUs!\n",
2890 MAXCPU, mp_naps);
2891 mp_naps = MAXCPU;
a0873f07
SZ
2892 }
2893
322abba7 2894 --mp_naps; /* subtract the BSP */
a0873f07 2895
322abba7
SZ
2896 /*
2897 * Link logical CPU id to local apic id
2898 */
2899 bzero(&arg2, sizeof(arg2));
2900 arg2.cpu = 1;
44c36320 2901 arg2.logical_cpus = logical_cpus;
a0873f07 2902
322abba7
SZ
2903 error = mptable_iterate_entries(cth,
2904 mptable_lapic_pass2_callback, &arg2);
2905 if (error)
2906 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2907 KKASSERT(arg2.found_bsp);
a0873f07 2908
322abba7
SZ
2909 /* Map local apic */
2910 lapic_init(lapic_addr);
a0873f07 2911}
5a16ccc3
SZ
2912
2913static void
a0eaef71
SZ
2914mptable_imcr(struct mptable_pos *mpt)
2915{
2916 /* record whether PIC or virtual-wire mode */
2917 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2918 mpt->mp_fps->mpfb2 & 0x80);
2919}
2920
2921static void
5a16ccc3
SZ
2922lapic_init(vm_offset_t lapic_addr)
2923{
2924 /* Local apic is mapped on last page */
2925 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2926 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2927
2928 /* Just for printing */
2929 cpu_apic_address = lapic_addr;
2930}