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brgphy: Remove debug prints
[dragonfly.git] / sys / dev / netif / mii_layer / brgphy.c
CommitLineData
46ad174e
SZ		 1/* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
2
984263bc
MD		 3/*
4 * Copyright (c) 2000
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
35 */
36
37/*
9bbc5585 38 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always
984263bc
MD		 39 * 1000mbps; all we need to negotiate here is full or half duplex.
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/socket.h>
46#include <sys/bus.h>
055d06f0 47#include <sys/sysctl.h>
984263bc 48
0ecb11d7 49#include <net/ethernet.h>
984263bc
MD		 50#include <net/if.h>
51#include <net/if_media.h>
7e40b8c5 52#include <net/if_arp.h>
984263bc 53
1f2de5d4
MD		 54#include "mii.h"
55#include "miivar.h"
56#include "miidevs.h"
1f2de5d4 57#include "brgphyreg.h"
984263bc
MD		 58
59#include "miibus_if.h"
60
984263bc
MD		 61static int brgphy_probe(device_t);
62static int brgphy_attach(device_t);
46ad174e
SZ		 63
64static const struct mii_phydesc brgphys[] = {
65 MII_PHYDESC(xxBROADCOM, BCM5400),
66 MII_PHYDESC(xxBROADCOM, BCM5401),
67 MII_PHYDESC(xxBROADCOM, BCM5411),
68 MII_PHYDESC(xxBROADCOM, BCM5421),
69 MII_PHYDESC(xxBROADCOM, BCM54K2),
0eed2f27 70 MII_PHYDESC(xxBROADCOM, BCM5461),
46ad174e 71 MII_PHYDESC(xxBROADCOM, BCM5462),
0eed2f27 72 MII_PHYDESC(xxBROADCOM, BCM5464),
46ad174e
SZ		 73
74 MII_PHYDESC(xxBROADCOM, BCM5701),
75 MII_PHYDESC(xxBROADCOM, BCM5703),
76 MII_PHYDESC(xxBROADCOM, BCM5704),
77 MII_PHYDESC(xxBROADCOM, BCM5705),
46ad174e
SZ		 78 MII_PHYDESC(xxBROADCOM, BCM5714),
79 MII_PHYDESC(xxBROADCOM, BCM5750),
80 MII_PHYDESC(xxBROADCOM, BCM5752),
81 MII_PHYDESC(xxBROADCOM, BCM5780),
0eed2f27
SZ		 82
83 MII_PHYDESC(xxBROADCOM2,BCM54XX),
84 MII_PHYDESC(xxBROADCOM2,BCM5481),
85 MII_PHYDESC(xxBROADCOM2,BCM5482),
86 MII_PHYDESC(xxBROADCOM2,BCM5722),
87 MII_PHYDESC(xxBROADCOM2,BCM5755),
88 MII_PHYDESC(xxBROADCOM2,BCM5761),
89 MII_PHYDESC(xxBROADCOM2,BCM5784),
0ecb11d7 90 MII_PHYDESC(xxBROADCOM2,BCM5787),
46ad174e
SZ		 91
92 MII_PHYDESC(xxBROADCOM, BCM5706C),
93 MII_PHYDESC(xxBROADCOM, BCM5708C),
d0092544
SZ		 94 MII_PHYDESC(xxBROADCOM2, BCM5709CAX),
95 MII_PHYDESC(xxBROADCOM2, BCM5709C),
46ad174e 96
0eed2f27
SZ		 97 MII_PHYDESC(xxBROADCOM3, BCM5717C),
98 MII_PHYDESC(xxBROADCOM3, BCM5719C),
99 MII_PHYDESC(xxBROADCOM3, BCM57765),
100 MII_PHYDESC(xxBROADCOM3, BCM57780),
101
591dfc77
SZ		 102 MII_PHYDESC(BROADCOM2, BCM5906),
103
46ad174e
SZ		 104 MII_PHYDESC_NULL
105};
984263bc
MD		 106
107static device_method_t brgphy_methods[] = {
108 /* device interface */
109 DEVMETHOD(device_probe, brgphy_probe),
110 DEVMETHOD(device_attach, brgphy_attach),
46ad174e 111 DEVMETHOD(device_detach, ukphy_detach),
984263bc
MD		 112 DEVMETHOD(device_shutdown, bus_generic_shutdown),
113 { 0, 0 }
114};
115
116static devclass_t brgphy_devclass;
117
118static driver_t brgphy_driver = {
119 "brgphy",
120 brgphy_methods,
121 sizeof(struct mii_softc)
122};
123
aa2b9d05 124DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, NULL, NULL);
984263bc
MD		 125
126static int brgphy_service(struct mii_softc *, struct mii_data *, int);
127static void brgphy_status(struct mii_softc *);
db861466 128static void brgphy_mii_phy_auto(struct mii_softc *);
984263bc
MD		 129static void brgphy_reset(struct mii_softc *);
130static void brgphy_loop(struct mii_softc *);
46ad174e 131
46ad174e
SZ		 132static void brgphy_bcm5401_dspcode(struct mii_softc *);
133static void brgphy_bcm5411_dspcode(struct mii_softc *);
134static void brgphy_bcm5421_dspcode(struct mii_softc *);
135static void brgphy_bcm54k2_dspcode(struct mii_softc *);
0ecb11d7
SZ		 136
137static void brgphy_adc_bug(struct mii_softc *);
138static void brgphy_5704_a0_bug(struct mii_softc *);
139static void brgphy_ber_bug(struct mii_softc *);
140static void brgphy_crc_bug(struct mii_softc *);
141
d0092544 142static void brgphy_disable_early_dac(struct mii_softc *);
0ecb11d7
SZ		 143static void brgphy_jumbo_settings(struct mii_softc *, u_long);
144static void brgphy_eth_wirespeed(struct mii_softc *);
984263bc 145
c436375a
SW		 146static int
147brgphy_probe(device_t dev)
984263bc 148{
46ad174e
SZ		 149 struct mii_attach_args *ma = device_get_ivars(dev);
150 const struct mii_phydesc *mpd;
984263bc 151
46ad174e
SZ		 152 mpd = mii_phy_match(ma, brgphys);
153 if (mpd != NULL) {
154 device_set_desc(dev, mpd->mpd_name);
155 return (0);
7e40b8c5 156 }
984263bc
MD		 157 return(ENXIO);
158}
159
160static int
c436375a 161brgphy_attach(device_t dev)
984263bc
MD		 162{
163 struct mii_softc *sc;
164 struct mii_attach_args *ma;
165 struct mii_data *mii;
984263bc
MD		 166
167 sc = device_get_softc(dev);
168 ma = device_get_ivars(dev);
b9bc8a8c 169 mii_softc_init(sc, ma);
984263bc
MD		 170 sc->mii_dev = device_get_parent(dev);
171 mii = device_get_softc(sc->mii_dev);
172 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
173
174 sc->mii_inst = mii->mii_instance;
984263bc 175 sc->mii_service = brgphy_service;
46ad174e 176 sc->mii_reset = brgphy_reset;
984263bc
MD		 177 sc->mii_pdata = mii;
178
179 sc->mii_flags |= MIIF_NOISOLATE;
180 mii->mii_instance++;
181
46ad174e
SZ		 182 brgphy_reset(sc);
183
984263bc 184#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
984263bc
MD		 185
186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
46ad174e 187 MII_MEDIA_NONE);
984263bc
MD		 188#if 0
189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
46ad174e 190 MII_MEDIA_100_TX);
984263bc
MD		 191#endif
192
46ad174e 193#undef ADD
984263bc 194
46ad174e
SZ		 195 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
196 if (sc->mii_capabilities & BMSR_EXTSTAT)
197 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
984263bc 198
46ad174e
SZ		 199 device_printf(dev, " ");
200 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
201 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
202 mii_phy_add_media(sc);
203 else
e3869ec7
SW		 204 kprintf("no media present");
205 kprintf("\n");
984263bc
MD		 206
207 MIIBUS_MEDIAINIT(sc->mii_dev);
208 return(0);
209}
210
211static int
c436375a 212brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
984263bc
MD		 213{
214 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
215 int reg, speed, gig;
216
217 switch (cmd) {
218 case MII_POLLSTAT:
219 /*
220 * If we're not polling our PHY instance, just return.
221 */
222 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
223 return (0);
224 break;
225
226 case MII_MEDIACHG:
227 /*
228 * If the media indicates a different PHY instance,
229 * isolate ourselves.
230 */
231 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
232 reg = PHY_READ(sc, MII_BMCR);
233 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
234 return (0);
235 }
236
237 /*
238 * If the interface is not up, don't do anything.
239 */
240 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
241 break;
242
243 brgphy_reset(sc); /* XXX hardware bug work-around */
244
245 switch (IFM_SUBTYPE(ife->ifm_media)) {
246 case IFM_AUTO:
247#ifdef foo
248 /*
249 * If we're already in auto mode, just return.
250 */
251 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
252 return (0);
253#endif
db861466 254 brgphy_mii_phy_auto(sc);
984263bc 255 break;
7f259627 256 case IFM_1000_T:
984263bc
MD		 257 speed = BRGPHY_S1000;
258 goto setit;
259 case IFM_100_TX:
260 speed = BRGPHY_S100;
261 goto setit;
262 case IFM_10_T:
263 speed = BRGPHY_S10;
264setit:
265 brgphy_loop(sc);
266 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
267 speed |= BRGPHY_BMCR_FDX;
268 gig = BRGPHY_1000CTL_AFD;
269 } else {
270 gig = BRGPHY_1000CTL_AHD;
271 }
272
273 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
984263bc 274 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
d0092544 275 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
984263bc 276
7f259627 277 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
984263bc
MD		 278 break;
279
280 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
281 PHY_WRITE(sc, BRGPHY_MII_BMCR,
282 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
283
46ad174e 284 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
984263bc
MD		 285 break;
286
287 /*
288 * When settning the link manually, one side must
289 * be the master and the other the slave. However
290 * ifmedia doesn't give us a good way to specify
291 * this, so we fake it by using one of the LINK
292 * flags. If LINK0 is set, we program the PHY to
293 * be a master, otherwise it's a slave.
294 */
295 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
296 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
297 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
298 } else {
299 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
300 gig|BRGPHY_1000CTL_MSE);
301 }
302 break;
303#ifdef foo
304 case IFM_NONE:
305 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
306 break;
307#endif
308 case IFM_100_T4:
309 default:
310 return (EINVAL);
311 }
312 break;
313
314 case MII_TICK:
315 /*
316 * If we're not currently selected, just return.
317 */
318 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
319 return (0);
320
321 /*
46ad174e 322 * Is the interface even up?
984263bc 323 */
46ad174e 324 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
984263bc
MD		 325 return (0);
326
327 /*
46ad174e 328 * Only used for autonegotiation.
984263bc 329 */
46ad174e
SZ		 330 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
331 break;
984263bc
MD		 332
333 /*
334 * Check to see if we have link. If we do, we don't
5a020756
SZ		 335 * need to restart the autonegotiation process. Read
336 * the BMSR twice in case it's latched.
984263bc 337 */
5a020756
SZ		 338 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
339 if (reg & BMSR_LINK) {
12b5e22d 340 sc->mii_ticks = 0;
984263bc 341 break;
12b5e22d 342 }
984263bc
MD		 343
344 /*
345 * Only retry autonegotiation every 5 seconds.
346 */
46ad174e
SZ		 347 if (++sc->mii_ticks <= sc->mii_anegticks)
348 break;
5a020756 349
984263bc 350 sc->mii_ticks = 0;
db861466 351 brgphy_mii_phy_auto(sc);
46ad174e 352 break;
984263bc
MD		 353 }
354
355 /* Update the media status. */
356 brgphy_status(sc);
357
358 /*
359 * Callback if something changed. Note that we need to poke
360 * the DSP on the Broadcom PHYs if the media changes.
361 */
46ad174e
SZ		 362 if (sc->mii_media_active != mii->mii_media_active ||
363 sc->mii_media_status != mii->mii_media_status ||
364 cmd == MII_MEDIACHG) {
365 switch (sc->mii_model) {
0ecb11d7
SZ		 366 case MII_MODEL_xxBROADCOM_BCM5400:
367 brgphy_bcm5401_dspcode(sc);
368 break;
984263bc 369 case MII_MODEL_xxBROADCOM_BCM5401:
0ecb11d7
SZ		 370 if (sc->mii_rev == 1 || sc->mii_rev == 3)
371 brgphy_bcm5401_dspcode(sc);
372 break;
984263bc 373 case MII_MODEL_xxBROADCOM_BCM5411:
0ecb11d7 374 brgphy_bcm5411_dspcode(sc);
984263bc
MD		 375 break;
376 }
377 }
46ad174e 378 mii_phy_update(sc, cmd);
984263bc
MD		 379 return (0);
380}
381
46ad174e 382static void
c436375a 383brgphy_status(struct mii_softc *sc)
984263bc
MD		 384{
385 struct mii_data *mii = sc->mii_pdata;
5a020756 386 int bmcr, bmsr;
984263bc
MD		 387
388 mii->mii_media_status = IFM_AVALID;
389 mii->mii_media_active = IFM_ETHER;
390
5a020756
SZ		 391 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
392 if (bmsr & BRGPHY_BMSR_LINK)
984263bc
MD		 393 mii->mii_media_status |= IFM_ACTIVE;
394
395 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
984263bc
MD		 396 if (bmcr & BRGPHY_BMCR_LOOP)
397 mii->mii_media_active |= IFM_LOOP;
398
399 if (bmcr & BRGPHY_BMCR_AUTOEN) {
5a020756
SZ		 400 int auxsts;
401
402 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
984263bc
MD		 403 /* Erg, still trying, I guess... */
404 mii->mii_media_active |= IFM_NONE;
405 return;
406 }
407
5a020756
SZ		 408 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
409
410 switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
984263bc 411 case BRGPHY_RES_1000FD:
7f259627 412 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
984263bc
MD		 413 break;
414 case BRGPHY_RES_1000HD:
7f259627 415 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
984263bc
MD		 416 break;
417 case BRGPHY_RES_100FD:
418 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
419 break;
420 case BRGPHY_RES_100T4:
421 mii->mii_media_active |= IFM_100_T4;
422 break;
423 case BRGPHY_RES_100HD:
424 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
425 break;
426 case BRGPHY_RES_10FD:
427 mii->mii_media_active |= IFM_10_T | IFM_FDX;
428 break;
429 case BRGPHY_RES_10HD:
430 mii->mii_media_active |= IFM_10_T | IFM_HDX;
431 break;
432 default:
5a020756
SZ		 433 if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) {
434 mii->mii_media_active |= (auxsts &
435 BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T;
436 mii->mii_media_active |= (auxsts &
437 BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX;
438 break;
439 }
984263bc
MD		 440 mii->mii_media_active |= IFM_NONE;
441 break;
442 }
db861466
SZ		 443 } else {
444 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
984263bc 445 }
984263bc
MD		 446}
447
448
db861466
SZ		 449static void
450brgphy_mii_phy_auto(struct mii_softc *sc)
984263bc 451{
5a020756 452 int ktcr;
46ad174e 453
db861466 454 brgphy_reset(sc);
5a020756
SZ		 455
456 PHY_WRITE(sc, BRGPHY_MII_ANAR,
457 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
458 DELAY(1000);
459
db861466
SZ		 460 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
461 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
462 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
463 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
464 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
465 DELAY(1000);
5a020756 466
db861466
SZ		 467 PHY_WRITE(sc, BRGPHY_MII_BMCR,
468 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
469 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
984263bc
MD		 470}
471
472static void
473brgphy_loop(struct mii_softc *sc)
474{
46ad174e 475 uint32_t bmsr;
984263bc
MD		 476 int i;
477
478 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
479 for (i = 0; i < 15000; i++) {
480 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
46ad174e 481 if (!(bmsr & BRGPHY_BMSR_LINK))
984263bc 482 break;
984263bc
MD		 483 DELAY(10);
484 }
485}
486
46ad174e
SZ		 487static void
488brgphy_reset(struct mii_softc *sc)
489{
46ad174e
SZ		 490 mii_phy_reset(sc);
491
0ecb11d7
SZ		 492 switch (sc->mii_model) {
493 case MII_MODEL_xxBROADCOM_BCM5400:
494 brgphy_bcm5401_dspcode(sc);
495 break;
496 case MII_MODEL_xxBROADCOM_BCM5401:
497 if (sc->mii_rev == 1 || sc->mii_rev == 3)
498 brgphy_bcm5401_dspcode(sc);
499 break;
500 case MII_MODEL_xxBROADCOM_BCM5411:
501 brgphy_bcm5411_dspcode(sc);
502 break;
503 case MII_MODEL_xxBROADCOM_BCM5421:
504 brgphy_bcm5421_dspcode(sc);
505 break;
506 case MII_MODEL_xxBROADCOM_BCM54K2:
507 brgphy_bcm54k2_dspcode(sc);
508 break;
509 }
510
f31c6e4d
SZ		 511 if (sc->mii_privtag != MII_PRIVTAG_BRGPHY)
512 return;
513
f31c6e4d
SZ		 514 if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG)
515 brgphy_adc_bug(sc);
516 if (sc->mii_priv & BRGPHY_FLAG_5704_A0)
517 brgphy_5704_a0_bug(sc);
518 if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) {
519 brgphy_ber_bug(sc);
520 } else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) {
521 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
522 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
523
524 if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) {
525 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
526 PHY_WRITE(sc, BRGPHY_TEST1,
527 BRGPHY_TEST1_TRIM_EN | 0x4);
d0092544 528 } else {
f31c6e4d 529 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
d0092544 530 }
f31c6e4d
SZ		 531
532 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
533 }
534 if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG)
535 brgphy_crc_bug(sc);
536 if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC)
537 brgphy_disable_early_dac(sc);
538
539 /* Set Jumbo frame settings in the PHY. */
540 brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu);
541
542 /* Adjust output voltage */
543 if (sc->mii_priv & BRGPHY_FLAG_5906)
544 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
545
546 /* Enable Ethernet@Wirespeed */
547 if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
548 brgphy_eth_wirespeed(sc);
549
550 /* Enable Link LED on Dell boxes */
551 if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) {
552 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
553 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
554 ~BRGPHY_PHY_EXTCTL_3_LED);
46ad174e
SZ		 555 }
556}
557
984263bc
MD		 558/* Turn off tap power management on 5401. */
559static void
46ad174e 560brgphy_bcm5401_dspcode(struct mii_softc *sc)
984263bc
MD		 561{
562 static const struct {
563 int reg;
564 uint16_t val;
565 } dspcode[] = {
566 { BRGPHY_MII_AUXCTL, 0x0c20 },
567 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
568 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
569 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
570 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
571 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
572 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
573 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
574 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
575 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
576 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
577 { 0, 0 },
578 };
579 int i;
580
581 for (i = 0; dspcode[i].reg != 0; i++)
582 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
583 DELAY(40);
584}
585
46ad174e 586/* Setting some undocumented voltage */
984263bc 587static void
46ad174e 588brgphy_bcm5411_dspcode(struct mii_softc *sc)
984263bc
MD		 589{
590 static const struct {
591 int reg;
592 uint16_t val;
593 } dspcode[] = {
594 { 0x1c, 0x8c23 },
595 { 0x1c, 0x8ca3 },
596 { 0x1c, 0x8c23 },
597 { 0, 0 },
598 };
599 int i;
600
601 for (i = 0; dspcode[i].reg != 0; i++)
602 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
603}
604
605static void
46ad174e
SZ		 606brgphy_bcm5421_dspcode(struct mii_softc *sc)
607{
608 uint16_t data;
609
610 /* Set Class A mode */
611 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
612 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
613 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
614
615 /* Set FFE gamma override to -0.125 */
616 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
617 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
618 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
619 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
620 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
621 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
622}
623
624static void
625brgphy_bcm54k2_dspcode(struct mii_softc *sc)
626{
627 static const struct {
628 int reg;
629 uint16_t val;
630 } dspcode[] = {
631 { 4, 0x01e1 },
632 { 9, 0x0300 },
633 { 0, 0 },
634 };
635 int i;
636
637 for (i = 0; dspcode[i].reg != 0; i++)
638 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
639}
640
641static void
0ecb11d7 642brgphy_adc_bug(struct mii_softc *sc)
984263bc
MD		 643{
644 static const struct {
645 int reg;
646 uint16_t val;
647 } dspcode[] = {
648 { BRGPHY_MII_AUXCTL, 0x0c00 },
649 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
650 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
0ecb11d7
SZ		 651 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
652 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
653 { BRGPHY_MII_AUXCTL, 0x0400 },
984263bc
MD		 654 { 0, 0 },
655 };
656 int i;
657
658 for (i = 0; dspcode[i].reg != 0; i++)
659 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
660}
661
662static void
0ecb11d7 663brgphy_5704_a0_bug(struct mii_softc *sc)
984263bc
MD		 664{
665 static const struct {
666 int reg;
667 u_int16_t val;
668 } dspcode[] = {
669 { 0x1c, 0x8d68 },
670 { 0x1c, 0x8d68 },
671 { 0, 0 },
672 };
673 int i;
674
675 for (i = 0; dspcode[i].reg != 0; i++)
676 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
677}
678
679static void
0ecb11d7 680brgphy_ber_bug(struct mii_softc *sc)
984263bc 681{
46ad174e
SZ		 682 static const struct {
683 int reg;
684 uint16_t val;
685 } dspcode[] = {
686 { BRGPHY_MII_AUXCTL, 0x0c00 },
687 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
688 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
689 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
690 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
691 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
692 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
693 { BRGPHY_MII_AUXCTL, 0x0400 },
694 { 0, 0 },
695 };
696 int i;
984263bc 697
46ad174e
SZ		 698 for (i = 0; dspcode[i].reg != 0; i++)
699 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
700}
984263bc 701
46ad174e 702static void
0ecb11d7 703brgphy_crc_bug(struct mii_softc *sc)
46ad174e 704{
0ecb11d7
SZ		 705 static const struct {
706 int reg;
707 uint16_t val;
708 } dspcode[] = {
709 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
710 { 0x1c, 0x8c68 },
711 { 0x1c, 0x8d68 },
712 { 0x1c, 0x8c68 },
713 { 0, 0 },
714 };
715 int i;
716
717 for (i = 0; dspcode[i].reg != 0; i++)
718 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
719}
720
721static void
722brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
723{
724 uint32_t val;
725
726 /* Set or clear jumbo frame settings in the PHY. */
727 if (mtu > ETHER_MAX_LEN) {
728 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
729 /* BCM5401 PHY cannot read-modify-write. */
730 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
731 } else {
732 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
733 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
734 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
735 val | BRGPHY_AUXCTL_LONG_PKT);
736 }
737
738 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
739 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
740 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
741 } else {
742 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
743 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
744 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
745 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
746
747 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
748 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
749 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
7e40b8c5 750 }
984263bc 751}
0ecb11d7
SZ		 752
753static void
754brgphy_eth_wirespeed(struct mii_softc *sc)
755{
756 u_int32_t val;
757
758 /* Enable Ethernet@Wirespeed */
759 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
760 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
761 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
762}
d0092544
SZ		 763
764static void
765brgphy_disable_early_dac(struct mii_softc *sc)
766{
767 uint32_t val;
768
769 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
770 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
771 val &= ~(1 << 8);
772 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
773}
DragonFly Project GIT Source repo