miidevs.h: regen
[dragonfly.git] / sys / dev / netif / mii_layer / miidevs.h
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1/*
2 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
984263bc 3 */
3a18dc9d 4/* $FreeBSD: src/sys/dev/mii/miidevs,v 1.4.2.13 2003/07/22 02:12:55 ps Exp $ */
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5/*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
6
7/*-
8 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
13 * NASA Ames Research Center.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the NetBSD
26 * Foundation, Inc. and its contributors.
27 * 4. Neither the name of The NetBSD Foundation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
42 */
43
44/*
45 * List of known MII OUIs.
46 * For a complete list see http://standards.ieee.org/regauth/oui/
47 *
48 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
49 * to the 16 bits available in the id registers. The MII_OUI() macro
50 * in "mii.h" reflects the most obvious way. If a vendor uses a
51 * different mapping, an "xx" prefixed OUI is defined here which is
52 * mangled accordingly to compensate.
53 */
54
55#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
56#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
9f447151 57#define MII_OUI_ATHEROS 0x001374 /* Atheros Communications */
984263bc 58#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
b381475d 59#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
46ad174e 60#define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
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61#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
62#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
63#define MII_OUI_INTEL 0x00aa00 /* Intel */
64#define MII_OUI_JATO 0x00e083 /* Jato Technologies */
db864db0 65#define MII_OUI_JMICRON 0x001b8c /* JMicron Technologies */
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66#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
67#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
68#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
69#define MII_OUI_REALTEK 0x000020 /* RealTek Semicondctor */
46ad174e 70#define MII_OUI_REALTEK2 0x00e04c /* RealTek Semicondctor */
984263bc 71#define MII_OUI_SEEQ 0x00a07d /* Seeq */
9a5b6617 72#define MII_OUI_AGERE 0x00a0bc /* Agere Systems */
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73#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
74#define MII_OUI_TDK 0x00c039 /* TDK */
75#define MII_OUI_TI 0x080028 /* Texas Instruments */
76#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
77#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
46ad174e 78#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
7896c317 79#define MII_OUI_VITESSE 0x0001c1 /* Vitesse Semiconductor */
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80
81/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
82#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
83
84/* Intel 82553 A/B steppings */
85#define MII_OUI_xxINTEL 0x00f800 /* Intel */
86
87/* some vendors have the bits swapped within bytes
88 (ie, ordered as on the wire) */
89#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
90#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
91#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
92#define MII_OUI_xxSEEQ 0x0005be /* Seeq */
93#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
94#define MII_OUI_xxTI 0x100014 /* Texas Instruments */
95#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
96
97/* Level 1 is completely different - from right to left.
98 (Two bits get lost in the third OUI byte.) */
99#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
46ad174e 100#define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */
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101
102/* Don't know what's going on here. */
103#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
6ccf6638 104#define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom Corporation */
984263bc 105
7896c317 106/* This is the OUI of the gigE PHY in the RealTek 8211B/8169S/8110S chips */
e2d6d204 107#define MII_OUI_xxREALTEK 0x000732 /* */
984263bc 108
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109#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
110#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
111
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112/*
113 * List of known models. Grouped by oui.
114 */
115
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116/* Agere Systems PHYs */
117#define MII_MODEL_AGERE_ET1011C 0x0004
118#define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
119
984263bc 120/* Altima Communications PHYs */
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121#define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001
122#define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 media interface"
123#define MII_MODEL_xxALTIMA_AC101L 0x0012
124#define MII_STR_xxALTIMA_AC101L "AC101L 10/100 media interface"
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125#define MII_MODEL_xxALTIMA_AC101 0x0021
126#define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
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127/* AMD Am79C875 have ALTIMA OUI */
128#define MII_MODEL_xxALTIMA_Am79C875 0x0014
129#define MII_STR_xxALTIMA_Am79C875 "Am79C875 10/100 media interface"
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130
131/* Advanced Micro Devices PHYs */
132#define MII_MODEL_xxAMD_79C873 0x0000
133#define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
134#define MII_MODEL_AMD_79c973phy 0x0036
135#define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
136#define MII_MODEL_AMD_79c978 0x0039
137#define MII_STR_AMD_79c978 "Am79c978 HomePNA PHY"
138
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139/* Atheros Communications/Attansic PHYs. */
140#define MII_MODEL_ATHEROS_F1 0x0001
141#define MII_STR_ATHEROS_F1 "Atheros F1 10/100/1000 PHY"
142#define MII_MODEL_ATHEROS_F2 0x0002
143#define MII_STR_ATHEROS_F2 "Atheros F2 10/100 PHY"
144
984263bc 145/* Broadcom Corp. PHYs. */
46ad174e 146#define MII_MODEL_BROADCOM_BCM5400 0x0004
ede40c20 147#define MII_STR_BROADCOM_BCM5400 "BCM5400 100/1000baseT PHY"
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148#define MII_MODEL_BROADCOM_BCM5401 0x0005
149#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY"
150#define MII_MODEL_BROADCOM_BCM5411 0x0007
151#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY"
152#define MII_MODEL_BROADCOM_3C905B 0x0012
153#define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY"
154#define MII_MODEL_BROADCOM_3C905C 0x0017
155#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
156#define MII_MODEL_BROADCOM_BCM5221 0x001e
157#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY"
158#define MII_MODEL_BROADCOM_BCM5201 0x0021
159#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY"
160#define MII_MODEL_BROADCOM_BCM5214 0x0028
161#define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY"
162#define MII_MODEL_BROADCOM_BCM5222 0x0032
163#define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY"
164#define MII_MODEL_BROADCOM_BCM5220 0x0033
165#define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY"
166#define MII_MODEL_BROADCOM_BCM4401 0x0036
167#define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY"
984263bc 168#define MII_MODEL_xxBROADCOM_BCM5400 0x0004
ede40c20 169#define MII_STR_xxBROADCOM_BCM5400 "Broadcom 100/1000baseT PHY"
984263bc 170#define MII_MODEL_xxBROADCOM_BCM5401 0x0005
ede40c20 171#define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY"
984263bc 172#define MII_MODEL_xxBROADCOM_BCM5411 0x0007
ede40c20 173#define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY"
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174#define MII_MODEL_xxBROADCOM_BCM5462 0x000d
175#define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY"
176#define MII_MODEL_xxBROADCOM_BCM5421 0x000e
177#define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY"
178#define MII_MODEL_xxBROADCOM_BCM5752 0x0010
179#define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY"
984263bc 180#define MII_MODEL_xxBROADCOM_BCM5701 0x0011
ede40c20 181#define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY"
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182#define MII_MODEL_xxBROADCOM_BCM5706C 0x0015
183#define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY"
984263bc 184#define MII_MODEL_xxBROADCOM_BCM5703 0x0016
ede40c20 185#define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY"
984263bc 186#define MII_MODEL_xxBROADCOM_BCM5704 0x0019
ede40c20 187#define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY"
7e40b8c5 188#define MII_MODEL_xxBROADCOM_BCM5705 0x001a
ede40c20 189#define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY"
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190#define MII_MODEL_xxBROADCOM_BCM5750 0x0018
191#define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY"
192#define MII_MODEL_xxBROADCOM_BCM54K2 0x002e
193#define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY"
194#define MII_MODEL_xxBROADCOM_BCM5714 0x0034
195#define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY"
196#define MII_MODEL_xxBROADCOM_BCM5780 0x0035
197#define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY"
198#define MII_MODEL_xxBROADCOM_BCM5708C 0x0036
199#define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY"
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200#define MII_MODEL_xxBROADCOM2_BCM5755 0x000c
201#define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY"
202#define MII_MODEL_xxBROADCOM2_BCM5787 0x000e
203#define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY"
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204#define MII_MODEL_xxBROADCOM2_BCM5709CAX 0x002c
205#define MII_STR_xxBROADCOM2_BCM5709CAX "BCM5709C(AX) 10/100/1000baseT PHY"
81f1f2b8 206#define MII_MODEL_xxBROADCOM2_BCM5722 0x002d
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207#define MII_STR_xxBROADCOM2_BCM5722 "BCM5722 10/100/1000baseT PHY"
208#define MII_MODEL_xxBROADCOM2_BCM5709C 0x003c
209#define MII_STR_xxBROADCOM2_BCM5709C "BCM5709C 10/100/1000baseT PHY"
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210#define MII_MODEL_BROADCOM2_BCM5906 0x0004
211#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX PHY"
984263bc 212
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213/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
214#define MII_MODEL_CICADA_CS8201 0x0001
ede40c20 215#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
fda59c4c 216#define MII_MODEL_CICADA_CS8201A 0x0020
ede40c20 217#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
fda59c4c 218#define MII_MODEL_CICADA_CS8201B 0x0021
ede40c20 219#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
46ad174e 220#define MII_MODEL_xxCICADA_CS8201 0x0001
ede40c20 221#define MII_STR_xxCICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
46ad174e 222#define MII_MODEL_xxCICADA_CS8201A 0x0020
ede40c20 223#define MII_STR_xxCICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
46ad174e 224#define MII_MODEL_xxCICADA_CS8201B 0x0021
ede40c20 225#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
fda59c4c 226
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227/* Davicom Semiconductor PHYs */
228#define MII_MODEL_xxDAVICOM_DM9101 0x0000
229#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
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230#define MII_MODEL_DAVICOM_DM9102 0x0004
231#define MII_STR_DAVICOM_DM9102 "DM9102 10/100 media interface"
232#define MII_MODEL_DAVICOM_DM9601 0x000c
233#define MII_STR_DAVICOM_DM9601 "DM9601 10/100 media interface"
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234
235/* Integrated Circuit Systems PHYs */
236#define MII_MODEL_xxICS_1890 0x0002
237#define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
238
239/* Intel PHYs */
240#define MII_MODEL_xxINTEL_I82553AB 0x0000
241#define MII_STR_xxINTEL_I82553AB "i83553 10/100 media interface"
242#define MII_MODEL_INTEL_I82555 0x0015
243#define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
244#define MII_MODEL_INTEL_I82562EM 0x0032
245#define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface"
246#define MII_MODEL_INTEL_I82562ET 0x0033
247#define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface"
248#define MII_MODEL_INTEL_I82553C 0x0035
249#define MII_STR_INTEL_I82553C "i82553 10/100 media interface"
250
251/* Jato Technologies PHYs */
252#define MII_MODEL_JATO_BASEX 0x0000
253#define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
254
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255/* JMicron Technologies PHYs */
256#define MII_MODEL_JMICRON_JMP211 0x0021
257#define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 media interface"
258#define MII_MODEL_JMICRON_JMP202 0x0022
259#define MII_STR_JMICRON_JMP202 "JMP202 10/100 media interface"
260
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261/* Level 1 PHYs */
262#define MII_MODEL_xxLEVEL1_LXT970 0x0000
263#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
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264#define MII_MODEL_xxLEVEL1a_LXT971 0x000e
265#define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 media interface"
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266
267/* National Semiconductor PHYs */
268#define MII_MODEL_NATSEMI_DP83840 0x0000
269#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
270#define MII_MODEL_NATSEMI_DP83843 0x0001
271#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
272#define MII_MODEL_NATSEMI_DP83891 0x0005
273#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
274#define MII_MODEL_NATSEMI_DP83861 0x0006
275#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
276
277/* Quality Semiconductor PHYs */
278#define MII_MODEL_QUALSEMI_QS6612 0x0000
279#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
280
281/* RealTek Semiconductor PHYs */
282#define MII_MODEL_REALTEK_RTL8201L 0x0020
283#define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 media interface"
e2d6d204 284#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
7896c317 285#define MII_STR_xxREALTEK_RTL8169S "8211B/RTL8169S/8110S media interface"
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286#define MII_MODEL_REALTEK2_RTL8169S 0x0011
287#define MII_STR_REALTEK2_RTL8169S "RTL8169S/8110S media interface"
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288
289/* Seeq PHYs */
290#define MII_MODEL_xxSEEQ_80220 0x0003
291#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
292#define MII_MODEL_xxSEEQ_84220 0x0004
293#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
294
295/* Silicon Integrated Systems PHYs */
296#define MII_MODEL_xxSIS_900 0x0000
297#define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
298
299/* TDK */
300#define MII_MODEL_TDK_78Q2120 0x0014
301#define MII_STR_TDK_78Q2120 "TDK 78Q2120 media interface"
302
303/* Texas Instruments PHYs */
304#define MII_MODEL_xxTI_TLAN10T 0x0001
305#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
306#define MII_MODEL_xxTI_100VGPMI 0x0002
307#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
308
309/* XaQti Corp. PHYs. */
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310#define MII_MODEL_xxXAQTI_XMACII 0x0000
311#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
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312
313/* Marvell Semiconductor PHYs */
314#define MII_MODEL_MARVELL_E1000 0x0000
315#define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"
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316#define MII_MODEL_MARVELL_E1011 0x0002
317#define MII_STR_MARVELL_E1011 "Marvell Semiconductor 88E1011 Gigabit PHY"
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318#define MII_MODEL_MARVELL_E1000_3 0x0003
319#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
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320#define MII_MODEL_MARVELL_E1000S 0x0004
321#define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
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322#define MII_MODEL_MARVELL_E1000_5 0x0005
323#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
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324#define MII_MODEL_MARVELL_E1101 0x0006
325#define MII_STR_MARVELL_E1101 "Marvell 88E1101 Gigabit PHY"
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326#define MII_MODEL_MARVELL_E3082 0x0008
327#define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 PHY"
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328#define MII_MODEL_MARVELL_E1112 0x0009
329#define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
330#define MII_MODEL_MARVELL_E1149 0x000b
331#define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
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332#define MII_MODEL_MARVELL_E1111 0x000c
333#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
334#define MII_MODEL_MARVELL_E1116 0x0021
335#define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
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336#define MII_MODEL_MARVELL_E1118 0x0022
337#define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
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338#define MII_MODEL_MARVELL_E1116R 0x0024
339#define MII_STR_MARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
340#define MII_MODEL_MARVELL_E1149R 0x0025
341#define MII_STR_MARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY"
342#define MII_MODEL_MARVELL_E3016 0x0026
343#define MII_STR_MARVELL_E3016 "Marvell 88E3016 10/100 PHY"
344#define MII_MODEL_MARVELL_PHYG65G 0x0027
345#define MII_STR_MARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY"
346#define MII_MODEL_xxMARVELL_E1011 0x0002
347#define MII_STR_xxMARVELL_E1011 "Marvell 88E1000 Gigabit PHY"
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348#define MII_MODEL_xxMARVELL_E1000_3 0x0003
349#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
350#define MII_MODEL_xxMARVELL_E1000_5 0x0005
351#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
352#define MII_MODEL_xxMARVELL_E1111 0x000c
353#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
354
355/* IC Plus Corp. PHYs */
356#define MII_MODEL_ICPLUS_IP101 0x0005
357#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
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SZ
358#define MII_MODEL_ICPLUS_IP1000A 0x0008
359#define MII_STR_ICPLUS_IP1000A "IC Plus 10/100/1000 media interface"
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HT
360
361/* Vitesse Semiconductor PHYs */
362#define MII_MODEL_VITESSE_VSC8601 0x0002
363#define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000TX PHY"
364