ed(4): Replace a forgotten crit_exit() with lwkt_serialize_exit().
[dragonfly.git] / sys / dev / netif / ed / if_ed.c
CommitLineData
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1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1f18ea8c 27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
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28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
1f18ea8c
JS
40#include "opt_ed.h"
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/sockio.h>
45#include <sys/mbuf.h>
46#include <sys/kernel.h>
47#include <sys/socket.h>
48#include <sys/syslog.h>
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49#include <sys/module.h>
50#include <sys/bus.h>
984263bc 51#include <sys/rman.h>
1f7ab7c9 52#include <sys/thread2.h>
b47b3275 53#include <sys/machintr.h>
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54
55#include <net/ethernet.h>
56#include <net/if.h>
68adc7bf 57#include <net/ifq_var.h>
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58#include <net/if_arp.h>
59#include <net/if_dl.h>
60#include <net/if_mib.h>
61#include <net/if_media.h>
62
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63#ifndef ED_NO_MIIBUS
64#include <dev/netif/mii_layer/mii.h>
65#include <dev/netif/mii_layer/miivar.h>
66#endif
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67
68#include <net/bpf.h>
984263bc 69
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70#include <machine/md_var.h>
71
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72#include "if_edreg.h"
73#include "if_edvar.h"
984263bc 74
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75devclass_t ed_devclass;
76
b5101a88 77static void ed_init (void *);
bd4539cc 78static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
b5101a88
RG
79static void ed_start (struct ifnet *);
80static void ed_reset (struct ifnet *);
81static void ed_watchdog (struct ifnet *);
1f18ea8c 82#ifndef ED_NO_MIIBUS
b5101a88 83static void ed_tick (void *);
1f18ea8c 84#endif
984263bc 85
b5101a88 86static void ds_getmcaf (struct ed_softc *, u_int32_t *);
984263bc 87
27b16ba9 88static void ed_get_packet (struct ed_softc *, char *, u_short);
984263bc 89
b5101a88
RG
90static __inline void ed_rint (struct ed_softc *);
91static __inline void ed_xmit (struct ed_softc *);
92static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
27b16ba9 93 u_short);
b5101a88 94static void ed_hpp_set_physical_link (struct ed_softc *);
27b16ba9
SZ
95static void ed_hpp_readmem (struct ed_softc *, u_short, u_char *, u_short);
96static void ed_hpp_writemem (struct ed_softc *, u_char *, u_short, u_short);
97static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *, int);
984263bc 98
27b16ba9 99static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *, int);
984263bc 100
b5101a88 101static void ed_setrcr (struct ed_softc *);
984263bc 102
1f18ea8c 103static uint32_t ds_mchash (const uint8_t *);
984263bc 104
32832096
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105DECLARE_DUMMY_MODULE(if_ed);
106
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107/*
108 * Interrupt conversion table for WD/SMC ASIC/83C584
109 */
27b16ba9 110static u_short ed_intr_val[] = {
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111 9,
112 3,
113 5,
114 7,
115 10,
116 11,
117 15,
118 4
119};
120
121/*
122 * Interrupt conversion table for 83C790
123 */
27b16ba9 124static u_short ed_790_intr_val[] = {
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125 0,
126 9,
127 3,
128 5,
129 7,
130 10,
131 11,
132 15
133};
134
135/*
136 * Interrupt conversion table for the HP PC LAN+
137 */
138
27b16ba9 139static u_short ed_hpp_intr_val[] = {
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140 0, /* 0 */
141 0, /* 1 */
142 0, /* 2 */
143 3, /* 3 */
144 4, /* 4 */
145 5, /* 5 */
146 6, /* 6 */
147 7, /* 7 */
148 0, /* 8 */
149 9, /* 9 */
150 10, /* 10 */
151 11, /* 11 */
152 12, /* 12 */
153 0, /* 13 */
154 0, /* 14 */
155 15 /* 15 */
156};
157
158/*
159 * Generic probe routine for testing for the existance of a DS8390.
160 * Must be called after the NIC has just been reset. This routine
161 * works by looking at certain register values that are guaranteed
162 * to be initialized a certain way after power-up or reset. Seems
163 * not to currently work on the 83C690.
164 *
165 * Specifically:
166 *
167 * Register reset bits set bits
168 * Command Register (CR) TXP, STA RD2, STP
169 * Interrupt Status (ISR) RST
170 * Interrupt Mask (IMR) All bits
171 * Data Control (DCR) LAS
172 * Transmit Config. (TCR) LB1, LB0
173 *
174 * We only look at the CR and ISR registers, however, because looking at
175 * the others would require changing register pages (which would be
176 * intrusive if this isn't an 8390).
177 *
178 * Return 1 if 8390 was found, 0 if not.
179 */
180
181int
27b16ba9 182ed_probe_generic8390(struct ed_softc *sc)
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183{
184 if ((ed_nic_inb(sc, ED_P0_CR) &
185 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
186 (ED_CR_RD2 | ED_CR_STP))
187 return (0);
188 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
189 return (0);
190
191 return (1);
192}
193
194/*
195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
196 */
197int
27b16ba9 198ed_probe_WD80x3_generic(device_t dev, int flags, u_short *intr_vals[])
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199{
200 struct ed_softc *sc = device_get_softc(dev);
201 int error;
202 int i;
203 u_int memsize, maddr;
204 u_char iptr, isa16bit, sum, totalsum;
205 u_long conf_maddr, conf_msize, irq, junk;
206
207 sc->chip_type = ED_CHIP_TYPE_DP8390;
208
209 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
210 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
211 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
212 DELAY(10000);
213 }
214 else
215 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
216
217 /*
218 * Attempt to do a checksum over the station address PROM. If it
219 * fails, it's probably not a SMC/WD board. There is a problem with
220 * this, though: some clone WD boards don't pass the checksum test.
221 * Danpex boards for one.
222 */
223 for (sum = 0, i = 0; i < 8; ++i)
224 sum += ed_asic_inb(sc, ED_WD_PROM + i);
225
226 if (sum != totalsum) {
227
228 /*
229 * Checksum is invalid. This often happens with cheap WD8003E
230 * clones. In this case, the checksum byte (the eighth byte)
231 * seems to always be zero.
232 */
233 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
234 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
235 return (ENXIO);
236 }
237 /* reset card to force it into a known state. */
238 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
239 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
240 else
241 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
242
243 DELAY(100);
244 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
245 /* wait in the case this card is reading its EEROM */
246 DELAY(5000);
247
248 sc->vendor = ED_VENDOR_WD_SMC;
249 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
250
251 /*
252 * Set initial values for width/size.
253 */
254 memsize = 8192;
255 isa16bit = 0;
256 switch (sc->type) {
257 case ED_TYPE_WD8003S:
258 sc->type_str = "WD8003S";
259 break;
260 case ED_TYPE_WD8003E:
261 sc->type_str = "WD8003E";
262 break;
263 case ED_TYPE_WD8003EB:
264 sc->type_str = "WD8003EB";
265 break;
266 case ED_TYPE_WD8003W:
267 sc->type_str = "WD8003W";
268 break;
269 case ED_TYPE_WD8013EBT:
270 sc->type_str = "WD8013EBT";
271 memsize = 16384;
272 isa16bit = 1;
273 break;
274 case ED_TYPE_WD8013W:
275 sc->type_str = "WD8013W";
276 memsize = 16384;
277 isa16bit = 1;
278 break;
279 case ED_TYPE_WD8013EP: /* also WD8003EP */
280 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
281 isa16bit = 1;
282 memsize = 16384;
283 sc->type_str = "WD8013EP";
284 } else {
285 sc->type_str = "WD8003EP";
286 }
287 break;
288 case ED_TYPE_WD8013WC:
289 sc->type_str = "WD8013WC";
290 memsize = 16384;
291 isa16bit = 1;
292 break;
293 case ED_TYPE_WD8013EBP:
294 sc->type_str = "WD8013EBP";
295 memsize = 16384;
296 isa16bit = 1;
297 break;
298 case ED_TYPE_WD8013EPC:
299 sc->type_str = "WD8013EPC";
300 memsize = 16384;
301 isa16bit = 1;
302 break;
303 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
304 case ED_TYPE_SMC8216T:
305 if (sc->type == ED_TYPE_SMC8216C) {
306 sc->type_str = "SMC8216/SMC8216C";
307 } else {
308 sc->type_str = "SMC8216T";
309 }
310
311 ed_asic_outb(sc, ED_WD790_HWR,
312 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
313 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
314 case ED_WD790_RAR_SZ64:
315 memsize = 65536;
316 break;
317 case ED_WD790_RAR_SZ32:
318 memsize = 32768;
319 break;
320 case ED_WD790_RAR_SZ16:
321 memsize = 16384;
322 break;
323 case ED_WD790_RAR_SZ8:
324 /* 8216 has 16K shared mem -- 8416 has 8K */
325 if (sc->type == ED_TYPE_SMC8216C) {
326 sc->type_str = "SMC8416C/SMC8416BT";
327 } else {
328 sc->type_str = "SMC8416T";
329 }
330 memsize = 8192;
331 break;
332 }
333 ed_asic_outb(sc, ED_WD790_HWR,
334 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
335
336 isa16bit = 1;
337 sc->chip_type = ED_CHIP_TYPE_WD790;
338 break;
339 case ED_TYPE_TOSHIBA1:
340 sc->type_str = "Toshiba1";
341 memsize = 32768;
342 isa16bit = 1;
343 break;
344 case ED_TYPE_TOSHIBA4:
345 sc->type_str = "Toshiba4";
346 memsize = 32768;
347 isa16bit = 1;
348 break;
349 default:
350 sc->type_str = "";
351 break;
352 }
353
354 /*
355 * Make some adjustments to initial values depending on what is found
356 * in the ICR.
357 */
358 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
359 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
360 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
361 isa16bit = 0;
362 memsize = 8192;
363 }
364
365 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
366 &conf_maddr, &conf_msize);
367 if (error)
368 return (error);
369
370#if ED_DEBUG
e3869ec7 371 kprintf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
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372 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
373 for (i = 0; i < 8; i++)
e3869ec7 374 kprintf("%x -> %x\n", i, ed_asic_inb(sc, i));
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375#endif
376
377 /*
378 * Allow the user to override the autoconfiguration
379 */
380 if (conf_msize > 1)
381 memsize = conf_msize;
382
383 maddr = conf_maddr;
384 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
385 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
386 maddr, maddr + memsize);
387 return (ENXIO);
388 }
389
390 /*
391 * (note that if the user specifies both of the following flags that
392 * '8bit' mode intentionally has precedence)
393 */
394 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
395 isa16bit = 1;
396 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
397 isa16bit = 0;
398
399 /*
400 * If possible, get the assigned interrupt number from the card and
401 * use it.
402 */
403 if ((sc->type & ED_WD_SOFTCONFIG) &&
404 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
405
406 /*
407 * Assemble together the encoded interrupt number.
408 */
409 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
410 ((ed_asic_inb(sc, ED_WD_IRR) &
411 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
412
413 /*
414 * If no interrupt specified (or "?"), use what the board tells us.
415 */
416 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
417 &irq, &junk);
418 if (error && intr_vals[0] != NULL) {
b47b3275
SZ
419 int intr_val = intr_vals[0][iptr];
420
984263bc 421 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
b47b3275 422 intr_val, 1, machintr_intr_cpuid(intr_val));
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MD
423 }
424 if (error)
425 return (error);
426
427 /*
428 * Enable the interrupt.
429 */
430 ed_asic_outb(sc, ED_WD_IRR,
431 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
432 }
433 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
434 ed_asic_outb(sc, ED_WD790_HWR,
435 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
436 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
437 (ed_asic_inb(sc, ED_WD790_GCR) &
438 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
439 ed_asic_outb(sc, ED_WD790_HWR,
440 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
441
442 /*
443 * If no interrupt specified (or "?"), use what the board tells us.
444 */
445 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
446 &irq, &junk);
447 if (error && intr_vals[1] != NULL) {
b47b3275
SZ
448 int intr_val = intr_vals[1][iptr];
449
984263bc 450 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
b47b3275 451 intr_val, 1, machintr_intr_cpuid(intr_val));
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MD
452 }
453 if (error)
454 return (error);
455
456 /*
457 * Enable interrupts.
458 */
459 ed_asic_outb(sc, ED_WD790_ICR,
460 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
461 }
462 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
463 &irq, &junk);
464 if (error) {
465 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
466 sc->type_str);
467 return (ENXIO);
468 }
469 sc->isa16bit = isa16bit;
470 sc->mem_shared = 1;
471
472 error = ed_alloc_memory(dev, 0, memsize);
473 if (error) {
e3869ec7 474 kprintf("*** ed_alloc_memory() failed! (%d)\n", error);
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475 return (error);
476 }
477 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
478
479 /*
480 * allocate one xmit buffer if < 16k, two buffers otherwise
481 */
482 if ((memsize < 16384) ||
483 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
484 sc->txb_cnt = 1;
485 } else {
486 sc->txb_cnt = 2;
487 }
488 sc->tx_page_start = ED_WD_PAGE_OFFSET;
489 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
490 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
491 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
492 sc->mem_size = memsize;
493 sc->mem_end = sc->mem_start + memsize;
494
495 /*
496 * Get station address from on-board ROM
497 */
498 for (i = 0; i < ETHER_ADDR_LEN; ++i)
499 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
500
501 /*
502 * Set upper address bits and 8/16 bit access to shared memory.
503 */
504 if (isa16bit) {
505 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
506 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
507 } else {
508 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
509 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
510 }
511 /*
512 * Enable 16bit access
513 */
514 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
515 ED_WD_LAAR_M16EN);
516 } else {
517 if (((sc->type & ED_WD_SOFTCONFIG) ||
518 (sc->type == ED_TYPE_TOSHIBA1) ||
519 (sc->type == ED_TYPE_TOSHIBA4) ||
520 (sc->type == ED_TYPE_WD8013EBT)) &&
521 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
522 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
523 ED_WD_LAAR_ADDRHI;
524 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
525 }
526 }
527
528 /*
529 * Set address and enable interface shared memory.
530 */
531 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
532 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
533 ed_asic_outb(sc, ED_WD_MSR + 1,
534 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
535 ed_asic_outb(sc, ED_WD_MSR + 2,
536 ((kvtop(sc->mem_start) >> 16) & 0x0f));
537 ed_asic_outb(sc, ED_WD_MSR,
538 ED_WD_MSR_MENB | ED_WD_MSR_POW);
539 } else {
540 ed_asic_outb(sc, ED_WD_MSR,
541 ((kvtop(sc->mem_start) >> 13) &
542 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
543 }
544 sc->cr_proto = ED_CR_RD2;
545 } else {
546 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
547 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
548 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
549 ((kvtop(sc->mem_start) >> 11) & 0x40) |
550 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
551 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
552 sc->cr_proto = 0;
553 }
554
555#if 0
e3869ec7 556 kprintf("starting memory performance test at 0x%x, size %d...\n",
984263bc
MD
557 sc->mem_start, memsize*16384);
558 for (i = 0; i < 16384; i++)
559 bzero(sc->mem_start, memsize);
e3869ec7 560 kprintf("***DONE***\n");
984263bc
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561#endif
562
563 /*
564 * Now zero memory and verify that it is clear
565 */
566 bzero(sc->mem_start, memsize);
567
568 for (i = 0; i < memsize; ++i) {
569 if (sc->mem_start[i]) {
79d1f4a5 570 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
1f18ea8c 571 (long long)kvtop(sc->mem_start + i));
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572
573 /*
574 * Disable 16 bit access to shared memory
575 */
576 if (isa16bit) {
577 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
578 ed_asic_outb(sc, ED_WD_MSR, 0x00);
579 }
580 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
581 ~ED_WD_LAAR_M16EN);
582 }
583 return (ENXIO);
584 }
585 }
586
587 /*
588 * Disable 16bit access to shared memory - we leave it
589 * disabled so that 1) machines reboot properly when the board
590 * is set 16 bit mode and there are conflicting 8bit
591 * devices/ROMS in the same 128k address space as this boards
592 * shared memory. and 2) so that other 8 bit devices with
593 * shared memory can be used in this 128k region, too.
594 */
595 if (isa16bit) {
596 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
597 ed_asic_outb(sc, ED_WD_MSR, 0x00);
598 }
599 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
600 ~ED_WD_LAAR_M16EN);
601 }
602 return (0);
603}
604
605int
27b16ba9 606ed_probe_WD80x3(device_t dev, int port_rid, int flags)
984263bc
MD
607{
608 struct ed_softc *sc = device_get_softc(dev);
609 int error;
27b16ba9 610 static u_short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
984263bc
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611
612 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
613 if (error)
614 return (error);
615
616 sc->asic_offset = ED_WD_ASIC_OFFSET;
617 sc->nic_offset = ED_WD_NIC_OFFSET;
618
619 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
620}
621
622/*
623 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
624 */
625int
27b16ba9 626ed_probe_3Com(device_t dev, int port_rid, int flags)
984263bc
MD
627{
628 struct ed_softc *sc = device_get_softc(dev);
629 int error;
630 int i;
631 u_int memsize;
632 u_char isa16bit;
633 u_long conf_maddr, conf_msize, irq, junk;
634
635 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
636 if (error)
637 return (error);
638
639 sc->asic_offset = ED_3COM_ASIC_OFFSET;
640 sc->nic_offset = ED_3COM_NIC_OFFSET;
641
642 /*
643 * Verify that the kernel configured I/O address matches the board
644 * configured address
645 */
646 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
647 case ED_3COM_BCFR_300:
648 if (rman_get_start(sc->port_res) != 0x300)
649 return (ENXIO);
650 break;
651 case ED_3COM_BCFR_310:
652 if (rman_get_start(sc->port_res) != 0x310)
653 return (ENXIO);
654 break;
655 case ED_3COM_BCFR_330:
656 if (rman_get_start(sc->port_res) != 0x330)
657 return (ENXIO);
658 break;
659 case ED_3COM_BCFR_350:
660 if (rman_get_start(sc->port_res) != 0x350)
661 return (ENXIO);
662 break;
663 case ED_3COM_BCFR_250:
664 if (rman_get_start(sc->port_res) != 0x250)
665 return (ENXIO);
666 break;
667 case ED_3COM_BCFR_280:
668 if (rman_get_start(sc->port_res) != 0x280)
669 return (ENXIO);
670 break;
671 case ED_3COM_BCFR_2A0:
672 if (rman_get_start(sc->port_res) != 0x2a0)
673 return (ENXIO);
674 break;
675 case ED_3COM_BCFR_2E0:
676 if (rman_get_start(sc->port_res) != 0x2e0)
677 return (ENXIO);
678 break;
679 default:
680 return (ENXIO);
681 }
682
683 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
684 &conf_maddr, &conf_msize);
685 if (error)
686 return (error);
687
688 /*
689 * Verify that the kernel shared memory address matches the board
690 * configured address.
691 */
692 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
693 case ED_3COM_PCFR_DC000:
694 if (conf_maddr != 0xdc000)
695 return (ENXIO);
696 break;
697 case ED_3COM_PCFR_D8000:
698 if (conf_maddr != 0xd8000)
699 return (ENXIO);
700 break;
701 case ED_3COM_PCFR_CC000:
702 if (conf_maddr != 0xcc000)
703 return (ENXIO);
704 break;
705 case ED_3COM_PCFR_C8000:
706 if (conf_maddr != 0xc8000)
707 return (ENXIO);
708 break;
709 default:
710 return (ENXIO);
711 }
712
713
714 /*
715 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
716 * sequence because it'll lock up if the cable isn't connected if we
717 * don't.
718 */
719 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
720
721 /*
722 * Wait for a while, then un-reset it
723 */
724 DELAY(50);
725
726 /*
727 * The 3Com ASIC defaults to rather strange settings for the CR after
728 * a reset - it's important to set it again after the following outb
729 * (this is done when we map the PROM below).
730 */
731 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
732
733 /*
734 * Wait a bit for the NIC to recover from the reset
735 */
736 DELAY(5000);
737
738 sc->vendor = ED_VENDOR_3COM;
739 sc->type_str = "3c503";
740 sc->mem_shared = 1;
741 sc->cr_proto = ED_CR_RD2;
742
743 /*
744 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
745 * to it.
746 */
747 memsize = 8192;
748
749 /*
750 * Get station address from on-board ROM
751 */
752
753 /*
754 * First, map ethernet address PROM over the top of where the NIC
755 * registers normally appear.
756 */
757 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
758
759 for (i = 0; i < ETHER_ADDR_LEN; ++i)
760 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
761
762 /*
763 * Unmap PROM - select NIC registers. The proper setting of the
764 * tranceiver is set in ed_init so that the attach code is given a
765 * chance to set the default based on a compile-time config option
766 */
767 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
768
769 /*
770 * Determine if this is an 8bit or 16bit board
771 */
772
773 /*
774 * select page 0 registers
775 */
776 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
777
778 /*
779 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
780 * board.
781 */
782 ed_nic_outb(sc, ED_P0_DCR, 0);
783
784 /*
785 * select page 2 registers
786 */
787 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
788
789 /*
790 * The 3c503 forces the WTS bit to a one if this is a 16bit board
791 */
792 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
793 isa16bit = 1;
794 else
795 isa16bit = 0;
796
797 /*
798 * select page 0 registers
799 */
800 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
801
802 error = ed_alloc_memory(dev, 0, memsize);
803 if (error)
804 return (error);
805
806 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
807 sc->mem_size = memsize;
808 sc->mem_end = sc->mem_start + memsize;
809
810 /*
811 * We have an entire 8k window to put the transmit buffers on the
812 * 16bit boards. But since the 16bit 3c503's shared memory is only
813 * fast enough to overlap the loading of one full-size packet, trying
814 * to load more than 2 buffers can actually leave the transmitter idle
815 * during the load. So 2 seems the best value. (Although a mix of
816 * variable-sized packets might change this assumption. Nonetheless,
817 * we optimize for linear transfers of same-size packets.)
818 */
819 if (isa16bit) {
820 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
821 sc->txb_cnt = 1;
822 else
823 sc->txb_cnt = 2;
824
825 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
826 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
827 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
828 ED_3COM_RX_PAGE_OFFSET_16BIT;
829 sc->mem_ring = sc->mem_start;
830 } else {
831 sc->txb_cnt = 1;
832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
833 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
834 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
835 ED_3COM_TX_PAGE_OFFSET_8BIT;
836 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
837 }
838
839 sc->isa16bit = isa16bit;
840
841 /*
842 * Initialize GA page start/stop registers. Probably only needed if
843 * doing DMA, but what the hell.
844 */
845 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
846 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
847
848 /*
849 * Set IRQ. 3c503 only allows a choice of irq 2-5.
850 */
851 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
852 if (error)
853 return (error);
854
855 switch (irq) {
856 case 2:
857 case 9:
858 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
859 break;
860 case 3:
861 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
862 break;
863 case 4:
864 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
865 break;
866 case 5:
867 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
868 break;
869 default:
870 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
871 irq);
872 return (ENXIO);
873 }
874
875 /*
876 * Initialize GA configuration register. Set bank and enable shared
877 * mem.
878 */
879 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
880 ED_3COM_GACFR_MBS0);
881
882 /*
883 * Initialize "Vector Pointer" registers. These gawd-awful things are
884 * compared to 20 bits of the address on ISA, and if they match, the
885 * shared memory is disabled. We set them to 0xffff0...allegedly the
886 * reset vector.
887 */
888 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
889 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
890 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
891
892 /*
893 * Zero memory and verify that it is clear
894 */
895 bzero(sc->mem_start, memsize);
896
897 for (i = 0; i < memsize; ++i)
898 if (sc->mem_start[i]) {
27b16ba9
SZ
899 device_printf(dev, "failed to clear shared memory "
900 "at %llx - check configuration\n",
901 (unsigned long long)kvtop(sc->mem_start + i));
984263bc
MD
902 return (ENXIO);
903 }
904 return (0);
905}
906
907/*
79d1f4a5
HP
908 * Probe and vendor-specific initialization routine for SIC boards
909 */
910int
27b16ba9 911ed_probe_SIC(device_t dev, int port_rid, int flags)
79d1f4a5
HP
912{
913 struct ed_softc *sc = device_get_softc(dev);
914 int error;
915 int i;
916 u_int memsize;
917 u_long conf_maddr, conf_msize;
918 u_char sum;
919
920 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
921 if (error)
922 return (error);
923
924 sc->asic_offset = ED_SIC_ASIC_OFFSET;
925 sc->nic_offset = ED_SIC_NIC_OFFSET;
926
927 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
928 &conf_maddr, &conf_msize);
929 if (error)
930 return (error);
931
932 memsize = 16384;
933 if (conf_msize > 1)
934 memsize = conf_msize;
935
936 error = ed_alloc_memory(dev, 0, memsize);
937 if (error)
938 return (error);
939
940 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
941 sc->mem_size = memsize;
942
943 /* Reset card to force it into a known state. */
944 ed_asic_outb(sc, 0, 0x00);
945 DELAY(100);
946
947 /*
948 * Here we check the card ROM, if the checksum passes, and the
949 * type code and ethernet address check out, then we know we have
950 * an SIC card.
951 */
952 ed_asic_outb(sc, 0, 0x81);
953 DELAY(100);
954
955 sum = sc->mem_start[6];
956 for (i = 0; i < ETHER_ADDR_LEN; i++) {
957 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
958 }
959#ifdef ED_DEBUG
960 device_printf(dev, "ed_probe_sic: got address %6D\n",
961 sc->arpcom.ac_enaddr, ":");
962#endif
963 if (sum != 0) {
964 return (ENXIO);
965 }
966 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
967 sc->arpcom.ac_enaddr[2]) == 0) {
968 return (ENXIO);
969 }
970
971 sc->vendor = ED_VENDOR_SIC;
972 sc->type_str = "SIC";
973 sc->isa16bit = 0;
974 sc->cr_proto = 0;
975
976 /*
977 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
978 */
979 ed_asic_outb(sc, 0, 0x80);
980 DELAY(100);
981
982 /*
983 * Now zero memory and verify that it is clear
984 */
985 bzero(sc->mem_start, sc->mem_size);
986
987 for (i = 0; i < sc->mem_size; i++) {
988 if (sc->mem_start[i]) {
989 device_printf(dev, "failed to clear shared memory "
990 "at %llx - check configuration\n",
1f18ea8c 991 (long long)kvtop(sc->mem_start + i));
79d1f4a5
HP
992
993 return (ENXIO);
994 }
995 }
996
997 sc->mem_shared = 1;
998 sc->mem_end = sc->mem_start + sc->mem_size;
999
1000 /*
1001 * allocate one xmit buffer if < 16k, two buffers otherwise
1002 */
1003 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1004 sc->txb_cnt = 1;
1005 } else {
1006 sc->txb_cnt = 2;
1007 }
1008 sc->tx_page_start = 0;
1009
1010 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1011 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1012
1013 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1014
1015 return (0);
1016}
1017
1018/*
984263bc
MD
1019 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1020 */
1021int
27b16ba9 1022ed_probe_Novell_generic(device_t dev, int flags)
984263bc
MD
1023{
1024 struct ed_softc *sc = device_get_softc(dev);
1025 u_int memsize, n;
1026 u_char romdata[16], tmp;
1027 static char test_pattern[32] = "THIS is A memory TEST pattern";
1028 char test_buffer[32];
1029
1030 /* XXX - do Novell-specific probe here */
1031
1032 /* Reset the board */
1033 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1034 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1035 DELAY(200);
1036 }
1037 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1038
1039 /*
1040 * I don't know if this is necessary; probably cruft leftover from
1041 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1f18ea8c 1042 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
984263bc
MD
1043 * non-invasive...but some boards don't seem to reset and I don't have
1044 * complete documentation on what the 'right' thing to do is...so we
1045 * do the invasive thing for now. Yuck.]
1046 */
1047 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1048 DELAY(5000);
1049
1050 /*
1051 * This is needed because some NE clones apparently don't reset the
1052 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1053 * - this makes the probe invasive! ...Done against my better
1054 * judgement. -DLG
1055 */
1056 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1057
1058 DELAY(5000);
1059
1060 /* Make sure that we really have an 8390 based board */
1061 if (!ed_probe_generic8390(sc))
1062 return (ENXIO);
1063
1064 sc->vendor = ED_VENDOR_NOVELL;
1065 sc->mem_shared = 0;
1066 sc->cr_proto = ED_CR_RD2;
1067
1068 /*
1069 * Test the ability to read and write to the NIC memory. This has the
1070 * side affect of determining if this is an NE1000 or an NE2000.
1071 */
1072
1073 /*
1074 * This prevents packets from being stored in the NIC memory when the
1075 * readmem routine turns on the start bit in the CR.
1076 */
1077 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1078
1079 /* Temporarily initialize DCR for byte operations */
1080 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1081
1082 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1083 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1084
1085 sc->isa16bit = 0;
1086
1087 /*
1088 * Write a test pattern in byte mode. If this fails, then there
1089 * probably isn't any memory at 8k - which likely means that the board
1090 * is an NE2000.
1091 */
1092 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1093 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1094
1095 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1096 sc->type = ED_TYPE_NE1000;
1097 sc->type_str = "NE1000";
1098 } else {
1099
1100 /* neither an NE1000 nor a Linksys - try NE2000 */
1101 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1102 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1103 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1104
1105 sc->isa16bit = 1;
1106
1107 /*
1108 * Write a test pattern in word mode. If this also fails, then
1109 * we don't know what this board is.
1110 */
1111 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1112 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1113 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1114 sc->type = ED_TYPE_NE2000;
1115 sc->type_str = "NE2000";
1116 } else {
1117 return (ENXIO);
1118 }
1119 }
1120
1121
1122 /* 8k of memory plus an additional 8k if 16bit */
1123 memsize = 8192 + sc->isa16bit * 8192;
1124
1125#if 0 /* probably not useful - NE boards only come two ways */
1126 /* allow kernel config file overrides */
1127 if (isa_dev->id_msize)
1128 memsize = isa_dev->id_msize;
1129#endif
1130
1131 sc->mem_size = memsize;
1132
1133 /* NIC memory doesn't start at zero on an NE board */
1134 /* The start address is tied to the bus width */
1135 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1136 sc->mem_end = sc->mem_start + memsize;
1137 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1138
1139 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1140 int x, i, mstart = 0, msize = 0;
1141 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1142
1143 for (i = 0; i < ED_PAGE_SIZE; i++)
1144 pbuf0[i] = 0;
1145
1146 /* Clear all the memory. */
1147 for (x = 1; x < 256; x++)
1148 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1149
1150 /* Search for the start of RAM. */
1151 for (x = 1; x < 256; x++) {
1152 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1153 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1154 for (i = 0; i < ED_PAGE_SIZE; i++)
1155 pbuf[i] = 255 - x;
1156 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1157 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1158 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1159 mstart = x * ED_PAGE_SIZE;
1160 msize = ED_PAGE_SIZE;
1161 break;
1162 }
1163 }
1164 }
1165
1166 if (mstart == 0) {
1167 device_printf(dev, "Cannot find start of RAM.\n");
1168 return (ENXIO);
1169 }
1170 /* Search for the start of RAM. */
1171 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1172 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1173 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1174 for (i = 0; i < ED_PAGE_SIZE; i++)
1175 pbuf[i] = 255 - x;
1176 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1177 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1178 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1179 msize += ED_PAGE_SIZE;
1180 else {
1181 break;
1182 }
1183 } else {
1184 break;
1185 }
1186 }
1187
1188 if (msize == 0) {
1189 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1190 return (ENXIO);
1191 }
1192 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1193
1194 sc->mem_size = msize;
1195 sc->mem_start = (caddr_t) mstart;
1196 sc->mem_end = (caddr_t) (msize + mstart);
1197 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1198 }
1199
1200 /*
1201 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1202 * otherwise).
1203 */
1204 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1205 sc->txb_cnt = 1;
1206 else
1207 sc->txb_cnt = 2;
1208
1209 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1210 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1211
1212 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1213
1214 ed_pio_readmem(sc, 0, romdata, 16);
1215 for (n = 0; n < ETHER_ADDR_LEN; n++)
1216 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1217
1218 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1219 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1220 sc->type_str = "Gateway AT";
1221 }
1222
1223 /* clear any pending interrupts that might have occurred above */
1224 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1225
1226 return (0);
1227}
1228
1229int
27b16ba9 1230ed_probe_Novell(device_t dev, int port_rid, int flags)
984263bc
MD
1231{
1232 struct ed_softc *sc = device_get_softc(dev);
1233 int error;
1234
1235 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1236 if (error)
1237 return (error);
1238
1239 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1240 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1241
1242 return ed_probe_Novell_generic(dev, flags);
1243}
1244
1245#define ED_HPP_TEST_SIZE 16
1246
1247/*
1248 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1249 * (HP Part nos: 27247B and 27252A).
1250 *
1251 * The card has an asic wrapper around a DS8390 core. The asic handles
1252 * host accesses and offers both standard register IO and memory mapped
1253 * IO. Memory mapped I/O allows better performance at the expense of greater
1254 * chance of an incompatibility with existing ISA cards.
1255 *
1256 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1257 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1258 * don't allow 32 bit accesses; these are indicated by a bit in the software
1259 * ID register (see if_edreg.h).
1260 *
1261 * Other caveats are: we should read the MAC address only when the card
1262 * is inactive.
1263 *
1264 * For more information; please consult the CRYNWR packet driver.
1265 *
1266 * The AUI port is turned on using the "link2" option on the ifconfig
1267 * command line.
1268 */
1269int
27b16ba9 1270ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
984263bc
MD
1271{
1272 struct ed_softc *sc = device_get_softc(dev);
1273 int error;
1274 int n; /* temp var */
1275 int memsize; /* mem on board */
1276 u_char checksum; /* checksum of board address */
1277 u_char irq; /* board configured IRQ */
1278 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1279 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1280 u_long conf_maddr, conf_msize, conf_irq, junk;
1281
1282 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1283 if (error)
1284 return (error);
1285
1286 /* Fill in basic information */
1287 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1288 sc->nic_offset = ED_HPP_NIC_OFFSET;
1289
1290 sc->chip_type = ED_CHIP_TYPE_DP8390;
1291 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1292
1293 /*
1294 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1295 */
1296
1297 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1298 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1299 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1300 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1301 return ENXIO;
1302
1303 /*
1304 * Read the MAC address and verify checksum on the address.
1305 */
1306
1307 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1308 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1309 checksum += (sc->arpcom.ac_enaddr[n] =
1310 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1311
1312 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1313
1314 if (checksum != 0xFF)
1315 return ENXIO;
1316
1317 /*
1318 * Verify that the software model number is 0.
1319 */
1320
1321 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1322 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1323 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1324 return ENXIO;
1325
1326 /*
1327 * Read in and save the current options configured on card.
1328 */
1329
1330 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1331
1332 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1333 ED_HPP_OPTION_CHIP_RESET |
1334 ED_HPP_OPTION_ENABLE_IRQ);
1335
1336 /*
1337 * Reset the chip. This requires writing to the option register
1338 * so take care to preserve the other bits.
1339 */
1340
1341 ed_asic_outw(sc, ED_HPP_OPTION,
1342 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1343 ED_HPP_OPTION_CHIP_RESET)));
1344
1345 DELAY(5000); /* wait for chip reset to complete */
1346
1347 ed_asic_outw(sc, ED_HPP_OPTION,
1348 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1349 ED_HPP_OPTION_CHIP_RESET |
1350 ED_HPP_OPTION_ENABLE_IRQ)));
1351
1352 DELAY(5000);
1353
1354 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1355 return ENXIO; /* reset did not complete */
1356
1357 /*
1358 * Read out configuration information.
1359 */
1360
1361 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1362
1363 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1364
1365 /*
1366 * Check for impossible IRQ.
1367 */
1368
c157ff7a 1369 if (irq >= NELEM(ed_hpp_intr_val))
984263bc
MD
1370 return ENXIO;
1371
1372 /*
1373 * If the kernel IRQ was specified with a '?' use the cards idea
1374 * of the IRQ. If the kernel IRQ was explicitly specified, it
1375 * should match that of the hardware.
1376 */
1377 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1378 &conf_irq, &junk);
1379 if (error) {
b47b3275
SZ
1380 int intr_val = ed_hpp_intr_val[irq];
1381
1382 bus_set_resource(dev, SYS_RES_IRQ, 0, intr_val, 1,
1383 machintr_intr_cpuid(intr_val));
984263bc
MD
1384 } else {
1385 if (conf_irq != ed_hpp_intr_val[irq])
1386 return (ENXIO);
1387 }
1388
1389 /*
1390 * Fill in softconfig info.
1391 */
1392
1393 sc->vendor = ED_VENDOR_HP;
1394 sc->type = ED_TYPE_HP_PCLANPLUS;
1395 sc->type_str = "HP-PCLAN+";
1396
1397 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1398 sc->mem_start = 0; /* we use offsets inside the card RAM */
1399
1400 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1401
1402 /*
1403 * The board has 32KB of memory. Is there a way to determine
1404 * this programmatically?
1405 */
1406
1407 memsize = 32768;
1408
1409 /*
1410 * Check if memory mapping of the I/O registers possible.
1411 */
1412
1413 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1414 {
1415 u_long mem_addr;
1416
1417 /*
1418 * determine the memory address from the board.
1419 */
1420
1421 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1422 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1423
1424 /*
1425 * Check that the kernel specified start of memory and
1426 * hardware's idea of it match.
1427 */
1428 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1429 &conf_maddr, &conf_msize);
1430 if (error)
1431 return (error);
1432
1433 if (mem_addr != conf_maddr)
1434 return ENXIO;
1435
1436 error = ed_alloc_memory(dev, 0, memsize);
1437 if (error)
1438 return (error);
1439
1440 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1441 }
1442
1443 /*
1444 * Fill in the rest of the soft config structure.
1445 */
1446
1447 /*
1448 * The transmit page index.
1449 */
1450
1451 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1452
1453 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1454 sc->txb_cnt = 1;
1455 else
1456 sc->txb_cnt = 2;
1457
1458 /*
1459 * Memory description
1460 */
1461
1462 sc->mem_size = memsize;
1463 sc->mem_ring = sc->mem_start +
1464 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1465 sc->mem_end = sc->mem_start + sc->mem_size;
1466
1467 /*
1468 * Receive area starts after the transmit area and
1469 * continues till the end of memory.
1470 */
1471
1472 sc->rec_page_start = sc->tx_page_start +
1473 (sc->txb_cnt * ED_TXBUF_SIZE);
1474 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1475
1476
1477 sc->cr_proto = 0; /* value works */
1478
1479 /*
1480 * Set the wrap registers for string I/O reads.
1481 */
1482
1483 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1484 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1485 ((sc->rec_page_start / ED_PAGE_SIZE) |
1486 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1487
1488 /*
1489 * Reset the register page to normal operation.
1490 */
1491
1492 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1493
1494 /*
1495 * Verify that we can read/write from adapter memory.
1496 * Create test pattern.
1497 */
1498
1499 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1500 {
1501 test_pattern[n] = (n*n) ^ ~n;
1502 }
1503
1504#undef ED_HPP_TEST_SIZE
1505
1506 /*
1507 * Check that the memory is accessible thru the I/O ports.
1508 * Write out the contents of "test_pattern", read back
1509 * into "test_buffer" and compare the two for any
1510 * mismatch.
1511 */
1512
1513 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1514
1515 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1516 sizeof(test_pattern));
1517 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1518 test_buffer, sizeof(test_pattern));
1519
1520 if (bcmp(test_pattern, test_buffer,
1521 sizeof(test_pattern)))
1522 return ENXIO;
1523 }
1524
1525 return (0);
1526
1527}
1528
1529/*
1530 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1531 */
1532
1f18ea8c 1533static void
984263bc
MD
1534ed_hpp_set_physical_link(struct ed_softc *sc)
1535{
1536 struct ifnet *ifp = &sc->arpcom.ac_if;
1537 int lan_page;
1538
1539 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1540 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1541
1542 if (ifp->if_flags & IFF_ALTPHYS) {
1543
1544 /*
1545 * Use the AUI port.
1546 */
1547
1548 lan_page |= ED_HPP_LAN_AUI;
1549
1550 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1551 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1552
1553
1554 } else {
1555
1556 /*
1557 * Use the ThinLan interface
1558 */
1559
1560 lan_page &= ~ED_HPP_LAN_AUI;
1561
1562 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1563 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1564
1565 }
1566
1567 /*
1568 * Wait for the lan card to re-initialize itself
1569 */
1570
1571 DELAY(150000); /* wait 150 ms */
1572
1573 /*
1574 * Restore normal pages.
1575 */
1576
1577 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1578
1579}
1580
1581/*
1582 * Allocate a port resource with the given resource id.
1583 */
1584int
27b16ba9 1585ed_alloc_port(device_t dev, int rid, int size)
984263bc
MD
1586{
1587 struct ed_softc *sc = device_get_softc(dev);
1588 struct resource *res;
1589
1590 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1591 0ul, ~0ul, size, RF_ACTIVE);
1592 if (res) {
1593 sc->port_rid = rid;
1594 sc->port_res = res;
1595 sc->port_used = size;
1596 return (0);
1597 } else {
1598 return (ENOENT);
1599 }
1600}
1601
1602/*
1603 * Allocate a memory resource with the given resource id.
1604 */
1605int
27b16ba9 1606ed_alloc_memory(device_t dev, int rid, int size)
984263bc
MD
1607{
1608 struct ed_softc *sc = device_get_softc(dev);
1609 struct resource *res;
1610
1611 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1612 0ul, ~0ul, size, RF_ACTIVE);
1613 if (res) {
1614 sc->mem_rid = rid;
1615 sc->mem_res = res;
1616 sc->mem_used = size;
1617 return (0);
1618 } else {
1619 return (ENOENT);
1620 }
1621}
1622
1623/*
1624 * Allocate an irq resource with the given resource id.
1625 */
1626int
27b16ba9 1627ed_alloc_irq(device_t dev, int rid, int flags)
984263bc
MD
1628{
1629 struct ed_softc *sc = device_get_softc(dev);
1630 struct resource *res;
1631
4e6d744d
JS
1632 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1633 (RF_ACTIVE | flags));
984263bc
MD
1634 if (res) {
1635 sc->irq_rid = rid;
1636 sc->irq_res = res;
1637 return (0);
1638 } else {
1639 return (ENOENT);
1640 }
1641}
1642
1643/*
1644 * Release all resources
1645 */
1646void
27b16ba9 1647ed_release_resources(device_t dev)
984263bc
MD
1648{
1649 struct ed_softc *sc = device_get_softc(dev);
1650
1651 if (sc->port_res) {
1f18ea8c
JS
1652 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1653 sc->port_rid, sc->port_res);
984263bc
MD
1654 bus_release_resource(dev, SYS_RES_IOPORT,
1655 sc->port_rid, sc->port_res);
1656 sc->port_res = 0;
1657 }
1658 if (sc->mem_res) {
1f18ea8c
JS
1659 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1660 sc->mem_rid, sc->mem_res);
984263bc
MD
1661 bus_release_resource(dev, SYS_RES_MEMORY,
1662 sc->mem_rid, sc->mem_res);
1663 sc->mem_res = 0;
1664 }
1665 if (sc->irq_res) {
1f18ea8c
JS
1666 bus_deactivate_resource(dev, SYS_RES_IRQ,
1667 sc->irq_rid, sc->irq_res);
984263bc
MD
1668 bus_release_resource(dev, SYS_RES_IRQ,
1669 sc->irq_rid, sc->irq_res);
1670 sc->irq_res = 0;
1671 }
1672}
1673
1674/*
1675 * Install interface into kernel networking data structures
1676 */
1677int
1f18ea8c 1678ed_attach(device_t dev)
984263bc 1679{
1f18ea8c 1680 struct ed_softc *sc = device_get_softc(dev);
984263bc
MD
1681 struct ifnet *ifp = &sc->arpcom.ac_if;
1682
4f65d502 1683 callout_init(&sc->ed_timer);
984263bc
MD
1684 /*
1685 * Set interface to stopped condition (reset)
1686 */
1687 ed_stop(sc);
1688
3e4a09e7
MD
1689 /*
1690 * Initialize ifnet structure
1691 */
1692 ifp->if_softc = sc;
1f18ea8c 1693 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1f18ea8c 1694 ifp->if_mtu = ETHERMTU;
3e4a09e7
MD
1695 ifp->if_start = ed_start;
1696 ifp->if_ioctl = ed_ioctl;
1697 ifp->if_watchdog = ed_watchdog;
1698 ifp->if_init = ed_init;
68adc7bf
JS
1699 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1700 ifq_set_ready(&ifp->if_snd);
3e4a09e7
MD
1701 ifp->if_linkmib = &sc->mibdata;
1702 ifp->if_linkmiblen = sizeof sc->mibdata;
1f18ea8c 1703 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3e4a09e7
MD
1704 /*
1705 * XXX - should do a better job.
1706 */
1707 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1708 sc->mibdata.dot3StatsEtherChipSet =
1709 DOT3CHIPSET(dot3VendorWesternDigital,
1710 dot3ChipSetWesternDigital83C790);
1711 else
1712 sc->mibdata.dot3StatsEtherChipSet =
1713 DOT3CHIPSET(dot3VendorNational,
1714 dot3ChipSetNational8390);
1715 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
984263bc 1716
3e4a09e7
MD
1717 /*
1718 * Set default state for ALTPHYS flag (used to disable the
1719 * tranceiver for AUI operation), based on compile-time
1720 * config option.
1721 */
1f18ea8c
JS
1722 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1723 ifp->if_flags |= IFF_ALTPHYS;
3e4a09e7
MD
1724
1725 /*
1726 * Attach the interface
1727 */
78195a76 1728 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
984263bc 1729
984263bc
MD
1730 /* device attach does transition from UNCONFIGURED to IDLE state */
1731
984263bc 1732 if (sc->type_str && (*sc->type_str != 0))
e3869ec7 1733 kprintf("type %s ", sc->type_str);
984263bc 1734 else
e3869ec7 1735 kprintf("type unknown (0x%x) ", sc->type);
984263bc
MD
1736
1737 if (sc->vendor == ED_VENDOR_HP)
e3869ec7 1738 kprintf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
984263bc
MD
1739 "16-bit" : "32-bit",
1740 sc->hpp_mem_start ? "memory mapped" : "regular");
1741 else
e3869ec7 1742 kprintf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
984263bc 1743
e3869ec7 1744 kprintf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
984263bc 1745 (sc->vendor == ED_VENDOR_HP)) &&
3f625015 1746 (ifp->if_flags & IFF_ALTPHYS)) ? " transceiver disabled" : "");
984263bc
MD
1747
1748 return (0);
1749}
1750
1751/*
1752 * Reset interface.
1753 */
1754static void
27b16ba9 1755ed_reset(struct ifnet *ifp)
984263bc
MD
1756{
1757 struct ed_softc *sc = ifp->if_softc;
984263bc 1758
888ab9b7
JS
1759 crit_enter();
1760
1761 if (sc->gone) {
1762 crit_exit();
984263bc 1763 return;
888ab9b7 1764 }
984263bc
MD
1765
1766 /*
1767 * Stop interface and re-initialize.
1768 */
1769 ed_stop(sc);
1770 ed_init(sc);
1771
888ab9b7 1772 crit_exit();
984263bc
MD
1773}
1774
1775/*
1776 * Take interface offline.
1777 */
1778void
27b16ba9 1779ed_stop(struct ed_softc *sc)
984263bc
MD
1780{
1781 int n = 5000;
1782
1f18ea8c 1783#ifndef ED_NO_MIIBUS
4f65d502 1784 callout_stop(&sc->ed_timer);
1f18ea8c 1785#endif
984263bc
MD
1786 if (sc->gone)
1787 return;
1788 /*
1789 * Stop everything on the interface, and select page 0 registers.
1790 */
1791 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1792
1793 /*
1794 * Wait for interface to enter stopped state, but limit # of checks to
1795 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1796 * just in case it's an old one.
1797 */
1798 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1799 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1800}
1801
1802/*
1803 * Device timeout/watchdog routine. Entered if the device neglects to
1804 * generate an interrupt after a transmit has been started on it.
1805 */
1806static void
27b16ba9 1807ed_watchdog(struct ifnet *ifp)
984263bc
MD
1808{
1809 struct ed_softc *sc = ifp->if_softc;
1810
1811 if (sc->gone)
1812 return;
3e4a09e7 1813 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
984263bc
MD
1814 ifp->if_oerrors++;
1815
1816 ed_reset(ifp);
1817}
1818
1f18ea8c 1819#ifndef ED_NO_MIIBUS
984263bc 1820static void
27b16ba9 1821ed_tick(void *arg)
984263bc
MD
1822{
1823 struct ed_softc *sc = arg;
1824 struct mii_data *mii;
78195a76 1825 struct ifnet *ifp;
984263bc 1826
78195a76
MD
1827 ifp = &sc->arpcom.ac_if;
1828 lwkt_serialize_enter(ifp->if_serializer);
888ab9b7
JS
1829
1830 if (sc->gone) {
ce0da71b 1831 lwkt_serialize_exit(ifp->if_serializer);
984263bc 1832 return;
888ab9b7
JS
1833 }
1834
984263bc
MD
1835 if (sc->miibus != NULL) {
1836 mii = device_get_softc(sc->miibus);
1837 mii_tick(mii);
1838 }
888ab9b7 1839
4f65d502 1840 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
78195a76 1841 lwkt_serialize_exit(ifp->if_serializer);
984263bc 1842}
1f18ea8c 1843#endif
984263bc
MD
1844
1845/*
1846 * Initialize device.
1847 */
1848static void
27b16ba9 1849ed_init(void *xsc)
984263bc
MD
1850{
1851 struct ed_softc *sc = xsc;
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
888ab9b7 1853 int i;
984263bc 1854
888ab9b7
JS
1855 crit_enter();
1856
1857 if (sc->gone) {
1858 crit_exit();
984263bc 1859 return;
888ab9b7 1860 }
984263bc 1861
984263bc
MD
1862 /*
1863 * Initialize the NIC in the exact order outlined in the NS manual.
1864 * This init procedure is "mandatory"...don't change what or when
1865 * things happen.
1866 */
984263bc
MD
1867
1868 /* reset transmitter flags */
1869 sc->xmit_busy = 0;
1870 ifp->if_timer = 0;
1871
1872 sc->txb_inuse = 0;
1873 sc->txb_new = 0;
1874 sc->txb_next_tx = 0;
1875
1876 /* This variable is used below - don't move this assignment */
1877 sc->next_packet = sc->rec_page_start + 1;
1878
1879 /*
1880 * Set interface for page 0, Remote DMA complete, Stopped
1881 */
1882 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1883
1884 if (sc->isa16bit) {
1885
1886 /*
1887 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1888 * order=80x86, word-wide DMA xfers,
1889 */
1890 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1891 } else {
1892
1893 /*
1894 * Same as above, but byte-wide DMA xfers
1895 */
1896 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1897 }
1898
1899 /*
1900 * Clear Remote Byte Count Registers
1901 */
1902 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1903 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1904
1905 /*
1906 * For the moment, don't store incoming packets in memory.
1907 */
1908 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1909
1910 /*
1911 * Place NIC in internal loopback mode
1912 */
1913 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1914
1915 /*
1916 * Initialize transmit/receive (ring-buffer) Page Start
1917 */
1918 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1919 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1920 /* Set lower bits of byte addressable framing to 0 */
1921 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1922 ed_nic_outb(sc, 0x09, 0);
1923
1924 /*
1925 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1926 */
1927 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1928 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1929
1930 /*
1931 * Clear all interrupts. A '1' in each bit position clears the
1932 * corresponding flag.
1933 */
1934 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1935
1936 /*
1937 * Enable the following interrupts: receive/transmit complete,
1938 * receive/transmit error, and Receiver OverWrite.
1939 *
1940 * Counter overflow and Remote DMA complete are *not* enabled.
1941 */
1942 ed_nic_outb(sc, ED_P0_IMR,
1943 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1944
1945 /*
1946 * Program Command Register for page 1
1947 */
1948 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1949
1950 /*
1951 * Copy out our station address
1952 */
1953 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1954 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1955
1956 /*
1957 * Set Current Page pointer to next_packet (initialized above)
1958 */
1959 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1960
1961 /*
1962 * Program Receiver Configuration Register and multicast filter. CR is
1963 * set to page 0 on return.
1964 */
1965 ed_setrcr(sc);
1966
1967 /*
1968 * Take interface out of loopback
1969 */
1970 ed_nic_outb(sc, ED_P0_TCR, 0);
1971
1972 /*
1973 * If this is a 3Com board, the tranceiver must be software enabled
1974 * (there is no settable hardware default).
1975 */
1976 if (sc->vendor == ED_VENDOR_3COM) {
1977 if (ifp->if_flags & IFF_ALTPHYS) {
1978 ed_asic_outb(sc, ED_3COM_CR, 0);
1979 } else {
1980 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1981 }
1982 }
1983
1f18ea8c 1984#ifndef ED_NO_MIIBUS
984263bc
MD
1985 if (sc->miibus != NULL) {
1986 struct mii_data *mii;
1987 mii = device_get_softc(sc->miibus);
1988 mii_mediachg(mii);
1989 }
1f18ea8c 1990#endif
984263bc
MD
1991 /*
1992 * Set 'running' flag, and clear output active flag.
1993 */
1994 ifp->if_flags |= IFF_RUNNING;
1995 ifp->if_flags &= ~IFF_OACTIVE;
1996
1997 /*
1998 * ...and attempt to start output
1999 */
9db4b353 2000 if_devstart(ifp);
984263bc 2001
1f18ea8c 2002#ifndef ED_NO_MIIBUS
4f65d502 2003 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1f18ea8c 2004#endif
888ab9b7
JS
2005
2006 crit_exit();
984263bc
MD
2007}
2008
2009/*
2010 * This routine actually starts the transmission on the interface
2011 */
2012static __inline void
27b16ba9 2013ed_xmit(struct ed_softc *sc)
984263bc
MD
2014{
2015 struct ifnet *ifp = (struct ifnet *)sc;
27b16ba9 2016 u_short len;
984263bc
MD
2017
2018 if (sc->gone)
2019 return;
2020 len = sc->txb_len[sc->txb_next_tx];
2021
2022 /*
2023 * Set NIC for page 0 register access
2024 */
2025 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2026
2027 /*
2028 * Set TX buffer start page
2029 */
2030 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2031 sc->txb_next_tx * ED_TXBUF_SIZE);
2032
2033 /*
2034 * Set TX length
2035 */
2036 ed_nic_outb(sc, ED_P0_TBCR0, len);
2037 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2038
2039 /*
2040 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2041 */
2042 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2043 sc->xmit_busy = 1;
2044
2045 /*
2046 * Point to next transmit buffer slot and wrap if necessary.
2047 */
2048 sc->txb_next_tx++;
2049 if (sc->txb_next_tx == sc->txb_cnt)
2050 sc->txb_next_tx = 0;
2051
2052 /*
2053 * Set a timer just in case we never hear from the board again
2054 */
2055 ifp->if_timer = 2;
2056}
2057
2058/*
2059 * Start output on interface.
2060 * We make two assumptions here:
2061 * 1) that the current priority is set to splimp _before_ this code
2062 * is called *and* is returned to the appropriate priority after
2063 * return
2064 * 2) that the IFF_OACTIVE flag is checked before this code is called
2065 * (i.e. that the output part of the interface is idle)
2066 */
2067static void
27b16ba9 2068ed_start(struct ifnet *ifp)
984263bc
MD
2069{
2070 struct ed_softc *sc = ifp->if_softc;
2071 struct mbuf *m0, *m;
2072 caddr_t buffer;
2073 int len;
2074
2075 if (sc->gone) {
e3869ec7 2076 kprintf("ed_start(%p) GONE\n",ifp);
9db4b353 2077 ifq_purge(&ifp->if_snd);
984263bc
MD
2078 return;
2079 }
2080outloop:
2081
2082 /*
2083 * First, see if there are buffered packets and an idle transmitter -
2084 * should never happen at this point.
2085 */
2086 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
e3869ec7 2087 kprintf("ed: packets buffered, but transmitter idle\n");
984263bc
MD
2088 ed_xmit(sc);
2089 }
2090
2091 /*
2092 * See if there is room to put another packet in the buffer.
2093 */
2094 if (sc->txb_inuse == sc->txb_cnt) {
2095
2096 /*
2097 * No room. Indicate this to the outside world and exit.
2098 */
2099 ifp->if_flags |= IFF_OACTIVE;
2100 return;
2101 }
d2c71fa0 2102 m = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
2103 if (m == 0) {
2104
2105 /*
2106 * We are using the !OACTIVE flag to indicate to the outside
2107 * world that we can accept an additional packet rather than
2108 * that the transmitter is _actually_ active. Indeed, the
2109 * transmitter may be active, but if we haven't filled all the
2110 * buffers with data then we still want to accept more.
2111 */
2112 ifp->if_flags &= ~IFF_OACTIVE;
2113 return;
2114 }
2115
2116 /*
2117 * Copy the mbuf chain into the transmit buffer
2118 */
2119
2120 m0 = m;
2121
2122 /* txb_new points to next open buffer slot */
2123 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2124
2125 if (sc->mem_shared) {
2126
2127 /*
2128 * Special case setup for 16 bit boards...
2129 */
2130 if (sc->isa16bit) {
2131 switch (sc->vendor) {
2132
2133 /*
2134 * For 16bit 3Com boards (which have 16k of
2135 * memory), we have the xmit buffers in a
2136 * different page of memory ('page 0') - so
2137 * change pages.
2138 */
2139 case ED_VENDOR_3COM:
2140 ed_asic_outb(sc, ED_3COM_GACFR,
2141 ED_3COM_GACFR_RSEL);
2142 break;
2143
2144 /*
2145 * Enable 16bit access to shared memory on
2146 * WD/SMC boards.
2147 */
2148 case ED_VENDOR_WD_SMC:
2149 ed_asic_outb(sc, ED_WD_LAAR,
2150 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2151 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2153 }
2154 break;
2155 }
2156 }
2157 for (len = 0; m != 0; m = m->m_next) {
2158 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2159 buffer += m->m_len;
2160 len += m->m_len;
2161 }
2162
2163 /*
2164 * Restore previous shared memory access
2165 */
2166 if (sc->isa16bit) {
2167 switch (sc->vendor) {
2168 case ED_VENDOR_3COM:
2169 ed_asic_outb(sc, ED_3COM_GACFR,
2170 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2171 break;
2172 case ED_VENDOR_WD_SMC:
2173 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2174 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2175 }
2176 ed_asic_outb(sc, ED_WD_LAAR,
2177 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2178 break;
2179 }
2180 }
2181 } else {
2182 len = ed_pio_write_mbufs(sc, m, (int)buffer);
1f18ea8c
JS
2183 if (len == 0) {
2184 m_freem(m0);
984263bc 2185 goto outloop;
1f18ea8c 2186 }
984263bc
MD
2187 }
2188
2189 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2190
2191 sc->txb_inuse++;
2192
2193 /*
2194 * Point to next buffer slot and wrap if necessary.
2195 */
2196 sc->txb_new++;
2197 if (sc->txb_new == sc->txb_cnt)
2198 sc->txb_new = 0;
2199
2200 if (sc->xmit_busy == 0)
2201 ed_xmit(sc);
2202
7600679e 2203 BPF_MTAP(ifp, m0);
984263bc
MD
2204
2205 m_freem(m0);
2206
2207 /*
2208 * Loop back to the top to possibly buffer more packets
2209 */
2210 goto outloop;
2211}
2212
2213/*
2214 * Ethernet interface receiver interrupt.
2215 */
2216static __inline void
27b16ba9 2217ed_rint(struct ed_softc *sc)
984263bc
MD
2218{
2219 struct ifnet *ifp = &sc->arpcom.ac_if;
2220 u_char boundry;
2221 u_short len;
2222 struct ed_ring packet_hdr;
2223 char *packet_ptr;
2224
2225 if (sc->gone)
2226 return;
2227
2228 /*
2229 * Set NIC to page 1 registers to get 'current' pointer
2230 */
2231 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2232
2233 /*
2234 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2235 * i.e. it points to where new data has been buffered. The 'CURR'
2236 * (current) register points to the logical end of the ring-buffer -
2237 * i.e. it points to where additional new data will be added. We loop
2238 * here until the logical beginning equals the logical end (or in
2239 * other words, until the ring-buffer is empty).
2240 */
2241 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2242
2243 /* get pointer to this buffer's header structure */
2244 packet_ptr = sc->mem_ring +
2245 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2246
2247 /*
2248 * The byte count includes a 4 byte header that was added by
2249 * the NIC.
2250 */
2251 if (sc->mem_shared)
2252 packet_hdr = *(struct ed_ring *) packet_ptr;
2253 else
2254 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2255 sizeof(packet_hdr));
2256 len = packet_hdr.count;
2257 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2258 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2259 /*
2260 * Length is a wild value. There's a good chance that
2261 * this was caused by the NIC being old and buggy.
2262 * The bug is that the length low byte is duplicated in
2263 * the high byte. Try to recalculate the length based on
2264 * the pointer to the next packet.
2265 */
2266 /*
2267 * NOTE: sc->next_packet is pointing at the current packet.
2268 */
2269 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2270 if (packet_hdr.next_packet >= sc->next_packet) {
2271 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2272 } else {
2273 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2274 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2275 }
2276 /*
2277 * because buffers are aligned on 256-byte boundary,
2278 * the length computed above is off by 256 in almost
2279 * all cases. Fix it...
2280 */
2281 if (len & 0xff)
2282 len -= 256 ;
2283 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2284 + sizeof(struct ed_ring)))
2285 sc->mibdata.dot3StatsFrameTooLongs++;
2286 }
2287 /*
2288 * Be fairly liberal about what we allow as a "reasonable" length
2289 * so that a [crufty] packet will make it to BPF (and can thus
2290 * be analyzed). Note that all that is really important is that
2291 * we have a length that will fit into one mbuf cluster or less;
2292 * the upper layer protocols can then figure out the length from
2293 * their own length field(s).
2294 * But make sure that we have at least a full ethernet header
2295 * or we would be unable to call ether_input() later.
2296 */
2297 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2298 (len <= MCLBYTES) &&
2299 (packet_hdr.next_packet >= sc->rec_page_start) &&
2300 (packet_hdr.next_packet < sc->rec_page_stop)) {
2301 /*
2302 * Go get packet.
2303 */
2304 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2305 len - sizeof(struct ed_ring));
2306 ifp->if_ipackets++;
2307 } else {
2308 /*
2309 * Really BAD. The ring pointers are corrupted.
2310 */
2311 log(LOG_ERR,
3e4a09e7
MD
2312 "%s: NIC memory corrupt - invalid packet length %d\n",
2313 ifp->if_xname, len);
984263bc
MD
2314 ifp->if_ierrors++;
2315 ed_reset(ifp);
2316 return;
2317 }
2318
2319 /*
2320 * Update next packet pointer
2321 */
2322 sc->next_packet = packet_hdr.next_packet;
2323
2324 /*
2325 * Update NIC boundry pointer - being careful to keep it one
2326 * buffer behind. (as recommended by NS databook)
2327 */
2328 boundry = sc->next_packet - 1;
2329 if (boundry < sc->rec_page_start)
2330 boundry = sc->rec_page_stop - 1;
2331
2332 /*
2333 * Set NIC to page 0 registers to update boundry register
2334 */
2335 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2336
2337 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2338
2339 /*
2340 * Set NIC to page 1 registers before looping to top (prepare
2341 * to get 'CURR' current pointer)
2342 */
2343 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2344 }
2345}
2346
2347/*
2348 * Ethernet interface interrupt processor
2349 */
2350void
27b16ba9 2351edintr(void *arg)
984263bc
MD
2352{
2353 struct ed_softc *sc = (struct ed_softc*) arg;
2354 struct ifnet *ifp = (struct ifnet *)sc;
2355 u_char isr;
1f18ea8c 2356 int count;
984263bc
MD
2357
2358 if (sc->gone)
2359 return;
2360 /*
2361 * Set NIC to page 0 registers
2362 */
2363 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2364
2365 /*
1f18ea8c
JS
2366 * loop until there are no more new interrupts. When the card
2367 * goes away, the hardware will read back 0xff. Looking at
2368 * the interrupts, it would appear that 0xff is impossible,
2369 * or at least extremely unlikely.
984263bc 2370 */
1f18ea8c 2371 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
984263bc
MD
2372
2373 /*
2374 * reset all the bits that we are 'acknowledging' by writing a
2375 * '1' to each bit position that was set (writing a '1'
2376 * *clears* the bit)
2377 */
2378 ed_nic_outb(sc, ED_P0_ISR, isr);
2379
1f18ea8c
JS
2380 /*
2381 * XXX workaround for AX88190
2382 * We limit this to 5000 iterations. At 1us per inb/outb,
2383 * this translates to about 15ms, which should be plenty
2384 * of time, and also gives protection in the card eject
2385 * case.
2386 */
984263bc 2387 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
1f18ea8c
JS
2388 count = 5000; /* 15ms */
2389 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2390 ed_nic_outb(sc, ED_P0_ISR,0);
2391 ed_nic_outb(sc, ED_P0_ISR,isr);
2392 }
2393 if (count == 0)
2394 break;
984263bc
MD
2395 }
2396
2397 /*
2398 * Handle transmitter interrupts. Handle these first because
2399 * the receiver will reset the board under some conditions.
2400 */
2401 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2402 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2403
2404 /*
2405 * Check for transmit error. If a TX completed with an
2406 * error, we end up throwing the packet away. Really
2407 * the only error that is possible is excessive
2408 * collisions, and in this case it is best to allow
2409 * the automatic mechanisms of TCP to backoff the
2410 * flow. Of course, with UDP we're screwed, but this
2411 * is expected when a network is heavily loaded.
2412 */
7b9f668c 2413 ed_nic_inb(sc, ED_P0_TSR);
984263bc
MD
2414 if (isr & ED_ISR_TXE) {
2415 u_char tsr;
2416
2417 /*
2418 * Excessive collisions (16)
2419 */
2420 tsr = ed_nic_inb(sc, ED_P0_TSR);
2421 if ((tsr & ED_TSR_ABT)
2422 && (collisions == 0)) {
2423
2424 /*
2425 * When collisions total 16, the
2426 * P0_NCR will indicate 0, and the
2427 * TSR_ABT is set.
2428 */
2429 collisions = 16;
2430 sc->mibdata.dot3StatsExcessiveCollisions++;
2431 sc->mibdata.dot3StatsCollFrequencies[15]++;
2432 }
2433 if (tsr & ED_TSR_OWC)
2434 sc->mibdata.dot3StatsLateCollisions++;
2435 if (tsr & ED_TSR_CDH)
2436 sc->mibdata.dot3StatsSQETestErrors++;
2437 if (tsr & ED_TSR_CRS)
2438 sc->mibdata.dot3StatsCarrierSenseErrors++;
2439 if (tsr & ED_TSR_FU)
2440 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2441
2442 /*
2443 * update output errors counter
2444 */
2445 ifp->if_oerrors++;
2446 } else {
2447
2448 /*
2449 * Update total number of successfully
2450 * transmitted packets.
2451 */
2452 ifp->if_opackets++;
2453 }
2454
2455 /*
2456 * reset tx busy and output active flags
2457 */
2458 sc->xmit_busy = 0;
2459 ifp->if_flags &= ~IFF_OACTIVE;
2460
2461 /*
2462 * clear watchdog timer
2463 */
2464 ifp->if_timer = 0;
2465
2466 /*
2467 * Add in total number of collisions on last
2468 * transmission.
2469 */
2470 ifp->if_collisions += collisions;
2471 switch(collisions) {
2472 case 0:
2473 case 16:
2474 break;
2475 case 1:
2476 sc->mibdata.dot3StatsSingleCollisionFrames++;
2477 sc->mibdata.dot3StatsCollFrequencies[0]++;
2478 break;
2479 default:
2480 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2481 sc->mibdata.
2482 dot3StatsCollFrequencies[collisions-1]
2483 ++;
2484 break;
2485 }
2486
2487 /*
2488 * Decrement buffer in-use count if not zero (can only
2489 * be zero if a transmitter interrupt occured while
2490 * not actually transmitting). If data is ready to
2491 * transmit, start it transmitting, otherwise defer
2492 * until after handling receiver
2493 */
2494 if (sc->txb_inuse && --sc->txb_inuse)
2495 ed_xmit(sc);
2496 }
2497
2498 /*
2499 * Handle receiver interrupts
2500 */
2501 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2502
2503 /*
2504 * Overwrite warning. In order to make sure that a
2505 * lockup of the local DMA hasn't occurred, we reset
2506 * and re-init the NIC. The NSC manual suggests only a
2507 * partial reset/re-init is necessary - but some chips
2508 * seem to want more. The DMA lockup has been seen
2509 * only with early rev chips - Methinks this bug was
2510 * fixed in later revs. -DG
2511 */
2512 if (isr & ED_ISR_OVW) {
2513 ifp->if_ierrors++;
2514#ifdef DIAGNOSTIC
2515 log(LOG_WARNING,
3e4a09e7
MD
2516 "%s: warning - receiver ring buffer overrun\n",
2517 ifp->if_xname);
984263bc
MD
2518#endif
2519
2520 /*
2521 * Stop/reset/re-init NIC
2522 */
2523 ed_reset(ifp);
2524 } else {
2525
2526 /*
2527 * Receiver Error. One or more of: CRC error,
2528 * frame alignment error FIFO overrun, or
2529 * missed packet.
2530 */
2531 if (isr & ED_ISR_RXE) {
2532 u_char rsr;
2533 rsr = ed_nic_inb(sc, ED_P0_RSR);
2534 if (rsr & ED_RSR_CRC)
2535 sc->mibdata.dot3StatsFCSErrors++;
2536 if (rsr & ED_RSR_FAE)
2537 sc->mibdata.dot3StatsAlignmentErrors++;
2538 if (rsr & ED_RSR_FO)
2539 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2540 ifp->if_ierrors++;
2541#ifdef ED_DEBUG
1f18ea8c 2542 if_printf("receive error %x\n",
984263bc
MD
2543 ed_nic_inb(sc, ED_P0_RSR));
2544#endif
2545 }
2546
2547 /*
2548 * Go get the packet(s) XXX - Doing this on an
2549 * error is dubious because there shouldn't be
2550 * any data to get (we've configured the
2551 * interface to not accept packets with
2552 * errors).
2553 */
2554
2555 /*
2556 * Enable 16bit access to shared memory first
2557 * on WD/SMC boards.
2558 */
2559 if (sc->isa16bit &&
2560 (sc->vendor == ED_VENDOR_WD_SMC)) {
2561
2562 ed_asic_outb(sc, ED_WD_LAAR,
2563 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2564 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2565 ed_asic_outb(sc, ED_WD_MSR,
2566 ED_WD_MSR_MENB);
2567 }
2568 }
2569 ed_rint(sc);
2570
2571 /* disable 16bit access */
2572 if (sc->isa16bit &&
2573 (sc->vendor == ED_VENDOR_WD_SMC)) {
2574
2575 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2576 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2577 }
2578 ed_asic_outb(sc, ED_WD_LAAR,
2579 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2580 }
2581 }
2582 }
2583
2584 /*
2585 * If it looks like the transmitter can take more data,
2586 * attempt to start output on the interface. This is done
2587 * after handling the receiver to give the receiver priority.
2588 */
2589 if ((ifp->if_flags & IFF_OACTIVE) == 0)
9db4b353 2590 if_devstart(ifp);
984263bc
MD
2591
2592 /*
2593 * return NIC CR to standard state: page 0, remote DMA
2594 * complete, start (toggling the TXP bit off, even if was just
2595 * set in the transmit routine, is *okay* - it is 'edge'
2596 * triggered from low to high)
2597 */
2598 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2599
2600 /*
2601 * If the Network Talley Counters overflow, read them to reset
2602 * them. It appears that old 8390's won't clear the ISR flag
2603 * otherwise - resulting in an infinite loop.
2604 */
2605 if (isr & ED_ISR_CNT) {
7b9f668c
SW
2606 ed_nic_inb(sc, ED_P0_CNTR0);
2607 ed_nic_inb(sc, ED_P0_CNTR1);
2608 ed_nic_inb(sc, ED_P0_CNTR2);
984263bc
MD
2609 }
2610 }
2611}
2612
2613/*
2614 * Process an ioctl request. This code needs some work - it looks
2615 * pretty ugly.
2616 */
2617static int
27b16ba9 2618ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
2619{
2620 struct ed_softc *sc = ifp->if_softc;
1f18ea8c 2621#ifndef ED_NO_MIIBUS
984263bc
MD
2622 struct ifreq *ifr = (struct ifreq *)data;
2623 struct mii_data *mii;
1f18ea8c 2624#endif
888ab9b7
JS
2625 int error = 0;
2626
2627 crit_enter();
984263bc
MD
2628
2629 if (sc == NULL || sc->gone) {
2630 ifp->if_flags &= ~IFF_RUNNING;
888ab9b7 2631 crit_exit();
984263bc
MD
2632 return ENXIO;
2633 }
984263bc
MD
2634
2635 switch (command) {
984263bc
MD
2636 case SIOCSIFFLAGS:
2637
2638 /*
2639 * If the interface is marked up and stopped, then start it.
2640 * If it is marked down and running, then stop it.
2641 */
2642 if (ifp->if_flags & IFF_UP) {
2643 if ((ifp->if_flags & IFF_RUNNING) == 0)
2644 ed_init(sc);
2645 } else {
2646 if (ifp->if_flags & IFF_RUNNING) {
2647 ed_stop(sc);
2648 ifp->if_flags &= ~IFF_RUNNING;
2649 }
2650 }
2651
2652 /*
2653 * Promiscuous flag may have changed, so reprogram the RCR.
2654 */
2655 ed_setrcr(sc);
2656
2657 /*
2658 * An unfortunate hack to provide the (required) software
2659 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2660 * disables the tranceiver if set.
2661 */
2662 if (sc->vendor == ED_VENDOR_3COM) {
2663 if (ifp->if_flags & IFF_ALTPHYS) {
2664 ed_asic_outb(sc, ED_3COM_CR, 0);
2665 } else {
2666 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2667 }
2668 } else if (sc->vendor == ED_VENDOR_HP)
2669 ed_hpp_set_physical_link(sc);
2670 break;
2671
2672 case SIOCADDMULTI:
2673 case SIOCDELMULTI:
2674 /*
2675 * Multicast list has changed; set the hardware filter
2676 * accordingly.
2677 */
2678 ed_setrcr(sc);
2679 error = 0;
2680 break;
2681
1f18ea8c 2682#ifndef ED_NO_MIIBUS
984263bc
MD
2683 case SIOCGIFMEDIA:
2684 case SIOCSIFMEDIA:
2685 if (sc->miibus == NULL) {
2686 error = EINVAL;
2687 break;
2688 }
2689 mii = device_get_softc(sc->miibus);
2690 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2691 break;
1f18ea8c 2692#endif
984263bc
MD
2693
2694 default:
4cde4dd5
JS
2695 error = ether_ioctl(ifp, command, data);
2696 break;
984263bc 2697 }
888ab9b7
JS
2698
2699 crit_exit();
2700
984263bc
MD
2701 return (error);
2702}
2703
2704/*
2705 * Given a source and destination address, copy 'amount' of a packet from
2706 * the ring buffer into a linear destination buffer. Takes into account
2707 * ring-wrap.
2708 */
2709static __inline char *
27b16ba9 2710ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
984263bc
MD
2711{
2712 u_short tmp_amount;
2713
2714 /* does copy wrap to lower addr in ring buffer? */
2715 if (src + amount > sc->mem_end) {
2716 tmp_amount = sc->mem_end - src;
2717
2718 /* copy amount up to end of NIC memory */
2719 if (sc->mem_shared)
2720 bcopy(src, dst, tmp_amount);
2721 else
2722 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2723
2724 amount -= tmp_amount;
2725 src = sc->mem_ring;
2726 dst += tmp_amount;
2727 }
2728 if (sc->mem_shared)
2729 bcopy(src, dst, amount);
2730 else
2731 ed_pio_readmem(sc, (int)src, dst, amount);
2732
2733 return (src + amount);
2734}
2735
2736/*
2737 * Retreive packet from shared memory and send to the next level up via
2738 * ether_input().
2739 */
2740static void
27b16ba9 2741ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
984263bc 2742{
1f18ea8c 2743 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
2744 struct ether_header *eh;
2745 struct mbuf *m;
2746
984263bc 2747 /*
17b71a59 2748 * Allocate a header mbuf.
984263bc
MD
2749 * We always put the received packet in a single buffer -
2750 * either with just an mbuf header or in a cluster attached
2751 * to the header. The +2 is to compensate for the alignment
2752 * fixup below.
2753 */
17b71a59
JH
2754 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
2755 if (m == NULL)
2756 return;
2757 m->m_pkthdr.rcvif = ifp;
2758 m->m_pkthdr.len = m->m_len = len;
984263bc
MD
2759
2760 /*
2761 * The +2 is to longword align the start of the real packet.
2762 * This is important for NFS.
2763 */
2764 m->m_data += 2;
2765 eh = mtod(m, struct ether_header *);
2766
2767 /*
a8d45119 2768 * Get packet, including link layer address, from interface.
984263bc 2769 */
a8d45119 2770 ed_ring_copy(sc, buf, (char *)eh, len);
984263bc 2771
3013ac0e 2772 m->m_pkthdr.len = m->m_len = len;
984263bc 2773
78195a76 2774 ifp->if_input(ifp, m);
984263bc
MD
2775}
2776
2777/*
2778 * Supporting routines
2779 */
2780
2781/*
2782 * Given a NIC memory source address and a host memory destination
2783 * address, copy 'amount' from NIC to host using Programmed I/O.
2784 * The 'amount' is rounded up to a word - okay as long as mbufs
2785 * are word sized.
2786 * This routine is currently Novell-specific.
2787 */
2788void
27b16ba9 2789ed_pio_readmem(struct ed_softc *sc, int src, u_char *dst, u_short amount)
984263bc
MD
2790{
2791 /* HP PC Lan+ cards need special handling */
2792 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2793 ed_hpp_readmem(sc, src, dst, amount);
2794 return;
2795 }
2796
2797 /* Regular Novell cards */
2798 /* select page 0 registers */
2799 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2800
2801 /* round up to a word */
2802 if (amount & 1)
2803 ++amount;
2804
2805 /* set up DMA byte count */
2806 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2807 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2808
2809 /* set up source address in NIC mem */
2810 ed_nic_outb(sc, ED_P0_RSAR0, src);
2811 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2812
2813 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2814
2815 if (sc->isa16bit) {
2816 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2817 } else {
2818 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2819 }
2820}
2821
2822/*
2823 * Stripped down routine for writing a linear buffer to NIC memory.
2824 * Only used in the probe routine to test the memory. 'len' must
2825 * be even.
2826 */
2827void
27b16ba9 2828ed_pio_writemem(struct ed_softc *sc, char *src, u_short dst, u_short len)
984263bc
MD
2829{
2830 int maxwait = 200; /* about 240us */
2831
2832 /* select page 0 registers */
2833 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2834
2835 /* reset remote DMA complete flag */
2836 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2837
2838 /* set up DMA byte count */
2839 ed_nic_outb(sc, ED_P0_RBCR0, len);
2840 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2841
2842 /* set up destination address in NIC mem */
2843 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2844 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2845
2846 /* set remote DMA write */
2847 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2848
2849 if (sc->isa16bit) {
2850 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2851 } else {
2852 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2853 }
2854
2855 /*
2856 * Wait for remote DMA complete. This is necessary because on the
2857 * transmit side, data is handled internally by the NIC in bursts and
2858 * we can't start another remote DMA until this one completes. Not
2859 * waiting causes really bad things to happen - like the NIC
2860 * irrecoverably jamming the ISA bus.
2861 */
2862 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2863}
2864
2865/*
2866 * Write an mbuf chain to the destination NIC memory address using
2867 * programmed I/O.
2868 */
2869static u_short
27b16ba9 2870ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
984263bc
MD
2871{
2872 struct ifnet *ifp = (struct ifnet *)sc;
27b16ba9 2873 u_short total_len, dma_len;
984263bc
MD
2874 struct mbuf *mp;
2875 int maxwait = 200; /* about 240us */
2876
2877 /* HP PC Lan+ cards need special handling */
2878 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2879 return ed_hpp_write_mbufs(sc, m, dst);
2880 }
2881
2882 /* Regular Novell cards */
2883 /* First, count up the total number of bytes to copy */
2884 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2885 total_len += mp->m_len;
2886
2887 dma_len = total_len;
2888 if (sc->isa16bit && (dma_len & 1))
2889 dma_len++;
2890
2891 /* select page 0 registers */
2892 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2893
2894 /* reset remote DMA complete flag */
2895 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2896
2897 /* set up DMA byte count */
2898 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2899 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2900
2901 /* set up destination address in NIC mem */
2902 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2903 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2904
2905 /* set remote DMA write */
2906 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2907
2908 /*
2909 * Transfer the mbuf chain to the NIC memory.
2910 * 16-bit cards require that data be transferred as words, and only words.
2911 * So that case requires some extra code to patch over odd-length mbufs.
2912 */
2913
2914 if (!sc->isa16bit) {
2915 /* NE1000s are easy */
2916 while (m) {
2917 if (m->m_len) {
2918 ed_asic_outsb(sc, ED_NOVELL_DATA,
2919 m->m_data, m->m_len);
2920 }
2921 m = m->m_next;
2922 }
2923 } else {
2924 /* NE2000s are a pain */
27b16ba9 2925 u_char *data;
984263bc 2926 int len, wantbyte;
27b16ba9 2927 u_char savebyte[2];
984263bc
MD
2928
2929 wantbyte = 0;
2930
2931 while (m) {
2932 len = m->m_len;
2933 if (len) {
2934 data = mtod(m, caddr_t);
2935 /* finish the last word */
2936 if (wantbyte) {
2937 savebyte[1] = *data;
2938 ed_asic_outw(sc, ED_NOVELL_DATA,
2939 *(u_short *)savebyte);
2940 data++;
2941 len--;
2942 wantbyte = 0;
2943 }
2944 /* output contiguous words */
2945 if (len > 1) {
2946 ed_asic_outsw(sc, ED_NOVELL_DATA,
2947 data, len >> 1);
2948 data += len & ~1;
2949 len &= 1;
2950 }
2951 /* save last byte, if necessary */
2952 if (len == 1) {
2953 savebyte[0] = *data;
2954 wantbyte = 1;
2955 }
2956 }
2957 m = m->m_next;
2958 }
2959 /* spit last byte */
2960 if (wantbyte) {
2961 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2962 }
2963 }
2964
2965 /*
2966 * Wait for remote DMA complete. This is necessary because on the
2967 * transmit side, data is handled internally by the NIC in bursts and
2968 * we can't start another remote DMA until this one completes. Not
2969 * waiting causes really bad things to happen - like the NIC
2970 * irrecoverably jamming the ISA bus.
2971 */
2972 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2973
2974 if (!maxwait) {
3e4a09e7
MD
2975 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
2976 ifp->if_xname);
984263bc
MD
2977 ed_reset(ifp);
2978 return(0);
2979 }
2980 return (total_len);
2981}
2982
2983/*
2984 * Support routines to handle the HP PC Lan+ card.
2985 */
2986
2987/*
2988 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2989 * IO.
2990 */
2991
2992static void
27b16ba9 2993ed_hpp_readmem(struct ed_softc *sc, u_short src, u_char *dst, u_short amount)
984263bc
MD
2994{
2995
2996 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2997
2998
2999 /* Program the source address in RAM */
3000 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3001
3002 /*
3003 * The HP PC Lan+ card supports word reads as well as
3004 * a memory mapped i/o port that is aliased to every
3005 * even address on the board.
3006 */
3007
3008 if (sc->hpp_mem_start) {
3009
3010 /* Enable memory mapped access. */
3011 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3012 ~(ED_HPP_OPTION_MEM_DISABLE |
3013 ED_HPP_OPTION_BOOT_ROM_ENB));
3014
3015 if (use_32bit_access && (amount > 3)) {
3016 u_int32_t *dl = (u_int32_t *) dst;
3017 volatile u_int32_t *const sl =
3018 (u_int32_t *) sc->hpp_mem_start;
3019 u_int32_t *const fence = dl + (amount >> 2);
3020
3021 /* Copy out NIC data. We could probably write this
3022 as a `movsl'. The currently generated code is lousy.
3023 */
3024
3025 while (dl < fence)
3026 *dl++ = *sl;
3027
3028 dst += (amount & ~3);
3029 amount &= 3;
3030
3031 }
3032
3033 /* Finish off any words left, as a series of short reads */
3034 if (amount > 1) {
3035 u_short *d = (u_short *) dst;
3036 volatile u_short *const s =
3037 (u_short *) sc->hpp_mem_start;
3038 u_short *const fence = d + (amount >> 1);
3039
3040 /* Copy out NIC data. */
3041
3042 while (d < fence)
3043 *d++ = *s;
3044
3045 dst += (amount & ~1);
3046 amount &= 1;
3047 }
3048
3049 /*
3050 * read in a byte; however we need to always read 16 bits
3051 * at a time or the hardware gets into a funny state
3052 */
3053
3054 if (amount == 1) {
3055 /* need to read in a short and copy LSB */
3056 volatile u_short *const s =
3057 (volatile u_short *) sc->hpp_mem_start;
3058
3059 *dst = (*s) & 0xFF;
3060 }
3061
3062 /* Restore Boot ROM access. */
3063
3064 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3065
3066
3067 } else {
3068 /* Read in data using the I/O port */
3069 if (use_32bit_access && (amount > 3)) {
3070 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3071 dst += (amount & ~3);
3072 amount &= 3;
3073 }
3074 if (amount > 1) {
3075 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3076 dst += (amount & ~1);
3077 amount &= 1;
3078 }
3079 if (amount == 1) { /* read in a short and keep the LSB */
3080 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3081 }
3082 }
3083}
3084
3085/*
3086 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3087 * IO.
3088 * Only used in the probe routine to test the memory. 'len' must
3089 * be even.
3090 */
1f18ea8c 3091static void
27b16ba9 3092ed_hpp_writemem(struct ed_softc *sc, u_char *src, u_short dst, u_short len)
984263bc
MD
3093{
3094 /* reset remote DMA complete flag */
3095 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3096
3097 /* program the write address in RAM */
3098 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3099
3100 if (sc->hpp_mem_start) {
3101 u_short *s = (u_short *) src;
3102 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3103 u_short *const fence = s + (len >> 1);
3104
3105 /*
3106 * Enable memory mapped access.
3107 */
3108
3109 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3110 ~(ED_HPP_OPTION_MEM_DISABLE |
3111 ED_HPP_OPTION_BOOT_ROM_ENB));
3112
3113 /*
3114 * Copy to NIC memory.
3115 */
3116
3117 while (s < fence)
3118 *d = *s++;
3119
3120 /*
3121 * Restore Boot ROM access.
3122 */
3123
3124 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3125
3126 } else {
3127 /* write data using I/O writes */
3128 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3129 }
3130}
3131
3132/*
3133 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3134 * outsw() or via the memory mapped interface to the same register.
3135 * Writes have to be in word units; byte accesses won't work and may cause
3e4db402 3136 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
984263bc
MD
3137 * allows it.
3138 */
3139
3140static u_short
3141ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3142{
3143 int len, wantbyte;
27b16ba9
SZ
3144 u_short total_len;
3145 u_char savebyte[2];
984263bc
MD
3146 volatile u_short * const d =
3147 (volatile u_short *) sc->hpp_mem_start;
3148 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3149
3150 /* select page 0 registers */
3151 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3152
3153 /* reset remote DMA complete flag */
3154 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3155
3156 /* program the write address in RAM */
3157 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3158
3159 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3160 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3161 ~(ED_HPP_OPTION_MEM_DISABLE |
3162 ED_HPP_OPTION_BOOT_ROM_ENB));
3163
3164 wantbyte = 0;
3165 total_len = 0;
3166
3167 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3168 while (m) {
3169 total_len += (len = m->m_len);
3170 if (len) {
3171 caddr_t data = mtod(m, caddr_t);
3172 /* finish the last word of the previous mbuf */
3173 if (wantbyte) {
3174 savebyte[1] = *data;
1f18ea8c 3175 *d = *((u_short *) savebyte);
984263bc
MD
3176 data++; len--; wantbyte = 0;
3177 }
3178 /* output contiguous words */
3179 if ((len > 3) && (use_32bit_accesses)) {
3180 volatile u_int32_t *const dl =
3181 (volatile u_int32_t *) d;
3182 u_int32_t *sl = (u_int32_t *) data;
3183 u_int32_t *fence = sl + (len >> 2);
3184
3185 while (sl < fence)
3186 *dl = *sl++;
3187
3188 data += (len & ~3);
3189 len &= 3;
3190 }
3191 /* finish off remain 16 bit writes */
3192 if (len > 1) {
3193 u_short *s = (u_short *) data;
3194 u_short *fence = s + (len >> 1);
3195
3196 while (s < fence)
3197 *d = *s++;
3198
3199 data += (len & ~1);
3200 len &= 1;
3201 }
3202 /* save last byte if needed */
3203 if ((wantbyte = (len == 1)) != 0)
3204 savebyte[0] = *data;
3205 }
3206 m = m->m_next; /* to next mbuf */
3207 }
3208 if (wantbyte) /* write last byte */
3209 *d = *((u_short *) savebyte);
3210 } else {
3211 /* use programmed I/O */
3212 while (m) {
3213 total_len += (len = m->m_len);
3214 if (len) {
3215 caddr_t data = mtod(m, caddr_t);
3216 /* finish the last word of the previous mbuf */
3217 if (wantbyte) {
3218 savebyte[1] = *data;
3219 ed_asic_outw(sc, ED_HPP_PAGE_4,
3220 *((u_short *)savebyte));
3221 data++;
3222 len--;
3223 wantbyte = 0;
3224 }
3225 /* output contiguous words */
3226 if ((len > 3) && use_32bit_accesses) {
3227 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3228 data, len >> 2);
3229 data += (len & ~3);
3230 len &= 3;
3231 }
3232 /* finish off remaining 16 bit accesses */
3233 if (len > 1) {
3234 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3235 data, len >> 1);
3236 data += (len & ~1);
3237 len &= 1;
3238 }
3239 if ((wantbyte = (len == 1)) != 0)
3240 savebyte[0] = *data;
3241
3242 } /* if len != 0 */
3243 m = m->m_next;
3244 }
3245 if (wantbyte) /* spit last byte */
3246 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3247
3248 }
3249
3250 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3251 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3252
3253 return (total_len);
3254}
3255
1f18ea8c 3256#ifndef ED_NO_MIIBUS
984263bc
MD
3257/*
3258 * MII bus support routines.
3259 */
3260int
27b16ba9 3261ed_miibus_readreg(device_t dev, int phy, int reg)
984263bc 3262{
888ab9b7
JS
3263 struct ed_softc *sc = device_get_softc(dev);
3264 int failed, val;
3265
3266 crit_enter();
984263bc 3267
984263bc 3268 if (sc->gone) {
888ab9b7 3269 crit_exit();
984263bc
MD
3270 return (0);
3271 }
1f18ea8c 3272
984263bc
MD
3273 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3274 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3275 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3276 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3277 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3278
3279 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3280 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3281 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3282
888ab9b7
JS
3283 crit_exit();
3284
984263bc
MD
3285 return (failed ? 0 : val);
3286}
3287
3288void
27b16ba9 3289ed_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 3290{
888ab9b7
JS
3291 struct ed_softc *sc = device_get_softc(dev);
3292
3293 crit_enter();
984263bc 3294
984263bc 3295 if (sc->gone) {
888ab9b7 3296 crit_exit();
984263bc
MD
3297 return;
3298 }
3299
3300 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3301 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3302 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3303 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3304 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3305 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3306 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3307 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3308
888ab9b7 3309 crit_exit();
984263bc
MD
3310}
3311
3312int
27b16ba9 3313ed_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
3314{
3315 struct ed_softc *sc;
3316 struct mii_data *mii;
3317
3318 sc = ifp->if_softc;
3319 if (sc->gone || sc->miibus == NULL)
3320 return (ENXIO);
3321
3322 mii = device_get_softc(sc->miibus);
3323 return mii_mediachg(mii);
3324}
3325
3326void
27b16ba9 3327ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
3328{
3329 struct ed_softc *sc;
3330 struct mii_data *mii;
3331
3332 sc = ifp->if_softc;
3333 if (sc->gone || sc->miibus == NULL)
3334 return;
3335
3336 mii = device_get_softc(sc->miibus);
3337 mii_pollstat(mii);
3338 ifmr->ifm_active = mii->mii_media_active;
3339 ifmr->ifm_status = mii->mii_media_status;
3340}
3341
3342void
27b16ba9 3343ed_child_detached(device_t dev, device_t child)
984263bc
MD
3344{
3345 struct ed_softc *sc;
3346
3347 sc = device_get_softc(dev);
3348 if (child == sc->miibus)
3349 sc->miibus = NULL;
3350}
1f18ea8c 3351#endif
984263bc
MD
3352
3353static void
27b16ba9 3354ed_setrcr(struct ed_softc *sc)
984263bc
MD
3355{
3356 struct ifnet *ifp = (struct ifnet *)sc;
3357 int i;
3358 u_char reg1;
3359
3360 /* Bit 6 in AX88190 RCR register must be set. */
3361 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3362 reg1 = ED_RCR_INTT;
3363 else
3364 reg1 = 0x00;
3365
3366 /* set page 1 registers */
3367 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3368
3369 if (ifp->if_flags & IFF_PROMISC) {
3370
3371 /*
3372 * Reconfigure the multicast filter.
3373 */
3374 for (i = 0; i < 8; i++)
3375 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3376
3377 /*
3378 * And turn on promiscuous mode. Also enable reception of
3379 * runts and packets with CRC & alignment errors.
3380 */
3381 /* Set page 0 registers */
3382 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3383
3384 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3385 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3386 } else {
3387 /* set up multicast addresses and filter modes */
3388 if (ifp->if_flags & IFF_MULTICAST) {
3389 u_int32_t mcaf[2];
3390
3391 if (ifp->if_flags & IFF_ALLMULTI) {
3392 mcaf[0] = 0xffffffff;
3393 mcaf[1] = 0xffffffff;
3394 } else
3395 ds_getmcaf(sc, mcaf);
3396
3397 /*
3398 * Set multicast filter on chip.
3399 */
3400 for (i = 0; i < 8; i++)
3401 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3402
3403 /* Set page 0 registers */
3404 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3405
3406 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3407 } else {
3408
3409 /*
3410 * Initialize multicast address hashing registers to
3411 * not accept multicasts.
3412 */
3413 for (i = 0; i < 8; ++i)
3414 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3415
3416 /* Set page 0 registers */
3417 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3418
3419 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3420 }
3421 }
3422
3423 /*
3424 * Start interface.
3425 */
3426 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3427}
3428
3429/*
3430 * Compute crc for ethernet address
3431 */
1f18ea8c 3432static uint32_t
27b16ba9 3433ds_mchash(const uint8_t *addr)
984263bc 3434{
1f18ea8c 3435#define ED_POLYNOMIAL 0x04c11db6
6de3da81
CP
3436 uint32_t crc = 0xffffffff;
3437 int carry, idx, bit;
3438 uint8_t data;
1f18ea8c
JS
3439
3440 for (idx = 6; --idx >= 0;) {
3441 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3442 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
984263bc 3443 crc <<= 1;
984263bc 3444 if (carry)
1f18ea8c 3445 crc = (crc ^ ED_POLYNOMIAL) | carry;
984263bc
MD
3446 }
3447 }
3448 return crc;
3449#undef POLYNOMIAL
3450}
3451
3452/*
3453 * Compute the multicast address filter from the
3454 * list of multicast addresses we need to listen to.
3455 */
3456static void
27b16ba9 3457ds_getmcaf(struct ed_softc *sc, u_int32_t *mcaf)
984263bc 3458{
f96d6c88
RG
3459 u_int32_t index;
3460 u_char *af = (u_char *) mcaf;
984263bc
MD
3461 struct ifmultiaddr *ifma;
3462
3463 mcaf[0] = 0;
3464 mcaf[1] = 0;
3465
441d34b2 3466 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
984263bc
MD
3467 if (ifma->ifma_addr->sa_family != AF_LINK)
3468 continue;
1f18ea8c 3469 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
984263bc
MD
3470 >> 26;
3471 af[index >> 3] |= 1 << (index & 7);
3472 }
3473}