machintr: Add intr_config interface
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
d916dbc1 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
87cf6827 51#include <machine/intr_machdep.h>
0b692e79 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
5f456c40 56
9e0e3f85 57#include <machine_base/apic/ioapic_abi.h>
a3dd9120 58#include <machine_base/isa/elcr_var.h>
9e0e3f85 59
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60#include "icu.h"
61#include "icu_ipl.h"
37e7efec 62
10ff1029 63extern inthand_t
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64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029 72
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73static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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82};
83
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84static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
88
89#define ICU_IMT_UNUSED 0 /* KEEP THIS */
90#define ICU_IMT_RESERVED 1
91#define ICU_IMT_LINE 2
474ba684 92#define ICU_IMT_SYSCALL 3
a3dd9120 93
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94extern void ICU_INTREN(int);
95extern void ICU_INTRDIS(int);
96
97static int icu_vectorctl(int, int, int);
98static int icu_setvar(int, const void *);
99static int icu_getvar(int, void *);
100static void icu_finalize(void);
101static void icu_cleanup(void);
102static void icu_setdefault(void);
7bf5fa56 103static void icu_stabilize(void);
a3dd9120 104static void icu_initmap(void);
d1ae7328 105static void icu_intr_config(int, enum intr_trigger, enum intr_polarity);
10db3cc6 106
30c5f287 107struct machintr_abi MachIntrABI_ICU = {
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108 MACHINTR_ICU,
109 .intrdis = ICU_INTRDIS,
110 .intren = ICU_INTREN,
111 .vectorctl = icu_vectorctl,
112 .setvar = icu_setvar,
113 .getvar = icu_getvar,
114 .finalize = icu_finalize,
10db3cc6 115 .cleanup = icu_cleanup,
7bf5fa56 116 .setdefault = icu_setdefault,
a3dd9120 117 .stabilize = icu_stabilize,
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118 .initmap = icu_initmap,
119 .intr_config = icu_intr_config
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120};
121
54e1df6b 122static int icu_imcr_present;
e96ee753 123
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124/*
125 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
126 */
54e1df6b 127static int
d916dbc1 128icu_setvar(int varid, const void *buf)
37e7efec 129{
54e1df6b 130 int error = 0;
e96ee753 131
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132 switch (varid) {
133 case MACHINTR_VAR_IMCR_PRESENT:
134 icu_imcr_present = *(const int *)buf;
135 break;
136
137 default:
138 error = ENOENT;
139 break;
140 }
141 return error;
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142}
143
54e1df6b 144static int
d916dbc1 145icu_getvar(int varid, void *buf)
37e7efec 146{
54e1df6b 147 int error = 0;
e96ee753 148
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149 switch (varid) {
150 case MACHINTR_VAR_IMCR_PRESENT:
151 *(int *)buf = icu_imcr_present;
152 break;
153
154 default:
155 error = ENOENT;
156 break;
157 }
158 return error;
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159}
160
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161/*
162 * Called before interrupts are physically enabled
163 */
37e7efec 164static void
7bf5fa56 165icu_stabilize(void)
37e7efec 166{
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167 int intr;
168
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169 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
170 machintr_intrdis(intr);
171 machintr_intren(ICU_IRQ_SLAVE);
172}
173
174/*
175 * Called after interrupts physically enabled but before the
176 * critical section is released.
177 */
178static void
179icu_cleanup(void)
180{
181 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
182}
183
184/*
185 * Called after stablize and cleanup; critical section is not
186 * held and interrupts are not physically disabled.
187 *
188 * For SMP:
189 * Further delayed after BSP's LAPIC is initialized
190 */
191static void
192icu_finalize(void)
193{
194 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
195
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196#ifdef SMP
197 if (apic_io_enable) {
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198 /*
199 * MachIntrABI switching will happen in
200 * MachIntrABI_IOAPIC.finalize()
201 */
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202 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
203 &icu_imcr_present);
204 MachIntrABI_IOAPIC.finalize();
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205 return;
206 }
54e1df6b 207
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208 /*
209 * If an IMCR is present, programming bit 0 disconnects the 8259
210 * from the BSP. The 8259 may still be connected to LINT0 on the
211 * BSP's LAPIC.
212 *
213 * If we are running SMP the LAPIC is active, try to use virtual
214 * wire mode so we can use other interrupt sources within the LAPIC
215 * in addition to the 8259.
216 */
217 if (icu_imcr_present) {
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218 u_long ef;
219
220 crit_enter();
221
222 ef = read_eflags();
223 cpu_disable_intr();
224
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225 outb(0x22, 0x70);
226 outb(0x23, 0x01);
37e7efec 227
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228 write_eflags(ef);
229
230 crit_exit();
231 }
232#endif /* SMP */
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233}
234
54e1df6b 235static int
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236icu_vectorctl(int op, int intr, int flags)
237{
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238 int error;
239 u_long ef;
240
241 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
242 return EINVAL;
243
244 ef = read_eflags();
245 cpu_disable_intr();
246 error = 0;
247
248 switch (op) {
249 case MACHINTR_VECTOR_SETUP:
081be8a5 250 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
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251 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
252 machintr_intren(intr);
253 break;
254
255 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 256 machintr_intrdis(intr);
081be8a5 257 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b 258 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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259 break;
260
261 default:
262 error = EOPNOTSUPP;
263 break;
264 }
265 write_eflags(ef);
266 return error;
10ff1029 267}
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268
269static void
270icu_setdefault(void)
271{
272 int intr;
273
274 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
275 if (intr == ICU_IRQ_SLAVE)
276 continue;
277 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
278 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
279 }
280}
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281
282static void
283icu_initmap(void)
284{
285 int i;
286
287 for (i = 0; i < ICU_HWI_VECTORS; ++i)
288 icu_irqmaps[i].im_type = ICU_IMT_LINE;
289 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
290
291 if (elcr_found) {
292 for (i = 0; i < ICU_HWI_VECTORS; ++i)
293 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
294 } else {
295 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
296 switch (i) {
297 case 0:
298 case 1:
299 case 2:
300 case 8:
301 case 13:
302 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
303 break;
304
305 default:
306 icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
307 break;
308 }
309 }
310 }
474ba684 311 icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
a3dd9120 312}
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313
314static void
315icu_intr_config(int irq __unused, enum intr_trigger trig __unused,
316 enum intr_polarity pola __unused)
317{
318}