i386: Always set LINTEN for AMD CPUs if their family >= 0xF
[dragonfly.git] / sys / platform / pc32 / apic / lapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
72740893 33#include <machine/globaldata.h>
984263bc 34#include <machine/smp.h>
90e8a35b 35#include <machine/cputypes.h>
d595a6c0 36#include <machine/md_var.h>
ad52b37b 37#include <machine/pmap.h>
d54b8204 38#include <machine/specialreg.h>
3340ac41 39#include <machine_base/apic/lapic.h>
ed4d621d 40#include <machine_base/apic/ioapic.h>
929c940f 41#include <machine_base/apic/ioapic_abi.h>
bfcc9e9b 42#include <machine_base/apic/apicvar.h>
d631ab59 43#include <machine_base/icu/icu_var.h>
984263bc 44#include <machine/segments.h>
96728c05 45#include <sys/thread2.h>
984263bc 46
87cf6827 47#include <machine/intr_machdep.h>
984263bc 48
2abaa030
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49extern int naps;
50
cb7d6921 51volatile lapic_t *lapic;
ad52b37b 52
b52c8db0 53static void lapic_timer_calibrate(void);
086575e9 54static void lapic_timer_set_divisor(int);
a9e511df 55static void lapic_timer_fixup_handler(void *);
76c58571 56static void lapic_timer_restart_handler(void *);
c5b8324c 57
78ea5a2a
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58void lapic_timer_process(void);
59void lapic_timer_process_frame(struct intrframe *);
c5b8324c 60
ef612539 61static int lapic_timer_enable = 1;
c5b8324c 62TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 63
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64static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
65static void lapic_timer_intr_enable(struct cputimer_intr *);
66static void lapic_timer_intr_restart(struct cputimer_intr *);
67static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
68
69static struct cputimer_intr lapic_cputimer_intr = {
70 .freq = 0,
71 .reload = lapic_timer_intr_reload,
72 .enable = lapic_timer_intr_enable,
73 .config = cputimer_intr_default_config,
74 .restart = lapic_timer_intr_restart,
75 .pmfixup = lapic_timer_intr_pmfixup,
76 .initclock = cputimer_intr_default_initclock,
77 .next = SLIST_ENTRY_INITIALIZER,
78 .name = "lapic",
79 .type = CPUTIMER_INTR_LAPIC,
80 .prio = CPUTIMER_INTR_PRIO_LAPIC,
81 .caps = CPUTIMER_INTR_CAP_NONE
82};
83
086575e9
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84static int lapic_timer_divisor_idx = -1;
85static const uint32_t lapic_timer_divisors[] = {
86 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
87 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
88};
c157ff7a 89#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
086575e9 90
68d62ec3 91/*
2d901d56 92 * APIC ID <-> CPU ID mapping structures.
68d62ec3 93 */
2d901d56
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94int cpu_id_to_apic_id[NAPICID];
95int apic_id_to_cpu_id[NAPICID];
1d6d7089 96int lapic_enable = 1;
68d62ec3 97
984263bc 98/*
d99d4acb 99 * Enable LAPIC, configure interrupts.
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100 */
101void
5ddeabb9 102lapic_init(boolean_t bsp)
984263bc 103{
78ea5a2a 104 uint32_t timer;
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105 u_int temp;
106
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107 /*
108 * Install vectors
109 *
110 * Since IDT is shared between BSP and APs, these vectors
111 * only need to be installed once; we do it on BSP.
112 */
113 if (bsp) {
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114 if (cpu_vendor_id == CPU_VENDOR_AMD &&
115 CPUID_TO_FAMILY(cpu_id) >= 0xf) {
116 uint32_t tcr;
117
118 /*
119 * Set the LINTEN bit in the HyperTransport
120 * Transaction Control Register.
121 *
122 * This will cause EXTINT and NMI interrupts
123 * routed over the hypertransport bus to be
124 * fed into the LAPIC LINT0/LINT1. If the bit
125 * isn't set, the interrupts will go to the
126 * general cpu INTR/NMI pins. On a dual-core
127 * cpu the interrupt winds up going to BOTH cpus.
128 * The first cpu that does the interrupt ack
129 * cycle will get the correct interrupt. The
130 * second cpu that does it will get a spurious
131 * interrupt vector (typically IRQ 7).
132 */
133 outl(0x0cf8,
134 (1 << 31) | /* enable */
135 (0 << 16) | /* bus */
136 (0x18 << 11) | /* dev (cpu + 0x18) */
137 (0 << 8) | /* func */
138 0x68 /* reg */
139 );
140 tcr = inl(0xcfc);
141 if ((tcr & 0x00010000) == 0) {
142 kprintf("LAPIC: AMD LINTEN on\n");
143 outl(0xcfc, tcr|0x00010000);
144 }
145 outl(0x0cf8, 0);
146 }
147
dbfb3a5a
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148 /* Install a 'Spurious INTerrupt' vector */
149 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
150 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
151
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152 /* Install a timer vector */
153 setidt(XTIMER_OFFSET, Xtimer,
154 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
155
156#ifdef SMP
dbfb3a5a
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157 /* Install an inter-CPU IPI for TLB invalidation */
158 setidt(XINVLTLB_OFFSET, Xinvltlb,
159 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
160
161 /* Install an inter-CPU IPI for IPIQ messaging */
162 setidt(XIPIQ_OFFSET, Xipiq,
163 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
164
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165 /* Install an inter-CPU IPI for CPU stop/restart */
166 setidt(XCPUSTOP_OFFSET, Xcpustop,
167 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1e7aaefa 168#endif
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169 }
170
9d6bf2df 171 /*
d99d4acb 172 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
97359a5b
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173 * aggregate interrupt input from the 8259. The INTA cycle
174 * will be routed to the external controller (the 8259) which
175 * is expected to supply the vector.
176 *
177 * Must be setup edge triggered, active high.
178 *
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179 * Disable LINT0 on BSP, if I/O APIC is enabled.
180 *
d99d4acb 181 * Disable LINT0 on the APs. It doesn't matter what delivery
97359a5b 182 * mode we use because we leave it masked.
9d6bf2df 183 */
cb7d6921 184 temp = lapic->lvt_lint0;
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185 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
186 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 187 if (bsp) {
9d6bf2df 188 temp |= APIC_LVT_DM_EXTINT;
f45bfca0 189 if (ioapic_enable)
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190 temp |= APIC_LVT_MASKED;
191 } else {
97359a5b 192 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 193 }
cb7d6921 194 lapic->lvt_lint0 = temp;
984263bc 195
9d6bf2df 196 /*
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197 * Setup LINT1 as NMI.
198 *
199 * Must be setup edge trigger, active high.
200 *
201 * Enable LINT1 on BSP, if I/O APIC is enabled.
202 *
203 * Disable LINT1 on the APs.
9d6bf2df 204 */
cb7d6921 205 temp = lapic->lvt_lint1;
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206 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
207 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
208 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
f45bfca0 209 if (bsp && ioapic_enable)
4d08e038 210 temp &= ~APIC_LVT_MASKED;
cb7d6921 211 lapic->lvt_lint1 = temp;
984263bc 212
c6a1aabe 213 /*
d99d4acb 214 * Mask the LAPIC error interrupt, LAPIC performance counter
78ea5a2a 215 * interrupt.
c6a1aabe 216 */
cb7d6921
SZ
217 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
218 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
78ea5a2a 219
d99d4acb
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220 /*
221 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
222 */
cb7d6921 223 timer = lapic->lvt_timer;
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224 timer &= ~APIC_LVTT_VECTOR;
225 timer |= XTIMER_OFFSET;
226 timer |= APIC_LVTT_MASKED;
cb7d6921 227 lapic->lvt_timer = timer;
c6a1aabe 228
d9eea1a5
MD
229 /*
230 * Set the Task Priority Register as needed. At the moment allow
231 * interrupts on all cpus (the APs will remain CLId until they are
1971051d 232 * ready to deal).
d9eea1a5 233 */
cb7d6921 234 temp = lapic->tpr;
984263bc 235 temp &= ~APIC_TPR_PRIO; /* clear priority field */
cb7d6921 236 lapic->tpr = temp;
984263bc 237
97359a5b 238 /*
d99d4acb 239 * Enable the LAPIC
97359a5b 240 */
cb7d6921 241 temp = lapic->svr;
d99d4acb 242 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
97359a5b 243 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 244
9d6bf2df
MD
245 /*
246 * Set the spurious interrupt vector. The low 4 bits of the vector
247 * must be 1111.
248 */
249 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 250 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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MD
251 temp &= ~APIC_SVR_VECTOR;
252 temp |= XSPURIOUSINT_OFFSET;
984263bc 253
cb7d6921 254 lapic->svr = temp;
984263bc 255
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256 /*
257 * Pump out a few EOIs to clean out interrupts that got through
258 * before we were able to set the TPR.
259 */
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SZ
260 lapic->eoi = 0;
261 lapic->eoi = 0;
262 lapic->eoi = 0;
0b692e79 263
c5b8324c 264 if (bsp) {
b52c8db0 265 lapic_timer_calibrate();
ef612539
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266 if (lapic_timer_enable) {
267 cputimer_intr_register(&lapic_cputimer_intr);
268 cputimer_intr_select(&lapic_cputimer_intr, 0);
269 }
c5b8324c 270 } else {
086575e9 271 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 272 }
b52c8db0 273
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274 if (bootverbose)
275 apic_dump("apic_initialize()");
276}
277
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278static void
279lapic_timer_set_divisor(int divisor_idx)
280{
281 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
cb7d6921 282 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
b52c8db0
SZ
283}
284
285static void
286lapic_timer_oneshot(u_int count)
287{
288 uint32_t value;
289
cb7d6921 290 value = lapic->lvt_timer;
b52c8db0 291 value &= ~APIC_LVTT_PERIODIC;
cb7d6921
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292 lapic->lvt_timer = value;
293 lapic->icr_timer = count;
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294}
295
6198c499
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296static void
297lapic_timer_oneshot_quick(u_int count)
298{
cb7d6921 299 lapic->icr_timer = count;
6198c499
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300}
301
b52c8db0
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302static void
303lapic_timer_calibrate(void)
304{
47bdf646 305 sysclock_t value;
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306
307 /* Try to calibrate the local APIC timer. */
308 for (lapic_timer_divisor_idx = 0;
309 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
310 lapic_timer_divisor_idx++) {
311 lapic_timer_set_divisor(lapic_timer_divisor_idx);
312 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
313 DELAY(2000000);
cb7d6921 314 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
b52c8db0
SZ
315 if (value != APIC_TIMER_MAX_COUNT)
316 break;
317 }
318 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
319 panic("lapic: no proper timer divisor?!\n");
ef612539 320 lapic_cputimer_intr.freq = value / 2;
b52c8db0 321
47bdf646 322 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 323 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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SZ
324}
325
c5b8324c
SZ
326static void
327lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
328{
329 sysclock_t count;
330
331 gd->gd_timer_running = 0;
332
333 count = sys_cputimer->count();
334 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
335 systimer_intr(&count, 0, frame);
336}
337
78ea5a2a
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338void
339lapic_timer_process(void)
340{
ae48d6cd 341 lapic_timer_process_oncpu(mycpu, NULL);
78ea5a2a
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342}
343
344void
345lapic_timer_process_frame(struct intrframe *frame)
346{
ae48d6cd 347 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
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348}
349
c5b8324c 350static void
ef612539 351lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
c5b8324c
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352{
353 struct globaldata *gd = mycpu;
354
ef612539 355 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
c5b8324c
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356 if (reload < 2)
357 reload = 2;
358
359 if (gd->gd_timer_running) {
cb7d6921 360 if (reload < lapic->ccr_timer)
c5b8324c
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361 lapic_timer_oneshot_quick(reload);
362 } else {
363 gd->gd_timer_running = 1;
364 lapic_timer_oneshot_quick(reload);
365 }
366}
367
ef612539
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368static void
369lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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370{
371 uint32_t timer;
372
cb7d6921 373 timer = lapic->lvt_timer;
6198c499 374 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
cb7d6921 375 lapic->lvt_timer = timer;
a9e511df
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376
377 lapic_timer_fixup_handler(NULL);
378}
379
380static void
76c58571 381lapic_timer_fixup_handler(void *arg)
a9e511df 382{
76c58571
SZ
383 int *started = arg;
384
385 if (started != NULL)
386 *started = 0;
387
90e8a35b 388 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
SZ
389 /*
390 * Detect the presence of C1E capability mostly on latest
391 * dual-cores (or future) k8 family. This feature renders
392 * the local APIC timer dead, so we disable it by reading
393 * the Interrupt Pending Message register and clearing both
394 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
395 *
396 * Reference:
397 * "BIOS and Kernel Developer's Guide for AMD NPT
398 * Family 0Fh Processors"
399 * #32559 revision 3.00
400 */
401 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
402 (cpu_id & 0x0fff0000) >= 0x00040000) {
403 uint64_t msr;
404
405 msr = rdmsr(0xc0010055);
406 if (msr & 0x18000000) {
407 struct globaldata *gd = mycpu;
408
409 kprintf("cpu%d: AMD C1E detected\n",
410 gd->gd_cpuid);
411 wrmsr(0xc0010055, msr & ~0x18000000ULL);
412
413 /*
414 * We are kinda stalled;
415 * kick start again.
416 */
417 gd->gd_timer_running = 1;
418 lapic_timer_oneshot_quick(2);
76c58571
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419
420 if (started != NULL)
421 *started = 1;
a9e511df
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422 }
423 }
424 }
425}
426
76c58571
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427static void
428lapic_timer_restart_handler(void *dummy __unused)
429{
430 int started;
431
432 lapic_timer_fixup_handler(&started);
433 if (!started) {
434 struct globaldata *gd = mycpu;
435
436 gd->gd_timer_running = 1;
437 lapic_timer_oneshot_quick(2);
438 }
439}
440
a9e511df
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441/*
442 * This function is called only by ACPI-CA code currently:
443 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
444 * module controls PM. So once ACPI-CA is attached, we try
445 * to apply the fixup to prevent LAPIC timer from hanging.
446 */
ef612539
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447static void
448lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 449{
1e7aaefa 450#ifdef SMP
ef612539
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451 lwkt_send_ipiq_mask(smp_active_mask,
452 lapic_timer_fixup_handler, NULL);
1e7aaefa
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453#else
454 lapic_timer_fixup_handler(NULL);
455#endif
6198c499
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456}
457
ef612539
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458static void
459lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 460{
1e7aaefa 461#ifdef SMP
76c58571 462 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
1e7aaefa
SZ
463#else
464 lapic_timer_restart_handler(NULL);
465#endif
76c58571
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466}
467
b52c8db0 468
984263bc
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469/*
470 * dump contents of local APIC registers
471 */
472void
473apic_dump(char* str)
474{
26be20a0
SW
475 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
476 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
cb7d6921 477 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
984263bc
MD
478}
479
1e7aaefa
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480#ifdef SMP
481
984263bc
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482/*
483 * Inter Processor Interrupt functions.
484 */
485
984263bc
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486/*
487 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
488 *
489 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
490 * vector is any valid SYSTEM INT vector
491 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
MD
492 *
493 * A backlog of requests can create a deadlock between cpus. To avoid this
494 * we have to be able to accept IPIs at the same time we are trying to send
495 * them. The critical section prevents us from attempting to send additional
496 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
497 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
498 * to occur but fortunately it does not happen too often.
984263bc 499 */
984263bc
MD
500int
501apic_ipi(int dest_type, int vector, int delivery_mode)
502{
503 u_long icr_lo;
504
96728c05 505 crit_enter();
cb7d6921 506 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
507 unsigned int eflags = read_eflags();
508 cpu_enable_intr();
cfaeae2a 509 DEBUG_PUSH_INFO("apic_ipi");
cb7d6921 510 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
511 lwkt_process_ipiq();
512 }
cfaeae2a 513 DEBUG_POP_INFO();
96728c05 514 write_eflags(eflags);
984263bc 515 }
984263bc 516
cb7d6921 517 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 518 delivery_mode | vector;
cb7d6921 519 lapic->icr_lo = icr_lo;
96728c05 520 crit_exit();
984263bc
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521 return 0;
522}
523
41a01a4d
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524void
525single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
MD
526{
527 u_long icr_lo;
528 u_long icr_hi;
984263bc 529
41a01a4d 530 crit_enter();
cb7d6921 531 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
532 unsigned int eflags = read_eflags();
533 cpu_enable_intr();
cfaeae2a 534 DEBUG_PUSH_INFO("single_apic_ipi");
cb7d6921 535 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
536 lwkt_process_ipiq();
537 }
cfaeae2a 538 DEBUG_POP_INFO();
96728c05 539 write_eflags(eflags);
984263bc 540 }
cb7d6921 541 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 542 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 543 lapic->icr_hi = icr_hi;
984263bc 544
b2f93ae9 545 /* build ICR_LOW */
cb7d6921 546 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
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MD
547 | APIC_DEST_DESTFLD | delivery_mode | vector;
548
549 /* write APIC ICR */
cb7d6921 550 lapic->icr_lo = icr_lo;
41a01a4d 551 crit_exit();
984263bc
MD
552}
553
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554#if 0
555
556/*
557 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
558 *
559 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
560 * to the target, and the scheduler does not 'poll' for IPI messages.
561 */
562int
563single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
564{
565 u_long icr_lo;
566 u_long icr_hi;
567
568 crit_enter();
cb7d6921 569 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
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570 crit_exit();
571 return(0);
572 }
cb7d6921 573 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2d901d56 574 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
cb7d6921 575 lapic->icr_hi = icr_hi;
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576
577 /* build IRC_LOW */
cb7d6921 578 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
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579 | APIC_DEST_DESTFLD | delivery_mode | vector;
580
581 /* write APIC ICR */
cb7d6921 582 lapic->icr_lo = icr_lo;
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583 crit_exit();
584 return(1);
585}
586
587#endif
588
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589/*
590 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
591 *
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592 * target is a bitmask of destination cpus. Vector is any
593 * valid system INT vector. Delivery mode may be either
594 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 595 */
41a01a4d 596void
da23a592 597selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 598{
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599 crit_enter();
600 while (target) {
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601 int n = BSFCPUMASK(target);
602 target &= ~CPUMASK(n);
41a01a4d 603 single_apic_ipi(n, vector, delivery_mode);
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604 }
605 crit_exit();
984263bc 606}
984263bc 607
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608#endif /* SMP */
609
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610/*
611 * Timer code, in development...
612 * - suggested by rgrimes@gndrsh.aac.dev.com
613 */
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614int
615get_apic_timer_frequency(void)
616{
617 return(lapic_cputimer_intr.freq);
618}
984263bc 619
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620/*
621 * Load a 'downcount time' in uSeconds.
622 */
623void
2942ed63 624set_apic_timer(int us)
984263bc 625{
2942ed63 626 u_int count;
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627
628 /*
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629 * When we reach here, lapic timer's frequency
630 * must have been calculated as well as the
631 * divisor (lapic.dcr_timer is setup during the
632 * divisor calculation).
984263bc 633 */
ef612539 634 KKASSERT(lapic_cputimer_intr.freq != 0 &&
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635 lapic_timer_divisor_idx >= 0);
636
ef612539 637 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 638 lapic_timer_oneshot(count);
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639}
640
641
642/*
643 * Read remaining time in timer.
644 */
645int
646read_apic_timer(void)
647{
648#if 0
649 /** XXX FIXME: we need to return the actual remaining time,
650 * for now we just return the remaining count.
651 */
652#else
cb7d6921 653 return lapic->ccr_timer;
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654#endif
655}
656
657
658/*
659 * Spin-style delay, set delay time in uS, spin till it drains.
660 */
661void
662u_sleep(int count)
663{
664 set_apic_timer(count);
665 while (read_apic_timer())
666 /* spin */ ;
667}
ad52b37b 668
11bae9b8 669int
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670lapic_unused_apic_id(int start)
671{
672 int i;
673
674 for (i = start; i < NAPICID; ++i) {
2d901d56 675 if (APICID_TO_CPUID(i) == -1)
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676 return i;
677 }
678 return NAPICID;
679}
680
ad52b37b 681void
1ebd15a6 682lapic_map(vm_paddr_t lapic_addr)
ad52b37b 683{
cb7d6921 684 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
ad52b37b 685}
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686
687static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
688 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
689
ac032dad 690int
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691lapic_config(void)
692{
693 struct lapic_enumerator *e;
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694 int error, i, ap_max;
695
696 KKASSERT(lapic_enable);
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697
698 for (i = 0; i < NAPICID; ++i)
2d901d56 699 APICID_TO_CPUID(i) = -1;
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700
701 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
702 error = e->lapic_probe(e);
703 if (!error)
704 break;
705 }
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706 if (e == NULL) {
707 kprintf("LAPIC: Can't find LAPIC\n");
708 return ENXIO;
709 }
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710
711 e->lapic_enumerate(e);
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712
713 ap_max = MAXCPU - 1;
714 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
715 if (ap_max > MAXCPU - 1)
716 ap_max = MAXCPU - 1;
717
2abaa030 718 if (naps > ap_max) {
fdab6c5c 719 kprintf("LAPIC: Warning use only %d out of %d "
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720 "available APs\n", ap_max, naps);
721 naps = ap_max;
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722 }
723
ac032dad 724 return 0;
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725}
726
727void
728lapic_enumerator_register(struct lapic_enumerator *ne)
729{
730 struct lapic_enumerator *e;
731
732 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
733 if (e->lapic_prio < ne->lapic_prio) {
734 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
735 return;
736 }
737 }
738 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
739}
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740
741void
742lapic_set_cpuid(int cpu_id, int apic_id)
743{
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744 CPUID_TO_APICID(cpu_id) = apic_id;
745 APICID_TO_CPUID(apic_id) = cpu_id;
41e2c7e0 746}
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747
748void
749lapic_fixup_noioapic(void)
750{
751 u_int temp;
752
753 /* Only allowed on BSP */
754 KKASSERT(mycpuid == 0);
f45bfca0 755 KKASSERT(!ioapic_enable);
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756
757 temp = lapic->lvt_lint0;
758 temp &= ~APIC_LVT_MASKED;
759 lapic->lvt_lint0 = temp;
760
761 temp = lapic->lvt_lint1;
762 temp |= APIC_LVT_MASKED;
763 lapic->lvt_lint1 = temp;
764}
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765
766static void
767lapic_sysinit(void *dummy __unused)
768{
769 if (lapic_enable) {
770 int error;
771
772 error = lapic_config();
773 if (error)
774 lapic_enable = 0;
775 }
776
777 if (lapic_enable) {
778 /* Initialize BSP's local APIC */
779 lapic_init(TRUE);
780 } else if (ioapic_enable) {
781 ioapic_enable = 0;
782 icu_reinit_noioapic();
783 }
784}
785SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL)