[dragonfly.git] / sys / boot / pc32 / bootasm.h

/* 
 * Copyright (c) 2004 The DragonFly Project.  All rights reserved.
 * 
 * This code is derived from software contributed to The DragonFly Project
 * by Matthew Dillon <dillon@backplane.com>
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name of The DragonFly Project nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific, prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $DragonFly: src/sys/boot/pc32/bootasm.h,v 1.4 2004/07/27 19:37:15 dillon Exp $
 */

/* 
 * Set the bootloader address set.
 *
 * UNSET - default backwards compatible boot blocks
 *   1   - experimental move addresses above 0x1000 and hardwire the user
 *	   stack.
 *   2   - experimental move addresses abobe 0x2000 and hardwire the user
 *	   stack.
 */
/* #define BOOT_NEWBOOTLOADER 2 */

/*
 * Various fixed constants that do not change
 */

#define BDA_MEM		0x413		/* Free memory		*/
#define BDA_KEYFLAGS	0x417		/* Keyboard shift-state flags	*/
#define BDA_SCR		0x449		/* Video mode		*/
#define BDA_POS		0x450		/* Cursor position	*/
#define BDA_BOOT	0x472		/* Boot howto flag	*/
#define BDA_NHRDRV	0x475
#define BDA_KEYBOARD	0x496		/* BDA byte with keyboard bit */

/*
 * Structural equivalences
 */
#define BOOTINFO_SIZE	0x48		/* bootinfo structure size */
#define MEM_ARG_SIZE	0x18
#define MEM_PAGE_SIZE	0x1000
#define MEM_BTX_LDR_OFF	MEM_PAGE_SIZE	/* offset of btx in the loader */
#define USR_ARGOFFSET	(BOOTINFO_SIZE+MEM_ARG_SIZE)

/* -------- WARNING, BOOT0 STACK BELOW MEM_BIOS_LADDR -------- */
#define MEM_BIOS_LADDR	0x7c00		/* Load address (static/BIOS) */

/*
 * This is the origin of boot2.bin relative to the BTX user address space
 * (e.g. physical address would be MEM_BTX_USR+BOOT2_VORIGIN).
 *
 * The physical origin is typically around 0xC000 and limits the size of
 * boot2 to 16K, otherwise the loader will overflow the segment in v86 mode.
 */
#define BOOT2_VORIGIN	0x2000

/*
 * NOTE: BOOT0_ORIGIN is extracted from this file and used in boot0/Makefile
 * 	 BOOT1_ORIGIN is extracted from this file and used in boot2/Makefile
 *
 *	 NOTE: boot0 has a variable space after its sector which contains
 *	 the fake partition and other variables.  ~128 bytes should be reserved
 *	 for this variable space, but it may overlap BOOT1's data space.
 */

#if !defined(BOOT_NEWBOOTLOADER)

/************************************************************************
 *			STANDARD BOOTLOADER ADDRESS SET 		*
 ************************************************************************
 *
 *
 */

#define USR_ARGSPACE	0x1000		/* BTX loader / ttl argspace reserved */

#define BOOT0_ORIGIN	0x600		/* boot0 relocated to (512+128 bytes) */
/* -------- WARNING, BOOT1 STACK BELOW BOOT1_ORIGIN ------- */
#define BOOT1_ORIGIN	0x700		/* boot1 relocated to (512 bytes) */
#define MEM_ARG		0x900		/* tmp arg store cdboot/pxeboot */

#define MEM_BTX_ESP	0x1000		/* btxldr top of stack? */
#define MEM_BTX_START	0x1000		/* start of BTX memory */
#define MEM_BTX_ESP0	0x1800		/* Supervisor stack */
#define MEM_BTX_BUF	0x1800		/* Scratch buffer stack */
#define MEM_BTX_ESP1	0x1e00		/* Link stack */
#define MEM_BTX_IDT	0x1e00		/* IDT */
#define MEM_BTX_TSS	0x1f98		/* TSS */
#define MEM_BTX_MAP	0x2000		/* I/O bit map */
#define MEM_BTX_DIR	0x4000		/* Page directory */

/*
 * NOTE: page table location is hardwired in /usr/src/usr.sbin/btxld/btx.h
 */
#define MEM_BTX_TBL	0x5000		/* Page tables */
#define MEM_BTX_ZEND	0x7000		/* Zero from IDT to here in btx.S */

/********************   0x7c00 BIOS LOAD ADDRESS (512 bytes) **********/

/*
 * NOTE: BOOT2_LOAD_BUF also determines where the btx loader and boot2.bin
 *       code are loaded, since they are all in the boot2 file.
 */
#define BOOT2_LOAD_BUF	0x8c00		/* boot1 loads boot2	*/
#define MEM_BTX_ORG	0x9000		/* base of BTX code */
#define MEM_BTX_ENTRY	0x9010		/* BTX starts execution here */
/*
 * WARNING!  The USR area may be messed around with in 16 bit code mode,
 *           data loaded should probably not cross 0xffff (e.g. boot2 loads
 *	     ~8K at MEM_BTX_USR).
 *
 *	     MEM_BTX_USR is basically the segment offset BTX uses when
 *	     running 'client' code.  So address 0 in the client code will
 *	     actually be physical address MEM_BTX_USR.
 */
#define MEM_BTX_USR	0xa000		/* base of BTX client/user memory */
#define MEM_BTX_USR_ARG	0xa100

#elif defined(BOOT_NEWBOOTLOADER) && BOOT_NEWBOOTLOADER == 1

/************************************************************************
 *		EXPERIMENTAL BOOTLOADER ADDRESS SET 1			*
 ************************************************************************
 *
 *
 */

#define USR_ARGSPACE	0x1000		/* BTX loader / ttl argspace reserved */
#define MEM_BTX_USR_STK	0x90000		/* (phys addr) btx client usr stack */

#define MEM_BTX_START	0x1000		/* (unchanged)		*/
#define MEM_BTX_ESP0	0x1800		/* (unchanged)		*/
#define MEM_BTX_BUF	0x1800		/* (unchanged)		*/
#define MEM_BTX_ESP1	0x1e00		/* (unchanged)		*/
#define MEM_BTX_IDT	0x1e00		/* (unchanged)		*/
#define MEM_BTX_TSS	0x1f98		/* (unchanged)		*/
#define MEM_BTX_MAP	0x2000		/* (unchanged)		*/
#define MEM_BTX_DIR	0x4000		/* (unchanged)		*/
#define MEM_BTX_TBL	0x5000		/* (unchanged)		*/
#define MEM_BTX_ZEND	0x7000		/* (unchanged)		*/

#define MEM_BTX_ESP	0x7800		/* don't use 0x1000 		*/
#define BOOT0_ORIGIN	0x7800		/* boot0 relocated		*/
#define BOOT1_ORIGIN	0x7900		/* boot1 relocated (data only?) */
#define MEM_ARG		0x7b00		/* cdboot/pxeboot disk/slice xfer */
/********************   0x7c00 BIOS LOAD ADDRESS (512 bytes) **********/

#define BOOT2_LOAD_BUF	0x8c00		/* (unchanged)		*/
#define MEM_BTX_ORG	0x9000		/* (unchanged)		*/
#define MEM_BTX_ENTRY	0x9010		/* (unchanged)		*/

#define MEM_BTX_USR	0xa000		/* (unchanged)		*/
#define MEM_BTX_USR_ARG	0xa100		/* (unchanged)		*/


#elif defined(BOOT_NEWBOOTLOADER) && BOOT_NEWBOOTLOADER == 2

/************************************************************************
 *		EXPERIMENTAL BOOTLOADER ADDRESS SET 2			*
 ************************************************************************
 *
 *
 */
#define USR_ARGSPACE	0x1000		/* BTX loader / ttl argspace reserved */
#define MEM_BTX_USR_STK	0x90000		/* (phys addr) btx client usr stack */

#define MEM_BTX_START	0x2000		/* (unchanged)		*/
#define MEM_BTX_ESP0	0x2800		/* (unchanged)		*/
#define MEM_BTX_BUF	0x2800		/* (unchanged)		*/
#define MEM_BTX_ESP1	0x2e00		/* (unchanged)		*/
#define MEM_BTX_IDT	0x2e00		/* (unchanged)		*/
#define MEM_BTX_TSS	0x2f98		/* (unchanged)		*/
#define MEM_BTX_MAP	0x3000		/* (unchanged)		*/
#define MEM_BTX_DIR	0x5000		/* (unchanged)		*/
/****** MEM_BTX_TBL (16K) SUPPORT REMOVED ***********************/
#define MEM_BTX_ZEND	0x6000		/* (unchanged)		*/

#define MEM_BTX_ESP	0x7800		/* don't use 0x1000 		*/
#define BOOT0_ORIGIN	0x7800		/* boot0 relocated		*/
#define BOOT1_ORIGIN	0x7900		/* boot1 relocated (data only?) */
#define MEM_ARG		0x7b00		/* cdboot/pxeboot disk/slice xfer */
/********************   0x7c00 BIOS LOAD ADDRESS (512 bytes) **********/

#define BOOT2_LOAD_BUF	0x8c00		/* (unchanged)		*/
#define MEM_BTX_ORG	0x9000		/* (unchanged)		*/
#define MEM_BTX_ENTRY	0x9010		/* (unchanged)		*/

#define MEM_BTX_USR	0xa000		/* base of BTX client/user memory */
#define MEM_BTX_USR_ARG	0xa100		/* boot1->boot2 disk/slice xfer */

#else

#error "BAD BOOT_NEWBOOTLOADER SETTING.  UNSET TO GET DEFAULT"

#endif	/* BOOT_NEWBOOTLOADER */
Commit	Line	Data
409cbc03 MD	1	/*
	2	* Copyright (c) 2004 The DragonFly Project. All rights reserved.
	3	*
	4	* This code is derived from software contributed to The DragonFly Project
	5	* by Matthew Dillon <dillon@backplane.com>
	6	*
	7	* Redistribution and use in source and binary forms, with or without
	8	* modification, are permitted provided that the following conditions
	9	* are met:
	10	*
	11	* 1. Redistributions of source code must retain the above copyright
	12	* notice, this list of conditions and the following disclaimer.
	13	* 2. Redistributions in binary form must reproduce the above copyright
	14	* notice, this list of conditions and the following disclaimer in
	15	* the documentation and/or other materials provided with the
	16	* distribution.
	17	* 3. Neither the name of The DragonFly Project nor the names of its
	18	* contributors may be used to endorse or promote products derived
	19	* from this software without specific, prior written permission.
	20	*
	21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	22	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	24	* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	25	* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	26	* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
	27	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	28	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
	29	* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
	31	* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	32	* SUCH DAMAGE.
	33	*
4e06dda7	34	* $DragonFly: src/sys/boot/pc32/bootasm.h,v 1.4 2004/07/27 19:37:15 dillon Exp $
409cbc03 MD	35	*/
409cbc03 MD	36
cacaceec MD	37	/*
	38	* Set the bootloader address set.
	39	*
	40	* UNSET - default backwards compatible boot blocks
	41	* 1 - experimental move addresses above 0x1000 and hardwire the user
	42	* stack.
	43	* 2 - experimental move addresses abobe 0x2000 and hardwire the user
	44	* stack.
04144d62	45	*/
cacaceec	46	/* #define BOOT_NEWBOOTLOADER 2 */
409cbc03	47
cacaceec MD	48	/*
	49	* Various fixed constants that do not change
	50	*/
04144d62	51
409cbc03 MD	52	#define BDA_MEM 0x413 /* Free memory */
	53	#define BDA_KEYFLAGS 0x417 /* Keyboard shift-state flags */
	54	#define BDA_SCR 0x449 /* Video mode */
	55	#define BDA_POS 0x450 /* Cursor position */
cacaceec MD	56	#define BDA_BOOT 0x472 /* Boot howto flag */
cacaceec MD	57	#define BDA_NHRDRV 0x475
409cbc03 MD	58	#define BDA_KEYBOARD 0x496 /* BDA byte with keyboard bit */
409cbc03 MD	59
cacaceec MD	60	/*
	61	* Structural equivalences
	62	*/
	63	#define BOOTINFO_SIZE 0x48 /* bootinfo structure size */
	64	#define MEM_ARG_SIZE 0x18
	65	#define MEM_PAGE_SIZE 0x1000
	66	#define MEM_BTX_LDR_OFF MEM_PAGE_SIZE /* offset of btx in the loader */
	67	#define USR_ARGOFFSET (BOOTINFO_SIZE+MEM_ARG_SIZE)
	68
	69	/* -------- WARNING, BOOT0 STACK BELOW MEM_BIOS_LADDR -------- */
	70	#define MEM_BIOS_LADDR 0x7c00 /* Load address (static/BIOS) */
	71
	72	/*
4e06dda7 MD	73	* This is the origin of boot2.bin relative to the BTX user address space
4e06dda7 MD	74	* (e.g. physical address would be MEM_BTX_USR+BOOT2_VORIGIN).
d64b2e33 MD	75	*
	76	* The physical origin is typically around 0xC000 and limits the size of
	77	* boot2 to 16K, otherwise the loader will overflow the segment in v86 mode.
4e06dda7	78	*/
d64b2e33	79	#define BOOT2_VORIGIN 0x2000
4e06dda7 MD	80
4e06dda7 MD	81	/*
cacaceec MD	82	* NOTE: BOOT0_ORIGIN is extracted from this file and used in boot0/Makefile
	83	* BOOT1_ORIGIN is extracted from this file and used in boot2/Makefile
	84	*
	85	* NOTE: boot0 has a variable space after its sector which contains
	86	* the fake partition and other variables. ~128 bytes should be reserved
	87	* for this variable space, but it may overlap BOOT1's data space.
	88	*/
	89
	90	#if !defined(BOOT_NEWBOOTLOADER)
	91
	92	/************************************************************************
	93	* STANDARD BOOTLOADER ADDRESS SET *
	94	************************************************************************
	95	*
	96	*
	97	*/
	98
	99	#define USR_ARGSPACE 0x1000 /* BTX loader / ttl argspace reserved */
	100
	101	#define BOOT0_ORIGIN 0x600 /* boot0 relocated to (512+128 bytes) */
	102	/* -------- WARNING, BOOT1 STACK BELOW BOOT1_ORIGIN ------- */
	103	#define BOOT1_ORIGIN 0x700 /* boot1 relocated to (512 bytes) */
	104	#define MEM_ARG 0x900 /* tmp arg store cdboot/pxeboot */
	105
04144d62	106	#define MEM_BTX_ESP 0x1000 /* btxldr top of stack? */
409cbc03 MD	107	#define MEM_BTX_START 0x1000 /* start of BTX memory */
	108	#define MEM_BTX_ESP0 0x1800 /* Supervisor stack */
	109	#define MEM_BTX_BUF 0x1800 /* Scratch buffer stack */
	110	#define MEM_BTX_ESP1 0x1e00 /* Link stack */
	111	#define MEM_BTX_IDT 0x1e00 /* IDT */
	112	#define MEM_BTX_TSS 0x1f98 /* TSS */
	113	#define MEM_BTX_MAP 0x2000 /* I/O bit map */
	114	#define MEM_BTX_DIR 0x4000 /* Page directory */
04144d62 MD	115
	116	/*
	117	* NOTE: page table location is hardwired in /usr/src/usr.sbin/btxld/btx.h
	118	*/
409cbc03	119	#define MEM_BTX_TBL 0x5000 /* Page tables */
cacaceec MD	120	#define MEM_BTX_ZEND 0x7000 /* Zero from IDT to here in btx.S */
	121
	122	/****************** 0x7c00 BIOS LOAD ADDRESS (512 bytes) ********/
04144d62 MD	123
	124	/*
	125	* NOTE: BOOT2_LOAD_BUF also determines where the btx loader and boot2.bin
	126	* code are loaded, since they are all in the boot2 file.
	127	*/
	128	#define BOOT2_LOAD_BUF 0x8c00 /* boot1 loads boot2 */
409cbc03 MD	129	#define MEM_BTX_ORG 0x9000 /* base of BTX code */
409cbc03 MD	130	#define MEM_BTX_ENTRY 0x9010 /* BTX starts execution here */
cacaceec MD	131	/*
	132	* WARNING! The USR area may be messed around with in 16 bit code mode,
	133	* data loaded should probably not cross 0xffff (e.g. boot2 loads
	134	* ~8K at MEM_BTX_USR).
	135	*
	136	* MEM_BTX_USR is basically the segment offset BTX uses when
	137	* running 'client' code. So address 0 in the client code will
	138	* actually be physical address MEM_BTX_USR.
	139	*/
409cbc03 MD	140	#define MEM_BTX_USR 0xa000 /* base of BTX client/user memory */
409cbc03 MD	141	#define MEM_BTX_USR_ARG 0xa100
cacaceec MD	142
	143	#elif defined(BOOT_NEWBOOTLOADER) && BOOT_NEWBOOTLOADER == 1
	144
	145	/************************************************************************
	146	* EXPERIMENTAL BOOTLOADER ADDRESS SET 1 *
	147	************************************************************************
	148	*
	149	*
	150	*/
	151
	152	#define USR_ARGSPACE 0x1000 /* BTX loader / ttl argspace reserved */
	153	#define MEM_BTX_USR_STK 0x90000 /* (phys addr) btx client usr stack */
	154
	155	#define MEM_BTX_START 0x1000 /* (unchanged) */
	156	#define MEM_BTX_ESP0 0x1800 /* (unchanged) */
	157	#define MEM_BTX_BUF 0x1800 /* (unchanged) */
	158	#define MEM_BTX_ESP1 0x1e00 /* (unchanged) */
	159	#define MEM_BTX_IDT 0x1e00 /* (unchanged) */
	160	#define MEM_BTX_TSS 0x1f98 /* (unchanged) */
	161	#define MEM_BTX_MAP 0x2000 /* (unchanged) */
	162	#define MEM_BTX_DIR 0x4000 /* (unchanged) */
	163	#define MEM_BTX_TBL 0x5000 /* (unchanged) */
	164	#define MEM_BTX_ZEND 0x7000 /* (unchanged) */
	165
	166	#define MEM_BTX_ESP 0x7800 /* don't use 0x1000 */
	167	#define BOOT0_ORIGIN 0x7800 /* boot0 relocated */
	168	#define BOOT1_ORIGIN 0x7900 /* boot1 relocated (data only?) */
	169	#define MEM_ARG 0x7b00 /* cdboot/pxeboot disk/slice xfer */
	170	/****************** 0x7c00 BIOS LOAD ADDRESS (512 bytes) ********/
	171
	172	#define BOOT2_LOAD_BUF 0x8c00 /* (unchanged) */
	173	#define MEM_BTX_ORG 0x9000 /* (unchanged) */
	174	#define MEM_BTX_ENTRY 0x9010 /* (unchanged) */
	175
	176	#define MEM_BTX_USR 0xa000 /* (unchanged) */
	177	#define MEM_BTX_USR_ARG 0xa100 /* (unchanged) */
	178
	179
	180	#elif defined(BOOT_NEWBOOTLOADER) && BOOT_NEWBOOTLOADER == 2
	181
	182	/************************************************************************
	183	* EXPERIMENTAL BOOTLOADER ADDRESS SET 2 *
	184	************************************************************************
	185	*
	186	*
	187	*/
	188	#define USR_ARGSPACE 0x1000 /* BTX loader / ttl argspace reserved */
	189	#define MEM_BTX_USR_STK 0x90000 /* (phys addr) btx client usr stack */
	190
	191	#define MEM_BTX_START 0x2000 /* (unchanged) */
	192	#define MEM_BTX_ESP0 0x2800 /* (unchanged) */
	193	#define MEM_BTX_BUF 0x2800 /* (unchanged) */
	194	#define MEM_BTX_ESP1 0x2e00 /* (unchanged) */
	195	#define MEM_BTX_IDT 0x2e00 /* (unchanged) */
	196	#define MEM_BTX_TSS 0x2f98 /* (unchanged) */
	197	#define MEM_BTX_MAP 0x3000 /* (unchanged) */
	198	#define MEM_BTX_DIR 0x5000 /* (unchanged) */
	199	/**** MEM_BTX_TBL (16K) SUPPORT REMOVED *********************/
	200	#define MEM_BTX_ZEND 0x6000 /* (unchanged) */
	201
	202	#define MEM_BTX_ESP 0x7800 /* don't use 0x1000 */
	203	#define BOOT0_ORIGIN 0x7800 /* boot0 relocated */
	204	#define BOOT1_ORIGIN 0x7900 /* boot1 relocated (data only?) */
	205	#define MEM_ARG 0x7b00 /* cdboot/pxeboot disk/slice xfer */
206	/****************** 0x7c00 BIOS LOAD ADDRESS (512 bytes) ********/
207
208	#define BOOT2_LOAD_BUF 0x8c00 /* (unchanged) */
209	#define MEM_BTX_ORG 0x9000 /* (unchanged) */
210	#define MEM_BTX_ENTRY 0x9010 /* (unchanged) */
211
212	#define MEM_BTX_USR 0xa000 /* base of BTX client/user memory */
213	#define MEM_BTX_USR_ARG 0xa100 /* boot1->boot2 disk/slice xfer */
214
215	#else
216
217	#error "BAD BOOT_NEWBOOTLOADER SETTING. UNSET TO GET DEFAULT"
218
219	#endif /* BOOT_NEWBOOTLOADER */
409cbc03	220