MPI Driver update
[dragonfly.git] / sys / dev / disk / mpt / mpt_pci.c
CommitLineData
d751f32e
MD
1/*-
2 * PCI specific probe and attach routines for LSI Fusion Adapters
984263bc
MD
3 * FreeBSD Version.
4 *
d751f32e 5 * Copyright (c) 2000, 2001 by Greg Ansley
984263bc 6 * Partially derived from Matt Jacob's ISP driver.
d751f32e
MD
7 * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob
8 * Feral Software
9 * All rights reserved.
984263bc
MD
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
d751f32e
MD
32/*-
33 * Copyright (c) 2002, 2006 by Matthew Jacob
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are
38 * met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
42 * substantially similar to the "NO WARRANTY" disclaimer below
43 * ("Disclaimer") and any redistribution must be conditioned upon including
44 * a substantially similar Disclaimer requirement for further binary
45 * redistribution.
46 * 3. Neither the names of the above listed copyright holders nor the names
47 * of any contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
60 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 * Support from Chris Ellsworth in order to make SAS adapters work
63 * is gratefully acknowledged.
64 *
65 * Support from LSI-Logic has also gone a great deal toward making this a
66 * workable subsystem and is gratefully acknowledged.
67 */
984263bc 68/*
d751f32e
MD
69 * Copyright (c) 2004, Avid Technology, Inc. and its contributors.
70 * Copyright (c) 2005, WHEEL Sp. z o.o.
71 * Copyright (c) 2004, 2005 Justin T. Gibbs
72 * All rights reserved.
73 *
74 * Redistribution and use in source and binary forms, with or without
75 * modification, are permitted provided that the following conditions are
76 * met:
77 * 1. Redistributions of source code must retain the above copyright
78 * notice, this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
80 * substantially similar to the "NO WARRANTY" disclaimer below
81 * ("Disclaimer") and any redistribution must be conditioned upon including
82 * a substantially similar Disclaimer requirement for further binary
83 * redistribution.
84 * 3. Neither the names of the above listed copyright holders nor the names
85 * of any contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
91 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
92 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
98 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
984263bc
MD
99 */
100
d751f32e
MD
101#include <sys/cdefs.h>
102__FBSDID("$FreeBSD: src/sys/dev/mpt/mpt_pci.c,v 1.54 2009/07/10 08:18:08 scottl Exp $");
103
104#include <dev/mpt/mpt.h>
105#include <dev/mpt/mpt_cam.h>
106#include <dev/mpt/mpt_raid.h>
984263bc 107
d751f32e
MD
108#if __FreeBSD_version < 700000
109#define pci_msix_count(x) 0
110#define pci_msi_count(x) 0
111#define pci_alloc_msi(x, y) 1
112#define pci_alloc_msix(x, y) 1
113#define pci_release_msi(x) do { ; } while (0)
114#endif
115
116#ifndef PCI_VENDOR_LSI
117#define PCI_VENDOR_LSI 0x1000
118#endif
984263bc 119
d751f32e
MD
120#ifndef PCI_PRODUCT_LSI_FC909
121#define PCI_PRODUCT_LSI_FC909 0x0620
122#endif
123
124#ifndef PCI_PRODUCT_LSI_FC909A
125#define PCI_PRODUCT_LSI_FC909A 0x0621
126#endif
127
128#ifndef PCI_PRODUCT_LSI_FC919
129#define PCI_PRODUCT_LSI_FC919 0x0624
130#endif
131
132#ifndef PCI_PRODUCT_LSI_FC929
133#define PCI_PRODUCT_LSI_FC929 0x0622
134#endif
135
136#ifndef PCI_PRODUCT_LSI_FC929X
137#define PCI_PRODUCT_LSI_FC929X 0x0626
138#endif
139
140#ifndef PCI_PRODUCT_LSI_FC919X
141#define PCI_PRODUCT_LSI_FC919X 0x0628
142#endif
143
144#ifndef PCI_PRODUCT_LSI_FC7X04X
145#define PCI_PRODUCT_LSI_FC7X04X 0x0640
146#endif
147
148#ifndef PCI_PRODUCT_LSI_FC646
149#define PCI_PRODUCT_LSI_FC646 0x0646
150#endif
151
152#ifndef PCI_PRODUCT_LSI_1030
153#define PCI_PRODUCT_LSI_1030 0x0030
154#endif
155
156#ifndef PCI_PRODUCT_LSI_SAS1064
157#define PCI_PRODUCT_LSI_SAS1064 0x0050
158#endif
159
160#ifndef PCI_PRODUCT_LSI_SAS1064A
161#define PCI_PRODUCT_LSI_SAS1064A 0x005C
162#endif
163
164#ifndef PCI_PRODUCT_LSI_SAS1064E
165#define PCI_PRODUCT_LSI_SAS1064E 0x0056
166#endif
167
168#ifndef PCI_PRODUCT_LSI_SAS1066
169#define PCI_PRODUCT_LSI_SAS1066 0x005E
170#endif
171
172#ifndef PCI_PRODUCT_LSI_SAS1066E
173#define PCI_PRODUCT_LSI_SAS1066E 0x005A
174#endif
175
176#ifndef PCI_PRODUCT_LSI_SAS1068
177#define PCI_PRODUCT_LSI_SAS1068 0x0054
178#endif
179
180#ifndef PCI_PRODUCT_LSI_SAS1068E
181#define PCI_PRODUCT_LSI_SAS1068E 0x0058
182#endif
183
184#ifndef PCI_PRODUCT_LSI_SAS1078
185#define PCI_PRODUCT_LSI_SAS1078 0x0062
186#endif
187
188#ifndef PCI_PRODUCT_LSI_SAS1078DE
189#define PCI_PRODUCT_LSI_SAS1078DE 0x007C
190#endif
984263bc 191
984263bc
MD
192#ifndef PCIM_CMD_SERRESPEN
193#define PCIM_CMD_SERRESPEN 0x0100
194#endif
195
196
d751f32e
MD
197#define MPT_IO_BAR 0
198#define MPT_MEM_BAR 1
984263bc 199
d751f32e
MD
200static int mpt_pci_probe(device_t);
201static int mpt_pci_attach(device_t);
202static void mpt_free_bus_resources(struct mpt_softc *mpt);
203static int mpt_pci_detach(device_t);
204static int mpt_pci_shutdown(device_t);
205static int mpt_dma_mem_alloc(struct mpt_softc *mpt);
206static void mpt_dma_mem_free(struct mpt_softc *mpt);
207static void mpt_read_config_regs(struct mpt_softc *mpt);
984263bc
MD
208static void mpt_pci_intr(void *);
209
210static device_method_t mpt_methods[] = {
211 /* Device interface */
d751f32e
MD
212 DEVMETHOD(device_probe, mpt_pci_probe),
213 DEVMETHOD(device_attach, mpt_pci_attach),
214 DEVMETHOD(device_detach, mpt_pci_detach),
215 DEVMETHOD(device_shutdown, mpt_pci_shutdown),
984263bc
MD
216 { 0, 0 }
217};
218
219static driver_t mpt_driver = {
d751f32e 220 "mpt", mpt_methods, sizeof(struct mpt_softc)
984263bc
MD
221};
222static devclass_t mpt_devclass;
223DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, 0, 0);
d751f32e 224MODULE_DEPEND(mpt, pci, 1, 1, 1);
984263bc
MD
225MODULE_VERSION(mpt, 1);
226
984263bc 227static int
d751f32e 228mpt_pci_probe(device_t dev)
984263bc
MD
229{
230 char *desc;
231
d751f32e 232 if (pci_get_vendor(dev) != PCI_VENDOR_LSI) {
984263bc 233 return (ENXIO);
d751f32e 234 }
984263bc
MD
235
236 switch ((pci_get_device(dev) & ~1)) {
d751f32e 237 case PCI_PRODUCT_LSI_FC909:
984263bc
MD
238 desc = "LSILogic FC909 FC Adapter";
239 break;
d751f32e 240 case PCI_PRODUCT_LSI_FC909A:
984263bc
MD
241 desc = "LSILogic FC909A FC Adapter";
242 break;
d751f32e 243 case PCI_PRODUCT_LSI_FC919:
984263bc
MD
244 desc = "LSILogic FC919 FC Adapter";
245 break;
d751f32e
MD
246 case PCI_PRODUCT_LSI_FC929:
247 desc = "Dual LSILogic FC929 FC Adapter";
984263bc 248 break;
d751f32e
MD
249 case PCI_PRODUCT_LSI_FC919X:
250 desc = "LSILogic FC919 FC PCI-X Adapter";
d30c73c7 251 break;
d751f32e
MD
252 case PCI_PRODUCT_LSI_FC929X:
253 desc = "Dual LSILogic FC929X 2Gb/s FC PCI-X Adapter";
254 break;
255 case PCI_PRODUCT_LSI_FC646:
256 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-Express Adapter";
257 break;
258 case PCI_PRODUCT_LSI_FC7X04X:
259 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-X Adapter";
260 break;
261 case PCI_PRODUCT_LSI_1030:
984263bc
MD
262 desc = "LSILogic 1030 Ultra4 Adapter";
263 break;
d751f32e
MD
264 case PCI_PRODUCT_LSI_SAS1064:
265 case PCI_PRODUCT_LSI_SAS1064A:
266 case PCI_PRODUCT_LSI_SAS1064E:
267 case PCI_PRODUCT_LSI_SAS1066:
268 case PCI_PRODUCT_LSI_SAS1066E:
269 case PCI_PRODUCT_LSI_SAS1068:
270 case PCI_PRODUCT_LSI_SAS1068E:
271 case PCI_PRODUCT_LSI_SAS1078:
272 case PCI_PRODUCT_LSI_SAS1078DE:
273 desc = "LSILogic SAS/SATA Adapter";
274 break;
984263bc
MD
275 default:
276 return (ENXIO);
277 }
278
279 device_set_desc(dev, desc);
280 return (0);
281}
282
d751f32e 283#if __FreeBSD_version < 500000
984263bc 284static void
d751f32e 285mpt_set_options(struct mpt_softc *mpt)
984263bc
MD
286{
287 int bitmap;
288
289 bitmap = 0;
d751f32e 290 if (getenv_int("mpt_disable", &bitmap)) {
984263bc
MD
291 if (bitmap & (1 << mpt->unit)) {
292 mpt->disabled = 1;
293 }
294 }
d751f32e
MD
295 bitmap = 0;
296 if (getenv_int("mpt_debug", &bitmap)) {
297 if (bitmap & (1 << mpt->unit)) {
298 mpt->verbose = MPT_PRT_DEBUG;
299 }
300 }
301 bitmap = 0;
302 if (getenv_int("mpt_debug1", &bitmap)) {
303 if (bitmap & (1 << mpt->unit)) {
304 mpt->verbose = MPT_PRT_DEBUG1;
305 }
306 }
307 bitmap = 0;
308 if (getenv_int("mpt_debug2", &bitmap)) {
309 if (bitmap & (1 << mpt->unit)) {
310 mpt->verbose = MPT_PRT_DEBUG2;
311 }
312 }
313 bitmap = 0;
314 if (getenv_int("mpt_debug3", &bitmap)) {
315 if (bitmap & (1 << mpt->unit)) {
316 mpt->verbose = MPT_PRT_DEBUG3;
317 }
318 }
984263bc 319
d751f32e
MD
320 mpt->cfg_role = MPT_ROLE_DEFAULT;
321 bitmap = 0;
322 if (getenv_int("mpt_nil_role", &bitmap)) {
323 if (bitmap & (1 << mpt->unit)) {
324 mpt->cfg_role = 0;
325 }
326 mpt->do_cfg_role = 1;
327 }
328 bitmap = 0;
329 if (getenv_int("mpt_tgt_role", &bitmap)) {
330 if (bitmap & (1 << mpt->unit)) {
331 mpt->cfg_role |= MPT_ROLE_TARGET;
332 }
333 mpt->do_cfg_role = 1;
334 }
984263bc 335 bitmap = 0;
d751f32e 336 if (getenv_int("mpt_ini_role", &bitmap)) {
984263bc 337 if (bitmap & (1 << mpt->unit)) {
d751f32e 338 mpt->cfg_role |= MPT_ROLE_INITIATOR;
984263bc 339 }
d751f32e
MD
340 mpt->do_cfg_role = 1;
341 }
342 mpt->msi_enable = 0;
343}
344#else
345static void
346mpt_set_options(struct mpt_softc *mpt)
347{
348 int tval;
349
350 tval = 0;
351 if (resource_int_value(device_get_name(mpt->dev),
352 device_get_unit(mpt->dev), "disable", &tval) == 0 && tval != 0) {
353 mpt->disabled = 1;
354 }
355 tval = 0;
356 if (resource_int_value(device_get_name(mpt->dev),
357 device_get_unit(mpt->dev), "debug", &tval) == 0 && tval != 0) {
358 mpt->verbose = tval;
359 }
360 tval = -1;
361 if (resource_int_value(device_get_name(mpt->dev),
362 device_get_unit(mpt->dev), "role", &tval) == 0 && tval >= 0 &&
363 tval <= 3) {
364 mpt->cfg_role = tval;
365 mpt->do_cfg_role = 1;
984263bc
MD
366 }
367
d751f32e
MD
368 tval = 0;
369 mpt->msi_enable = 0;
370 if (resource_int_value(device_get_name(mpt->dev),
371 device_get_unit(mpt->dev), "msi_enable", &tval) == 0 && tval == 1) {
372 mpt->msi_enable = 1;
373 }
984263bc 374}
d751f32e
MD
375#endif
376
984263bc
MD
377
378static void
d751f32e 379mpt_link_peer(struct mpt_softc *mpt)
984263bc 380{
d751f32e 381 struct mpt_softc *mpt2;
984263bc
MD
382
383 if (mpt->unit == 0) {
384 return;
385 }
984263bc
MD
386 /*
387 * XXX: depends on probe order
388 */
d751f32e 389 mpt2 = (struct mpt_softc *)devclass_get_softc(mpt_devclass,mpt->unit-1);
984263bc
MD
390
391 if (mpt2 == NULL) {
392 return;
393 }
394 if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) {
395 return;
396 }
397 if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) {
398 return;
399 }
400 mpt->mpt2 = mpt2;
401 mpt2->mpt2 = mpt;
d751f32e
MD
402 if (mpt->verbose >= MPT_PRT_DEBUG) {
403 mpt_prt(mpt, "linking with peer (mpt%d)\n",
984263bc
MD
404 device_get_unit(mpt2->dev));
405 }
406}
407
d751f32e
MD
408static void
409mpt_unlink_peer(struct mpt_softc *mpt)
410{
411 if (mpt->mpt2) {
412 mpt->mpt2->mpt2 = NULL;
413 }
414}
415
984263bc
MD
416
417static int
d751f32e 418mpt_pci_attach(device_t dev)
984263bc 419{
d751f32e
MD
420 struct mpt_softc *mpt;
421 int iqd;
422 uint32_t data, cmd;
984263bc
MD
423
424 /* Allocate the softc structure */
d751f32e 425 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
426 if (mpt == NULL) {
427 device_printf(dev, "cannot allocate softc\n");
428 return (ENOMEM);
429 }
d751f32e 430 memset(mpt, 0, sizeof(struct mpt_softc));
984263bc 431 switch ((pci_get_device(dev) & ~1)) {
d751f32e
MD
432 case PCI_PRODUCT_LSI_FC909:
433 case PCI_PRODUCT_LSI_FC909A:
434 case PCI_PRODUCT_LSI_FC919:
435 case PCI_PRODUCT_LSI_FC929:
436 case PCI_PRODUCT_LSI_FC919X:
437 case PCI_PRODUCT_LSI_FC646:
438 case PCI_PRODUCT_LSI_FC7X04X:
984263bc
MD
439 mpt->is_fc = 1;
440 break;
d751f32e
MD
441 case PCI_PRODUCT_LSI_SAS1064:
442 case PCI_PRODUCT_LSI_SAS1064A:
443 case PCI_PRODUCT_LSI_SAS1064E:
444 case PCI_PRODUCT_LSI_SAS1066:
445 case PCI_PRODUCT_LSI_SAS1066E:
446 case PCI_PRODUCT_LSI_SAS1068:
447 case PCI_PRODUCT_LSI_SAS1068E:
448 case PCI_PRODUCT_LSI_SAS1078:
449 case PCI_PRODUCT_LSI_SAS1078DE:
450 mpt->is_sas = 1;
451 break;
984263bc 452 default:
d751f32e 453 mpt->is_spi = 1;
984263bc
MD
454 break;
455 }
456 mpt->dev = dev;
457 mpt->unit = device_get_unit(dev);
d751f32e
MD
458 mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT;
459 mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT;
460 mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT;
461 mpt->verbose = MPT_PRT_NONE;
462 mpt->role = MPT_ROLE_NONE;
984263bc 463 mpt_set_options(mpt);
d751f32e
MD
464 if (mpt->verbose == MPT_PRT_NONE) {
465 mpt->verbose = MPT_PRT_WARN;
466 /* Print INFO level (if any) if bootverbose is set */
467 mpt->verbose += (bootverbose != 0)? 1 : 0;
468 }
984263bc
MD
469 /* Make sure memory access decoders are enabled */
470 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
471 if ((cmd & PCIM_CMD_MEMEN) == 0) {
472 device_printf(dev, "Memory accesses disabled");
d751f32e 473 return (ENXIO);
984263bc
MD
474 }
475
476 /*
477 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
478 */
479 cmd |=
480 PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
481 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
482 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
483
484 /*
485 * Make sure we've disabled the ROM.
486 */
487 data = pci_read_config(dev, PCIR_BIOS, 4);
488 data &= ~1;
489 pci_write_config(dev, PCIR_BIOS, data, 4);
490
984263bc
MD
491 /*
492 * Is this part a dual?
493 * If so, link with our partner (around yet)
494 */
d751f32e
MD
495 if ((pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC929 ||
496 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC646 ||
497 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC7X04X ||
498 (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_1030) {
984263bc
MD
499 mpt_link_peer(mpt);
500 }
501
d751f32e
MD
502 /*
503 * Set up register access. PIO mode is required for
504 * certain reset operations (but must be disabled for
505 * some cards otherwise).
506 */
507 mpt->pci_pio_rid = PCIR_BAR(MPT_IO_BAR);
508 mpt->pci_pio_reg = bus_alloc_resource(dev, SYS_RES_IOPORT,
509 &mpt->pci_pio_rid, 0, ~0, 0, RF_ACTIVE);
510 if (mpt->pci_pio_reg == NULL) {
511 device_printf(dev, "unable to map registers in PIO mode\n");
512 goto bad;
513 }
514 mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg);
515 mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
516
984263bc 517 /* Allocate kernel virtual memory for the 9x9's Mem0 region */
d751f32e 518 mpt->pci_mem_rid = PCIR_BAR(MPT_MEM_BAR);
984263bc 519 mpt->pci_reg = bus_alloc_resource(dev, SYS_RES_MEMORY,
d751f32e 520 &mpt->pci_mem_rid, 0, ~0, 0, RF_ACTIVE);
984263bc 521 if (mpt->pci_reg == NULL) {
d751f32e
MD
522 device_printf(dev, "Unable to memory map registers.\n");
523 if (mpt->is_sas) {
524 device_printf(dev, "Giving Up.\n");
525 goto bad;
526 }
527 device_printf(dev, "Falling back to PIO mode.\n");
528 mpt->pci_st = mpt->pci_pio_st;
529 mpt->pci_sh = mpt->pci_pio_sh;
530 } else {
531 mpt->pci_st = rman_get_bustag(mpt->pci_reg);
532 mpt->pci_sh = rman_get_bushandle(mpt->pci_reg);
984263bc 533 }
984263bc
MD
534
535 /* Get a handle to the interrupt */
536 iqd = 0;
d751f32e
MD
537 if (mpt->msi_enable) {
538 /*
539 * First try to alloc an MSI-X message. If that
540 * fails, then try to alloc an MSI message instead.
541 */
542 if (pci_msix_count(dev) == 1) {
543 mpt->pci_msi_count = 1;
544 if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) {
545 iqd = 1;
546 } else {
547 mpt->pci_msi_count = 0;
548 }
549 }
550 if (iqd == 0 && pci_msi_count(dev) == 1) {
551 mpt->pci_msi_count = 1;
552 if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) {
553 iqd = 1;
554 } else {
555 mpt->pci_msi_count = 0;
556 }
557 }
558 }
559 mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
560 RF_ACTIVE | RF_SHAREABLE);
984263bc
MD
561 if (mpt->pci_irq == NULL) {
562 device_printf(dev, "could not allocate interrupt\n");
563 goto bad;
564 }
565
984263bc
MD
566 MPT_LOCK_SETUP(mpt);
567
568 /* Disable interrupts at the part */
569 mpt_disable_ints(mpt);
570
d751f32e
MD
571 /* Register the interrupt handler */
572 if (mpt_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, NULL, mpt_pci_intr,
573 mpt, &mpt->ih)) {
574 device_printf(dev, "could not setup interrupt\n");
575 goto bad;
576 }
577
984263bc 578 /* Allocate dma memory */
d751f32e 579/* XXX JGibbs -Should really be done based on IOCFacts. */
984263bc 580 if (mpt_dma_mem_alloc(mpt)) {
d751f32e 581 mpt_prt(mpt, "Could not allocate DMA memory\n");
984263bc
MD
582 goto bad;
583 }
584
585 /*
586 * Save the PCI config register values
587 *
588 * Hard resets are known to screw up the BAR for diagnostic
589 * memory accesses (Mem1).
590 *
591 * Using Mem1 is known to make the chip stop responding to
592 * configuration space transfers, so we need to save it now
593 */
594
595 mpt_read_config_regs(mpt);
596
d751f32e
MD
597 /*
598 * Disable PIO until we need it
599 */
600 if (mpt->is_sas) {
601 pci_disable_io(dev, SYS_RES_IOPORT);
602 }
603
984263bc
MD
604 /* Initialize the hardware */
605 if (mpt->disabled == 0) {
d751f32e 606 if (mpt_attach(mpt) != 0) {
984263bc
MD
607 goto bad;
608 }
d751f32e
MD
609 } else {
610 mpt_prt(mpt, "device disabled at user request\n");
611 goto bad;
984263bc
MD
612 }
613
d751f32e
MD
614 mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown,
615 dev, SHUTDOWN_PRI_DEFAULT);
616
617 if (mpt->eh == NULL) {
618 mpt_prt(mpt, "shutdown event registration failed\n");
619 (void) mpt_detach(mpt);
620 goto bad;
621 }
984263bc
MD
622 return (0);
623
624bad:
625 mpt_dma_mem_free(mpt);
626 mpt_free_bus_resources(mpt);
d751f32e
MD
627 mpt_unlink_peer(mpt);
628
629 MPT_LOCK_DESTROY(mpt);
984263bc
MD
630
631 /*
632 * but return zero to preserve unit numbering
633 */
634 return (0);
635}
636
637/*
638 * Free bus resources
639 */
640static void
d751f32e 641mpt_free_bus_resources(struct mpt_softc *mpt)
984263bc
MD
642{
643 if (mpt->ih) {
644 bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih);
645 mpt->ih = 0;
646 }
647
648 if (mpt->pci_irq) {
d751f32e
MD
649 bus_release_resource(mpt->dev, SYS_RES_IRQ,
650 mpt->pci_msi_count ? 1 : 0, mpt->pci_irq);
984263bc
MD
651 mpt->pci_irq = 0;
652 }
653
d751f32e
MD
654 if (mpt->pci_msi_count) {
655 pci_release_msi(mpt->dev);
656 mpt->pci_msi_count = 0;
657 }
658
659 if (mpt->pci_pio_reg) {
660 bus_release_resource(mpt->dev, SYS_RES_IOPORT, mpt->pci_pio_rid,
661 mpt->pci_pio_reg);
662 mpt->pci_pio_reg = 0;
663 }
984263bc 664 if (mpt->pci_reg) {
d751f32e 665 bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_mem_rid,
984263bc
MD
666 mpt->pci_reg);
667 mpt->pci_reg = 0;
668 }
669 MPT_LOCK_DESTROY(mpt);
670}
671
672
673/*
674 * Disconnect ourselves from the system.
675 */
676static int
d751f32e 677mpt_pci_detach(device_t dev)
984263bc 678{
d751f32e 679 struct mpt_softc *mpt;
984263bc 680
d751f32e 681 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
682
683 if (mpt) {
684 mpt_disable_ints(mpt);
d751f32e
MD
685 mpt_detach(mpt);
686 mpt_reset(mpt, /*reinit*/FALSE);
984263bc
MD
687 mpt_dma_mem_free(mpt);
688 mpt_free_bus_resources(mpt);
d751f32e
MD
689 mpt_raid_free_mem(mpt);
690 if (mpt->eh != NULL) {
691 EVENTHANDLER_DEREGISTER(shutdown_post_sync, mpt->eh);
692 }
984263bc
MD
693 }
694 return(0);
695}
696
697
698/*
699 * Disable the hardware
700 */
701static int
d751f32e 702mpt_pci_shutdown(device_t dev)
984263bc 703{
d751f32e 704 struct mpt_softc *mpt;
984263bc 705
d751f32e 706 mpt = (struct mpt_softc *)device_get_softc(dev);
984263bc 707 if (mpt) {
d751f32e
MD
708 int r;
709 r = mpt_shutdown(mpt);
710 return (r);
984263bc
MD
711 }
712 return(0);
713}
714
984263bc 715static int
d751f32e 716mpt_dma_mem_alloc(struct mpt_softc *mpt)
984263bc 717{
d751f32e
MD
718 int i, error, nsegs;
719 uint8_t *vptr;
720 uint32_t pptr, end;
984263bc 721 size_t len;
d751f32e 722 struct mpt_map_info mi;
984263bc
MD
723
724 /* Check if we alreay have allocated the reply memory */
3641b7ca 725 if (mpt->reply_phys != 0) {
984263bc
MD
726 return 0;
727 }
728
d751f32e
MD
729 len = sizeof (request_t) * MPT_MAX_REQUESTS(mpt);
730#ifdef RELENG_4
731 mpt->request_pool = (request_t *)malloc(len, M_DEVBUF, M_WAITOK);
732 if (mpt->request_pool == NULL) {
733 mpt_prt(mpt, "cannot allocate request pool\n");
734 return (1);
735 }
736 memset(mpt->request_pool, 0, len);
737#else
738 mpt->request_pool = (request_t *)malloc(len, M_DEVBUF, M_WAITOK|M_ZERO);
739 if (mpt->request_pool == NULL) {
740 mpt_prt(mpt, "cannot allocate request pool\n");
741 return (1);
742 }
743#endif
984263bc
MD
744
745 /*
d751f32e 746 * Create a parent dma tag for this device.
984263bc 747 *
d751f32e
MD
748 * Align at byte boundaries,
749 * Limit to 32-bit addressing for request/reply queues.
984263bc 750 */
d751f32e
MD
751 if (mpt_dma_tag_create(mpt, /*parent*/bus_get_dma_tag(mpt->dev),
752 /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
753 /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL,
754 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
755 /*nsegments*/BUS_SPACE_MAXSIZE_32BIT,
756 /*maxsegsz*/BUS_SPACE_UNRESTRICTED, /*flags*/0,
984263bc 757 &mpt->parent_dmat) != 0) {
d751f32e 758 mpt_prt(mpt, "cannot create parent dma tag\n");
984263bc
MD
759 return (1);
760 }
761
762 /* Create a child tag for reply buffers */
d751f32e
MD
763 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
764 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
765 NULL, NULL, 2 * PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 766 &mpt->reply_dmat) != 0) {
d751f32e 767 mpt_prt(mpt, "cannot create a dma tag for replies\n");
984263bc
MD
768 return (1);
769 }
770
771 /* Allocate some DMA accessable memory for replies */
772 if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply,
773 BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) {
d751f32e
MD
774 mpt_prt(mpt, "cannot allocate %lu bytes of reply memory\n",
775 (u_long) (2 * PAGE_SIZE));
984263bc
MD
776 return (1);
777 }
778
d751f32e
MD
779 mi.mpt = mpt;
780 mi.error = 0;
984263bc
MD
781
782 /* Load and lock it into "bus space" */
783 bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply,
d751f32e 784 2 * PAGE_SIZE, mpt_map_rquest, &mi, 0);
984263bc 785
d751f32e
MD
786 if (mi.error) {
787 mpt_prt(mpt, "error %d loading dma map for DMA reply queue\n",
788 mi.error);
984263bc
MD
789 return (1);
790 }
d751f32e 791 mpt->reply_phys = mi.phys;
984263bc
MD
792
793 /* Create a child tag for data buffers */
d751f32e
MD
794
795 /*
796 * XXX: we should say that nsegs is 'unrestricted, but that
797 * XXX: tickles a horrible bug in the busdma code. Instead,
798 * XXX: we'll derive a reasonable segment limit from MPT_MAXPHYS
799 */
800 nsegs = (MPT_MAXPHYS / PAGE_SIZE) + 1;
801 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, 1,
984263bc 802 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
d751f32e 803 NULL, NULL, MAXBSIZE, nsegs, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 804 &mpt->buffer_dmat) != 0) {
d751f32e 805 mpt_prt(mpt, "cannot create a dma tag for data buffers\n");
984263bc
MD
806 return (1);
807 }
808
809 /* Create a child tag for request buffers */
d751f32e
MD
810 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
811 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
984263bc
MD
812 NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0,
813 &mpt->request_dmat) != 0) {
d751f32e 814 mpt_prt(mpt, "cannot create a dma tag for requests\n");
984263bc
MD
815 return (1);
816 }
817
818 /* Allocate some DMA accessable memory for requests */
819 if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request,
820 BUS_DMA_NOWAIT, &mpt->request_dmap) != 0) {
d751f32e 821 mpt_prt(mpt, "cannot allocate %d bytes of request memory\n",
984263bc
MD
822 MPT_REQ_MEM_SIZE(mpt));
823 return (1);
824 }
825
d751f32e
MD
826 mi.mpt = mpt;
827 mi.error = 0;
984263bc
MD
828
829 /* Load and lock it into "bus space" */
830 bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request,
d751f32e 831 MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &mi, 0);
984263bc 832
d751f32e
MD
833 if (mi.error) {
834 mpt_prt(mpt, "error %d loading dma map for DMA request queue\n",
835 mi.error);
984263bc
MD
836 return (1);
837 }
d751f32e 838 mpt->request_phys = mi.phys;
984263bc 839
d751f32e
MD
840 /*
841 * Now create per-request dma maps
842 */
984263bc
MD
843 i = 0;
844 pptr = mpt->request_phys;
845 vptr = mpt->request;
846 end = pptr + MPT_REQ_MEM_SIZE(mpt);
847 while(pptr < end) {
848 request_t *req = &mpt->request_pool[i];
849 req->index = i++;
850
851 /* Store location of Request Data */
852 req->req_pbuf = pptr;
853 req->req_vbuf = vptr;
854
855 pptr += MPT_REQUEST_AREA;
856 vptr += MPT_REQUEST_AREA;
857
858 req->sense_pbuf = (pptr - MPT_SENSE_SIZE);
859 req->sense_vbuf = (vptr - MPT_SENSE_SIZE);
860
861 error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap);
862 if (error) {
d751f32e
MD
863 mpt_prt(mpt, "error %d creating per-cmd DMA maps\n",
864 error);
984263bc
MD
865 return (1);
866 }
867 }
d751f32e 868
984263bc
MD
869 return (0);
870}
871
872
873
874/* Deallocate memory that was allocated by mpt_dma_mem_alloc
875 */
876static void
d751f32e 877mpt_dma_mem_free(struct mpt_softc *mpt)
984263bc
MD
878{
879 int i;
880
881 /* Make sure we aren't double destroying */
882 if (mpt->reply_dmat == 0) {
d751f32e 883 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n");
984263bc
MD
884 return;
885 }
886
887 for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) {
888 bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap);
889 }
890 bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap);
891 bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap);
892 bus_dma_tag_destroy(mpt->request_dmat);
893 bus_dma_tag_destroy(mpt->buffer_dmat);
894 bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap);
895 bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap);
896 bus_dma_tag_destroy(mpt->reply_dmat);
897 bus_dma_tag_destroy(mpt->parent_dmat);
898 mpt->reply_dmat = 0;
d751f32e 899 free(mpt->request_pool, M_DEVBUF);
984263bc
MD
900 mpt->request_pool = 0;
901
902}
903
904
905
906/* Reads modifiable (via PCI transactions) config registers */
907static void
d751f32e 908mpt_read_config_regs(struct mpt_softc *mpt)
984263bc
MD
909{
910 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
911 mpt->pci_cfg.LatencyTimer_LineSize =
912 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
d751f32e
MD
913 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
914 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
915 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
916 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
917 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4);
984263bc
MD
918 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4);
919 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1);
920 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4);
921}
922
923/* Sets modifiable config registers */
924void
d751f32e 925mpt_set_config_regs(struct mpt_softc *mpt)
984263bc 926{
d751f32e 927 uint32_t val;
984263bc
MD
928
929#define MPT_CHECK(reg, offset, size) \
930 val = pci_read_config(mpt->dev, offset, size); \
931 if (mpt->pci_cfg.reg != val) { \
d751f32e 932 mpt_prt(mpt, \
984263bc
MD
933 "Restoring " #reg " to 0x%X from 0x%X\n", \
934 mpt->pci_cfg.reg, val); \
935 }
936
d751f32e 937 if (mpt->verbose >= MPT_PRT_DEBUG) {
984263bc
MD
938 MPT_CHECK(Command, PCIR_COMMAND, 2);
939 MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2);
d751f32e
MD
940 MPT_CHECK(IO_BAR, PCIR_BAR(0), 4);
941 MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4);
942 MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4);
943 MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4);
944 MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4);
984263bc
MD
945 MPT_CHECK(ROM_BAR, PCIR_BIOS, 4);
946 MPT_CHECK(IntLine, PCIR_INTLINE, 1);
947 MPT_CHECK(PMCSR, 0x44, 4);
948 }
949#undef MPT_CHECK
950
951 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
952 pci_write_config(mpt->dev, PCIR_CACHELNSZ,
953 mpt->pci_cfg.LatencyTimer_LineSize, 2);
d751f32e
MD
954 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4);
955 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4);
956 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4);
957 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4);
958 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4);
984263bc
MD
959 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4);
960 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1);
961 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4);
962}
963
964static void
965mpt_pci_intr(void *arg)
966{
d751f32e
MD
967 struct mpt_softc *mpt;
968
969 mpt = (struct mpt_softc *)arg;
984263bc 970 MPT_LOCK(mpt);
d751f32e 971 mpt_intr(mpt);
984263bc
MD
972 MPT_UNLOCK(mpt);
973}