pci: Put back PCI Express related bits
[dragonfly.git] / sys / bus / pci / pci_pci.c
CommitLineData
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1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $");
30 */
31
32#include <sys/cdefs.h>
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45
46#include <bus/pci/pcivar.h>
47#include <bus/pci/pcireg.h>
48#include <bus/pci/pcib_private.h>
49
50#include "pcib_if.h"
51
52static int pcib_probe(device_t dev);
53
54static device_method_t pcib_methods[] = {
55 /* Device interface */
56 DEVMETHOD(device_probe, pcib_probe),
57 DEVMETHOD(device_attach, pcib_attach),
58 DEVMETHOD(device_detach, bus_generic_detach),
59 DEVMETHOD(device_shutdown, bus_generic_shutdown),
60 DEVMETHOD(device_suspend, bus_generic_suspend),
61 DEVMETHOD(device_resume, bus_generic_resume),
62
63 /* Bus interface */
64 DEVMETHOD(bus_print_child, bus_generic_print_child),
65 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
66 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
68 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
73
74 /* pcib interface */
75 DEVMETHOD(pcib_maxslots, pcib_maxslots),
76 DEVMETHOD(pcib_read_config, pcib_read_config),
77 DEVMETHOD(pcib_write_config, pcib_write_config),
78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
79 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
80 DEVMETHOD(pcib_release_msi, pcib_release_msi),
81 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
82 DEVMETHOD(pcib_release_msix, pcib_release_msix),
83 DEVMETHOD(pcib_map_msi, pcib_map_msi),
84
85 { 0, 0 }
86};
87
88static devclass_t pcib_devclass;
89
90DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
91DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
92
93/*
94 * Is the prefetch window open (eg, can we allocate memory in it?)
95 */
96static int
97pcib_is_prefetch_open(struct pcib_softc *sc)
98{
99 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
100}
101
102/*
103 * Is the nonprefetch window open (eg, can we allocate memory in it?)
104 */
105static int
106pcib_is_nonprefetch_open(struct pcib_softc *sc)
107{
108 return (sc->membase > 0 && sc->membase < sc->memlimit);
109}
110
111/*
112 * Is the io window open (eg, can we allocate ports in it?)
113 */
114static int
115pcib_is_io_open(struct pcib_softc *sc)
116{
117 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
118}
119
120/*
121 * Generic device interface
122 */
123static int
124pcib_probe(device_t dev)
125{
126 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
127 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
128 device_set_desc(dev, "PCI-PCI bridge");
129 return(-10000);
130 }
131 return(ENXIO);
132}
133
134void
135pcib_attach_common(device_t dev)
136{
137 struct pcib_softc *sc;
138 uint8_t iolow;
139
140 sc = device_get_softc(dev);
141 sc->dev = dev;
142
143 /*
144 * Get current bridge configuration.
145 */
146 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
147 sc->domain = pci_get_domain(dev);
148 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
149 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
150 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
151 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
152 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
153
154 /*
155 * Determine current I/O decode.
156 */
157 if (sc->command & PCIM_CMD_PORTEN) {
158 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
159 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
160 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
161 pci_read_config(dev, PCIR_IOBASEL_1, 1));
162 } else {
163 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
164 }
165
166 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
167 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
168 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
169 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
170 } else {
171 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
172 }
173 }
174
175 /*
176 * Determine current memory decode.
177 */
178 if (sc->command & PCIM_CMD_MEMEN) {
179 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
180 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
181 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
182 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
183 sc->pmembase = PCI_PPBMEMBASE(
184 pci_read_config(dev, PCIR_PMBASEH_1, 4),
185 pci_read_config(dev, PCIR_PMBASEL_1, 2));
186 else
187 sc->pmembase = PCI_PPBMEMBASE(0,
188 pci_read_config(dev, PCIR_PMBASEL_1, 2));
189 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
190 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
191 sc->pmemlimit = PCI_PPBMEMLIMIT(
192 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
193 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
194 else
195 sc->pmemlimit = PCI_PPBMEMLIMIT(0,
196 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
197 }
198
199 /*
200 * Quirk handling.
201 */
202 switch (pci_get_devid(dev)) {
203 case 0x12258086: /* Intel 82454KX/GX (Orion) */
204 {
205 uint8_t supbus;
206
207 supbus = pci_read_config(dev, 0x41, 1);
208 if (supbus != 0xff) {
209 sc->secbus = supbus + 1;
210 sc->subbus = supbus + 1;
211 }
212 break;
213 }
214
215 /*
216 * The i82380FB mobile docking controller is a PCI-PCI bridge,
217 * and it is a subtractive bridge. However, the ProgIf is wrong
218 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
219 * happen. There's also a Toshiba bridge that behaves this
220 * way.
221 */
222 case 0x124b8086: /* Intel 82380FB Mobile */
223 case 0x060513d7: /* Toshiba ???? */
224 sc->flags |= PCIB_SUBTRACTIVE;
225 break;
226
227 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
228 case 0x00dd10de:
229 {
230 char *cp;
231
232 if ((cp = kgetenv("smbios.planar.maker")) == NULL)
233 break;
234 if (strncmp(cp, "Compal", 6) != 0) {
235 kfreeenv(cp);
236 break;
237 }
238 kfreeenv(cp);
239 if ((cp = kgetenv("smbios.planar.product")) == NULL)
240 break;
241 if (strncmp(cp, "08A0", 4) != 0) {
242 kfreeenv(cp);
243 break;
244 }
245 kfreeenv(cp);
246 if (sc->subbus < 0xa) {
247 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
248 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
249 }
250 break;
251 }
252 }
253
254 if (pci_msi_device_blacklisted(dev))
255 sc->flags |= PCIB_DISABLE_MSI;
256
257 /*
258 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
259 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
260 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
261 * This means they act as if they were subtractively decoding
262 * bridges and pass all transactions. Mark them and real ProgIf 1
263 * parts as subtractive.
264 */
265 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
266 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
267 sc->flags |= PCIB_SUBTRACTIVE;
268
269 if (bootverbose) {
270 device_printf(dev, " domain %d\n", sc->domain);
271 device_printf(dev, " secondary bus %d\n", sc->secbus);
272 device_printf(dev, " subordinate bus %d\n", sc->subbus);
273 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
274 if (pcib_is_nonprefetch_open(sc))
275 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
276 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
277 if (pcib_is_prefetch_open(sc))
278 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
279 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
280 else
281 device_printf(dev, " no prefetched decode\n");
282 if (sc->flags & PCIB_SUBTRACTIVE)
283 device_printf(dev, " Subtractively decoded bridge.\n");
284 }
285
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286 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) {
287 uint16_t slot_ctrl;
288 uint8_t ptr;
289
290 /*
291 * XXX
292 * Before proper PCI Express hot-plug support is in place,
293 * disable all hot-plug interrupts on the PCI Express root
294 * port or down stream port for now.
295 */
296#define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN)
297
298 ptr = pci_get_pciecap_ptr(dev);
299 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTRL, 2);
300 if (slot_ctrl & HPINTRS) {
301 device_printf(dev, "Disable PCI Express hot-plug "
302 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS);
303 slot_ctrl &= ~HPINTRS;
304 pci_write_config(dev, ptr + PCIER_SLOTCTRL, slot_ctrl, 2);
305 }
306
307#undef HPINTRS
308 }
309
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310 /*
311 * XXX If the secondary bus number is zero, we should assign a bus number
312 * since the BIOS hasn't, then initialise the bridge.
313 */
314
315 /*
316 * XXX If the subordinate bus number is less than the secondary bus number,
317 * we should pick a better value. One sensible alternative would be to
318 * pick 255; the only tradeoff here is that configuration transactions
319 * would be more widely routed than absolutely necessary.
320 */
321}
322
323int
324pcib_attach(device_t dev)
325{
326 struct pcib_softc *sc;
327 device_t child;
328
329 pcib_attach_common(dev);
330 sc = device_get_softc(dev);
331 if (sc->secbus != 0) {
332 child = device_add_child(dev, "pci", sc->secbus);
333 if (child != NULL)
334 return(bus_generic_attach(dev));
335 }
336
337 /* no secondary bus; we should have fixed this */
338 return(0);
339}
340
341int
342pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
343{
344 struct pcib_softc *sc = device_get_softc(dev);
345
346 switch (which) {
347 case PCIB_IVAR_DOMAIN:
348 *result = sc->domain;
349 return(0);
350 case PCIB_IVAR_BUS:
351 *result = sc->secbus;
352 return(0);
353 }
354 return(ENOENT);
355}
356
357int
358pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
359{
360 struct pcib_softc *sc = device_get_softc(dev);
361
362 switch (which) {
363 case PCIB_IVAR_DOMAIN:
364 return(EINVAL);
365 case PCIB_IVAR_BUS:
366 sc->secbus = value;
367 return(0);
368 }
369 return(ENOENT);
370}
371
372/*
373 * We have to trap resource allocation requests and ensure that the bridge
374 * is set up to, or capable of handling them.
375 */
376struct resource *
377pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
378 u_long start, u_long end, u_long count, u_int flags)
379{
380 struct pcib_softc *sc = device_get_softc(dev);
381 const char *name, *suffix;
382 int ok;
383
384 /*
385 * Fail the allocation for this range if it's not supported.
386 */
387 name = device_get_nameunit(child);
388 if (name == NULL) {
389 name = "";
390 suffix = "";
391 } else
392 suffix = " ";
393 switch (type) {
394 case SYS_RES_IOPORT:
395 ok = 0;
396 if (!pcib_is_io_open(sc))
397 break;
398 ok = (start >= sc->iobase && end <= sc->iolimit);
399
400 /*
401 * Make sure we allow access to VGA I/O addresses when the
402 * bridge has the "VGA Enable" bit set.
403 */
404 if (!ok && pci_is_vga_ioport_range(start, end))
405 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
406
407 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
408 if (!ok) {
409 if (start < sc->iobase)
410 start = sc->iobase;
411 if (end > sc->iolimit)
412 end = sc->iolimit;
413 if (start < end)
414 ok = 1;
415 }
416 } else {
417 ok = 1;
418#if 1
419 if (start < sc->iobase && end > sc->iolimit) {
420 start = sc->iobase;
421 end = sc->iolimit;
422 }
423#endif
424 }
425 if (end < start) {
426 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
427 end, start);
428 start = 0;
429 end = 0;
430 ok = 0;
431 }
432 if (!ok) {
433 device_printf(dev, "%s%srequested unsupported I/O "
434 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
435 name, suffix, start, end, sc->iobase, sc->iolimit);
436 return (NULL);
437 }
438 if (bootverbose)
439 device_printf(dev,
440 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
441 name, suffix, start, end);
442 break;
443
444 case SYS_RES_MEMORY:
445 ok = 0;
446 if (pcib_is_nonprefetch_open(sc))
447 ok = ok || (start >= sc->membase && end <= sc->memlimit);
448 if (pcib_is_prefetch_open(sc))
449 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
450
451 /*
452 * Make sure we allow access to VGA memory addresses when the
453 * bridge has the "VGA Enable" bit set.
454 */
455 if (!ok && pci_is_vga_memory_range(start, end))
456 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
457
458 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
459 if (!ok) {
460 ok = 1;
461 if (flags & RF_PREFETCHABLE) {
462 if (pcib_is_prefetch_open(sc)) {
463 if (start < sc->pmembase)
464 start = sc->pmembase;
465 if (end > sc->pmemlimit)
466 end = sc->pmemlimit;
467 } else {
468 ok = 0;
469 }
470 } else { /* non-prefetchable */
471 if (pcib_is_nonprefetch_open(sc)) {
472 if (start < sc->membase)
473 start = sc->membase;
474 if (end > sc->memlimit)
475 end = sc->memlimit;
476 } else {
477 ok = 0;
478 }
479 }
480 }
481 } else if (!ok) {
482 ok = 1; /* subtractive bridge: always ok */
483#if 1
484 if (pcib_is_nonprefetch_open(sc)) {
485 if (start < sc->membase && end > sc->memlimit) {
486 start = sc->membase;
487 end = sc->memlimit;
488 }
489 }
490 if (pcib_is_prefetch_open(sc)) {
491 if (start < sc->pmembase && end > sc->pmemlimit) {
492 start = sc->pmembase;
493 end = sc->pmemlimit;
494 }
495 }
496#endif
497 }
498 if (end < start) {
499 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
500 end, start);
501 start = 0;
502 end = 0;
503 ok = 0;
504 }
505 if (!ok && bootverbose)
506 device_printf(dev,
507 "%s%srequested unsupported memory range %#lx-%#lx "
508 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
509 name, suffix, start, end,
510 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
511 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
512 if (!ok)
513 return (NULL);
514 if (bootverbose)
515 device_printf(dev,"%s%srequested memory range "
516 "0x%lx-0x%lx: good\n",
517 name, suffix, start, end);
518 break;
519
520 default:
521 break;
522 }
523 /*
524 * Bridge is OK decoding this resource, so pass it up.
525 */
526 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
527 count, flags));
528}
529
530/*
531 * PCIB interface.
532 */
533int
534pcib_maxslots(device_t dev)
535{
536 return(PCI_SLOTMAX);
537}
538
539/*
540 * Since we are a child of a PCI bus, its parent must support the pcib interface.
541 */
542uint32_t
543pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
544{
545 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
546}
547
548void
549pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
550{
551 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
552}
553
554/*
555 * Route an interrupt across a PCI bridge.
556 */
557int
558pcib_route_interrupt(device_t pcib, device_t dev, int pin)
559{
560 device_t bus;
561 int parent_intpin;
562 int intnum;
563
564 /*
565 *
566 * The PCI standard defines a swizzle of the child-side device/intpin to
567 * the parent-side intpin as follows.
568 *
569 * device = device on child bus
570 * child_intpin = intpin on child bus slot (0-3)
571 * parent_intpin = intpin on parent bus slot (0-3)
572 *
573 * parent_intpin = (device + child_intpin) % 4
574 */
575 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
576
577 /*
578 * Our parent is a PCI bus. Its parent must export the pcib interface
579 * which includes the ability to route interrupts.
580 */
581 bus = device_get_parent(pcib);
582 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
583 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
584 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
585 pci_get_slot(dev), 'A' + pin - 1, intnum);
586 }
587 return(intnum);
588}
589
590/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
591int
592pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
593{
594 struct pcib_softc *sc = device_get_softc(pcib);
595 device_t bus;
596
597 if (sc->flags & PCIB_DISABLE_MSI)
598 return (ENXIO);
599 bus = device_get_parent(pcib);
600 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
601 irqs));
602}
603
604/* Pass request to release MSI/MSI-X messages up to the parent bridge. */
605int
606pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
607{
608 device_t bus;
609
610 bus = device_get_parent(pcib);
611 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
612}
613
614/* Pass request to alloc an MSI-X message up to the parent bridge. */
615int
616pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
617{
618 struct pcib_softc *sc = device_get_softc(pcib);
619 device_t bus;
620
621 if (sc->flags & PCIB_DISABLE_MSI)
622 return (ENXIO);
623 bus = device_get_parent(pcib);
624 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
625}
626
627/* Pass request to release an MSI-X message up to the parent bridge. */
628int
629pcib_release_msix(device_t pcib, device_t dev, int irq)
630{
631 device_t bus;
632
633 bus = device_get_parent(pcib);
634 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
635}
636
637/* Pass request to map MSI/MSI-X message up to parent bridge. */
638int
639pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
640 uint32_t *data)
641{
642 device_t bus;
643 int error;
644
645 bus = device_get_parent(pcib);
646 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
647 if (error)
648 return (error);
649
650 pci_ht_map_msi(pcib, *addr);
651 return (0);
652}
653
654/*
655 * Try to read the bus number of a host-PCI bridge using appropriate config
656 * registers.
657 */
658int
659host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
660 uint8_t *busnum)
661{
662 uint32_t id;
663
664 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
665 if (id == 0xffffffff)
666 return (0);
667
668 switch (id) {
669 case 0x12258086:
670 /* Intel 824?? */
671 /* XXX This is a guess */
672 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
673 *busnum = bus;
674 break;
675 case 0x84c48086:
676 /* Intel 82454KX/GX (Orion) */
677 *busnum = read_config(bus, slot, func, 0x4a, 1);
678 break;
679 case 0x84ca8086:
680 /*
681 * For the 450nx chipset, there is a whole bundle of
682 * things pretending to be host bridges. The MIOC will
683 * be seen first and isn't really a pci bridge (the
684 * actual busses are attached to the PXB's). We need to
685 * read the registers of the MIOC to figure out the
686 * bus numbers for the PXB channels.
687 *
688 * Since the MIOC doesn't have a pci bus attached, we
689 * pretend it wasn't there.
690 */
691 return (0);
692 case 0x84cb8086:
693 switch (slot) {
694 case 0x12:
695 /* Intel 82454NX PXB#0, Bus#A */
696 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
697 break;
698 case 0x13:
699 /* Intel 82454NX PXB#0, Bus#B */
700 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
701 break;
702 case 0x14:
703 /* Intel 82454NX PXB#1, Bus#A */
704 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
705 break;
706 case 0x15:
707 /* Intel 82454NX PXB#1, Bus#B */
708 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
709 break;
710 }
711 break;
712
713 /* ServerWorks -- vendor 0x1166 */
714 case 0x00051166:
715 case 0x00061166:
716 case 0x00081166:
717 case 0x00091166:
718 case 0x00101166:
719 case 0x00111166:
720 case 0x00171166:
721 case 0x01011166:
722 case 0x010f1014:
723 case 0x02011166:
724 case 0x03021014:
725 *busnum = read_config(bus, slot, func, 0x44, 1);
726 break;
727
728 /* Compaq/HP -- vendor 0x0e11 */
729 case 0x60100e11:
730 *busnum = read_config(bus, slot, func, 0xc8, 1);
731 break;
732 default:
733 /* Don't know how to read bus number. */
734 return 0;
735 }
736
737 return 1;
738}