pci: Put back PCI Express related bits
[dragonfly.git] / sys / bus / pci / pcivar.h
CommitLineData
4d28e78f 1/*-
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2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
4d28e78f 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
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27 *
28 */
29
30#ifndef _PCIVAR_H_
4d28e78f 31#define _PCIVAR_H_
984263bc 32
e2c4df7c 33#ifndef _SYS_QUEUE_H_
984263bc 34#include <sys/queue.h>
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35#endif
36
4d28e78f 37extern const char *pcib_owner; /* arbitrate who owns the pci device arch */
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38
39/* some PCI bus constants */
40
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41#define PCI_DOMAINMAX 65535 /* highest supported domain number */
42#define PCI_BUSMAX 255 /* highest supported bus number */
43#define PCI_SLOTMAX 31 /* highest supported slot number */
44#define PCI_FUNCMAX 7 /* highest supported function number */
45#define PCI_REGMAX 255 /* highest supported config register addr. */
984263bc 46
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47#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
48#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
49#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
984263bc 50
4d28e78f 51typedef uint64_t pci_addr_t;
984263bc 52
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53/* Interesting values for PCI power management */
54struct pcicfg_pp {
55 uint16_t pp_cap; /* PCI power management capabilities */
56 uint8_t pp_status; /* config space address of PCI power status reg */
57 uint8_t pp_pmcsr; /* config space address of PMCSR reg */
58 uint8_t pp_data; /* config space address of PCI power data reg */
1f7d9fe0 59};
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60
61struct vpd_readonly {
62 char keyword[2];
63 char *value;
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64};
65
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66struct vpd_write {
67 char keyword[2];
68 char *value;
69 int start;
70 int len;
71};
638744c5 72
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73struct pcicfg_vpd {
74 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
75 char vpd_cached;
76 char *vpd_ident; /* string identifier */
77 int vpd_rocnt;
78 struct vpd_readonly *vpd_ros;
79 int vpd_wcnt;
80 struct vpd_write *vpd_w;
81};
984263bc 82
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83/* Interesting values for PCI MSI */
84struct pcicfg_msi {
85 uint16_t msi_ctrl; /* Message Control */
86 uint8_t msi_location; /* Offset of MSI capability registers. */
87 uint8_t msi_msgnum; /* Number of messages */
88 int msi_alloc; /* Number of allocated messages. */
89 uint64_t msi_addr; /* Contents of address register. */
90 uint16_t msi_data; /* Contents of data register. */
91 u_int msi_handlers;
92};
984263bc 93
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94/* Interesting values for PCI MSI-X */
95struct msix_vector {
96 uint64_t mv_address; /* Contents of address register. */
97 uint32_t mv_data; /* Contents of data register. */
98 int mv_irq;
99};
984263bc 100
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101struct msix_table_entry {
102 u_int mte_vector; /* 1-based index into msix_vectors array. */
103 u_int mte_handlers;
104};
984263bc 105
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106struct pcicfg_msix {
107 uint16_t msix_ctrl; /* Message Control */
108 uint16_t msix_msgnum; /* Number of messages */
109 uint8_t msix_location; /* Offset of MSI-X capability registers. */
110 uint8_t msix_table_bar; /* BAR containing vector table. */
111 uint8_t msix_pba_bar; /* BAR containing PBA. */
112 uint32_t msix_table_offset;
113 uint32_t msix_pba_offset;
114 int msix_alloc; /* Number of allocated vectors. */
115 int msix_table_len; /* Length of virtual table. */
116 struct msix_table_entry *msix_table; /* Virtual table. */
117 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
118 struct resource *msix_table_res; /* Resource containing vector table. */
119 struct resource *msix_pba_res; /* Resource containing PBA. */
120};
984263bc 121
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122/* Interesting values for HyperTransport */
123struct pcicfg_ht {
124 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
125 uint16_t ht_msictrl; /* MSI mapping control */
126 uint64_t ht_msiaddr; /* MSI mapping base address */
127};
984263bc 128
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129/* Interesting values for PCI Express capability */
130struct pcicfg_expr {
131 uint8_t expr_ptr; /* capability ptr */
132 uint16_t expr_cap; /* capabilities */
133 uint32_t expr_slotcap; /* slot capabilities */
134};
135
136/* Interesting values for PCI-X */
137struct pcicfg_pcix {
138 uint8_t pcix_ptr;
139};
140
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141/* config header information common to all header types */
142typedef struct pcicfg {
143 struct device *dev; /* device which owns this */
984263bc 144
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145 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
146 uint32_t bios; /* BIOS mapping */
984263bc 147
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148 uint16_t subvendor; /* card vendor ID */
149 uint16_t subdevice; /* card device ID, assigned by card vendor */
150 uint16_t vendor; /* chip vendor ID */
151 uint16_t device; /* chip device ID, assigned by chip vendor */
152
153 uint16_t cmdreg; /* disable/enable chip and PCI options */
154 uint16_t statreg; /* supported PCI features and error state */
155
156 uint8_t baseclass; /* chip PCI class */
157 uint8_t subclass; /* chip PCI subclass */
158 uint8_t progif; /* chip PCI programming interface */
159 uint8_t revid; /* chip revision ID */
160
161 uint8_t hdrtype; /* chip config header type */
162 uint8_t cachelnsz; /* cache line size in 4byte units */
163 uint8_t intpin; /* PCI interrupt pin */
164 uint8_t intline; /* interrupt line (IRQ for PC arch) */
165
166 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
167 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
168 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
169
170 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
171 uint8_t nummaps; /* actual number of PCI maps used */
172
173 uint32_t domain; /* PCI domain */
174 uint8_t bus; /* config space bus address */
175 uint8_t slot; /* config space slot address */
176 uint8_t func; /* config space function number */
177
178 struct pcicfg_pp pp; /* pci power management */
179 struct pcicfg_vpd vpd; /* pci vital product data */
180 struct pcicfg_msi msi; /* pci msi */
181 struct pcicfg_msix msix; /* pci msi-x */
182 struct pcicfg_ht ht; /* HyperTransport */
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183 struct pcicfg_expr expr; /* PCI Express */
184 struct pcicfg_pcix pcix; /* PCI-X */
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185} pcicfgregs;
186
187/* additional type 1 device config header information (PCI to PCI bridge) */
188
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189#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
190#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
191#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
192#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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193
194typedef struct {
195 pci_addr_t pmembase; /* base address of prefetchable memory */
196 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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197 uint32_t membase; /* base address of memory window */
198 uint32_t memlimit; /* topmost address of memory window */
199 uint32_t iobase; /* base address of port window */
200 uint32_t iolimit; /* topmost address of port window */
201 uint16_t secstat; /* secondary bus status register */
202 uint16_t bridgectl; /* bridge control register */
203 uint8_t seclat; /* CardBus latency timer */
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204} pcih1cfgregs;
205
206/* additional type 2 device config header information (CardBus bridge) */
207
208typedef struct {
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209 uint32_t membase0; /* base address of memory window */
210 uint32_t memlimit0; /* topmost address of memory window */
211 uint32_t membase1; /* base address of memory window */
212 uint32_t memlimit1; /* topmost address of memory window */
213 uint32_t iobase0; /* base address of port window */
214 uint32_t iolimit0; /* topmost address of port window */
215 uint32_t iobase1; /* base address of port window */
216 uint32_t iolimit1; /* topmost address of port window */
217 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
218 uint16_t secstat; /* secondary bus status register */
219 uint16_t bridgectl; /* bridge control register */
220 uint8_t seclat; /* CardBus latency timer */
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221} pcih2cfgregs;
222
4d28e78f 223extern uint32_t pci_numdevs;
984263bc 224
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225/* Only if the prerequisites are present */
226#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
227struct pci_devinfo {
228 STAILQ_ENTRY(pci_devinfo) pci_links;
229 struct resource_list resources;
230 pcicfgregs cfg;
231 struct pci_conf conf;
232};
233#endif
984263bc 234
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235#ifdef _SYS_BUS_H_
236
237#include "pci_if.h"
238
239/*
240 * Define pci-specific resource flags for accessing memory via dense
241 * or bwx memory spaces. These flags are ignored on i386.
242 */
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243#define PCI_RF_DENSE 0x10000
244#define PCI_RF_BWX 0x20000
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245
246enum pci_device_ivars {
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247 PCI_IVAR_SUBVENDOR,
248 PCI_IVAR_SUBDEVICE,
249 PCI_IVAR_VENDOR,
250 PCI_IVAR_DEVICE,
251 PCI_IVAR_DEVID,
252 PCI_IVAR_CLASS,
253 PCI_IVAR_SUBCLASS,
254 PCI_IVAR_PROGIF,
255 PCI_IVAR_REVID,
256 PCI_IVAR_INTPIN,
257 PCI_IVAR_IRQ,
258 PCI_IVAR_DOMAIN,
259 PCI_IVAR_BUS,
260 PCI_IVAR_SLOT,
261 PCI_IVAR_FUNCTION,
262 PCI_IVAR_ETHADDR,
263 PCI_IVAR_CMDREG,
264 PCI_IVAR_CACHELNSZ,
265 PCI_IVAR_MINGNT,
266 PCI_IVAR_MAXLAT,
267 PCI_IVAR_LATTIMER,
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268 PCI_IVAR_PCIXCAP_PTR,
269 PCI_IVAR_PCIECAP_PTR,
270 PCI_IVAR_VPDCAP_PTR
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271};
272
273/*
274 * Simplified accessors for pci devices
275 */
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276#define PCI_ACCESSOR(var, ivar, type) \
277 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
278
279PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
280PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
281PCI_ACCESSOR(vendor, VENDOR, uint16_t)
282PCI_ACCESSOR(device, DEVICE, uint16_t)
283PCI_ACCESSOR(devid, DEVID, uint32_t)
284PCI_ACCESSOR(class, CLASS, uint8_t)
285PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
286PCI_ACCESSOR(progif, PROGIF, uint8_t)
287PCI_ACCESSOR(revid, REVID, uint8_t)
288PCI_ACCESSOR(intpin, INTPIN, uint8_t)
289PCI_ACCESSOR(irq, IRQ, uint8_t)
290PCI_ACCESSOR(domain, DOMAIN, uint32_t)
291PCI_ACCESSOR(bus, BUS, uint8_t)
292PCI_ACCESSOR(slot, SLOT, uint8_t)
293PCI_ACCESSOR(function, FUNCTION, uint8_t)
f72d3d23 294PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
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295PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
296PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
297PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
298PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
299PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
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300PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t)
301PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t)
302PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t)
984263bc 303
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304#undef PCI_ACCESSOR
305
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306/*
307 * Operations on configuration space.
308 */
309static __inline uint32_t
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310pci_read_config(device_t dev, int reg, int width)
311{
312 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
313}
314
315static __inline void
4d28e78f 316pci_write_config(device_t dev, int reg, uint32_t val, int width)
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317{
318 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
319}
320
321/*
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322 * Ivars for pci bridges.
323 */
324
325/*typedef enum pci_device_ivars pcib_device_ivars;*/
326enum pcib_device_ivars {
327 PCIB_IVAR_DOMAIN,
328 PCIB_IVAR_BUS
329};
330
331#define PCIB_ACCESSOR(var, ivar, type) \
332 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
333
334PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
335PCIB_ACCESSOR(bus, BUS, uint32_t)
336
337#undef PCIB_ACCESSOR
338
339/*
340 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
341 * on i386 or other platforms should be mapped out in the MD pcireadconf
342 * code and not here, since the only MI invalid IRQ is 255.
343 */
344#define PCI_INVALID_IRQ 255
345#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
346
347/*
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348 * Convenience functions.
349 *
350 * These should be used in preference to manually manipulating
351 * configuration space.
352 */
4d28e78f 353static __inline int
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354pci_enable_busmaster(device_t dev)
355{
4d28e78f 356 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
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357}
358
4d28e78f 359static __inline int
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360pci_disable_busmaster(device_t dev)
361{
4d28e78f 362 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
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363}
364
4d28e78f 365static __inline int
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366pci_enable_io(device_t dev, int space)
367{
4d28e78f 368 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
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369}
370
4d28e78f 371static __inline int
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372pci_disable_io(device_t dev, int space)
373{
4d28e78f 374 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
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375}
376
c7e4e7eb 377static __inline int
4d28e78f 378pci_get_vpd_ident(device_t dev, const char **identptr)
c7e4e7eb 379{
4d28e78f 380 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
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381}
382
383static __inline int
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384pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
385{
386 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
387}
388
389/*
390 * Check if the address range falls within the VGA defined address range(s)
391 */
392static __inline int
393pci_is_vga_ioport_range(u_long start, u_long end)
394{
395
396 return (((start >= 0x3b0 && end <= 0x3bb) ||
397 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
398}
399
400static __inline int
401pci_is_vga_memory_range(u_long start, u_long end)
c7e4e7eb 402{
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403
404 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
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405}
406
d85e7311 407int pcie_slot_implemented(device_t);
4d28e78f 408void pcie_set_max_readrq(device_t, uint16_t);
d85e7311 409
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410/*
411 * PCI power states are as defined by ACPI:
412 *
413 * D0 State in which device is on and running. It is receiving full
414 * power from the system and delivering full functionality to the user.
415 * D1 Class-specific low-power state in which device context may or may not
416 * be lost. Buses in D1 cannot do anything to the bus that would force
4d28e78f 417 * devices on that bus to lose context.
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418 * D2 Class-specific low-power state in which device context may or may
419 * not be lost. Attains greater power savings than D1. Buses in D2
4d28e78f 420 * can cause devices on that bus to lose some context. Devices in D2
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421 * must be prepared for the bus to be in D2 or higher.
422 * D3 State in which the device is off and not running. Device context is
423 * lost. Power can be removed from the device.
424 */
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425#define PCI_POWERSTATE_D0 0
426#define PCI_POWERSTATE_D1 1
427#define PCI_POWERSTATE_D2 2
428#define PCI_POWERSTATE_D3 3
429#define PCI_POWERSTATE_UNKNOWN -1
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430
431static __inline int
432pci_set_powerstate(device_t dev, int state)
433{
434 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
435}
436
437static __inline int
438pci_get_powerstate(device_t dev)
439{
440 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
441}
442
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443static __inline int
444pci_find_extcap(device_t dev, int capability, int *capreg)
445{
446 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
447}
448
449static __inline int
450pci_is_pcie(device_t dev)
451{
d85e7311 452 return (pci_get_pciecap_ptr(dev) != 0);
4d28e78f 453}
984263bc 454
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455static __inline int
456pci_is_pcix(device_t dev)
457{
d85e7311 458 return (pci_get_pcixcap_ptr(dev) != 0);
4d28e78f 459}
984263bc 460
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461static __inline int
462pci_alloc_msi(device_t dev, int *count)
463{
464 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
465}
466
467static __inline int
468pci_alloc_msix(device_t dev, int *count)
469{
470 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
471}
984263bc 472
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473static __inline int
474pci_remap_msix(device_t dev, int count, const u_int *vectors)
475{
476 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
477}
984263bc 478
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479static __inline int
480pci_release_msi(device_t dev)
481{
482 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
483}
984263bc 484
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485static __inline int
486pci_msi_count(device_t dev)
487{
488 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
489}
984263bc 490
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491static __inline int
492pci_msix_count(device_t dev)
493{
494 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
495}
984263bc 496
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497device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
498device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
499device_t pci_find_device(uint16_t, uint16_t);
500
501/*
502 * Can be used by MD code to request the PCI bus to re-map an MSI or
503 * MSI-X message.
504 */
505int pci_remap_msi_irq(device_t dev, u_int irq);
506
507/* Can be used by drivers to manage the MSI-X table. */
508int pci_pending_msix(device_t dev, u_int index);
509
510int pci_msi_device_blacklisted(device_t dev);
511
512void pci_ht_map_msi(device_t dev, uint64_t addr);
513
514#endif /* _SYS_BUS_H_ */
515
516/*
517 * cdev switch for control device, initialised in generic PCI code
518 */
519extern struct cdevsw pcicdev;
520
521/*
522 * List of all PCI devices, generation count for the list.
523 */
524STAILQ_HEAD(devlist, pci_devinfo);
525
526extern struct devlist pci_devq;
527extern uint32_t pci_generation;
984263bc 528
984263bc 529#endif /* _PCIVAR_H_ */