proc->thread stage 4: rework the VFS and DEVICE subsystems to take thread
[dragonfly.git] / sys / dev / serial / sio / sio.c
CommitLineData
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/isa/sio.c,v 1.291.2.35 2003/05/18 08:51:15 murray Exp $
dadab5e9 34 * $DragonFly: src/sys/dev/serial/sio/sio.c,v 1.4 2003/06/25 03:55:56 dillon Exp $
984263bc
MD
35 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
36 * from: i386/isa sio.c,v 1.234
37 */
38
39#include "opt_comconsole.h"
40#include "opt_compat.h"
41#include "opt_ddb.h"
42#include "opt_sio.h"
43#include "card.h"
44#include "pci.h"
45#ifdef __i386__
46#include "puc.h"
47#endif
48#include "sio.h"
49
50/*
51 * Serial driver, based on 386BSD-0.1 com driver.
52 * Mostly rewritten to use pseudo-DMA.
53 * Works for National Semiconductor NS8250-NS16550AF UARTs.
54 * COM driver, based on HP dca driver.
55 *
56 * Changes for PC-Card integration:
57 * - Added PC-Card driver table and handlers
58 */
59#include <sys/param.h>
60#include <sys/systm.h>
61#include <sys/reboot.h>
62#include <sys/malloc.h>
63#include <sys/tty.h>
64#include <sys/proc.h>
65#include <sys/module.h>
66#include <sys/conf.h>
67#include <sys/dkstat.h>
68#include <sys/fcntl.h>
69#include <sys/interrupt.h>
70#include <sys/kernel.h>
71#include <sys/syslog.h>
72#include <sys/sysctl.h>
73#include <sys/bus.h>
74#include <machine/bus_pio.h>
75#include <machine/bus.h>
76#include <sys/rman.h>
77#include <sys/timepps.h>
78
79#include <machine/limits.h>
80
81#include <isa/isareg.h>
82#include <isa/isavar.h>
83#if NPCI > 0
84#include <pci/pcireg.h>
85#include <pci/pcivar.h>
86#endif
87#if NPUC > 0
88#include <dev/puc/pucvar.h>
89#endif
90#include <machine/lock.h>
91
92#include <machine/clock.h>
93#include <machine/ipl.h>
94#ifndef SMP
95#include <machine/lock.h>
96#endif
97#include <machine/resource.h>
98
99#include <isa/sioreg.h>
100
101#ifdef COM_ESP
102#include <dev/ic/esp.h>
103#endif
104#include <dev/ic/ns16550.h>
105
106#ifndef __i386__
107#define disable_intr()
108#define enable_intr()
109#endif
110
111#ifdef SMP
112#define disable_intr() COM_DISABLE_INTR()
113#define enable_intr() COM_ENABLE_INTR()
114#endif /* SMP */
115
116#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
117
118#define CALLOUT_MASK 0x80
119#define CONTROL_MASK 0x60
120#define CONTROL_INIT_STATE 0x20
121#define CONTROL_LOCK_STATE 0x40
122#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
123#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \
124 | ((mynor) & 0x1f))
125#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \
126 | ((unit) & 0x1f))
127
128#ifdef COM_MULTIPORT
129/* checks in flags for multiport and which is multiport "master chip"
130 * for a given card
131 */
132#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
133#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
134#define COM_NOTAST4(flags) ((flags) & 0x04)
135#endif /* COM_MULTIPORT */
136
137#define COM_CONSOLE(flags) ((flags) & 0x10)
138#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
139#define COM_LLCONSOLE(flags) ((flags) & 0x40)
140#define COM_DEBUGGER(flags) ((flags) & 0x80)
141#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
142#define COM_NOFIFO(flags) ((flags) & 0x02)
143#define COM_ST16650A(flags) ((flags) & 0x20000)
144#define COM_C_NOPROBE (0x40000)
145#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
146#define COM_C_IIR_TXRDYBUG (0x80000)
147#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
148#define COM_TI16754(flags) ((flags) & 0x200000)
149#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
150
151#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
152
153#define sio_getreg(com, off) \
154 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
155#define sio_setreg(com, off, value) \
156 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
157
158/*
159 * com state bits.
160 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
161 * than the other bits so that they can be tested as a group without masking
162 * off the low bits.
163 *
164 * The following com and tty flags correspond closely:
165 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
166 * comstop())
167 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
168 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
169 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
170 * TS_FLUSH is not used.
171 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
172 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
173 */
174#define CS_BUSY 0x80 /* output in progress */
175#define CS_TTGO 0x40 /* output not stopped by XOFF */
176#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
177#define CS_CHECKMSR 1 /* check of MSR scheduled */
178#define CS_CTS_OFLOW 2 /* use CTS output flow control */
179#define CS_DTR_OFF 0x10 /* DTR held off */
180#define CS_ODONE 4 /* output completed */
181#define CS_RTS_IFLOW 8 /* use RTS input flow control */
182#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
183
184static char const * const error_desc[] = {
185#define CE_OVERRUN 0
186 "silo overflow",
187#define CE_INTERRUPT_BUF_OVERFLOW 1
188 "interrupt-level buffer overflow",
189#define CE_TTY_BUF_OVERFLOW 2
190 "tty-level buffer overflow",
191};
192
193#define CE_NTYPES 3
194#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
195
196/* types. XXX - should be elsewhere */
197typedef u_int Port_t; /* hardware port */
198typedef u_char bool_t; /* boolean */
199
200/* queue of linear buffers */
201struct lbq {
202 u_char *l_head; /* next char to process */
203 u_char *l_tail; /* one past the last char to process */
204 struct lbq *l_next; /* next in queue */
205 bool_t l_queued; /* nonzero if queued */
206};
207
208/* com device structure */
209struct com_s {
210 u_int flags; /* Copy isa device flags */
211 u_char state; /* miscellaneous flag bits */
212 bool_t active_out; /* nonzero if the callout device is open */
213 u_char cfcr_image; /* copy of value written to CFCR */
214#ifdef COM_ESP
215 bool_t esp; /* is this unit a hayes esp board? */
216#endif
217 u_char extra_state; /* more flag bits, separate for order trick */
218 u_char fifo_image; /* copy of value written to FIFO */
219 bool_t hasfifo; /* nonzero for 16550 UARTs */
220 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
221 bool_t loses_outints; /* nonzero if device loses output interrupts */
222 u_char mcr_image; /* copy of value written to MCR */
223#ifdef COM_MULTIPORT
224 bool_t multiport; /* is this unit part of a multiport device? */
225#endif /* COM_MULTIPORT */
226 bool_t no_irq; /* nonzero if irq is not attached */
227 bool_t gone; /* hardware disappeared */
228 bool_t poll; /* nonzero if polling is required */
229 bool_t poll_output; /* nonzero if polling for output is required */
230 int unit; /* unit number */
231 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
232 u_int tx_fifo_size;
233 u_int wopeners; /* # processes waiting for DCD in open() */
234
235 /*
236 * The high level of the driver never reads status registers directly
237 * because there would be too many side effects to handle conveniently.
238 * Instead, it reads copies of the registers stored here by the
239 * interrupt handler.
240 */
241 u_char last_modem_status; /* last MSR read by intr handler */
242 u_char prev_modem_status; /* last MSR handled by high level */
243
244 u_char hotchar; /* ldisc-specific char to be handled ASAP */
245 u_char *ibuf; /* start of input buffer */
246 u_char *ibufend; /* end of input buffer */
247 u_char *ibufold; /* old input buffer, to be freed */
248 u_char *ihighwater; /* threshold in input buffer */
249 u_char *iptr; /* next free spot in input buffer */
250 int ibufsize; /* size of ibuf (not include error bytes) */
251 int ierroff; /* offset of error bytes in ibuf */
252
253 struct lbq obufq; /* head of queue of output buffers */
254 struct lbq obufs[2]; /* output buffers */
255
256 bus_space_tag_t bst;
257 bus_space_handle_t bsh;
258
259 Port_t data_port; /* i/o ports */
260#ifdef COM_ESP
261 Port_t esp_port;
262#endif
263 Port_t int_id_port;
264 Port_t modem_ctl_port;
265 Port_t line_status_port;
266 Port_t modem_status_port;
267 Port_t intr_ctl_port; /* Ports of IIR register */
268
269 struct tty *tp; /* cross reference */
270
271 /* Initial state. */
272 struct termios it_in; /* should be in struct tty */
273 struct termios it_out;
274
275 /* Lock state. */
276 struct termios lt_in; /* should be in struct tty */
277 struct termios lt_out;
278
279 bool_t do_timestamp;
280 bool_t do_dcd_timestamp;
281 struct timeval timestamp;
282 struct timeval dcd_timestamp;
283 struct pps_state pps;
284
285 u_long bytes_in; /* statistics */
286 u_long bytes_out;
287 u_int delta_error_counts[CE_NTYPES];
288 u_long error_counts[CE_NTYPES];
289
290 u_long rclk;
291
292 struct resource *irqres;
293 struct resource *ioportres;
294 void *cookie;
295
296 /*
297 * Data area for output buffers. Someday we should build the output
298 * buffer queue without copying data.
299 */
300 u_char obuf1[256];
301 u_char obuf2[256];
302};
303
304#ifdef COM_ESP
305static int espattach __P((struct com_s *com, Port_t esp_port));
306#endif
307static int sioattach __P((device_t dev, int rid, u_long rclk));
308static int sio_isa_attach __P((device_t dev));
309
310static timeout_t siobusycheck;
311static u_int siodivisor __P((u_long rclk, speed_t speed));
312static timeout_t siodtrwakeup;
313static void comhardclose __P((struct com_s *com));
314static void sioinput __P((struct com_s *com));
315static void siointr1 __P((struct com_s *com));
316static void siointr __P((void *arg));
317static int commctl __P((struct com_s *com, int bits, int how));
318static int comparam __P((struct tty *tp, struct termios *t));
319static swihand_t siopoll;
320static int sioprobe __P((device_t dev, int xrid, u_long rclk));
321static int sio_isa_probe __P((device_t dev));
322static void siosettimeout __P((void));
323static int siosetwater __P((struct com_s *com, speed_t speed));
324static void comstart __P((struct tty *tp));
325static void comstop __P((struct tty *tp, int rw));
326static timeout_t comwakeup;
327static void disc_optim __P((struct tty *tp, struct termios *t,
328 struct com_s *com));
329
330#if NCARD > 0
331static int sio_pccard_attach __P((device_t dev));
332static int sio_pccard_detach __P((device_t dev));
333static int sio_pccard_probe __P((device_t dev));
334#endif /* NCARD > 0 */
335
336#if NPCI > 0
337static int sio_pci_attach __P((device_t dev));
338static void sio_pci_kludge_unit __P((device_t dev));
339static int sio_pci_probe __P((device_t dev));
340#endif /* NPCI > 0 */
341
342#if NPUC > 0
343static int sio_puc_attach __P((device_t dev));
344static int sio_puc_probe __P((device_t dev));
345#endif /* NPUC > 0 */
346
347static char driver_name[] = "sio";
348
349/* table and macro for fast conversion from a unit number to its com struct */
350static devclass_t sio_devclass;
351#define com_addr(unit) ((struct com_s *) \
352 devclass_get_softc(sio_devclass, unit))
353
354static device_method_t sio_isa_methods[] = {
355 /* Device interface */
356 DEVMETHOD(device_probe, sio_isa_probe),
357 DEVMETHOD(device_attach, sio_isa_attach),
358
359 { 0, 0 }
360};
361
362static driver_t sio_isa_driver = {
363 driver_name,
364 sio_isa_methods,
365 sizeof(struct com_s),
366};
367
368#if NCARD > 0
369static device_method_t sio_pccard_methods[] = {
370 /* Device interface */
371 DEVMETHOD(device_probe, sio_pccard_probe),
372 DEVMETHOD(device_attach, sio_pccard_attach),
373 DEVMETHOD(device_detach, sio_pccard_detach),
374
375 { 0, 0 }
376};
377
378static driver_t sio_pccard_driver = {
379 driver_name,
380 sio_pccard_methods,
381 sizeof(struct com_s),
382};
383#endif /* NCARD > 0 */
384
385#if NPCI > 0
386static device_method_t sio_pci_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, sio_pci_probe),
389 DEVMETHOD(device_attach, sio_pci_attach),
390
391 { 0, 0 }
392};
393
394static driver_t sio_pci_driver = {
395 driver_name,
396 sio_pci_methods,
397 sizeof(struct com_s),
398};
399#endif /* NPCI > 0 */
400
401#if NPUC > 0
402static device_method_t sio_puc_methods[] = {
403 /* Device interface */
404 DEVMETHOD(device_probe, sio_puc_probe),
405 DEVMETHOD(device_attach, sio_puc_attach),
406
407 { 0, 0 }
408};
409
410static driver_t sio_puc_driver = {
411 driver_name,
412 sio_puc_methods,
413 sizeof(struct com_s),
414};
415#endif /* NPUC > 0 */
416
417static d_open_t sioopen;
418static d_close_t sioclose;
419static d_read_t sioread;
420static d_write_t siowrite;
421static d_ioctl_t sioioctl;
422
423#define CDEV_MAJOR 28
424static struct cdevsw sio_cdevsw = {
425 /* open */ sioopen,
426 /* close */ sioclose,
427 /* read */ sioread,
428 /* write */ siowrite,
429 /* ioctl */ sioioctl,
430 /* poll */ ttypoll,
431 /* mmap */ nommap,
432 /* strategy */ nostrategy,
433 /* name */ driver_name,
434 /* maj */ CDEV_MAJOR,
435 /* dump */ nodump,
436 /* psize */ nopsize,
437 /* flags */ D_TTY | D_KQFILTER,
438 /* bmaj */ -1,
439 /* kqfilter */ ttykqfilter,
440};
441
442int comconsole = -1;
443static volatile speed_t comdefaultrate = CONSPEED;
444static u_long comdefaultrclk = DEFAULT_RCLK;
445SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
446#ifdef __alpha__
447static volatile speed_t gdbdefaultrate = CONSPEED;
448#endif
449static u_int com_events; /* input chars + weighted output completions */
450static Port_t siocniobase;
451static int siocnunit;
452static Port_t siogdbiobase;
453static int siogdbunit = -1;
454static bool_t sio_registered;
455static int sio_timeout;
456static int sio_timeouts_until_log;
457static struct callout_handle sio_timeout_handle
458 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
459static int sio_numunits;
460
461#ifdef COM_ESP
462/* XXX configure this properly. */
463static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
464static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
465#endif
466
467/*
468 * handle sysctl read/write requests for console speed
469 *
470 * In addition to setting comdefaultrate for I/O through /dev/console,
471 * also set the initial and lock values for the /dev/ttyXX device
472 * if there is one associated with the console. Finally, if the /dev/tty
473 * device has already been open, change the speed on the open running port
474 * itself.
475 */
476
477static int
478sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
479{
480 int error, s;
481 speed_t newspeed;
482 struct com_s *com;
483 struct tty *tp;
484
485 newspeed = comdefaultrate;
486
487 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
488 if (error || !req->newptr)
489 return (error);
490
491 comdefaultrate = newspeed;
492
493 if (comconsole < 0) /* serial console not selected? */
494 return (0);
495
496 com = com_addr(comconsole);
497 if (com == NULL)
498 return (ENXIO);
499
500 /*
501 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
502 * (note, the lock rates really are boolean -- if non-zero, disallow
503 * speed changes)
504 */
505 com->it_in.c_ispeed = com->it_in.c_ospeed =
506 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
507 com->it_out.c_ispeed = com->it_out.c_ospeed =
508 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
509
510 /*
511 * if we're open, change the running rate too
512 */
513 tp = com->tp;
514 if (tp && (tp->t_state & TS_ISOPEN)) {
515 tp->t_termios.c_ispeed =
516 tp->t_termios.c_ospeed = comdefaultrate;
517 s = spltty();
518 error = comparam(tp, &tp->t_termios);
519 splx(s);
520 }
521 return error;
522}
523
524SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
525 0, 0, sysctl_machdep_comdefaultrate, "I", "");
526
527#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
528#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
529
530#if NCARD > 0
531static int
532sio_pccard_probe(dev)
533 device_t dev;
534{
535 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */
536 /* until bus_setup_intr */
537 SET_FLAG(dev, COM_C_NOPROBE);
538
539 return (sioprobe(dev, 0, 0UL));
540}
541
542static int
543sio_pccard_attach(dev)
544 device_t dev;
545{
546 return (sioattach(dev, 0, 0UL));
547}
548
549/*
550 * sio_detach - unload the driver and clear the table.
551 * XXX TODO:
552 * This is usually called when the card is ejected, but
553 * can be caused by a modunload of a controller driver.
554 * The idea is to reset the driver's view of the device
555 * and ensure that any driver entry points such as
556 * read and write do not hang.
557 */
558static int
559sio_pccard_detach(dev)
560 device_t dev;
561{
562 struct com_s *com;
563
564 com = (struct com_s *) device_get_softc(dev);
565 if (com == NULL) {
566 device_printf(dev, "NULL com in siounload\n");
567 return (0);
568 }
569 com->gone = 1;
570 if (com->irqres) {
571 bus_teardown_intr(dev, com->irqres, com->cookie);
572 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
573 }
574 if (com->ioportres)
575 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
576 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
577 device_printf(dev, "still open, forcing close\n");
578 com->tp->t_gen++;
579 ttyclose(com->tp);
580 ttwakeup(com->tp);
581 ttwwakeup(com->tp);
582 } else {
583 if (com->ibuf != NULL)
584 free(com->ibuf, M_DEVBUF);
585 }
586 device_printf(dev, "unloaded\n");
587 return (0);
588}
589#endif /* NCARD > 0 */
590
591#if NPCI > 0
592struct pci_ids {
593 u_int32_t type;
594 const char *desc;
595 int rid;
596};
597
598static struct pci_ids pci_ids[] = {
599 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
600 { 0x2000131f, "CyberSerial (1-port) 16550", 0x10 },
601 { 0x01101407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
602 { 0x01111407, "Koutech IOFLEX-2S PCI Dual Port Serial", 0x10 },
603 { 0x048011c1, "Lucent kermit based PCI Modem", 0x14 },
604 { 0x95211415, "Oxford Semiconductor PCI Dual Port Serial", 0x10 },
605 { 0x7101135e, "SeaLevel Ultra 530.PCI Single Port Serial", 0x18 },
606 { 0x0000151f, "SmartLink 5634PCV SurfRider", 0x10 },
607 { 0x98459710, "Netmos Nm9845 PCI Bridge with Dual UART", 0x10 },
608 { 0x00000000, NULL, 0 }
609};
610
611static int
612sio_pci_attach(dev)
613 device_t dev;
614{
615 u_int32_t type;
616 struct pci_ids *id;
617
618 type = pci_get_devid(dev);
619 id = pci_ids;
620 while (id->type && id->type != type)
621 id++;
622 if (id->desc == NULL)
623 return (ENXIO);
624 sio_pci_kludge_unit(dev);
625 return (sioattach(dev, id->rid, 0UL));
626}
627
628/*
629 * Don't cut and paste this to other drivers. It is a horrible kludge
630 * which will fail to work and also be unnecessary in future versions.
631 */
632static void
633sio_pci_kludge_unit(dev)
634 device_t dev;
635{
636 devclass_t dc;
637 int err;
638 int start;
639 int unit;
640
641 unit = 0;
642 start = 0;
643 while (resource_int_value("sio", unit, "port", &start) == 0 &&
644 start > 0)
645 unit++;
646 if (device_get_unit(dev) < unit) {
647 dc = device_get_devclass(dev);
648 while (devclass_get_device(dc, unit))
649 unit++;
650 device_printf(dev, "moving to sio%d\n", unit);
651 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
652 if (err)
653 device_printf(dev, "error moving device %d\n", err);
654 }
655}
656
657static int
658sio_pci_probe(dev)
659 device_t dev;
660{
661 u_int32_t type;
662 struct pci_ids *id;
663
664 type = pci_get_devid(dev);
665 id = pci_ids;
666 while (id->type && id->type != type)
667 id++;
668 if (id->desc == NULL)
669 return (ENXIO);
670 device_set_desc(dev, id->desc);
671 return (sioprobe(dev, id->rid, 0UL));
672}
673#endif /* NPCI > 0 */
674
675#if NPUC > 0
676static int
677sio_puc_attach(dev)
678 device_t dev;
679{
680 u_int rclk;
681
682 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
683 &rclk) != 0)
684 rclk = DEFAULT_RCLK;
685 return (sioattach(dev, 0, rclk));
686}
687
688static int
689sio_puc_probe(dev)
690 device_t dev;
691{
692 u_int rclk;
693
694 if (BUS_READ_IVAR(device_get_parent(dev), dev, PUC_IVAR_FREQ,
695 &rclk) != 0)
696 rclk = DEFAULT_RCLK;
697 return (sioprobe(dev, 0, rclk));
698}
699#endif /* NPUC */
700
701static struct isa_pnp_id sio_ids[] = {
702 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
703 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
704 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
705 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
706 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
707 /* Devices that do not have a compatid */
708 {0x12206804, NULL}, /* ACH2012 - 5634BTS 56K Video Ready Modem */
709 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
710 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
711 {0x21107905, NULL}, /* AKY1021 - 56K Plug&Play Modem */
712 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
713 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
714 {0x56159008, NULL}, /* BDP1556 - B.D. Smart One 56SPS,Voice Modem*/
715 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
716 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
717 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
718 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
719 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */
720 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
721 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
722 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
723 {0x01308c0e, NULL}, /* CTL3001 - Creative Labs Phoneblaster */
724 {0x36033610, NULL}, /* DAV0336 - DAVICOM 336PNP MODEM */
725 {0x01009416, NULL}, /* ETT0001 - E-Tech Bullet 33k6 PnP */
726 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */
727 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
728 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
729 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
730 {0x0116c31e, NULL}, /* GVC1601 - Rockwell V.34 Plug & Play Modem */
731 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
732 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
733 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
734 {0x8100e425, NULL}, /* IOD0081 - I-O DATA DEVICE,INC. IFML-560 */
735 {0x21002534, NULL}, /* MAE0021 - Jetstream Int V.90 56k Voice Series 2*/
736 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
737 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
738 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
739 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
740 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
741 {0x08804f3f, NULL}, /* OZO8008 - Zoom (33.6k Modem) */
742 {0x0f804f3f, NULL}, /* OZO800f - Zoom 2812 (56k Modem) */
743 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
744 {0x00914f3f, NULL}, /* OZO9100 - Zoom 2919 (K56 Faxmodem) */
745 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
746 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
747 {0x1200b23d, NULL}, /* RSS0012 - OMRON ME5614ISA */
748 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
749 {0x6202734a, NULL}, /* RSS0262 - 5614Jx3[G] V90+K56Flex Modem */
750 {0x1010104d, NULL}, /* SHP1010 - Rockwell 33600bps Modem */
751 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
752 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
753 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
754 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
755 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
756 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
757 {0x7016b04e, NULL}, /* SUP1670 - Supra 336i V+ Intl */
758 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
759 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
760 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
761 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
762 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
763 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
764 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
765 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
766 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
767 {0x11007256, NULL}, /* USR0011 - USR ? */
768 {0x01017256, NULL}, /* USR0101 - USR ? */
769 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
770 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
771 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
772 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
773 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
774 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
775 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
776 {0x90307256, NULL}, /* USR3090 - USR ? */
777 {0x70917256, NULL}, /* USR9170 - U.S. Robotics 56K FAX INT */
778 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
779 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
780 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */
781 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
782 {0}
783};
784
785
786
787static int
788sio_isa_probe(dev)
789 device_t dev;
790{
791 /* Check isapnp ids */
792 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
793 return (ENXIO);
794 return (sioprobe(dev, 0, 0UL));
795}
796
797static int
798sioprobe(dev, xrid, rclk)
799 device_t dev;
800 int xrid;
801 u_long rclk;
802{
803#if 0
804 static bool_t already_init;
805 device_t xdev;
806#endif
807 struct com_s *com;
808 u_int divisor;
809 bool_t failures[10];
810 int fn;
811 device_t idev;
812 Port_t iobase;
813 intrmask_t irqmap[4];
814 intrmask_t irqs;
815 u_char mcr_image;
816 int result;
817 u_long xirq;
818 u_int flags = device_get_flags(dev);
819 int rid;
820 struct resource *port;
821
822 rid = xrid;
823 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
824 0, ~0, IO_COMSIZE, RF_ACTIVE);
825 if (!port)
826 return (ENXIO);
827
828 com = device_get_softc(dev);
829 com->bst = rman_get_bustag(port);
830 com->bsh = rman_get_bushandle(port);
831 if (rclk == 0)
832 rclk = DEFAULT_RCLK;
833 com->rclk = rclk;
834
835#if 0
836 /*
837 * XXX this is broken - when we are first called, there are no
838 * previously configured IO ports. We could hard code
839 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
840 * This code has been doing nothing since the conversion since
841 * "count" is zero the first time around.
842 */
843 if (!already_init) {
844 /*
845 * Turn off MCR_IENABLE for all likely serial ports. An unused
846 * port with its MCR_IENABLE gate open will inhibit interrupts
847 * from any used port that shares the interrupt vector.
848 * XXX the gate enable is elsewhere for some multiports.
849 */
850 device_t *devs;
851 int count, i, xioport;
852
853 devclass_get_devices(sio_devclass, &devs, &count);
854 for (i = 0; i < count; i++) {
855 xdev = devs[i];
856 if (device_is_enabled(xdev) &&
857 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
858 NULL) == 0)
859 outb(xioport + com_mcr, 0);
860 }
861 free(devs, M_TEMP);
862 already_init = TRUE;
863 }
864#endif
865
866 if (COM_LLCONSOLE(flags)) {
867 printf("sio%d: reserved for low-level i/o\n",
868 device_get_unit(dev));
869 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
870 return (ENXIO);
871 }
872
873 /*
874 * If the device is on a multiport card and has an AST/4
875 * compatible interrupt control register, initialize this
876 * register and prepare to leave MCR_IENABLE clear in the mcr.
877 * Otherwise, prepare to set MCR_IENABLE in the mcr.
878 * Point idev to the device struct giving the correct id_irq.
879 * This is the struct for the master device if there is one.
880 */
881 idev = dev;
882 mcr_image = MCR_IENABLE;
883#ifdef COM_MULTIPORT
884 if (COM_ISMULTIPORT(flags)) {
885 Port_t xiobase;
886 u_long io;
887
888 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
889 if (idev == NULL) {
890 printf("sio%d: master device %d not configured\n",
891 device_get_unit(dev), COM_MPMASTER(flags));
892 idev = dev;
893 }
894 if (!COM_NOTAST4(flags)) {
895 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
896 NULL) == 0) {
897 xiobase = io;
898 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
899 NULL, NULL) == 0)
900 outb(xiobase + com_scr, 0x80);
901 else
902 outb(xiobase + com_scr, 0);
903 }
904 mcr_image = 0;
905 }
906 }
907#endif /* COM_MULTIPORT */
908 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
909 mcr_image = 0;
910
911 bzero(failures, sizeof failures);
912 iobase = rman_get_start(port);
913
914 /*
915 * We don't want to get actual interrupts, just masked ones.
916 * Interrupts from this line should already be masked in the ICU,
917 * but mask them in the processor as well in case there are some
918 * (misconfigured) shared interrupts.
919 */
920 disable_intr();
921/* EXTRA DELAY? */
922
923 /*
924 * For the TI16754 chips, set prescaler to 1 (4 is often the
925 * default after-reset value) as otherwise it's impossible to
926 * get highest baudrates.
927 */
928 if (COM_TI16754(flags)) {
929 u_char cfcr, efr;
930
931 cfcr = sio_getreg(com, com_cfcr);
932 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
933 efr = sio_getreg(com, com_efr);
934 /* Unlock extended features to turn off prescaler. */
935 sio_setreg(com, com_efr, efr | EFR_EFE);
936 /* Disable EFR. */
937 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
938 /* Turn off prescaler. */
939 sio_setreg(com, com_mcr,
940 sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
941 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
942 sio_setreg(com, com_efr, efr);
943 sio_setreg(com, com_cfcr, cfcr);
944 }
945
946 /*
947 * Initialize the speed and the word size and wait long enough to
948 * drain the maximum of 16 bytes of junk in device output queues.
949 * The speed is undefined after a master reset and must be set
950 * before relying on anything related to output. There may be
951 * junk after a (very fast) soft reboot and (apparently) after
952 * master reset.
953 * XXX what about the UART bug avoided by waiting in comparam()?
954 * We don't want to to wait long enough to drain at 2 bps.
955 */
956 if (iobase == siocniobase)
957 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
958 else {
959 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
960 divisor = siodivisor(rclk, SIO_TEST_SPEED);
961 sio_setreg(com, com_dlbl, divisor & 0xff);
962 sio_setreg(com, com_dlbh, divisor >> 8);
963 sio_setreg(com, com_cfcr, CFCR_8BITS);
964 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
965 }
966
967 /*
968 * Enable the interrupt gate and disable device interupts. This
969 * should leave the device driving the interrupt line low and
970 * guarantee an edge trigger if an interrupt can be generated.
971 */
972/* EXTRA DELAY? */
973 sio_setreg(com, com_mcr, mcr_image);
974 sio_setreg(com, com_ier, 0);
975 DELAY(1000); /* XXX */
976 irqmap[0] = isa_irq_pending();
977
978 /*
979 * Attempt to set loopback mode so that we can send a null byte
980 * without annoying any external device.
981 */
982/* EXTRA DELAY? */
983 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
984
985 /*
986 * Attempt to generate an output interrupt. On 8250's, setting
987 * IER_ETXRDY generates an interrupt independent of the current
988 * setting and independent of whether the THR is empty. On 16450's,
989 * setting IER_ETXRDY generates an interrupt independent of the
990 * current setting. On 16550A's, setting IER_ETXRDY only
991 * generates an interrupt when IER_ETXRDY is not already set.
992 */
993 sio_setreg(com, com_ier, IER_ETXRDY);
994
995 /*
996 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
997 * an interrupt. They'd better generate one for actually doing
998 * output. Loopback may be broken on the same incompatibles but
999 * it's unlikely to do more than allow the null byte out.
1000 */
1001 sio_setreg(com, com_data, 0);
1002 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1003
1004 /*
1005 * Turn off loopback mode so that the interrupt gate works again
1006 * (MCR_IENABLE was hidden). This should leave the device driving
1007 * an interrupt line high. It doesn't matter if the interrupt
1008 * line oscillates while we are not looking at it, since interrupts
1009 * are disabled.
1010 */
1011/* EXTRA DELAY? */
1012 sio_setreg(com, com_mcr, mcr_image);
1013
1014 /*
1015 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1016 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1017 */
1018 if (COM_NOPROBE(flags)) {
1019 /* Reading IIR register twice */
1020 for (fn = 0; fn < 2; fn ++) {
1021 DELAY(10000);
1022 failures[6] = sio_getreg(com, com_iir);
1023 }
1024 /* Check IIR_TXRDY clear ? */
1025 result = 0;
1026 if (failures[6] & IIR_TXRDY) {
1027 /* Nop, Double check with clearing IER */
1028 sio_setreg(com, com_ier, 0);
1029 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1030 /* Ok. we're familia this gang */
1031 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1032 } else {
1033 /* Unknown, Just omit this chip.. XXX */
1034 result = ENXIO;
1035 sio_setreg(com, com_mcr, 0);
1036 }
1037 } else {
1038 /* OK. this is well-known guys */
1039 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1040 }
1041 sio_setreg(com, com_ier, 0);
1042 sio_setreg(com, com_cfcr, CFCR_8BITS);
1043 enable_intr();
1044 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1045 return (iobase == siocniobase ? 0 : result);
1046 }
1047
1048 /*
1049 * Check that
1050 * o the CFCR, IER and MCR in UART hold the values written to them
1051 * (the values happen to be all distinct - this is good for
1052 * avoiding false positive tests from bus echoes).
1053 * o an output interrupt is generated and its vector is correct.
1054 * o the interrupt goes away when the IIR in the UART is read.
1055 */
1056/* EXTRA DELAY? */
1057 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1058 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1059 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1060 DELAY(10000); /* Some internal modems need this time */
1061 irqmap[1] = isa_irq_pending();
1062 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1063 DELAY(1000); /* XXX */
1064 irqmap[2] = isa_irq_pending();
1065 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1066
1067 /*
1068 * Turn off all device interrupts and check that they go off properly.
1069 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1070 * the OUT2 output of the UART to
1071 * the ICU input. Closing the gate would give a floating ICU input
1072 * (unless there is another device driving it) and spurious interrupts.
1073 * (On the system that this was first tested on, the input floats high
1074 * and gives a (masked) interrupt as soon as the gate is closed.)
1075 */
1076 sio_setreg(com, com_ier, 0);
1077 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1078 failures[7] = sio_getreg(com, com_ier);
1079 DELAY(1000); /* XXX */
1080 irqmap[3] = isa_irq_pending();
1081 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1082
1083 enable_intr();
1084
1085 irqs = irqmap[1] & ~irqmap[0];
1086 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1087 ((1 << xirq) & irqs) == 0)
1088 printf(
1089 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1090 device_get_unit(dev), xirq, irqs);
1091 if (bootverbose)
1092 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1093 device_get_unit(dev),
1094 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1095
1096 result = 0;
1097 for (fn = 0; fn < sizeof failures; ++fn)
1098 if (failures[fn]) {
1099 sio_setreg(com, com_mcr, 0);
1100 result = ENXIO;
1101 if (bootverbose) {
1102 printf("sio%d: probe failed test(s):",
1103 device_get_unit(dev));
1104 for (fn = 0; fn < sizeof failures; ++fn)
1105 if (failures[fn])
1106 printf(" %d", fn);
1107 printf("\n");
1108 }
1109 break;
1110 }
1111 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1112 return (iobase == siocniobase ? 0 : result);
1113}
1114
1115#ifdef COM_ESP
1116static int
1117espattach(com, esp_port)
1118 struct com_s *com;
1119 Port_t esp_port;
1120{
1121 u_char dips;
1122 u_char val;
1123
1124 /*
1125 * Check the ESP-specific I/O port to see if we're an ESP
1126 * card. If not, return failure immediately.
1127 */
1128 if ((inb(esp_port) & 0xf3) == 0) {
1129 printf(" port 0x%x is not an ESP board?\n", esp_port);
1130 return (0);
1131 }
1132
1133 /*
1134 * We've got something that claims to be a Hayes ESP card.
1135 * Let's hope so.
1136 */
1137
1138 /* Get the dip-switch configuration */
1139 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1140 dips = inb(esp_port + ESP_STATUS1);
1141
1142 /*
1143 * Bits 0,1 of dips say which COM port we are.
1144 */
1145 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1146 printf(" : ESP");
1147 else {
1148 printf(" esp_port has com %d\n", dips & 0x03);
1149 return (0);
1150 }
1151
1152 /*
1153 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1154 */
1155 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1156 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1157 val = inb(esp_port + ESP_STATUS2);
1158 if ((val & 0x70) < 0x20) {
1159 printf("-old (%o)", val & 0x70);
1160 return (0);
1161 }
1162
1163 /*
1164 * Check for ability to emulate 16550: bit 7 == 1
1165 */
1166 if ((dips & 0x80) == 0) {
1167 printf(" slave");
1168 return (0);
1169 }
1170
1171 /*
1172 * Okay, we seem to be a Hayes ESP card. Whee.
1173 */
1174 com->esp = TRUE;
1175 com->esp_port = esp_port;
1176 return (1);
1177}
1178#endif /* COM_ESP */
1179
1180static int
1181sio_isa_attach(dev)
1182 device_t dev;
1183{
1184 return (sioattach(dev, 0, 0UL));
1185}
1186
1187static int
1188sioattach(dev, xrid, rclk)
1189 device_t dev;
1190 int xrid;
1191 u_long rclk;
1192{
1193 struct com_s *com;
1194#ifdef COM_ESP
1195 Port_t *espp;
1196#endif
1197 Port_t iobase;
1198 int minorbase;
1199 int unit;
1200 u_int flags;
1201 int rid;
1202 struct resource *port;
1203 int ret;
1204
1205 rid = xrid;
1206 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1207 0, ~0, IO_COMSIZE, RF_ACTIVE);
1208 if (!port)
1209 return (ENXIO);
1210
1211 iobase = rman_get_start(port);
1212 unit = device_get_unit(dev);
1213 com = device_get_softc(dev);
1214 flags = device_get_flags(dev);
1215
1216 if (unit >= sio_numunits)
1217 sio_numunits = unit + 1;
1218 /*
1219 * sioprobe() has initialized the device registers as follows:
1220 * o cfcr = CFCR_8BITS.
1221 * It is most important that CFCR_DLAB is off, so that the
1222 * data port is not hidden when we enable interrupts.
1223 * o ier = 0.
1224 * Interrupts are only enabled when the line is open.
1225 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1226 * interrupt control register or the config specifies no irq.
1227 * Keeping MCR_DTR and MCR_RTS off might stop the external
1228 * device from sending before we are ready.
1229 */
1230 bzero(com, sizeof *com);
1231 com->unit = unit;
1232 com->ioportres = port;
1233 com->bst = rman_get_bustag(port);
1234 com->bsh = rman_get_bushandle(port);
1235 com->cfcr_image = CFCR_8BITS;
1236 com->dtr_wait = 3 * hz;
1237 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1238 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1239 com->tx_fifo_size = 1;
1240 com->obufs[0].l_head = com->obuf1;
1241 com->obufs[1].l_head = com->obuf2;
1242
1243 com->data_port = iobase + com_data;
1244 com->int_id_port = iobase + com_iir;
1245 com->modem_ctl_port = iobase + com_mcr;
1246 com->mcr_image = inb(com->modem_ctl_port);
1247 com->line_status_port = iobase + com_lsr;
1248 com->modem_status_port = iobase + com_msr;
1249 com->intr_ctl_port = iobase + com_ier;
1250
1251 if (rclk == 0)
1252 rclk = DEFAULT_RCLK;
1253 com->rclk = rclk;
1254
1255 /*
1256 * We don't use all the flags from <sys/ttydefaults.h> since they
1257 * are only relevant for logins. It's important to have echo off
1258 * initially so that the line doesn't start blathering before the
1259 * echo flag can be turned off.
1260 */
1261 com->it_in.c_iflag = 0;
1262 com->it_in.c_oflag = 0;
1263 com->it_in.c_cflag = TTYDEF_CFLAG;
1264 com->it_in.c_lflag = 0;
1265 if (unit == comconsole) {
1266 com->it_in.c_iflag = TTYDEF_IFLAG;
1267 com->it_in.c_oflag = TTYDEF_OFLAG;
1268 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1269 com->it_in.c_lflag = TTYDEF_LFLAG;
1270 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1271 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1272 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1273 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1274 } else
1275 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1276 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1277 enable_intr();
1278 /*
1279 * Leave i/o resources allocated if this is a `cn'-level
1280 * console, so that other devices can't snarf them.
1281 */
1282 if (iobase != siocniobase)
1283 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1284 return (ENOMEM);
1285 }
1286 enable_intr();
1287 termioschars(&com->it_in);
1288 com->it_out = com->it_in;
1289
1290 /* attempt to determine UART type */
1291 printf("sio%d: type", unit);
1292
1293
1294#ifdef COM_MULTIPORT
1295 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1296#else
1297 if (!COM_IIR_TXRDYBUG(flags))
1298#endif
1299 {
1300 u_char scr;
1301 u_char scr1;
1302 u_char scr2;
1303
1304 scr = sio_getreg(com, com_scr);
1305 sio_setreg(com, com_scr, 0xa5);
1306 scr1 = sio_getreg(com, com_scr);
1307 sio_setreg(com, com_scr, 0x5a);
1308 scr2 = sio_getreg(com, com_scr);
1309 sio_setreg(com, com_scr, scr);
1310 if (scr1 != 0xa5 || scr2 != 0x5a) {
1311 printf(" 8250");
1312 goto determined_type;
1313 }
1314 }
1315 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1316 DELAY(100);
1317 com->st16650a = 0;
1318 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1319 case FIFO_RX_LOW:
1320 printf(" 16450");
1321 break;
1322 case FIFO_RX_MEDL:
1323 printf(" 16450?");
1324 break;
1325 case FIFO_RX_MEDH:
1326 printf(" 16550?");
1327 break;
1328 case FIFO_RX_HIGH:
1329 if (COM_NOFIFO(flags)) {
1330 printf(" 16550A fifo disabled");
1331 } else {
1332 com->hasfifo = TRUE;
1333 if (COM_ST16650A(flags)) {
1334 com->st16650a = 1;
1335 com->tx_fifo_size = 32;
1336 printf(" ST16650A");
1337 } else if (COM_TI16754(flags)) {
1338 com->tx_fifo_size = 64;
1339 printf(" TI16754");
1340 } else {
1341 com->tx_fifo_size = COM_FIFOSIZE(flags);
1342 printf(" 16550A");
1343 }
1344 }
1345#ifdef COM_ESP
1346 for (espp = likely_esp_ports; *espp != 0; espp++)
1347 if (espattach(com, *espp)) {
1348 com->tx_fifo_size = 1024;
1349 break;
1350 }
1351#endif
1352 if (!com->st16650a && !COM_TI16754(flags)) {
1353 if (!com->tx_fifo_size)
1354 com->tx_fifo_size = 16;
1355 else
1356 printf(" lookalike with %d bytes FIFO",
1357 com->tx_fifo_size);
1358 }
1359
1360 break;
1361 }
1362
1363#ifdef COM_ESP
1364 if (com->esp) {
1365 /*
1366 * Set 16550 compatibility mode.
1367 * We don't use the ESP_MODE_SCALE bit to increase the
1368 * fifo trigger levels because we can't handle large
1369 * bursts of input.
1370 * XXX flow control should be set in comparam(), not here.
1371 */
1372 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1373 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1374
1375 /* Set RTS/CTS flow control. */
1376 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1377 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1378 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1379
1380 /* Set flow-control levels. */
1381 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1382 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1383 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1384 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1385 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1386 }
1387#endif /* COM_ESP */
1388 sio_setreg(com, com_fifo, 0);
1389determined_type: ;
1390
1391#ifdef COM_MULTIPORT
1392 if (COM_ISMULTIPORT(flags)) {
1393 device_t masterdev;
1394
1395 com->multiport = TRUE;
1396 printf(" (multiport");
1397 if (unit == COM_MPMASTER(flags))
1398 printf(" master");
1399 printf(")");
1400 masterdev = devclass_get_device(sio_devclass,
1401 COM_MPMASTER(flags));
1402 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1403 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1404 }
1405#endif /* COM_MULTIPORT */
1406 if (unit == comconsole)
1407 printf(", console");
1408 if (COM_IIR_TXRDYBUG(flags))
1409 printf(" with a bogus IIR_TXRDY register");
1410 printf("\n");
1411
1412 if (!sio_registered) {
1413 register_swi(SWI_TTY, siopoll);
1414 sio_registered = TRUE;
1415 }
1416 minorbase = UNIT_TO_MINOR(unit);
1417 make_dev(&sio_cdevsw, minorbase,
1418 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1419 make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE,
1420 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1421 make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE,
1422 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1423 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK,
1424 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1425 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_INIT_STATE,
1426 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1427 make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE,
1428 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1429 com->flags = flags;
1430 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1431 pps_init(&com->pps);
1432
1433 rid = 0;
1434 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1435 RF_ACTIVE);
1436 if (com->irqres) {
1437 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1438 INTR_TYPE_TTY | INTR_TYPE_FAST,
1439 siointr, com, &com->cookie);
1440 if (ret) {
1441 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1442 com->irqres, INTR_TYPE_TTY,
1443 siointr, com, &com->cookie);
1444 if (ret == 0)
1445 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1446 }
1447 if (ret)
1448 device_printf(dev, "could not activate interrupt\n");
1449#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1450 defined(ALT_BREAK_TO_DEBUGGER))
1451 /*
1452 * Enable interrupts for early break-to-debugger support
1453 * on the console.
1454 */
1455 if (ret == 0 && unit == comconsole)
1456 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1457 IER_EMSC);
1458#endif
1459 }
1460
1461 return (0);
1462}
1463
1464static int
41c20dac 1465sioopen(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1466{
1467 struct com_s *com;
1468 int error;
1469 int mynor;
1470 int s;
1471 struct tty *tp;
1472 int unit;
1473
1474 mynor = minor(dev);
1475 unit = MINOR_TO_UNIT(mynor);
1476 com = com_addr(unit);
1477 if (com == NULL)
1478 return (ENXIO);
1479 if (com->gone)
1480 return (ENXIO);
1481 if (mynor & CONTROL_MASK)
1482 return (0);
1483 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1484 s = spltty();
1485 /*
1486 * We jump to this label after all non-interrupted sleeps to pick
1487 * up any changes of the device state.
1488 */
1489open_top:
1490 while (com->state & CS_DTR_OFF) {
1491 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1492 if (com_addr(unit) == NULL)
1493 return (ENXIO);
1494 if (error != 0 || com->gone)
1495 goto out;
1496 }
1497 if (tp->t_state & TS_ISOPEN) {
1498 /*
1499 * The device is open, so everything has been initialized.
1500 * Handle conflicts.
1501 */
1502 if (mynor & CALLOUT_MASK) {
1503 if (!com->active_out) {
1504 error = EBUSY;
1505 goto out;
1506 }
1507 } else {
1508 if (com->active_out) {
1509 if (flag & O_NONBLOCK) {
1510 error = EBUSY;
1511 goto out;
1512 }
1513 error = tsleep(&com->active_out,
1514 TTIPRI | PCATCH, "siobi", 0);
1515 if (com_addr(unit) == NULL)
1516 return (ENXIO);
1517 if (error != 0 || com->gone)
1518 goto out;
1519 goto open_top;
1520 }
1521 }
dadab5e9 1522 if (tp->t_state & TS_XCLUDE && suser(td)) {
984263bc
MD
1523 error = EBUSY;
1524 goto out;
1525 }
1526 } else {
1527 /*
1528 * The device isn't open, so there are no conflicts.
1529 * Initialize it. Initialization is done twice in many
1530 * cases: to preempt sleeping callin opens if we are
1531 * callout, and to complete a callin open after DCD rises.
1532 */
1533 tp->t_oproc = comstart;
1534 tp->t_param = comparam;
1535 tp->t_stop = comstop;
1536 tp->t_dev = dev;
1537 tp->t_termios = mynor & CALLOUT_MASK
1538 ? com->it_out : com->it_in;
1539 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1540 com->poll = com->no_irq;
1541 com->poll_output = com->loses_outints;
1542 ++com->wopeners;
1543 error = comparam(tp, &tp->t_termios);
1544 --com->wopeners;
1545 if (error != 0)
1546 goto out;
1547 /*
1548 * XXX we should goto open_top if comparam() slept.
1549 */
1550 if (com->hasfifo) {
1551 /*
1552 * (Re)enable and drain fifos.
1553 *
1554 * Certain SMC chips cause problems if the fifos
1555 * are enabled while input is ready. Turn off the
1556 * fifo if necessary to clear the input. We test
1557 * the input ready bit after enabling the fifos
1558 * since we've already enabled them in comparam()
1559 * and to handle races between enabling and fresh
1560 * input.
1561 */
1562 while (TRUE) {
1563 sio_setreg(com, com_fifo,
1564 FIFO_RCV_RST | FIFO_XMT_RST
1565 | com->fifo_image);
1566 /*
1567 * XXX the delays are for superstitious
1568 * historical reasons. It must be less than
1569 * the character time at the maximum
1570 * supported speed (87 usec at 115200 bps
1571 * 8N1). Otherwise we might loop endlessly
1572 * if data is streaming in. We used to use
1573 * delays of 100. That usually worked
1574 * because DELAY(100) used to usually delay
1575 * for about 85 usec instead of 100.
1576 */
1577 DELAY(50);
1578 if (!(inb(com->line_status_port) & LSR_RXRDY))
1579 break;
1580 sio_setreg(com, com_fifo, 0);
1581 DELAY(50);
1582 (void) inb(com->data_port);
1583 }
1584 }
1585
1586 disable_intr();
1587 (void) inb(com->line_status_port);
1588 (void) inb(com->data_port);
1589 com->prev_modem_status = com->last_modem_status
1590 = inb(com->modem_status_port);
1591 if (COM_IIR_TXRDYBUG(com->flags)) {
1592 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1593 | IER_EMSC);
1594 } else {
1595 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1596 | IER_ERLS | IER_EMSC);
1597 }
1598 enable_intr();
1599 /*
1600 * Handle initial DCD. Callout devices get a fake initial
1601 * DCD (trapdoor DCD). If we are callout, then any sleeping
1602 * callin opens get woken up and resume sleeping on "siobi"
1603 * instead of "siodcd".
1604 */
1605 /*
1606 * XXX `mynor & CALLOUT_MASK' should be
1607 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1608 * TRAPDOOR_CARRIER is the default initial state for callout
1609 * devices and SOFT_CARRIER is like CLOCAL except it hides
1610 * the true carrier.
1611 */
1612 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1613 (*linesw[tp->t_line].l_modem)(tp, 1);
1614 }
1615 /*
1616 * Wait for DCD if necessary.
1617 */
1618 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1619 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1620 ++com->wopeners;
1621 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1622 if (com_addr(unit) == NULL)
1623 return (ENXIO);
1624 --com->wopeners;
1625 if (error != 0 || com->gone)
1626 goto out;
1627 goto open_top;
1628 }
1629 error = (*linesw[tp->t_line].l_open)(dev, tp);
1630 disc_optim(tp, &tp->t_termios, com);
1631 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1632 com->active_out = TRUE;
1633 siosettimeout();
1634out:
1635 splx(s);
1636 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1637 comhardclose(com);
1638 return (error);
1639}
1640
1641static int
41c20dac 1642sioclose(dev_t dev, int flag, int mode, struct thread *td)
984263bc
MD
1643{
1644 struct com_s *com;
1645 int mynor;
1646 int s;
1647 struct tty *tp;
1648
1649 mynor = minor(dev);
1650 if (mynor & CONTROL_MASK)
1651 return (0);
1652 com = com_addr(MINOR_TO_UNIT(mynor));
1653 if (com == NULL)
1654 return (ENODEV);
1655 tp = com->tp;
1656 s = spltty();
1657 (*linesw[tp->t_line].l_close)(tp, flag);
1658 disc_optim(tp, &tp->t_termios, com);
1659 comstop(tp, FREAD | FWRITE);
1660 comhardclose(com);
1661 ttyclose(tp);
1662 siosettimeout();
1663 splx(s);
1664 if (com->gone) {
1665 printf("sio%d: gone\n", com->unit);
1666 s = spltty();
1667 if (com->ibuf != NULL)
1668 free(com->ibuf, M_DEVBUF);
1669 bzero(tp, sizeof *tp);
1670 splx(s);
1671 }
1672 return (0);
1673}
1674
1675static void
1676comhardclose(com)
1677 struct com_s *com;
1678{
1679 int s;
1680 struct tty *tp;
1681 int unit;
1682
1683 unit = com->unit;
1684 s = spltty();
1685 com->poll = FALSE;
1686 com->poll_output = FALSE;
1687 com->do_timestamp = FALSE;
1688 com->do_dcd_timestamp = FALSE;
1689 com->pps.ppsparam.mode = 0;
1690 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1691 tp = com->tp;
1692
1693#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1694 defined(ALT_BREAK_TO_DEBUGGER))
1695 /*
1696 * Leave interrupts enabled and don't clear DTR if this is the
1697 * console. This allows us to detect break-to-debugger events
1698 * while the console device is closed.
1699 */
1700 if (com->unit != comconsole)
1701#endif
1702 {
1703 sio_setreg(com, com_ier, 0);
1704 if (tp->t_cflag & HUPCL
1705 /*
1706 * XXX we will miss any carrier drop between here and the
1707 * next open. Perhaps we should watch DCD even when the
1708 * port is closed; it is not sufficient to check it at
1709 * the next open because it might go up and down while
1710 * we're not watching.
1711 */
1712 || (!com->active_out
1713 && !(com->prev_modem_status & MSR_DCD)
1714 && !(com->it_in.c_cflag & CLOCAL))
1715 || !(tp->t_state & TS_ISOPEN)) {
1716 (void)commctl(com, TIOCM_DTR, DMBIC);
1717 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1718 timeout(siodtrwakeup, com, com->dtr_wait);
1719 com->state |= CS_DTR_OFF;
1720 }
1721 }
1722 }
1723 if (com->hasfifo) {
1724 /*
1725 * Disable fifos so that they are off after controlled
1726 * reboots. Some BIOSes fail to detect 16550s when the
1727 * fifos are enabled.
1728 */
1729 sio_setreg(com, com_fifo, 0);
1730 }
1731 com->active_out = FALSE;
1732 wakeup(&com->active_out);
1733 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1734 splx(s);
1735}
1736
1737static int
1738sioread(dev, uio, flag)
1739 dev_t dev;
1740 struct uio *uio;
1741 int flag;
1742{
1743 int mynor;
1744 struct com_s *com;
1745
1746 mynor = minor(dev);
1747 if (mynor & CONTROL_MASK)
1748 return (ENODEV);
1749 com = com_addr(MINOR_TO_UNIT(mynor));
1750 if (com == NULL || com->gone)
1751 return (ENODEV);
1752 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1753}
1754
1755static int
1756siowrite(dev, uio, flag)
1757 dev_t dev;
1758 struct uio *uio;
1759 int flag;
1760{
1761 int mynor;
1762 struct com_s *com;
1763 int unit;
1764
1765 mynor = minor(dev);
1766 if (mynor & CONTROL_MASK)
1767 return (ENODEV);
1768
1769 unit = MINOR_TO_UNIT(mynor);
1770 com = com_addr(unit);
1771 if (com == NULL || com->gone)
1772 return (ENODEV);
1773 /*
1774 * (XXX) We disallow virtual consoles if the physical console is
1775 * a serial port. This is in case there is a display attached that
1776 * is not the console. In that situation we don't need/want the X
1777 * server taking over the console.
1778 */
1779 if (constty != NULL && unit == comconsole)
1780 constty = NULL;
1781 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1782}
1783
1784static void
1785siobusycheck(chan)
1786 void *chan;
1787{
1788 struct com_s *com;
1789 int s;
1790
1791 com = (struct com_s *)chan;
1792
1793 /*
1794 * Clear TS_BUSY if low-level output is complete.
1795 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1796 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1797 * called again. Reading the line status port outside of siointr1()
1798 * is safe because CS_BUSY is clear so there are no output interrupts
1799 * to lose.
1800 */
1801 s = spltty();
1802 if (com->state & CS_BUSY)
1803 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1804 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1805 == (LSR_TSRE | LSR_TXRDY)) {
1806 com->tp->t_state &= ~TS_BUSY;
1807 ttwwakeup(com->tp);
1808 com->extra_state &= ~CSE_BUSYCHECK;
1809 } else
1810 timeout(siobusycheck, com, hz / 100);
1811 splx(s);
1812}
1813
1814static u_int
1815siodivisor(rclk, speed)
1816 u_long rclk;
1817 speed_t speed;
1818{
1819 long actual_speed;
1820 u_int divisor;
1821 int error;
1822
1823 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1824 return (0);
1825 divisor = (rclk / (8UL * speed) + 1) / 2;
1826 if (divisor == 0 || divisor >= 65536)
1827 return (0);
1828 actual_speed = rclk / (16UL * divisor);
1829
1830 /* 10 times error in percent: */
1831 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1832
1833 /* 3.0% maximum error tolerance: */
1834 if (error < -30 || error > 30)
1835 return (0);
1836
1837 return (divisor);
1838}
1839
1840static void
1841siodtrwakeup(chan)
1842 void *chan;
1843{
1844 struct com_s *com;
1845
1846 com = (struct com_s *)chan;
1847 com->state &= ~CS_DTR_OFF;
1848 wakeup(&com->dtr_wait);
1849}
1850
1851static void
1852sioinput(com)
1853 struct com_s *com;
1854{
1855 u_char *buf;
1856 int incc;
1857 u_char line_status;
1858 int recv_data;
1859 struct tty *tp;
1860
1861 buf = com->ibuf;
1862 tp = com->tp;
1863 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1864 com_events -= (com->iptr - com->ibuf);
1865 com->iptr = com->ibuf;
1866 return;
1867 }
1868 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1869 /*
1870 * Avoid the grotesquely inefficient lineswitch routine
1871 * (ttyinput) in "raw" mode. It usually takes about 450
1872 * instructions (that's without canonical processing or echo!).
1873 * slinput is reasonably fast (usually 40 instructions plus
1874 * call overhead).
1875 */
1876 do {
1877 enable_intr();
1878 incc = com->iptr - buf;
1879 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1880 && (com->state & CS_RTS_IFLOW
1881 || tp->t_iflag & IXOFF)
1882 && !(tp->t_state & TS_TBLOCK))
1883 ttyblock(tp);
1884 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1885 += b_to_q((char *)buf, incc, &tp->t_rawq);
1886 buf += incc;
1887 tk_nin += incc;
1888 tk_rawcc += incc;
1889 tp->t_rawcc += incc;
1890 ttwakeup(tp);
1891 if (tp->t_state & TS_TTSTOP
1892 && (tp->t_iflag & IXANY
1893 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1894 tp->t_state &= ~TS_TTSTOP;
1895 tp->t_lflag &= ~FLUSHO;
1896 comstart(tp);
1897 }
1898 disable_intr();
1899 } while (buf < com->iptr);
1900 } else {
1901 do {
1902 enable_intr();
1903 line_status = buf[com->ierroff];
1904 recv_data = *buf++;
1905 if (line_status
1906 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1907 if (line_status & LSR_BI)
1908 recv_data |= TTY_BI;
1909 if (line_status & LSR_FE)
1910 recv_data |= TTY_FE;
1911 if (line_status & LSR_OE)
1912 recv_data |= TTY_OE;
1913 if (line_status & LSR_PE)
1914 recv_data |= TTY_PE;
1915 }
1916 (*linesw[tp->t_line].l_rint)(recv_data, tp);
1917 disable_intr();
1918 } while (buf < com->iptr);
1919 }
1920 com_events -= (com->iptr - com->ibuf);
1921 com->iptr = com->ibuf;
1922
1923 /*
1924 * There is now room for another low-level buffer full of input,
1925 * so enable RTS if it is now disabled and there is room in the
1926 * high-level buffer.
1927 */
1928 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1929 !(tp->t_state & TS_TBLOCK))
1930 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1931}
1932
1933void
1934siointr(arg)
1935 void *arg;
1936{
1937#ifndef COM_MULTIPORT
1938 COM_LOCK();
1939 siointr1((struct com_s *) arg);
1940 COM_UNLOCK();
1941#else /* COM_MULTIPORT */
1942 bool_t possibly_more_intrs;
1943 int unit;
1944 struct com_s *com;
1945
1946 /*
1947 * Loop until there is no activity on any port. This is necessary
1948 * to get an interrupt edge more than to avoid another interrupt.
1949 * If the IRQ signal is just an OR of the IRQ signals from several
1950 * devices, then the edge from one may be lost because another is
1951 * on.
1952 */
1953 COM_LOCK();
1954 do {
1955 possibly_more_intrs = FALSE;
1956 for (unit = 0; unit < sio_numunits; ++unit) {
1957 com = com_addr(unit);
1958 /*
1959 * XXX COM_LOCK();
1960 * would it work here, or be counter-productive?
1961 */
1962 if (com != NULL
1963 && !com->gone
1964 && (inb(com->int_id_port) & IIR_IMASK)
1965 != IIR_NOPEND) {
1966 siointr1(com);
1967 possibly_more_intrs = TRUE;
1968 }
1969 /* XXX COM_UNLOCK(); */
1970 }
1971 } while (possibly_more_intrs);
1972 COM_UNLOCK();
1973#endif /* COM_MULTIPORT */
1974}
1975
1976static void
1977siointr1(com)
1978 struct com_s *com;
1979{
1980 u_char line_status;
1981 u_char modem_status;
1982 u_char *ioptr;
1983 u_char recv_data;
1984 u_char int_ctl;
1985 u_char int_ctl_new;
1986 struct timecounter *tc;
1987 u_int count;
1988
1989 int_ctl = inb(com->intr_ctl_port);
1990 int_ctl_new = int_ctl;
1991
1992 while (!com->gone) {
1993 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1994 modem_status = inb(com->modem_status_port);
1995 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
1996 tc = timecounter;
1997 count = tc->tc_get_timecount(tc);
1998 pps_event(&com->pps, tc, count,
1999 (modem_status & MSR_DCD) ?
2000 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2001 }
2002 }
2003 line_status = inb(com->line_status_port);
2004
2005 /* input event? (check first to help avoid overruns) */
2006 while (line_status & LSR_RCV_MASK) {
2007 /* break/unnattached error bits or real input? */
2008 if (!(line_status & LSR_RXRDY))
2009 recv_data = 0;
2010 else
2011 recv_data = inb(com->data_port);
2012#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
2013 /*
2014 * Solaris implements a new BREAK which is initiated
2015 * by a character sequence CR ~ ^b which is similar
2016 * to a familiar pattern used on Sun servers by the
2017 * Remote Console.
2018 */
2019#define KEY_CRTLB 2 /* ^B */
2020#define KEY_CR 13 /* CR '\r' */
2021#define KEY_TILDE 126 /* ~ */
2022
2023 if (com->unit == comconsole) {
2024 static int brk_state1 = 0, brk_state2 = 0;
2025 if (recv_data == KEY_CR) {
2026 brk_state1 = recv_data;
2027 brk_state2 = 0;
2028 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) {
2029 if (recv_data == KEY_TILDE)
2030 brk_state2 = recv_data;
2031 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) {
2032 breakpoint();
2033 brk_state1 = brk_state2 = 0;
2034 goto cont;
2035 } else
2036 brk_state2 = 0;
2037 } else
2038 brk_state1 = 0;
2039 }
2040#endif
2041 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2042 /*
2043 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2044 * Otherwise, push the work to a higher level
2045 * (to handle PARMRK) if we're bypassing.
2046 * Otherwise, convert BI/FE and PE+INPCK to 0.
2047 *
2048 * This makes bypassing work right in the
2049 * usual "raw" case (IGNBRK set, and IGNPAR
2050 * and INPCK clear).
2051 *
2052 * Note: BI together with FE/PE means just BI.
2053 */
2054 if (line_status & LSR_BI) {
2055#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2056 if (com->unit == comconsole) {
2057 breakpoint();
2058 goto cont;
2059 }
2060#endif
2061 if (com->tp == NULL
2062 || com->tp->t_iflag & IGNBRK)
2063 goto cont;
2064 } else {
2065 if (com->tp == NULL
2066 || com->tp->t_iflag & IGNPAR)
2067 goto cont;
2068 }
2069 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2070 && (line_status & (LSR_BI | LSR_FE)
2071 || com->tp->t_iflag & INPCK))
2072 recv_data = 0;
2073 }
2074 ++com->bytes_in;
2075 if (com->hotchar != 0 && recv_data == com->hotchar)
2076 setsofttty();
2077 ioptr = com->iptr;
2078 if (ioptr >= com->ibufend)
2079 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2080 else {
2081 if (com->do_timestamp)
2082 microtime(&com->timestamp);
2083 ++com_events;
2084 schedsofttty();
2085#if 0 /* for testing input latency vs efficiency */
2086if (com->iptr - com->ibuf == 8)
2087 setsofttty();
2088#endif
2089 ioptr[0] = recv_data;
2090 ioptr[com->ierroff] = line_status;
2091 com->iptr = ++ioptr;
2092 if (ioptr == com->ihighwater
2093 && com->state & CS_RTS_IFLOW)
2094 outb(com->modem_ctl_port,
2095 com->mcr_image &= ~MCR_RTS);
2096 if (line_status & LSR_OE)
2097 CE_RECORD(com, CE_OVERRUN);
2098 }
2099cont:
2100 /*
2101 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2102 * jump from the top of the loop to here
2103 */
2104 line_status = inb(com->line_status_port) & 0x7F;
2105 }
2106
2107 /* modem status change? (always check before doing output) */
2108 modem_status = inb(com->modem_status_port);
2109 if (modem_status != com->last_modem_status) {
2110 if (com->do_dcd_timestamp
2111 && !(com->last_modem_status & MSR_DCD)
2112 && modem_status & MSR_DCD)
2113 microtime(&com->dcd_timestamp);
2114
2115 /*
2116 * Schedule high level to handle DCD changes. Note
2117 * that we don't use the delta bits anywhere. Some
2118 * UARTs mess them up, and it's easy to remember the
2119 * previous bits and calculate the delta.
2120 */
2121 com->last_modem_status = modem_status;
2122 if (!(com->state & CS_CHECKMSR)) {
2123 com_events += LOTS_OF_EVENTS;
2124 com->state |= CS_CHECKMSR;
2125 setsofttty();
2126 }
2127
2128 /* handle CTS change immediately for crisp flow ctl */
2129 if (com->state & CS_CTS_OFLOW) {
2130 if (modem_status & MSR_CTS)
2131 com->state |= CS_ODEVREADY;
2132 else
2133 com->state &= ~CS_ODEVREADY;
2134 }
2135 }
2136
2137 /* output queued and everything ready? */
2138 if (line_status & LSR_TXRDY
2139 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2140 ioptr = com->obufq.l_head;
2141 if (com->tx_fifo_size > 1) {
2142 u_int ocount;
2143
2144 ocount = com->obufq.l_tail - ioptr;
2145 if (ocount > com->tx_fifo_size)
2146 ocount = com->tx_fifo_size;
2147 com->bytes_out += ocount;
2148 do
2149 outb(com->data_port, *ioptr++);
2150 while (--ocount != 0);
2151 } else {
2152 outb(com->data_port, *ioptr++);
2153 ++com->bytes_out;
2154 }
2155 com->obufq.l_head = ioptr;
2156 if (COM_IIR_TXRDYBUG(com->flags)) {
2157 int_ctl_new = int_ctl | IER_ETXRDY;
2158 }
2159 if (ioptr >= com->obufq.l_tail) {
2160 struct lbq *qp;
2161
2162 qp = com->obufq.l_next;
2163 qp->l_queued = FALSE;
2164 qp = qp->l_next;
2165 if (qp != NULL) {
2166 com->obufq.l_head = qp->l_head;
2167 com->obufq.l_tail = qp->l_tail;
2168 com->obufq.l_next = qp;
2169 } else {
2170 /* output just completed */
2171 if (COM_IIR_TXRDYBUG(com->flags)) {
2172 int_ctl_new = int_ctl & ~IER_ETXRDY;
2173 }
2174 com->state &= ~CS_BUSY;
2175 }
2176 if (!(com->state & CS_ODONE)) {
2177 com_events += LOTS_OF_EVENTS;
2178 com->state |= CS_ODONE;
2179 setsofttty(); /* handle at high level ASAP */
2180 }
2181 }
2182 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2183 outb(com->intr_ctl_port, int_ctl_new);
2184 }
2185 }
2186
2187 /* finished? */
2188#ifndef COM_MULTIPORT
2189 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2190#endif /* COM_MULTIPORT */
2191 return;
2192 }
2193}
2194
2195static int
41c20dac 2196sioioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc
MD
2197{
2198 struct com_s *com;
2199 int error;
2200 int mynor;
2201 int s;
2202 struct tty *tp;
2203#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2204 u_long oldcmd;
2205 struct termios term;
2206#endif
2207
2208 mynor = minor(dev);
2209 com = com_addr(MINOR_TO_UNIT(mynor));
2210 if (com == NULL || com->gone)
2211 return (ENODEV);
2212 if (mynor & CONTROL_MASK) {
2213 struct termios *ct;
2214
2215 switch (mynor & CONTROL_MASK) {
2216 case CONTROL_INIT_STATE:
2217 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2218 break;
2219 case CONTROL_LOCK_STATE:
2220 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2221 break;
2222 default:
2223 return (ENODEV); /* /dev/nodev */
2224 }
2225 switch (cmd) {
2226 case TIOCSETA:
dadab5e9 2227 error = suser(td);
984263bc
MD
2228 if (error != 0)
2229 return (error);
2230 *ct = *(struct termios *)data;
2231 return (0);
2232 case TIOCGETA:
2233 *(struct termios *)data = *ct;
2234 return (0);
2235 case TIOCGETD:
2236 *(int *)data = TTYDISC;
2237 return (0);
2238 case TIOCGWINSZ:
2239 bzero(data, sizeof(struct winsize));
2240 return (0);
2241 default:
2242 return (ENOTTY);
2243 }
2244 }
2245 tp = com->tp;
2246#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2247 term = tp->t_termios;
2248 oldcmd = cmd;
2249 error = ttsetcompat(tp, &cmd, data, &term);
2250 if (error != 0)
2251 return (error);
2252 if (cmd != oldcmd)
2253 data = (caddr_t)&term;
2254#endif
2255 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2256 int cc;
2257 struct termios *dt = (struct termios *)data;
2258 struct termios *lt = mynor & CALLOUT_MASK
2259 ? &com->lt_out : &com->lt_in;
2260
2261 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2262 | (dt->c_iflag & ~lt->c_iflag);
2263 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2264 | (dt->c_oflag & ~lt->c_oflag);
2265 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2266 | (dt->c_cflag & ~lt->c_cflag);
2267 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2268 | (dt->c_lflag & ~lt->c_lflag);
2269 for (cc = 0; cc < NCCS; ++cc)
2270 if (lt->c_cc[cc] != 0)
2271 dt->c_cc[cc] = tp->t_cc[cc];
2272 if (lt->c_ispeed != 0)
2273 dt->c_ispeed = tp->t_ispeed;
2274 if (lt->c_ospeed != 0)
2275 dt->c_ospeed = tp->t_ospeed;
2276 }
41c20dac 2277 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
984263bc
MD
2278 if (error != ENOIOCTL)
2279 return (error);
2280 s = spltty();
2281 error = ttioctl(tp, cmd, data, flag);
2282 disc_optim(tp, &tp->t_termios, com);
2283 if (error != ENOIOCTL) {
2284 splx(s);
2285 return (error);
2286 }
2287 switch (cmd) {
2288 case TIOCSBRK:
2289 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2290 break;
2291 case TIOCCBRK:
2292 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2293 break;
2294 case TIOCSDTR:
2295 (void)commctl(com, TIOCM_DTR, DMBIS);
2296 break;
2297 case TIOCCDTR:
2298 (void)commctl(com, TIOCM_DTR, DMBIC);
2299 break;
2300 /*
2301 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2302 * changes get undone on the next call to comparam().
2303 */
2304 case TIOCMSET:
2305 (void)commctl(com, *(int *)data, DMSET);
2306 break;
2307 case TIOCMBIS:
2308 (void)commctl(com, *(int *)data, DMBIS);
2309 break;
2310 case TIOCMBIC:
2311 (void)commctl(com, *(int *)data, DMBIC);
2312 break;
2313 case TIOCMGET:
2314 *(int *)data = commctl(com, 0, DMGET);
2315 break;
2316 case TIOCMSDTRWAIT:
2317 /* must be root since the wait applies to following logins */
dadab5e9 2318 error = suser(td);
984263bc
MD
2319 if (error != 0) {
2320 splx(s);
2321 return (error);
2322 }
2323 com->dtr_wait = *(int *)data * hz / 100;
2324 break;
2325 case TIOCMGDTRWAIT:
2326 *(int *)data = com->dtr_wait * 100 / hz;
2327 break;
2328 case TIOCTIMESTAMP:
2329 com->do_timestamp = TRUE;
2330 *(struct timeval *)data = com->timestamp;
2331 break;
2332 case TIOCDCDTIMESTAMP:
2333 com->do_dcd_timestamp = TRUE;
2334 *(struct timeval *)data = com->dcd_timestamp;
2335 break;
2336 default:
2337 splx(s);
2338 error = pps_ioctl(cmd, data, &com->pps);
2339 if (error == ENODEV)
2340 error = ENOTTY;
2341 return (error);
2342 }
2343 splx(s);
2344 return (0);
2345}
2346
2347static void
2348siopoll()
2349{
2350 int unit;
2351
2352 if (com_events == 0)
2353 return;
2354repeat:
2355 for (unit = 0; unit < sio_numunits; ++unit) {
2356 struct com_s *com;
2357 int incc;
2358 struct tty *tp;
2359
2360 com = com_addr(unit);
2361 if (com == NULL)
2362 continue;
2363 tp = com->tp;
2364 if (tp == NULL || com->gone) {
2365 /*
2366 * Discard any events related to never-opened or
2367 * going-away devices.
2368 */
2369 disable_intr();
2370 incc = com->iptr - com->ibuf;
2371 com->iptr = com->ibuf;
2372 if (com->state & CS_CHECKMSR) {
2373 incc += LOTS_OF_EVENTS;
2374 com->state &= ~CS_CHECKMSR;
2375 }
2376 com_events -= incc;
2377 enable_intr();
2378 continue;
2379 }
2380 if (com->iptr != com->ibuf) {
2381 disable_intr();
2382 sioinput(com);
2383 enable_intr();
2384 }
2385 if (com->state & CS_CHECKMSR) {
2386 u_char delta_modem_status;
2387
2388 disable_intr();
2389 delta_modem_status = com->last_modem_status
2390 ^ com->prev_modem_status;
2391 com->prev_modem_status = com->last_modem_status;
2392 com_events -= LOTS_OF_EVENTS;
2393 com->state &= ~CS_CHECKMSR;
2394 enable_intr();
2395 if (delta_modem_status & MSR_DCD)
2396 (*linesw[tp->t_line].l_modem)
2397 (tp, com->prev_modem_status & MSR_DCD);
2398 }
2399 if (com->state & CS_ODONE) {
2400 disable_intr();
2401 com_events -= LOTS_OF_EVENTS;
2402 com->state &= ~CS_ODONE;
2403 enable_intr();
2404 if (!(com->state & CS_BUSY)
2405 && !(com->extra_state & CSE_BUSYCHECK)) {
2406 timeout(siobusycheck, com, hz / 100);
2407 com->extra_state |= CSE_BUSYCHECK;
2408 }
2409 (*linesw[tp->t_line].l_start)(tp);
2410 }
2411 if (com_events == 0)
2412 break;
2413 }
2414 if (com_events >= LOTS_OF_EVENTS)
2415 goto repeat;
2416}
2417
2418static int
2419comparam(tp, t)
2420 struct tty *tp;
2421 struct termios *t;
2422{
2423 u_int cfcr;
2424 int cflag;
2425 struct com_s *com;
2426 u_int divisor;
2427 u_char dlbh;
2428 u_char dlbl;
2429 int s;
2430 int unit;
2431
2432 unit = DEV_TO_UNIT(tp->t_dev);
2433 com = com_addr(unit);
2434 if (com == NULL)
2435 return (ENODEV);
2436
2437 /* do historical conversions */
2438 if (t->c_ispeed == 0)
2439 t->c_ispeed = t->c_ospeed;
2440
2441 /* check requested parameters */
2442 if (t->c_ospeed == 0)
2443 divisor = 0;
2444 else {
2445 if (t->c_ispeed != t->c_ospeed)
2446 return (EINVAL);
2447 divisor = siodivisor(com->rclk, t->c_ispeed);
2448 if (divisor == 0)
2449 return (EINVAL);
2450 }
2451
2452 /* parameters are OK, convert them to the com struct and the device */
2453 s = spltty();
2454 if (divisor == 0)
2455 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2456 else
2457 (void)commctl(com, TIOCM_DTR, DMBIS);
2458 cflag = t->c_cflag;
2459 switch (cflag & CSIZE) {
2460 case CS5:
2461 cfcr = CFCR_5BITS;
2462 break;
2463 case CS6:
2464 cfcr = CFCR_6BITS;
2465 break;
2466 case CS7:
2467 cfcr = CFCR_7BITS;
2468 break;
2469 default:
2470 cfcr = CFCR_8BITS;
2471 break;
2472 }
2473 if (cflag & PARENB) {
2474 cfcr |= CFCR_PENAB;
2475 if (!(cflag & PARODD))
2476 cfcr |= CFCR_PEVEN;
2477 }
2478 if (cflag & CSTOPB)
2479 cfcr |= CFCR_STOPB;
2480
2481 if (com->hasfifo && divisor != 0) {
2482 /*
2483 * Use a fifo trigger level low enough so that the input
2484 * latency from the fifo is less than about 16 msec and
2485 * the total latency is less than about 30 msec. These
2486 * latencies are reasonable for humans. Serial comms
2487 * protocols shouldn't expect anything better since modem
2488 * latencies are larger.
2489 *
2490 * Interrupts can be held up for long periods of time
2491 * due to inefficiencies in other parts of the kernel,
2492 * certain video cards, etc. Setting the FIFO trigger
2493 * point to MEDH instead of HIGH gives us 694uS of slop
2494 * (8 character times) instead of 173uS (2 character times)
2495 * @ 115200 bps.
2496 */
2497 com->fifo_image = t->c_ospeed <= 4800
2498 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2499#ifdef COM_ESP
2500 /*
2501 * The Hayes ESP card needs the fifo DMA mode bit set
2502 * in compatibility mode. If not, it will interrupt
2503 * for each character received.
2504 */
2505 if (com->esp)
2506 com->fifo_image |= FIFO_DMA_MODE;
2507#endif
2508 sio_setreg(com, com_fifo, com->fifo_image);
2509 }
2510
2511 /*
2512 * This returns with interrupts disabled so that we can complete
2513 * the speed change atomically. Keeping interrupts disabled is
2514 * especially important while com_data is hidden.
2515 */
2516 (void) siosetwater(com, t->c_ispeed);
2517
2518 if (divisor != 0) {
2519 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2520 /*
2521 * Only set the divisor registers if they would change,
2522 * since on some 16550 incompatibles (UMC8669F), setting
2523 * them while input is arriving them loses sync until
2524 * data stops arriving.
2525 */
2526 dlbl = divisor & 0xFF;
2527 if (sio_getreg(com, com_dlbl) != dlbl)
2528 sio_setreg(com, com_dlbl, dlbl);
2529 dlbh = divisor >> 8;
2530 if (sio_getreg(com, com_dlbh) != dlbh)
2531 sio_setreg(com, com_dlbh, dlbh);
2532 }
2533
2534 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2535
2536 if (!(tp->t_state & TS_TTSTOP))
2537 com->state |= CS_TTGO;
2538
2539 if (cflag & CRTS_IFLOW) {
2540 if (com->st16650a) {
2541 sio_setreg(com, com_cfcr, 0xbf);
2542 sio_setreg(com, com_fifo,
2543 sio_getreg(com, com_fifo) | 0x40);
2544 }
2545 com->state |= CS_RTS_IFLOW;
2546 /*
2547 * If CS_RTS_IFLOW just changed from off to on, the change
2548 * needs to be propagated to MCR_RTS. This isn't urgent,
2549 * so do it later by calling comstart() instead of repeating
2550 * a lot of code from comstart() here.
2551 */
2552 } else if (com->state & CS_RTS_IFLOW) {
2553 com->state &= ~CS_RTS_IFLOW;
2554 /*
2555 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2556 * on here, since comstart() won't do it later.
2557 */
2558 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2559 if (com->st16650a) {
2560 sio_setreg(com, com_cfcr, 0xbf);
2561 sio_setreg(com, com_fifo,
2562 sio_getreg(com, com_fifo) & ~0x40);
2563 }
2564 }
2565
2566
2567 /*
2568 * Set up state to handle output flow control.
2569 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2570 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2571 */
2572 com->state |= CS_ODEVREADY;
2573 com->state &= ~CS_CTS_OFLOW;
2574 if (cflag & CCTS_OFLOW) {
2575 com->state |= CS_CTS_OFLOW;
2576 if (!(com->last_modem_status & MSR_CTS))
2577 com->state &= ~CS_ODEVREADY;
2578 if (com->st16650a) {
2579 sio_setreg(com, com_cfcr, 0xbf);
2580 sio_setreg(com, com_fifo,
2581 sio_getreg(com, com_fifo) | 0x80);
2582 }
2583 } else {
2584 if (com->st16650a) {
2585 sio_setreg(com, com_cfcr, 0xbf);
2586 sio_setreg(com, com_fifo,
2587 sio_getreg(com, com_fifo) & ~0x80);
2588 }
2589 }
2590
2591 sio_setreg(com, com_cfcr, com->cfcr_image);
2592
2593 /* XXX shouldn't call functions while intrs are disabled. */
2594 disc_optim(tp, t, com);
2595 /*
2596 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2597 * unconditionally, but that defeated the careful discarding of
2598 * stale input in sioopen().
2599 */
2600 if (com->state >= (CS_BUSY | CS_TTGO))
2601 siointr1(com);
2602
2603 enable_intr();
2604 splx(s);
2605 comstart(tp);
2606 if (com->ibufold != NULL) {
2607 free(com->ibufold, M_DEVBUF);
2608 com->ibufold = NULL;
2609 }
2610 return (0);
2611}
2612
2613static int
2614siosetwater(com, speed)
2615 struct com_s *com;
2616 speed_t speed;
2617{
2618 int cp4ticks;
2619 u_char *ibuf;
2620 int ibufsize;
2621 struct tty *tp;
2622
2623 /*
2624 * Make the buffer size large enough to handle a softtty interrupt
2625 * latency of about 2 ticks without loss of throughput or data
2626 * (about 3 ticks if input flow control is not used or not honoured,
2627 * but a bit less for CS5-CS7 modes).
2628 */
2629 cp4ticks = speed / 10 / hz * 4;
2630 for (ibufsize = 128; ibufsize < cp4ticks;)
2631 ibufsize <<= 1;
2632 if (ibufsize == com->ibufsize) {
2633 disable_intr();
2634 return (0);
2635 }
2636
2637 /*
2638 * Allocate input buffer. The extra factor of 2 in the size is
2639 * to allow for an error byte for each input byte.
2640 */
2641 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2642 if (ibuf == NULL) {
2643 disable_intr();
2644 return (ENOMEM);
2645 }
2646
2647 /* Initialize non-critical variables. */
2648 com->ibufold = com->ibuf;
2649 com->ibufsize = ibufsize;
2650 tp = com->tp;
2651 if (tp != NULL) {
2652 tp->t_ififosize = 2 * ibufsize;
2653 tp->t_ispeedwat = (speed_t)-1;
2654 tp->t_ospeedwat = (speed_t)-1;
2655 }
2656
2657 /*
2658 * Read current input buffer, if any. Continue with interrupts
2659 * disabled.
2660 */
2661 disable_intr();
2662 if (com->iptr != com->ibuf)
2663 sioinput(com);
2664
2665 /*-
2666 * Initialize critical variables, including input buffer watermarks.
2667 * The external device is asked to stop sending when the buffer
2668 * exactly reaches high water, or when the high level requests it.
2669 * The high level is notified immediately (rather than at a later
2670 * clock tick) when this watermark is reached.
2671 * The buffer size is chosen so the watermark should almost never
2672 * be reached.
2673 * The low watermark is invisibly 0 since the buffer is always
2674 * emptied all at once.
2675 */
2676 com->iptr = com->ibuf = ibuf;
2677 com->ibufend = ibuf + ibufsize;
2678 com->ierroff = ibufsize;
2679 com->ihighwater = ibuf + 3 * ibufsize / 4;
2680 return (0);
2681}
2682
2683static void
2684comstart(tp)
2685 struct tty *tp;
2686{
2687 struct com_s *com;
2688 int s;
2689 int unit;
2690
2691 unit = DEV_TO_UNIT(tp->t_dev);
2692 com = com_addr(unit);
2693 if (com == NULL)
2694 return;
2695 s = spltty();
2696 disable_intr();
2697 if (tp->t_state & TS_TTSTOP)
2698 com->state &= ~CS_TTGO;
2699 else
2700 com->state |= CS_TTGO;
2701 if (tp->t_state & TS_TBLOCK) {
2702 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2703 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2704 } else {
2705 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2706 && com->state & CS_RTS_IFLOW)
2707 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2708 }
2709 enable_intr();
2710 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2711 ttwwakeup(tp);
2712 splx(s);
2713 return;
2714 }
2715 if (tp->t_outq.c_cc != 0) {
2716 struct lbq *qp;
2717 struct lbq *next;
2718
2719 if (!com->obufs[0].l_queued) {
2720 com->obufs[0].l_tail
2721 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2722 sizeof com->obuf1);
2723 com->obufs[0].l_next = NULL;
2724 com->obufs[0].l_queued = TRUE;
2725 disable_intr();
2726 if (com->state & CS_BUSY) {
2727 qp = com->obufq.l_next;
2728 while ((next = qp->l_next) != NULL)
2729 qp = next;
2730 qp->l_next = &com->obufs[0];
2731 } else {
2732 com->obufq.l_head = com->obufs[0].l_head;
2733 com->obufq.l_tail = com->obufs[0].l_tail;
2734 com->obufq.l_next = &com->obufs[0];
2735 com->state |= CS_BUSY;
2736 }
2737 enable_intr();
2738 }
2739 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2740 com->obufs[1].l_tail
2741 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2742 sizeof com->obuf2);
2743 com->obufs[1].l_next = NULL;
2744 com->obufs[1].l_queued = TRUE;
2745 disable_intr();
2746 if (com->state & CS_BUSY) {
2747 qp = com->obufq.l_next;
2748 while ((next = qp->l_next) != NULL)
2749 qp = next;
2750 qp->l_next = &com->obufs[1];
2751 } else {
2752 com->obufq.l_head = com->obufs[1].l_head;
2753 com->obufq.l_tail = com->obufs[1].l_tail;
2754 com->obufq.l_next = &com->obufs[1];
2755 com->state |= CS_BUSY;
2756 }
2757 enable_intr();
2758 }
2759 tp->t_state |= TS_BUSY;
2760 }
2761 disable_intr();
2762 if (com->state >= (CS_BUSY | CS_TTGO))
2763 siointr1(com); /* fake interrupt to start output */
2764 enable_intr();
2765 ttwwakeup(tp);
2766 splx(s);
2767}
2768
2769static void
2770comstop(tp, rw)
2771 struct tty *tp;
2772 int rw;
2773{
2774 struct com_s *com;
2775
2776 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2777 if (com == NULL || com->gone)
2778 return;
2779 disable_intr();
2780 if (rw & FWRITE) {
2781 if (com->hasfifo)
2782#ifdef COM_ESP
2783 /* XXX avoid h/w bug. */
2784 if (!com->esp)
2785#endif
2786 sio_setreg(com, com_fifo,
2787 FIFO_XMT_RST | com->fifo_image);
2788 com->obufs[0].l_queued = FALSE;
2789 com->obufs[1].l_queued = FALSE;
2790 if (com->state & CS_ODONE)
2791 com_events -= LOTS_OF_EVENTS;
2792 com->state &= ~(CS_ODONE | CS_BUSY);
2793 com->tp->t_state &= ~TS_BUSY;
2794 }
2795 if (rw & FREAD) {
2796 if (com->hasfifo)
2797#ifdef COM_ESP
2798 /* XXX avoid h/w bug. */
2799 if (!com->esp)
2800#endif
2801 sio_setreg(com, com_fifo,
2802 FIFO_RCV_RST | com->fifo_image);
2803 com_events -= (com->iptr - com->ibuf);
2804 com->iptr = com->ibuf;
2805 }
2806 enable_intr();
2807 comstart(tp);
2808}
2809
2810static int
2811commctl(com, bits, how)
2812 struct com_s *com;
2813 int bits;
2814 int how;
2815{
2816 int mcr;
2817 int msr;
2818
2819 if (how == DMGET) {
2820 bits = TIOCM_LE; /* XXX - always enabled while open */
2821 mcr = com->mcr_image;
2822 if (mcr & MCR_DTR)
2823 bits |= TIOCM_DTR;
2824 if (mcr & MCR_RTS)
2825 bits |= TIOCM_RTS;
2826 msr = com->prev_modem_status;
2827 if (msr & MSR_CTS)
2828 bits |= TIOCM_CTS;
2829 if (msr & MSR_DCD)
2830 bits |= TIOCM_CD;
2831 if (msr & MSR_DSR)
2832 bits |= TIOCM_DSR;
2833 /*
2834 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2835 * more volatile by reading the modem status a lot. Perhaps
2836 * we should latch both bits until the status is read here.
2837 */
2838 if (msr & (MSR_RI | MSR_TERI))
2839 bits |= TIOCM_RI;
2840 return (bits);
2841 }
2842 mcr = 0;
2843 if (bits & TIOCM_DTR)
2844 mcr |= MCR_DTR;
2845 if (bits & TIOCM_RTS)
2846 mcr |= MCR_RTS;
2847 if (com->gone)
2848 return(0);
2849 disable_intr();
2850 switch (how) {
2851 case DMSET:
2852 outb(com->modem_ctl_port,
2853 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2854 break;
2855 case DMBIS:
2856 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2857 break;
2858 case DMBIC:
2859 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2860 break;
2861 }
2862 enable_intr();
2863 return (0);
2864}
2865
2866static void
2867siosettimeout()
2868{
2869 struct com_s *com;
2870 bool_t someopen;
2871 int unit;
2872
2873 /*
2874 * Set our timeout period to 1 second if no polled devices are open.
2875 * Otherwise set it to max(1/200, 1/hz).
2876 * Enable timeouts iff some device is open.
2877 */
2878 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2879 sio_timeout = hz;
2880 someopen = FALSE;
2881 for (unit = 0; unit < sio_numunits; ++unit) {
2882 com = com_addr(unit);
2883 if (com != NULL && com->tp != NULL
2884 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2885 someopen = TRUE;
2886 if (com->poll || com->poll_output) {
2887 sio_timeout = hz > 200 ? hz / 200 : 1;
2888 break;
2889 }
2890 }
2891 }
2892 if (someopen) {
2893 sio_timeouts_until_log = hz / sio_timeout;
2894 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2895 sio_timeout);
2896 } else {
2897 /* Flush error messages, if any. */
2898 sio_timeouts_until_log = 1;
2899 comwakeup((void *)NULL);
2900 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2901 }
2902}
2903
2904static void
2905comwakeup(chan)
2906 void *chan;
2907{
2908 struct com_s *com;
2909 int unit;
2910
2911 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2912
2913 /*
2914 * Recover from lost output interrupts.
2915 * Poll any lines that don't use interrupts.
2916 */
2917 for (unit = 0; unit < sio_numunits; ++unit) {
2918 com = com_addr(unit);
2919 if (com != NULL && !com->gone
2920 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2921 disable_intr();
2922 siointr1(com);
2923 enable_intr();
2924 }
2925 }
2926
2927 /*
2928 * Check for and log errors, but not too often.
2929 */
2930 if (--sio_timeouts_until_log > 0)
2931 return;
2932 sio_timeouts_until_log = hz / sio_timeout;
2933 for (unit = 0; unit < sio_numunits; ++unit) {
2934 int errnum;
2935
2936 com = com_addr(unit);
2937 if (com == NULL)
2938 continue;
2939 if (com->gone)
2940 continue;
2941 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2942 u_int delta;
2943 u_long total;
2944
2945 disable_intr();
2946 delta = com->delta_error_counts[errnum];
2947 com->delta_error_counts[errnum] = 0;
2948 enable_intr();
2949 if (delta == 0)
2950 continue;
2951 total = com->error_counts[errnum] += delta;
2952 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2953 unit, delta, error_desc[errnum],
2954 delta == 1 ? "" : "s", total);
2955 }
2956 }
2957}
2958
2959static void
2960disc_optim(tp, t, com)
2961 struct tty *tp;
2962 struct termios *t;
2963 struct com_s *com;
2964{
2965 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2966 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2967 && (!(t->c_iflag & PARMRK)
2968 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2969 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2970 && linesw[tp->t_line].l_rint == ttyinput)
2971 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2972 else
2973 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2974 com->hotchar = linesw[tp->t_line].l_hotchar;
2975}
2976
2977/*
2978 * Following are all routines needed for SIO to act as console
2979 */
2980#include <sys/cons.h>
2981
2982struct siocnstate {
2983 u_char dlbl;
2984 u_char dlbh;
2985 u_char ier;
2986 u_char cfcr;
2987 u_char mcr;
2988};
2989
2990static speed_t siocngetspeed __P((Port_t, u_long rclk));
2991static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
2992static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
2993static void siocntxwait __P((Port_t iobase));
2994
2995static cn_probe_t siocnprobe;
2996static cn_init_t siocninit;
2997static cn_checkc_t siocncheckc;
2998static cn_getc_t siocngetc;
2999static cn_putc_t siocnputc;
3000
3001#ifdef __i386__
3002CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
3003 siocnputc, NULL);
3004#endif
3005
3006/* To get the GDB related variables */
3007#if DDB > 0
3008#include <ddb/ddb.h>
3009#endif
3010
3011static void
3012siocntxwait(iobase)
3013 Port_t iobase;
3014{
3015 int timo;
3016
3017 /*
3018 * Wait for any pending transmission to finish. Required to avoid
3019 * the UART lockup bug when the speed is changed, and for normal
3020 * transmits.
3021 */
3022 timo = 100000;
3023 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3024 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3025 ;
3026}
3027
3028/*
3029 * Read the serial port specified and try to figure out what speed
3030 * it's currently running at. We're assuming the serial port has
3031 * been initialized and is basicly idle. This routine is only intended
3032 * to be run at system startup.
3033 *
3034 * If the value read from the serial port doesn't make sense, return 0.
3035 */
3036
3037static speed_t
3038siocngetspeed(iobase, rclk)
3039 Port_t iobase;
3040 u_long rclk;
3041{
3042 u_int divisor;
3043 u_char dlbh;
3044 u_char dlbl;
3045 u_char cfcr;
3046
3047 cfcr = inb(iobase + com_cfcr);
3048 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3049
3050 dlbl = inb(iobase + com_dlbl);
3051 dlbh = inb(iobase + com_dlbh);
3052
3053 outb(iobase + com_cfcr, cfcr);
3054
3055 divisor = dlbh << 8 | dlbl;
3056
3057 /* XXX there should be more sanity checking. */
3058 if (divisor == 0)
3059 return (CONSPEED);
3060 return (rclk / (16UL * divisor));
3061}
3062
3063static void
3064siocnopen(sp, iobase, speed)
3065 struct siocnstate *sp;
3066 Port_t iobase;
3067 int speed;
3068{
3069 u_int divisor;
3070 u_char dlbh;
3071 u_char dlbl;
3072
3073 /*
3074 * Save all the device control registers except the fifo register
3075 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3076 * We can't save the fifo register since it is read-only.
3077 */
3078 sp->ier = inb(iobase + com_ier);
3079 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3080 siocntxwait(iobase);
3081 sp->cfcr = inb(iobase + com_cfcr);
3082 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3083 sp->dlbl = inb(iobase + com_dlbl);
3084 sp->dlbh = inb(iobase + com_dlbh);
3085 /*
3086 * Only set the divisor registers if they would change, since on
3087 * some 16550 incompatibles (Startech), setting them clears the
3088 * data input register. This also reduces the effects of the
3089 * UMC8669F bug.
3090 */
3091 divisor = siodivisor(comdefaultrclk, speed);
3092 dlbl = divisor & 0xFF;
3093 if (sp->dlbl != dlbl)
3094 outb(iobase + com_dlbl, dlbl);
3095 dlbh = divisor >> 8;
3096 if (sp->dlbh != dlbh)
3097 outb(iobase + com_dlbh, dlbh);
3098 outb(iobase + com_cfcr, CFCR_8BITS);
3099 sp->mcr = inb(iobase + com_mcr);
3100 /*
3101 * We don't want interrupts, but must be careful not to "disable"
3102 * them by clearing the MCR_IENABLE bit, since that might cause
3103 * an interrupt by floating the IRQ line.
3104 */
3105 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3106}
3107
3108static void
3109siocnclose(sp, iobase)
3110 struct siocnstate *sp;
3111 Port_t iobase;
3112{
3113 /*
3114 * Restore the device control registers.
3115 */
3116 siocntxwait(iobase);
3117 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3118 if (sp->dlbl != inb(iobase + com_dlbl))
3119 outb(iobase + com_dlbl, sp->dlbl);
3120 if (sp->dlbh != inb(iobase + com_dlbh))
3121 outb(iobase + com_dlbh, sp->dlbh);
3122 outb(iobase + com_cfcr, sp->cfcr);
3123 /*
3124 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3125 */
3126 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3127 outb(iobase + com_ier, sp->ier);
3128}
3129
3130static void
3131siocnprobe(cp)
3132 struct consdev *cp;
3133{
3134 speed_t boot_speed;
3135 u_char cfcr;
3136 u_int divisor;
3137 int s, unit;
3138 struct siocnstate sp;
3139
3140 /*
3141 * Find our first enabled console, if any. If it is a high-level
3142 * console device, then initialize it and return successfully.
3143 * If it is a low-level console device, then initialize it and
3144 * return unsuccessfully. It must be initialized in both cases
3145 * for early use by console drivers and debuggers. Initializing
3146 * the hardware is not necessary in all cases, since the i/o
3147 * routines initialize it on the fly, but it is necessary if
3148 * input might arrive while the hardware is switched back to an
3149 * uninitialized state. We can't handle multiple console devices
3150 * yet because our low-level routines don't take a device arg.
3151 * We trust the user to set the console flags properly so that we
3152 * don't need to probe.
3153 */
3154 cp->cn_pri = CN_DEAD;
3155
3156 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
3157 int flags;
3158 int disabled;
3159 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
3160 if (disabled)
3161 continue;
3162 }
3163 if (resource_int_value("sio", unit, "flags", &flags))
3164 continue;
3165 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
3166 int port;
3167 Port_t iobase;
3168
3169 if (resource_int_value("sio", unit, "port", &port))
3170 continue;
3171 iobase = port;
3172 s = spltty();
3173 if (boothowto & RB_SERIAL) {
3174 boot_speed =
3175 siocngetspeed(iobase, comdefaultrclk);
3176 if (boot_speed)
3177 comdefaultrate = boot_speed;
3178 }
3179
3180 /*
3181 * Initialize the divisor latch. We can't rely on
3182 * siocnopen() to do this the first time, since it
3183 * avoids writing to the latch if the latch appears
3184 * to have the correct value. Also, if we didn't
3185 * just read the speed from the hardware, then we
3186 * need to set the speed in hardware so that
3187 * switching it later is null.
3188 */
3189 cfcr = inb(iobase + com_cfcr);
3190 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3191 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3192 outb(iobase + com_dlbl, divisor & 0xff);
3193 outb(iobase + com_dlbh, divisor >> 8);
3194 outb(iobase + com_cfcr, cfcr);
3195
3196 siocnopen(&sp, iobase, comdefaultrate);
3197
3198 splx(s);
3199 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
3200 cp->cn_dev = makedev(CDEV_MAJOR, unit);
3201 cp->cn_pri = COM_FORCECONSOLE(flags)
3202 || boothowto & RB_SERIAL
3203 ? CN_REMOTE : CN_NORMAL;
3204 siocniobase = iobase;
3205 siocnunit = unit;
3206 }
3207 if (COM_DEBUGGER(flags)) {
3208 printf("sio%d: gdb debugging port\n", unit);
3209 siogdbiobase = iobase;
3210 siogdbunit = unit;
3211#if DDB > 0
3212 gdbdev = makedev(CDEV_MAJOR, unit);
3213 gdb_getc = siocngetc;
3214 gdb_putc = siocnputc;
3215#endif
3216 }
3217 }
3218 }
3219#ifdef __i386__
3220#if DDB > 0
3221 /*
3222 * XXX Ugly Compatability.
3223 * If no gdb port has been specified, set it to be the console
3224 * as some configuration files don't specify the gdb port.
3225 */
3226 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
3227 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
3228 siocnunit);
3229 printf("Set flag 0x80 on desired GDB port in your\n");
3230 printf("configuration file (currently sio only).\n");
3231 siogdbiobase = siocniobase;
3232 siogdbunit = siocnunit;
3233 gdbdev = makedev(CDEV_MAJOR, siocnunit);
3234 gdb_getc = siocngetc;
3235 gdb_putc = siocnputc;
3236 }
3237#endif
3238#endif
3239}
3240
3241#ifdef __alpha__
3242
3243CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
3244
3245int
3246siocnattach(port, speed)
3247 int port;
3248 int speed;
3249{
3250 int s;
3251 u_char cfcr;
3252 u_int divisor;
3253 struct siocnstate sp;
3254
3255 siocniobase = port;
3256 comdefaultrate = speed;
3257 sio_consdev.cn_pri = CN_NORMAL;
3258 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
3259
3260 s = spltty();
3261
3262 /*
3263 * Initialize the divisor latch. We can't rely on
3264 * siocnopen() to do this the first time, since it
3265 * avoids writing to the latch if the latch appears
3266 * to have the correct value. Also, if we didn't
3267 * just read the speed from the hardware, then we
3268 * need to set the speed in hardware so that
3269 * switching it later is null.
3270 */
3271 cfcr = inb(siocniobase + com_cfcr);
3272 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3273 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3274 outb(siocniobase + com_dlbl, divisor & 0xff);
3275 outb(siocniobase + com_dlbh, divisor >> 8);
3276 outb(siocniobase + com_cfcr, cfcr);
3277
3278 siocnopen(&sp, siocniobase, comdefaultrate);
3279 splx(s);
3280
3281 cn_tab = &sio_consdev;
3282 return (0);
3283}
3284
3285int
3286siogdbattach(port, speed)
3287 int port;
3288 int speed;
3289{
3290 int s;
3291 u_char cfcr;
3292 u_int divisor;
3293 struct siocnstate sp;
3294
3295 siogdbiobase = port;
3296 gdbdefaultrate = speed;
3297
3298 s = spltty();
3299
3300 /*
3301 * Initialize the divisor latch. We can't rely on
3302 * siocnopen() to do this the first time, since it
3303 * avoids writing to the latch if the latch appears
3304 * to have the correct value. Also, if we didn't
3305 * just read the speed from the hardware, then we
3306 * need to set the speed in hardware so that
3307 * switching it later is null.
3308 */
3309 cfcr = inb(siogdbiobase + com_cfcr);
3310 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3311 divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3312 outb(siogdbiobase + com_dlbl, divisor & 0xff);
3313 outb(siogdbiobase + com_dlbh, divisor >> 8);
3314 outb(siogdbiobase + com_cfcr, cfcr);
3315
3316 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3317 splx(s);
3318
3319 return (0);
3320}
3321
3322#endif
3323
3324static void
3325siocninit(cp)
3326 struct consdev *cp;
3327{
3328 comconsole = DEV_TO_UNIT(cp->cn_dev);
3329}
3330
3331static int
3332siocncheckc(dev)
3333 dev_t dev;
3334{
3335 int c;
3336 Port_t iobase;
3337 int s;
3338 struct siocnstate sp;
3339
3340 if (minor(dev) == siogdbunit)
3341 iobase = siogdbiobase;
3342 else
3343 iobase = siocniobase;
3344 s = spltty();
3345 siocnopen(&sp, iobase, comdefaultrate);
3346 if (inb(iobase + com_lsr) & LSR_RXRDY)
3347 c = inb(iobase + com_data);
3348 else
3349 c = -1;
3350 siocnclose(&sp, iobase);
3351 splx(s);
3352 return (c);
3353}
3354
3355
3356int
3357siocngetc(dev)
3358 dev_t dev;
3359{
3360 int c;
3361 Port_t iobase;
3362 int s;
3363 struct siocnstate sp;
3364
3365 if (minor(dev) == siogdbunit)
3366 iobase = siogdbiobase;
3367 else
3368 iobase = siocniobase;
3369 s = spltty();
3370 siocnopen(&sp, iobase, comdefaultrate);
3371 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3372 ;
3373 c = inb(iobase + com_data);
3374 siocnclose(&sp, iobase);
3375 splx(s);
3376 return (c);
3377}
3378
3379void
3380siocnputc(dev, c)
3381 dev_t dev;
3382 int c;
3383{
3384 int s;
3385 struct siocnstate sp;
3386 Port_t iobase;
3387
3388 if (minor(dev) == siogdbunit)
3389 iobase = siogdbiobase;
3390 else
3391 iobase = siocniobase;
3392 s = spltty();
3393 siocnopen(&sp, iobase, comdefaultrate);
3394 siocntxwait(iobase);
3395 outb(iobase + com_data, c);
3396 siocnclose(&sp, iobase);
3397 splx(s);
3398}
3399
3400#ifdef __alpha__
3401int
3402siogdbgetc()
3403{
3404 int c;
3405 Port_t iobase;
3406 int s;
3407 struct siocnstate sp;
3408
3409 iobase = siogdbiobase;
3410 s = spltty();
3411 siocnopen(&sp, iobase, gdbdefaultrate);
3412 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3413 ;
3414 c = inb(iobase + com_data);
3415 siocnclose(&sp, iobase);
3416 splx(s);
3417 return (c);
3418}
3419
3420void
3421siogdbputc(c)
3422 int c;
3423{
3424 int s;
3425 struct siocnstate sp;
3426
3427 s = spltty();
3428 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3429 siocntxwait(siogdbiobase);
3430 outb(siogdbiobase + com_data, c);
3431 siocnclose(&sp, siogdbiobase);
3432 splx(s);
3433}
3434#endif
3435
3436DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
3437#if NCARD > 0
3438DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0);
3439#endif
3440#if NPCI > 0
3441DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
3442#endif
3443#if NPUC > 0
3444DRIVER_MODULE(sio, puc, sio_puc_driver, sio_devclass, 0, 0);
3445#endif