EST's module was being installed before the module list got initialized,
[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c
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1/*
2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
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3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
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5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
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8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
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11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
a9295349 39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.11 2006/11/07 06:43:24 dillon Exp $
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40 */
41
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42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
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46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
a9295349 51#include <machine_base/isa/intr_machdep.h>
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52
53#include "icu.h"
54#include "icu_ipl.h"
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55
56#ifndef APIC_IO
57
58extern void ICU_INTREN(int);
59extern void ICU_INTRDIS(int);
60
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61extern inthand_t
62 IDTVEC(icu_fastintr0), IDTVEC(icu_fastintr1),
63 IDTVEC(icu_fastintr2), IDTVEC(icu_fastintr3),
64 IDTVEC(icu_fastintr4), IDTVEC(icu_fastintr5),
65 IDTVEC(icu_fastintr6), IDTVEC(icu_fastintr7),
66 IDTVEC(icu_fastintr8), IDTVEC(icu_fastintr9),
67 IDTVEC(icu_fastintr10), IDTVEC(icu_fastintr11),
68 IDTVEC(icu_fastintr12), IDTVEC(icu_fastintr13),
69 IDTVEC(icu_fastintr14), IDTVEC(icu_fastintr15);
70
71extern inthand_t
72 IDTVEC(icu_slowintr0), IDTVEC(icu_slowintr1),
73 IDTVEC(icu_slowintr2), IDTVEC(icu_slowintr3),
74 IDTVEC(icu_slowintr4), IDTVEC(icu_slowintr5),
75 IDTVEC(icu_slowintr6), IDTVEC(icu_slowintr7),
76 IDTVEC(icu_slowintr8), IDTVEC(icu_slowintr9),
77 IDTVEC(icu_slowintr10), IDTVEC(icu_slowintr11),
78 IDTVEC(icu_slowintr12), IDTVEC(icu_slowintr13),
79 IDTVEC(icu_slowintr14), IDTVEC(icu_slowintr15);
80
10ff1029 81static int icu_vectorctl(int, int, int);
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82static int icu_setvar(int, const void *);
83static int icu_getvar(int, void *);
84static void icu_finalize(void);
85
5f456c40 86static inthand_t *icu_fastintr[ICU_HWI_VECTORS] = {
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87 &IDTVEC(icu_fastintr0), &IDTVEC(icu_fastintr1),
88 &IDTVEC(icu_fastintr2), &IDTVEC(icu_fastintr3),
89 &IDTVEC(icu_fastintr4), &IDTVEC(icu_fastintr5),
90 &IDTVEC(icu_fastintr6), &IDTVEC(icu_fastintr7),
91 &IDTVEC(icu_fastintr8), &IDTVEC(icu_fastintr9),
92 &IDTVEC(icu_fastintr10), &IDTVEC(icu_fastintr11),
93 &IDTVEC(icu_fastintr12), &IDTVEC(icu_fastintr13),
94 &IDTVEC(icu_fastintr14), &IDTVEC(icu_fastintr15)
95};
96
5f456c40 97static inthand_t *icu_slowintr[ICU_HWI_VECTORS] = {
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98 &IDTVEC(icu_slowintr0), &IDTVEC(icu_slowintr1),
99 &IDTVEC(icu_slowintr2), &IDTVEC(icu_slowintr3),
100 &IDTVEC(icu_slowintr4), &IDTVEC(icu_slowintr5),
101 &IDTVEC(icu_slowintr6), &IDTVEC(icu_slowintr7),
102 &IDTVEC(icu_slowintr8), &IDTVEC(icu_slowintr9),
103 &IDTVEC(icu_slowintr10), &IDTVEC(icu_slowintr11),
104 &IDTVEC(icu_slowintr12), &IDTVEC(icu_slowintr13),
105 &IDTVEC(icu_slowintr14), &IDTVEC(icu_slowintr15)
106};
107
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108struct machintr_abi MachIntrABI = {
109 MACHINTR_ICU,
110 ICU_INTRDIS,
111 ICU_INTREN,
10ff1029 112 icu_vectorctl,
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113 icu_setvar,
114 icu_getvar,
115 icu_finalize
116};
117
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118static int icu_imcr_present;
119
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120/*
121 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
122 */
123
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124static
125int
126icu_setvar(int varid __unused, const void *buf __unused)
127{
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128 int error = 0;
129
130 switch(varid) {
131 case MACHINTR_VAR_IMCR_PRESENT:
132 icu_imcr_present = *(const int *)buf;
133 break;
134 default:
135 error = ENOENT;
136 break;
137 }
138 return (error);
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139}
140
141static
142int
143icu_getvar(int varid __unused, void *buf __unused)
144{
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145 int error = 0;
146
147 switch(varid) {
148 case MACHINTR_VAR_IMCR_PRESENT:
149 *(int *)buf = icu_imcr_present;
150 break;
151 default:
152 error = ENOENT;
153 break;
154 }
155 return (error);
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156}
157
158static void
159icu_finalize(void)
160{
161 machintr_intren(ICU_IRQ_SLAVE);
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162
163 /*
164 * If an IMCR is present, programming bit 0 disconnects the 8259
165 * from the BSP. The 8259 may still be connected to LINT0 on the BSP's
166 * LAPIC.
167 *
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168 * If we are running SMP the LAPIC is active, try to use virtual wire
169 * mode so we can use other interrupt sources within the LAPIC in
170 * addition to the 8259.
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171 */
172 if (icu_imcr_present) {
f4582d09 173#if defined(SMP)
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174 outb(0x22, 0x70);
175 outb(0x23, 0x01);
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176#endif
177 }
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178}
179
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180static
181int
182icu_vectorctl(int op, int intr, int flags)
183{
184 int error;
185 u_long ef;
186
5f456c40 187 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
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188 return (EINVAL);
189
190 ef = read_eflags();
191 cpu_disable_intr();
192 error = 0;
193
194 switch(op) {
195 case MACHINTR_VECTOR_SETUP:
5f456c40 196 setidt(IDT_OFFSET + intr,
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197 flags & INTR_FAST ? icu_fastintr[intr] : icu_slowintr[intr],
198 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
199 machintr_intren(intr);
200 break;
201 case MACHINTR_VECTOR_TEARDOWN:
35408d22 202 case MACHINTR_VECTOR_SETDEFAULT:
5f456c40 203 setidt(IDT_OFFSET + intr, icu_slowintr[intr], SDT_SYS386IGT, SEL_KPL,
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204 GSEL(GCODE_SEL, SEL_KPL));
205 machintr_intrdis(intr);
206 break;
207 default:
208 error = EOPNOTSUPP;
209 break;
210 }
211 write_eflags(ef);
212 return (error);
213}
214
37e7efec 215#endif