igb: Utilize power of 2 mask based CPUID to subqueue mapping
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
CommitLineData
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1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
d0f59cad 32#include "opt_ifpoll.h"
8d6600da 33#include "opt_igb.h"
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34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/interrupt.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/proc.h>
43#include <sys/rman.h>
44#include <sys/serialize.h>
45#include <sys/serialize2.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <sys/sysctl.h>
49#include <sys/systm.h>
50
51#include <net/bpf.h>
52#include <net/ethernet.h>
53#include <net/if.h>
54#include <net/if_arp.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/ifq_var.h>
58#include <net/toeplitz.h>
59#include <net/toeplitz2.h>
60#include <net/vlan/if_vlan_var.h>
61#include <net/vlan/if_vlan_ether.h>
62#include <net/if_poll.h>
63
64#include <netinet/in_systm.h>
65#include <netinet/in.h>
66#include <netinet/ip.h>
67#include <netinet/tcp.h>
68#include <netinet/udp.h>
69
70#include <bus/pci/pcivar.h>
71#include <bus/pci/pcireg.h>
72
73#include <dev/netif/ig_hal/e1000_api.h>
74#include <dev/netif/ig_hal/e1000_82575.h>
75#include <dev/netif/igb/if_igb.h>
76
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77#ifdef IGB_RSS_DEBUG
78#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79do { \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82} while (0)
83#else /* !IGB_RSS_DEBUG */
84#define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85#endif /* IGB_RSS_DEBUG */
86
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87#define IGB_NAME "Intel(R) PRO/1000 "
88#define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90#define IGB_DEVICE_NULL { 0, 0, NULL }
91
92static struct igb_device {
93 uint16_t vid;
94 uint16_t did;
95 const char *desc;
96} igb_devices[] = {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
123 IGB_DEVICE(I350_VF),
124
125 /* required last entry */
126 IGB_DEVICE_NULL
127};
128
129static int igb_probe(device_t);
130static int igb_attach(device_t);
131static int igb_detach(device_t);
132static int igb_shutdown(device_t);
133static int igb_suspend(device_t);
134static int igb_resume(device_t);
135
136static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137static void igb_setup_ifp(struct igb_softc *);
48faa653 138static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
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139static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
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141static void igb_add_sysctl(struct igb_softc *);
142static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
9c0ecdcc 143static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
b6220144 144static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
708575bb 145static int igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
9d8e892a 146static int igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
9c0ecdcc 147static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
4b21dd0f 148static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
d802cc67 149static int igb_get_txring_inuse(const struct igb_softc *, boolean_t);
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150#ifdef IFPOLL_ENABLE
151static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
152static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
153#endif
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154
155static void igb_vf_init_stats(struct igb_softc *);
156static void igb_reset(struct igb_softc *);
157static void igb_update_stats_counters(struct igb_softc *);
158static void igb_update_vf_stats_counters(struct igb_softc *);
159static void igb_update_link_status(struct igb_softc *);
160static void igb_init_tx_unit(struct igb_softc *);
161static void igb_init_rx_unit(struct igb_softc *);
162
163static void igb_set_vlan(struct igb_softc *);
164static void igb_set_multi(struct igb_softc *);
165static void igb_set_promisc(struct igb_softc *);
166static void igb_disable_promisc(struct igb_softc *);
167
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168static int igb_alloc_rings(struct igb_softc *);
169static void igb_free_rings(struct igb_softc *);
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170static int igb_create_tx_ring(struct igb_tx_ring *);
171static int igb_create_rx_ring(struct igb_rx_ring *);
172static void igb_free_tx_ring(struct igb_tx_ring *);
173static void igb_free_rx_ring(struct igb_rx_ring *);
174static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
175static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
176static void igb_init_tx_ring(struct igb_tx_ring *);
177static int igb_init_rx_ring(struct igb_rx_ring *);
178static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
871c0e2b 179static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
b56e8196 180static void igb_rx_refresh(struct igb_rx_ring *, int);
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181
182static void igb_stop(struct igb_softc *);
183static void igb_init(void *);
184static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
185static void igb_media_status(struct ifnet *, struct ifmediareq *);
186static int igb_media_change(struct ifnet *);
187static void igb_timer(void *);
16109efc 188static void igb_watchdog(struct ifaltq_subque *);
f0a26983 189static void igb_start(struct ifnet *, struct ifaltq_subque *);
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190#ifdef IFPOLL_ENABLE
191static void igb_npoll(struct ifnet *, struct ifpoll_info *);
192static void igb_npoll_rx(struct ifnet *, void *, int);
193static void igb_npoll_tx(struct ifnet *, void *, int);
2f00683b 194static void igb_npoll_status(struct ifnet *);
1f7e3916 195#endif
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196static void igb_serialize(struct ifnet *, enum ifnet_serialize);
197static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
198static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
199#ifdef INVARIANTS
200static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
201 boolean_t);
202#endif
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203
204static void igb_intr(void *);
9c0ecdcc 205static void igb_intr_shared(void *);
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206static void igb_rxeof(struct igb_rx_ring *, int);
207static void igb_txeof(struct igb_tx_ring *);
9c0ecdcc 208static void igb_set_eitr(struct igb_softc *, int, int);
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209static void igb_enable_intr(struct igb_softc *);
210static void igb_disable_intr(struct igb_softc *);
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211static void igb_init_unshared_intr(struct igb_softc *);
212static void igb_init_intr(struct igb_softc *);
213static int igb_setup_intr(struct igb_softc *);
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214static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
215static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
be922da6 216static void igb_set_intr_mask(struct igb_softc *);
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217static int igb_alloc_intr(struct igb_softc *);
218static void igb_free_intr(struct igb_softc *);
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219static void igb_teardown_intr(struct igb_softc *);
220static void igb_msix_try_alloc(struct igb_softc *);
221static void igb_msix_free(struct igb_softc *, boolean_t);
222static int igb_msix_setup(struct igb_softc *);
223static void igb_msix_teardown(struct igb_softc *, int);
224static void igb_msix_rx(void *);
225static void igb_msix_tx(void *);
226static void igb_msix_status(void *);
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227
228/* Management and WOL Support */
229static void igb_get_mgmt(struct igb_softc *);
230static void igb_rel_mgmt(struct igb_softc *);
231static void igb_get_hw_control(struct igb_softc *);
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232static void igb_rel_hw_control(struct igb_softc *);
233static void igb_enable_wol(device_t);
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234
235static device_method_t igb_methods[] = {
236 /* Device interface */
237 DEVMETHOD(device_probe, igb_probe),
238 DEVMETHOD(device_attach, igb_attach),
239 DEVMETHOD(device_detach, igb_detach),
240 DEVMETHOD(device_shutdown, igb_shutdown),
241 DEVMETHOD(device_suspend, igb_suspend),
242 DEVMETHOD(device_resume, igb_resume),
243 { 0, 0 }
244};
245
246static driver_t igb_driver = {
247 "igb",
248 igb_methods,
249 sizeof(struct igb_softc),
250};
251
252static devclass_t igb_devclass;
253
254DECLARE_DUMMY_MODULE(if_igb);
255MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
256DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
257
258static int igb_rxd = IGB_DEFAULT_RXD;
259static int igb_txd = IGB_DEFAULT_TXD;
8d6600da 260static int igb_rxr = 0;
d802cc67 261static int igb_txr = 0;
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262static int igb_msi_enable = 1;
263static int igb_msix_enable = 1;
264static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
265static int igb_fc_setting = e1000_fc_full;
266
267/*
268 * DMA Coalescing, only for i350 - default to off,
269 * this feature is for power savings
270 */
271static int igb_dma_coalesce = 0;
272
273TUNABLE_INT("hw.igb.rxd", &igb_rxd);
274TUNABLE_INT("hw.igb.txd", &igb_txd);
8d6600da 275TUNABLE_INT("hw.igb.rxr", &igb_rxr);
d802cc67 276TUNABLE_INT("hw.igb.txr", &igb_txr);
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277TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
278TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
279TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
280
281/* i350 specific */
282TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
283TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
284
285static __inline void
286igb_rxcsum(uint32_t staterr, struct mbuf *mp)
287{
288 /* Ignore Checksum bit is set */
289 if (staterr & E1000_RXD_STAT_IXSM)
290 return;
291
292 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
293 E1000_RXD_STAT_IPCS)
294 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
295
296 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
297 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
298 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
299 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
300 mp->m_pkthdr.csum_data = htons(0xffff);
301 }
302 }
303}
304
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305static __inline struct pktinfo *
306igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
307 uint32_t hash, uint32_t hashtype, uint32_t staterr)
308{
309 switch (hashtype) {
310 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
311 pi->pi_netisr = NETISR_IP;
312 pi->pi_flags = 0;
313 pi->pi_l3proto = IPPROTO_TCP;
314 break;
315
316 case E1000_RXDADV_RSSTYPE_IPV4:
317 if (staterr & E1000_RXD_STAT_IXSM)
318 return NULL;
319
320 if ((staterr &
321 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
322 E1000_RXD_STAT_TCPCS) {
323 pi->pi_netisr = NETISR_IP;
324 pi->pi_flags = 0;
325 pi->pi_l3proto = IPPROTO_UDP;
326 break;
327 }
328 /* FALL THROUGH */
329 default:
330 return NULL;
331 }
332
333 m->m_flags |= M_HASH;
334 m->m_pkthdr.hash = toeplitz_hash(hash);
335 return pi;
336}
337
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338static int
339igb_probe(device_t dev)
340{
341 const struct igb_device *d;
342 uint16_t vid, did;
343
344 vid = pci_get_vendor(dev);
345 did = pci_get_device(dev);
346
347 for (d = igb_devices; d->desc != NULL; ++d) {
348 if (vid == d->vid && did == d->did) {
349 device_set_desc(dev, d->desc);
350 return 0;
351 }
352 }
353 return ENXIO;
354}
355
356static int
357igb_attach(device_t dev)
358{
359 struct igb_softc *sc = device_get_softc(dev);
1f7e3916 360 uint16_t eeprom_data;
8d6600da 361 int error = 0, i, j, ring_max;
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362#ifdef IFPOLL_ENABLE
363 int offset, offset_def;
364#endif
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365
366#ifdef notyet
367 /* SYSCTL stuff */
368 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
369 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
370 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
371 igb_sysctl_nvm_info, "I", "NVM Information");
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372 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
373 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
374 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
375 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
376#endif
377
378 callout_init_mp(&sc->timer);
9c0ecdcc 379 lwkt_serialize_init(&sc->main_serialize);
1f7e3916 380
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381 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
382 device_get_unit(dev));
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383 sc->dev = sc->osdep.dev = dev;
384
385 /*
386 * Determine hardware and mac type
387 */
388 sc->hw.vendor_id = pci_get_vendor(dev);
389 sc->hw.device_id = pci_get_device(dev);
390 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
391 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
392 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
393
394 if (e1000_set_mac_type(&sc->hw))
395 return ENXIO;
396
397 /* Are we a VF device? */
398 if (sc->hw.mac.type == e1000_vfadapt ||
399 sc->hw.mac.type == e1000_vfadapt_i350)
400 sc->vf_ifp = 1;
401 else
402 sc->vf_ifp = 0;
403
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404 /*
405 * Configure total supported RX/TX ring count
406 */
407 switch (sc->hw.mac.type) {
408 case e1000_82575:
409 ring_max = IGB_MAX_RING_82575;
410 break;
411 case e1000_82580:
412 ring_max = IGB_MAX_RING_82580;
413 break;
414 case e1000_i350:
415 ring_max = IGB_MAX_RING_I350;
416 break;
417 case e1000_82576:
418 ring_max = IGB_MAX_RING_82576;
419 break;
420 default:
421 ring_max = IGB_MIN_RING;
422 break;
423 }
d802cc67 424
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425 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
426 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
427#ifdef IGB_RSS_DEBUG
428 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
429#endif
430 sc->rx_ring_inuse = sc->rx_ring_cnt;
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431
432 sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
433 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
434#ifdef IGB_TSS_DEBUG
435 sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
436#endif
437 sc->tx_ring_inuse = sc->tx_ring_cnt;
9b7aa975 438
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439 /* Enable bus mastering */
440 pci_enable_busmaster(dev);
441
442 /*
443 * Allocate IO memory
444 */
445 sc->mem_rid = PCIR_BAR(0);
446 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
447 RF_ACTIVE);
448 if (sc->mem_res == NULL) {
449 device_printf(dev, "Unable to allocate bus resource: memory\n");
450 error = ENXIO;
451 goto failed;
452 }
453 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
454 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
455
456 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
457
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458 /* Save PCI command register for Shared Code */
459 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
460 sc->hw.back = &sc->osdep;
461
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462 /* Do Shared Code initialization */
463 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
464 device_printf(dev, "Setup of Shared code failed\n");
465 error = ENXIO;
466 goto failed;
467 }
468
469 e1000_get_bus_info(&sc->hw);
470
471 sc->hw.mac.autoneg = DO_AUTO_NEG;
472 sc->hw.phy.autoneg_wait_to_complete = FALSE;
473 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
474
475 /* Copper options */
476 if (sc->hw.phy.media_type == e1000_media_type_copper) {
477 sc->hw.phy.mdix = AUTO_ALL_MODES;
478 sc->hw.phy.disable_polarity_correction = FALSE;
479 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
480 }
481
482 /* Set the frame limits assuming standard ethernet sized frames. */
483 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
1f7e3916 484
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485 /* Allocate RX/TX rings */
486 error = igb_alloc_rings(sc);
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487 if (error)
488 goto failed;
489
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490#ifdef IFPOLL_ENABLE
491 /*
492 * NPOLLING RX CPU offset
493 */
494 if (sc->rx_ring_cnt == ncpus2) {
495 offset = 0;
496 } else {
497 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
498 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
499 if (offset >= ncpus2 ||
500 offset % sc->rx_ring_cnt != 0) {
501 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
502 offset, offset_def);
503 offset = offset_def;
504 }
505 }
506 sc->rx_npoll_off = offset;
507
508 /*
509 * NPOLLING TX CPU offset
510 */
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511 if (sc->tx_ring_cnt == ncpus2) {
512 offset = 0;
513 } else {
514 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
515 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
516 if (offset >= ncpus2 ||
517 offset % sc->tx_ring_cnt != 0) {
518 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
519 offset, offset_def);
520 offset = offset_def;
521 }
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522 }
523 sc->tx_npoll_off = offset;
524#endif
525
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526 /* Allocate interrupt */
527 error = igb_alloc_intr(sc);
528 if (error)
a1647e40 529 goto failed;
a1647e40
SZ
530
531 /*
7d235eb5
SZ
532 * Setup serializers
533 */
7d235eb5
SZ
534 i = 0;
535 sc->serializes[i++] = &sc->main_serialize;
536
537 sc->tx_serialize = i;
538 for (j = 0; j < sc->tx_ring_cnt; ++j)
539 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
540
541 sc->rx_serialize = i;
542 for (j = 0; j < sc->rx_ring_cnt; ++j)
543 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
544
545 sc->serialize_cnt = i;
546 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
547
1f7e3916
SZ
548 /* Allocate the appropriate stats memory */
549 if (sc->vf_ifp) {
550 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
551 M_WAITOK | M_ZERO);
552 igb_vf_init_stats(sc);
553 } else {
554 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
555 M_WAITOK | M_ZERO);
556 }
557
558 /* Allocate multicast array memory. */
559 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
560 M_DEVBUF, M_WAITOK);
561
562 /* Some adapter-specific advanced features */
563 if (sc->hw.mac.type >= e1000_i350) {
564#ifdef notyet
565 igb_set_sysctl_value(adapter, "dma_coalesce",
566 "configure dma coalesce",
567 &adapter->dma_coalesce, igb_dma_coalesce);
568 igb_set_sysctl_value(adapter, "eee_disabled",
569 "enable Energy Efficient Ethernet",
570 &adapter->hw.dev_spec._82575.eee_disable,
571 igb_eee_disabled);
572#else
573 sc->dma_coalesce = igb_dma_coalesce;
574 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
575#endif
576 e1000_set_eee_i350(&sc->hw);
577 }
578
579 /*
580 * Start from a known state, this is important in reading the nvm and
581 * mac from that.
582 */
583 e1000_reset_hw(&sc->hw);
584
585 /* Make sure we have a good EEPROM before we read from it */
586 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
587 /*
588 * Some PCI-E parts fail the first check due to
589 * the link being in sleep state, call it again,
590 * if it fails a second time its a real issue.
591 */
592 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
593 device_printf(dev,
594 "The EEPROM Checksum Is Not Valid\n");
595 error = EIO;
596 goto failed;
597 }
598 }
599
600 /* Copy the permanent MAC address out of the EEPROM */
601 if (e1000_read_mac_addr(&sc->hw) < 0) {
602 device_printf(dev, "EEPROM read error while reading MAC"
603 " address\n");
604 error = EIO;
605 goto failed;
606 }
607 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
608 device_printf(dev, "Invalid MAC address\n");
609 error = EIO;
610 goto failed;
611 }
612
1f7e3916
SZ
613 /* Setup OS specific network interface */
614 igb_setup_ifp(sc);
615
616 /* Add sysctl tree, must after igb_setup_ifp() */
617 igb_add_sysctl(sc);
618
619 /* Now get a good starting state */
620 igb_reset(sc);
621
622 /* Initialize statistics */
623 igb_update_stats_counters(sc);
624
625 sc->hw.mac.get_link_status = 1;
626 igb_update_link_status(sc);
627
628 /* Indicate SOL/IDER usage */
629 if (e1000_check_reset_block(&sc->hw)) {
630 device_printf(dev,
631 "PHY reset is blocked due to SOL/IDER session.\n");
632 }
633
634 /* Determine if we have to control management hardware */
396b7048
SZ
635 if (e1000_enable_mng_pass_thru(&sc->hw))
636 sc->flags |= IGB_FLAG_HAS_MGMT;
1f7e3916
SZ
637
638 /*
639 * Setup Wake-on-Lan
640 */
641 /* APME bit in EEPROM is mapped to WUC.APME */
642 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
643 if (eeprom_data)
644 sc->wol = E1000_WUFC_MAG;
645 /* XXX disable WOL */
646 sc->wol = 0;
647
648#ifdef notyet
649 /* Register for VLAN events */
650 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
651 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
652 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
653 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
654#endif
655
656#ifdef notyet
657 igb_add_hw_stats(adapter);
658#endif
659
f6167a56 660 error = igb_setup_intr(sc);
1f7e3916 661 if (error) {
1f7e3916
SZ
662 ether_ifdetach(&sc->arpcom.ac_if);
663 goto failed;
664 }
f0a26983
SZ
665
666 for (i = 0; i < sc->tx_ring_cnt; ++i) {
667 struct ifaltq_subque *ifsq =
668 ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
669 struct igb_tx_ring *txr = &sc->tx_rings[i];
670
671 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
672 ifsq_set_priv(ifsq, txr);
673 txr->ifsq = ifsq;
16109efc
SZ
674
675 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
f0a26983 676 }
0e23628a 677
1f7e3916
SZ
678 return 0;
679
680failed:
681 igb_detach(dev);
682 return error;
683}
684
685static int
686igb_detach(device_t dev)
687{
688 struct igb_softc *sc = device_get_softc(dev);
689
690 if (device_is_attached(dev)) {
691 struct ifnet *ifp = &sc->arpcom.ac_if;
692
693 ifnet_serialize_all(ifp);
694
695 igb_stop(sc);
696
697 e1000_phy_hw_reset(&sc->hw);
698
699 /* Give control back to firmware */
700 igb_rel_mgmt(sc);
701 igb_rel_hw_control(sc);
702
703 if (sc->wol) {
704 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
705 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
706 igb_enable_wol(dev);
707 }
708
9c0ecdcc 709 igb_teardown_intr(sc);
1f7e3916
SZ
710
711 ifnet_deserialize_all(ifp);
712
713 ether_ifdetach(ifp);
714 } else if (sc->mem_res != NULL) {
715 igb_rel_hw_control(sc);
716 }
717 bus_generic_detach(dev);
718
9c0ecdcc
SZ
719 if (sc->sysctl_tree != NULL)
720 sysctl_ctx_free(&sc->sysctl_ctx);
721
3c7cc5e2 722 igb_free_intr(sc);
1f7e3916 723
9c0ecdcc
SZ
724 if (sc->msix_mem_res != NULL) {
725 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
726 sc->msix_mem_res);
727 }
1f7e3916
SZ
728 if (sc->mem_res != NULL) {
729 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
730 sc->mem_res);
731 }
732
a619b256 733 igb_free_rings(sc);
1f7e3916
SZ
734
735 if (sc->mta != NULL)
736 kfree(sc->mta, M_DEVBUF);
737 if (sc->stats != NULL)
738 kfree(sc->stats, M_DEVBUF);
739
1f7e3916
SZ
740 return 0;
741}
742
743static int
744igb_shutdown(device_t dev)
745{
746 return igb_suspend(dev);
747}
748
749static int
750igb_suspend(device_t dev)
751{
752 struct igb_softc *sc = device_get_softc(dev);
753 struct ifnet *ifp = &sc->arpcom.ac_if;
754
755 ifnet_serialize_all(ifp);
756
757 igb_stop(sc);
758
759 igb_rel_mgmt(sc);
760 igb_rel_hw_control(sc);
761
762 if (sc->wol) {
763 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
764 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
765 igb_enable_wol(dev);
766 }
767
768 ifnet_deserialize_all(ifp);
769
770 return bus_generic_suspend(dev);
771}
772
773static int
774igb_resume(device_t dev)
775{
776 struct igb_softc *sc = device_get_softc(dev);
777 struct ifnet *ifp = &sc->arpcom.ac_if;
f0a26983 778 int i;
1f7e3916
SZ
779
780 ifnet_serialize_all(ifp);
781
782 igb_init(sc);
783 igb_get_mgmt(sc);
784
d802cc67 785 for (i = 0; i < sc->tx_ring_inuse; ++i)
73397ddb 786 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
1f7e3916
SZ
787
788 ifnet_deserialize_all(ifp);
789
790 return bus_generic_resume(dev);
791}
792
793static int
794igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
795{
796 struct igb_softc *sc = ifp->if_softc;
797 struct ifreq *ifr = (struct ifreq *)data;
798 int max_frame_size, mask, reinit;
799 int error = 0;
800
801 ASSERT_IFNET_SERIALIZED_ALL(ifp);
802
803 switch (command) {
804 case SIOCSIFMTU:
805 max_frame_size = 9234;
806 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
807 ETHER_CRC_LEN) {
808 error = EINVAL;
809 break;
810 }
811
812 ifp->if_mtu = ifr->ifr_mtu;
813 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
814 ETHER_CRC_LEN;
815
816 if (ifp->if_flags & IFF_RUNNING)
817 igb_init(sc);
818 break;
819
820 case SIOCSIFFLAGS:
821 if (ifp->if_flags & IFF_UP) {
822 if (ifp->if_flags & IFF_RUNNING) {
823 if ((ifp->if_flags ^ sc->if_flags) &
824 (IFF_PROMISC | IFF_ALLMULTI)) {
825 igb_disable_promisc(sc);
826 igb_set_promisc(sc);
827 }
828 } else {
829 igb_init(sc);
830 }
831 } else if (ifp->if_flags & IFF_RUNNING) {
832 igb_stop(sc);
833 }
834 sc->if_flags = ifp->if_flags;
835 break;
836
837 case SIOCADDMULTI:
838 case SIOCDELMULTI:
839 if (ifp->if_flags & IFF_RUNNING) {
840 igb_disable_intr(sc);
841 igb_set_multi(sc);
d0f59cad
SZ
842#ifdef IFPOLL_ENABLE
843 if (!(ifp->if_flags & IFF_NPOLLING))
1f7e3916
SZ
844#endif
845 igb_enable_intr(sc);
846 }
847 break;
848
849 case SIOCSIFMEDIA:
850 /*
851 * As the speed/duplex settings are being
852 * changed, we need toreset the PHY.
853 */
854 sc->hw.phy.reset_disable = FALSE;
855
856 /* Check SOL/IDER usage */
857 if (e1000_check_reset_block(&sc->hw)) {
858 if_printf(ifp, "Media change is "
859 "blocked due to SOL/IDER session.\n");
860 break;
861 }
862 /* FALL THROUGH */
863
864 case SIOCGIFMEDIA:
865 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
866 break;
867
868 case SIOCSIFCAP:
869 reinit = 0;
870 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
77d8cab9
SZ
871 if (mask & IFCAP_RXCSUM) {
872 ifp->if_capenable ^= IFCAP_RXCSUM;
1f7e3916
SZ
873 reinit = 1;
874 }
875 if (mask & IFCAP_VLAN_HWTAGGING) {
876 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
877 reinit = 1;
878 }
77d8cab9
SZ
879 if (mask & IFCAP_TXCSUM) {
880 ifp->if_capenable ^= IFCAP_TXCSUM;
881 if (ifp->if_capenable & IFCAP_TXCSUM)
882 ifp->if_hwassist |= IGB_CSUM_FEATURES;
883 else
884 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
885 }
23f6ffe4
SZ
886 if (mask & IFCAP_TSO) {
887 ifp->if_capenable ^= IFCAP_TSO;
888 if (ifp->if_capenable & IFCAP_TSO)
889 ifp->if_hwassist |= CSUM_TSO;
890 else
891 ifp->if_hwassist &= ~CSUM_TSO;
892 }
8d6600da
SZ
893 if (mask & IFCAP_RSS)
894 ifp->if_capenable ^= IFCAP_RSS;
1f7e3916
SZ
895 if (reinit && (ifp->if_flags & IFF_RUNNING))
896 igb_init(sc);
897 break;
898
899 default:
900 error = ether_ioctl(ifp, command, data);
901 break;
902 }
903 return error;
904}
905
906static void
907igb_init(void *xsc)
908{
909 struct igb_softc *sc = xsc;
910 struct ifnet *ifp = &sc->arpcom.ac_if;
9c0ecdcc 911 boolean_t polling;
1f7e3916
SZ
912 int i;
913
914 ASSERT_IFNET_SERIALIZED_ALL(ifp);
915
916 igb_stop(sc);
917
918 /* Get the latest mac address, User can use a LAA */
919 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
920
921 /* Put the address into the Receive Address Array */
922 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
923
924 igb_reset(sc);
925 igb_update_link_status(sc);
926
927 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
928
1f7e3916
SZ
929 /* Configure for OS presence */
930 igb_get_mgmt(sc);
931
9c0ecdcc 932 polling = FALSE;
d0f59cad
SZ
933#ifdef IFPOLL_ENABLE
934 if (ifp->if_flags & IFF_NPOLLING)
9c0ecdcc 935 polling = TRUE;
be922da6 936#endif
9c0ecdcc
SZ
937
938 /* Configured used RX/TX rings */
939 igb_set_ring_inuse(sc, polling);
dd3f3290 940 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
9c0ecdcc
SZ
941
942 /* Initialize interrupt */
943 igb_init_intr(sc);
be922da6 944
1f7e3916 945 /* Prepare transmit descriptors and buffers */
d802cc67 946 for (i = 0; i < sc->tx_ring_inuse; ++i)
1f7e3916
SZ
947 igb_init_tx_ring(&sc->tx_rings[i]);
948 igb_init_tx_unit(sc);
949
950 /* Setup Multicast table */
951 igb_set_multi(sc);
952
953#if 0
954 /*
955 * Figure out the desired mbuf pool
956 * for doing jumbo/packetsplit
957 */
958 if (adapter->max_frame_size <= 2048)
959 adapter->rx_mbuf_sz = MCLBYTES;
960 else if (adapter->max_frame_size <= 4096)
961 adapter->rx_mbuf_sz = MJUMPAGESIZE;
962 else
963 adapter->rx_mbuf_sz = MJUM9BYTES;
1f7e3916
SZ
964#endif
965
966 /* Prepare receive descriptors and buffers */
be922da6 967 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
968 int error;
969
970 error = igb_init_rx_ring(&sc->rx_rings[i]);
971 if (error) {
972 if_printf(ifp, "Could not setup receive structures\n");
973 igb_stop(sc);
974 return;
975 }
976 }
977 igb_init_rx_unit(sc);
978
979 /* Enable VLAN support */
980 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
981 igb_set_vlan(sc);
982
983 /* Don't lose promiscuous settings */
984 igb_set_promisc(sc);
985
1f7e3916 986 ifp->if_flags |= IFF_RUNNING;
d802cc67 987 for (i = 0; i < sc->tx_ring_inuse; ++i) {
f0a26983 988 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
16109efc
SZ
989 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
990 }
1f7e3916 991
7b61c9f2
SZ
992 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
993 sc->timer_cpuid = 0; /* XXX fixed */
994 else
995 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
996 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1f7e3916
SZ
997 e1000_clear_hw_cntrs_base_generic(&sc->hw);
998
9c0ecdcc 999 /* This clears any pending interrupts */
1f7e3916 1000 E1000_READ_REG(&sc->hw, E1000_ICR);
9c0ecdcc 1001
1f7e3916
SZ
1002 /*
1003 * Only enable interrupts if we are not polling, make sure
1004 * they are off otherwise.
1005 */
9c0ecdcc 1006 if (polling) {
1f7e3916 1007 igb_disable_intr(sc);
9c0ecdcc 1008 } else {
1f7e3916
SZ
1009 igb_enable_intr(sc);
1010 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1011 }
1012
1013 /* Set Energy Efficient Ethernet */
1014 e1000_set_eee_i350(&sc->hw);
1015
1016 /* Don't reset the phy next time init gets called */
1017 sc->hw.phy.reset_disable = TRUE;
1018}
1019
1020static void
1021igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1022{
1023 struct igb_softc *sc = ifp->if_softc;
1024 u_char fiber_type = IFM_1000_SX;
1025
1026 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1027
1028 igb_update_link_status(sc);
1029
1030 ifmr->ifm_status = IFM_AVALID;
1031 ifmr->ifm_active = IFM_ETHER;
1032
1033 if (!sc->link_active)
1034 return;
1035
1036 ifmr->ifm_status |= IFM_ACTIVE;
1037
1038 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1039 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1040 ifmr->ifm_active |= fiber_type | IFM_FDX;
1041 } else {
1042 switch (sc->link_speed) {
1043 case 10:
1044 ifmr->ifm_active |= IFM_10_T;
1045 break;
1046
1047 case 100:
1048 ifmr->ifm_active |= IFM_100_TX;
1049 break;
1050
1051 case 1000:
1052 ifmr->ifm_active |= IFM_1000_T;
1053 break;
1054 }
1055 if (sc->link_duplex == FULL_DUPLEX)
1056 ifmr->ifm_active |= IFM_FDX;
1057 else
1058 ifmr->ifm_active |= IFM_HDX;
1059 }
1060}
1061
1062static int
1063igb_media_change(struct ifnet *ifp)
1064{
1065 struct igb_softc *sc = ifp->if_softc;
1066 struct ifmedia *ifm = &sc->media;
1067
1068 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1069
1070 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1071 return EINVAL;
1072
1073 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1074 case IFM_AUTO:
1075 sc->hw.mac.autoneg = DO_AUTO_NEG;
1076 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1077 break;
1078
1079 case IFM_1000_LX:
1080 case IFM_1000_SX:
1081 case IFM_1000_T:
1082 sc->hw.mac.autoneg = DO_AUTO_NEG;
1083 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1084 break;
1085
1086 case IFM_100_TX:
1087 sc->hw.mac.autoneg = FALSE;
1088 sc->hw.phy.autoneg_advertised = 0;
1089 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1090 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1091 else
1092 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1093 break;
1094
1095 case IFM_10_T:
1096 sc->hw.mac.autoneg = FALSE;
1097 sc->hw.phy.autoneg_advertised = 0;
1098 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1099 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1100 else
1101 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1102 break;
1103
1104 default:
1105 if_printf(ifp, "Unsupported media type\n");
1106 break;
1107 }
1108
1109 igb_init(sc);
1110
1111 return 0;
1112}
1113
1114static void
1115igb_set_promisc(struct igb_softc *sc)
1116{
1117 struct ifnet *ifp = &sc->arpcom.ac_if;
1118 struct e1000_hw *hw = &sc->hw;
1119 uint32_t reg;
1120
1121 if (sc->vf_ifp) {
1122 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1123 return;
1124 }
1125
1126 reg = E1000_READ_REG(hw, E1000_RCTL);
1127 if (ifp->if_flags & IFF_PROMISC) {
1128 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1129 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1130 } else if (ifp->if_flags & IFF_ALLMULTI) {
1131 reg |= E1000_RCTL_MPE;
1132 reg &= ~E1000_RCTL_UPE;
1133 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1134 }
1135}
1136
1137static void
1138igb_disable_promisc(struct igb_softc *sc)
1139{
1140 struct e1000_hw *hw = &sc->hw;
1141 uint32_t reg;
1142
1143 if (sc->vf_ifp) {
1144 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1145 return;
1146 }
1147 reg = E1000_READ_REG(hw, E1000_RCTL);
1148 reg &= ~E1000_RCTL_UPE;
1149 reg &= ~E1000_RCTL_MPE;
1150 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1151}
1152
1153static void
1154igb_set_multi(struct igb_softc *sc)
1155{
1156 struct ifnet *ifp = &sc->arpcom.ac_if;
1157 struct ifmultiaddr *ifma;
1158 uint32_t reg_rctl = 0;
1159 uint8_t *mta;
1160 int mcnt = 0;
1161
1162 mta = sc->mta;
1163 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1164
1165 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1166 if (ifma->ifma_addr->sa_family != AF_LINK)
1167 continue;
1168
1169 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1170 break;
1171
1172 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1173 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1174 mcnt++;
1175 }
1176
1177 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1178 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1179 reg_rctl |= E1000_RCTL_MPE;
1180 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1181 } else {
1182 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1183 }
1184}
1185
1186static void
1187igb_timer(void *xsc)
1188{
1189 struct igb_softc *sc = xsc;
1f7e3916 1190
27dd00d6 1191 lwkt_serialize_enter(&sc->main_serialize);
1f7e3916
SZ
1192
1193 igb_update_link_status(sc);
1194 igb_update_stats_counters(sc);
1195
7b61c9f2 1196 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1f7e3916 1197
27dd00d6 1198 lwkt_serialize_exit(&sc->main_serialize);
1f7e3916
SZ
1199}
1200
1201static void
1202igb_update_link_status(struct igb_softc *sc)
1203{
1204 struct ifnet *ifp = &sc->arpcom.ac_if;
1205 struct e1000_hw *hw = &sc->hw;
1206 uint32_t link_check, thstat, ctrl;
1207
1208 link_check = thstat = ctrl = 0;
1209
1210 /* Get the cached link value or read for real */
1211 switch (hw->phy.media_type) {
1212 case e1000_media_type_copper:
1213 if (hw->mac.get_link_status) {
1214 /* Do the work to read phy */
1215 e1000_check_for_link(hw);
1216 link_check = !hw->mac.get_link_status;
1217 } else {
1218 link_check = TRUE;
1219 }
1220 break;
1221
1222 case e1000_media_type_fiber:
1223 e1000_check_for_link(hw);
1224 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1225 break;
1226
1227 case e1000_media_type_internal_serdes:
1228 e1000_check_for_link(hw);
1229 link_check = hw->mac.serdes_has_link;
1230 break;
1231
1232 /* VF device is type_unknown */
1233 case e1000_media_type_unknown:
1234 e1000_check_for_link(hw);
1235 link_check = !hw->mac.get_link_status;
1236 /* Fall thru */
1237 default:
1238 break;
1239 }
1240
1241 /* Check for thermal downshift or shutdown */
1242 if (hw->mac.type == e1000_i350) {
1243 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1244 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1245 }
1246
1247 /* Now we check if a transition has happened */
1248 if (link_check && sc->link_active == 0) {
1249 e1000_get_speed_and_duplex(hw,
1250 &sc->link_speed, &sc->link_duplex);
1251 if (bootverbose) {
1252 if_printf(ifp, "Link is up %d Mbps %s\n",
1253 sc->link_speed,
1254 sc->link_duplex == FULL_DUPLEX ?
1255 "Full Duplex" : "Half Duplex");
1256 }
1257 sc->link_active = 1;
1258
1259 ifp->if_baudrate = sc->link_speed * 1000000;
1260 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1261 (thstat & E1000_THSTAT_LINK_THROTTLE))
1262 if_printf(ifp, "Link: thermal downshift\n");
1263 /* This can sleep */
1264 ifp->if_link_state = LINK_STATE_UP;
1265 if_link_state_change(ifp);
1266 } else if (!link_check && sc->link_active == 1) {
1267 ifp->if_baudrate = sc->link_speed = 0;
1268 sc->link_duplex = 0;
1269 if (bootverbose)
1270 if_printf(ifp, "Link is Down\n");
1271 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1272 (thstat & E1000_THSTAT_PWR_DOWN))
1273 if_printf(ifp, "Link: thermal shutdown\n");
1274 sc->link_active = 0;
1275 /* This can sleep */
1276 ifp->if_link_state = LINK_STATE_DOWN;
1277 if_link_state_change(ifp);
1278 }
1279}
1280
1281static void
1282igb_stop(struct igb_softc *sc)
1283{
1284 struct ifnet *ifp = &sc->arpcom.ac_if;
1285 int i;
1286
1287 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1288
1289 igb_disable_intr(sc);
1290
1291 callout_stop(&sc->timer);
1292
9ed293e0 1293 ifp->if_flags &= ~IFF_RUNNING;
16109efc 1294 for (i = 0; i < sc->tx_ring_cnt; ++i) {
f0a26983 1295 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
16109efc 1296 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
ddaf4d42 1297 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
16109efc 1298 }
1f7e3916
SZ
1299
1300 e1000_reset_hw(&sc->hw);
1301 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1302
1303 e1000_led_off(&sc->hw);
1304 e1000_cleanup_led(&sc->hw);
1305
27866bf1 1306 for (i = 0; i < sc->tx_ring_cnt; ++i)
1f7e3916 1307 igb_free_tx_ring(&sc->tx_rings[i]);
27866bf1 1308 for (i = 0; i < sc->rx_ring_cnt; ++i)
1f7e3916
SZ
1309 igb_free_rx_ring(&sc->rx_rings[i]);
1310}
1311
1312static void
1313igb_reset(struct igb_softc *sc)
1314{
1315 struct ifnet *ifp = &sc->arpcom.ac_if;
1316 struct e1000_hw *hw = &sc->hw;
1317 struct e1000_fc_info *fc = &hw->fc;
1318 uint32_t pba = 0;
1319 uint16_t hwm;
1320
1321 /* Let the firmware know the OS is in control */
1322 igb_get_hw_control(sc);
1323
1324 /*
1325 * Packet Buffer Allocation (PBA)
1326 * Writing PBA sets the receive portion of the buffer
1327 * the remainder is used for the transmit buffer.
1328 */
1329 switch (hw->mac.type) {
1330 case e1000_82575:
1331 pba = E1000_PBA_32K;
1332 break;
1333
1334 case e1000_82576:
1335 case e1000_vfadapt:
1336 pba = E1000_READ_REG(hw, E1000_RXPBS);
1337 pba &= E1000_RXPBS_SIZE_MASK_82576;
1338 break;
1339
1340 case e1000_82580:
1341 case e1000_i350:
1342 case e1000_vfadapt_i350:
1343 pba = E1000_READ_REG(hw, E1000_RXPBS);
1344 pba = e1000_rxpbs_adjust_82580(pba);
1345 break;
1346 /* XXX pba = E1000_PBA_35K; */
1347
1348 default:
1349 break;
1350 }
1351
1352 /* Special needs in case of Jumbo frames */
1353 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1354 uint32_t tx_space, min_tx, min_rx;
1355
1356 pba = E1000_READ_REG(hw, E1000_PBA);
1357 tx_space = pba >> 16;
1358 pba &= 0xffff;
1359
1360 min_tx = (sc->max_frame_size +
1361 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1362 min_tx = roundup2(min_tx, 1024);
1363 min_tx >>= 10;
1364 min_rx = sc->max_frame_size;
1365 min_rx = roundup2(min_rx, 1024);
1366 min_rx >>= 10;
1367 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1368 pba = pba - (min_tx - tx_space);
1369 /*
1370 * if short on rx space, rx wins
1371 * and must trump tx adjustment
1372 */
1373 if (pba < min_rx)
1374 pba = min_rx;
1375 }
1376 E1000_WRITE_REG(hw, E1000_PBA, pba);
1377 }
1378
1379 /*
1380 * These parameters control the automatic generation (Tx) and
1381 * response (Rx) to Ethernet PAUSE frames.
1382 * - High water mark should allow for at least two frames to be
1383 * received after sending an XOFF.
1384 * - Low water mark works best when it is very near the high water mark.
1385 * This allows the receiver to restart by sending XON when it has
1386 * drained a bit.
1387 */
1388 hwm = min(((pba << 10) * 9 / 10),
1389 ((pba << 10) - 2 * sc->max_frame_size));
1390
1391 if (hw->mac.type < e1000_82576) {
1392 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1393 fc->low_water = fc->high_water - 8;
1394 } else {
1395 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1396 fc->low_water = fc->high_water - 16;
1397 }
1398 fc->pause_time = IGB_FC_PAUSE_TIME;
1399 fc->send_xon = TRUE;
1400
1401 /* Issue a global reset */
1402 e1000_reset_hw(hw);
1403 E1000_WRITE_REG(hw, E1000_WUC, 0);
1404
1405 if (e1000_init_hw(hw) < 0)
1406 if_printf(ifp, "Hardware Initialization Failed\n");
1407
1408 /* Setup DMA Coalescing */
1409 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1410 uint32_t reg;
1411
1412 hwm = (pba - 4) << 10;
1413 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1414 & E1000_DMACR_DMACTHR_MASK;
1415
1416 /* transition to L0x or L1 if available..*/
1417 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1418
1419 /* timer = +-1000 usec in 32usec intervals */
1420 reg |= (1000 >> 5);
1421 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1422
1423 /* No lower threshold */
1424 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1425
1426 /* set hwm to PBA - 2 * max frame size */
1427 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1428
1429 /* Set the interval before transition */
1430 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1431 reg |= 0x800000FF; /* 255 usec */
1432 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1433
1434 /* free space in tx packet buffer to wake from DMA coal */
1435 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1436 (20480 - (2 * sc->max_frame_size)) >> 6);
1437
1438 /* make low power state decision controlled by DMA coal */
1439 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1440 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1441 reg | E1000_PCIEMISC_LX_DECISION);
1442 if_printf(ifp, "DMA Coalescing enabled\n");
1443 }
1444
1445 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1446 e1000_get_phy_info(hw);
1447 e1000_check_for_link(hw);
1448}
1449
1450static void
1451igb_setup_ifp(struct igb_softc *sc)
1452{
1453 struct ifnet *ifp = &sc->arpcom.ac_if;
1454
1f7e3916
SZ
1455 ifp->if_softc = sc;
1456 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
9c0ecdcc 1457 ifp->if_init = igb_init;
1f7e3916
SZ
1458 ifp->if_ioctl = igb_ioctl;
1459 ifp->if_start = igb_start;
7d235eb5
SZ
1460 ifp->if_serialize = igb_serialize;
1461 ifp->if_deserialize = igb_deserialize;
1462 ifp->if_tryserialize = igb_tryserialize;
1463#ifdef INVARIANTS
1464 ifp->if_serialize_assert = igb_serialize_assert;
1465#endif
d0f59cad
SZ
1466#ifdef IFPOLL_ENABLE
1467 ifp->if_npoll = igb_npoll;
1f7e3916 1468#endif
1f7e3916 1469
91b8700a 1470 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1f7e3916 1471 ifq_set_ready(&ifp->if_snd);
2dc56c28 1472 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1f7e3916 1473
dd3f3290
SZ
1474 ifp->if_mapsubq = ifq_mapsubq_mask;
1475 ifq_set_subq_mask(&ifp->if_snd, 0);
1476
1f7e3916
SZ
1477 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1478
1479 ifp->if_capabilities =
23f6ffe4 1480 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
8d6600da
SZ
1481 if (IGB_ENABLE_HWRSS(sc))
1482 ifp->if_capabilities |= IFCAP_RSS;
1f7e3916 1483 ifp->if_capenable = ifp->if_capabilities;
23f6ffe4 1484 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1f7e3916
SZ
1485
1486 /*
1487 * Tell the upper layer(s) we support long frames
1488 */
1489 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1490
1491 /*
1492 * Specify the media types supported by this adapter and register
1493 * callbacks to update media and link information
1494 */
1495 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1496 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1497 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1498 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1499 0, NULL);
1500 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1501 } else {
1502 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1503 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1504 0, NULL);
1505 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1506 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1507 0, NULL);
1508 if (sc->hw.phy.type != e1000_phy_ife) {
1509 ifmedia_add(&sc->media,
1510 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1511 ifmedia_add(&sc->media,
1512 IFM_ETHER | IFM_1000_T, 0, NULL);
1513 }
1514 }
1515 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1516 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1517}
1518
1519static void
1520igb_add_sysctl(struct igb_softc *sc)
1521{
9c0ecdcc 1522 char node[32];
8d6600da 1523 int i;
8d6600da 1524
1f7e3916
SZ
1525 sysctl_ctx_init(&sc->sysctl_ctx);
1526 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1527 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1528 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1529 if (sc->sysctl_tree == NULL) {
1530 device_printf(sc->dev, "can't add sysctl node\n");
1531 return;
1532 }
1533
1534 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1535 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1536 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
be922da6
SZ
1537 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1538 "# of RX rings used");
1539 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
d802cc67
SZ
1540 OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1541 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1542 OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1543 "# of TX rings used");
1544 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1545 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1546 "# of RX descs");
1f7e3916 1547 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
8d6600da
SZ
1548 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1549 "# of TX descs");
1f7e3916 1550
9c0ecdcc
SZ
1551 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1552 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1553 SYSCTL_CHILDREN(sc->sysctl_tree),
1554 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1555 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1556 } else {
1557 for (i = 0; i < sc->msix_cnt; ++i) {
1558 struct igb_msix_data *msix = &sc->msix_data[i];
1559
1560 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1561 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1562 SYSCTL_CHILDREN(sc->sysctl_tree),
1563 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1564 msix, 0, igb_sysctl_msix_rate, "I",
1565 msix->msix_rate_desc);
1566 }
1567 }
b6220144
SZ
1568
1569 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1570 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1571 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
8d6600da
SZ
1572 "# of segments per TX interrupt");
1573
708575bb
SZ
1574 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1575 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1576 sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
9d8e892a
SZ
1577 "# of segments sent before write to hardware register");
1578
1579 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1580 OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1581 sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1582 "# of segments received before write to hardware register");
871c0e2b 1583
d0f59cad
SZ
1584#ifdef IFPOLL_ENABLE
1585 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1586 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1587 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1588 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1589 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1590 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1591#endif
1592
8d6600da
SZ
1593#ifdef IGB_RSS_DEBUG
1594 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1595 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1596 "RSS debug level");
1597 for (i = 0; i < sc->rx_ring_cnt; ++i) {
9c0ecdcc 1598 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
8d6600da 1599 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
9c0ecdcc 1600 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
8d6600da 1601 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
b56e8196 1602 }
9d8e892a 1603#endif
5d1c889d
SZ
1604#ifdef IGB_TSS_DEBUG
1605 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1606 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1607 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1608 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1609 CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1610 }
1611#endif
1f7e3916
SZ
1612}
1613
1614static int
a619b256 1615igb_alloc_rings(struct igb_softc *sc)
1f7e3916
SZ
1616{
1617 int error, i;
1618
1f7e3916
SZ
1619 /*
1620 * Create top level busdma tag
1621 */
1622 error = bus_dma_tag_create(NULL, 1, 0,
1623 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1624 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1625 &sc->parent_tag);
1626 if (error) {
1627 device_printf(sc->dev, "could not create top level DMA tag\n");
1628 return error;
1629 }
1630
1631 /*
1632 * Allocate TX descriptor rings and buffers
1633 */
7b269c72
SZ
1634 sc->tx_rings = kmalloc_cachealign(
1635 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1f7e3916 1636 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1637 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1f7e3916
SZ
1638 struct igb_tx_ring *txr = &sc->tx_rings[i];
1639
1640 /* Set up some basics */
1641 txr->sc = sc;
1642 txr->me = i;
7d235eb5 1643 lwkt_serialize_init(&txr->tx_serialize);
1f7e3916
SZ
1644
1645 error = igb_create_tx_ring(txr);
1646 if (error)
1647 return error;
1648 }
1649
1650 /*
1651 * Allocate RX descriptor rings and buffers
1652 */
7b269c72
SZ
1653 sc->rx_rings = kmalloc_cachealign(
1654 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1f7e3916 1655 M_DEVBUF, M_WAITOK | M_ZERO);
27866bf1 1656 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1f7e3916
SZ
1657 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1658
1659 /* Set up some basics */
1660 rxr->sc = sc;
1661 rxr->me = i;
7d235eb5 1662 lwkt_serialize_init(&rxr->rx_serialize);
1f7e3916
SZ
1663
1664 error = igb_create_rx_ring(rxr);
1665 if (error)
1666 return error;
1667 }
1668
1f7e3916
SZ
1669 return 0;
1670}
1671
1672static void
a619b256 1673igb_free_rings(struct igb_softc *sc)
1f7e3916
SZ
1674{
1675 int i;
1676
1f7e3916 1677 if (sc->tx_rings != NULL) {
91b8700a
SZ
1678 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1679 struct igb_tx_ring *txr = &sc->tx_rings[i];
1680
1681 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1682 }
1f7e3916
SZ
1683 kfree(sc->tx_rings, M_DEVBUF);
1684 }
1685
1686 if (sc->rx_rings != NULL) {
91b8700a
SZ
1687 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1688 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1689
1690 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1691 }
1f7e3916
SZ
1692 kfree(sc->rx_rings, M_DEVBUF);
1693 }
1694}
1695
1696static int
1697igb_create_tx_ring(struct igb_tx_ring *txr)
1698{
c1a8a339 1699 int tsize, error, i, ntxd;
1f7e3916
SZ
1700
1701 /*
1702 * Validate number of transmit descriptors. It must not exceed
1703 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1704 */
c1a8a339
SZ
1705 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1706 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1707 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1f7e3916
SZ
1708 device_printf(txr->sc->dev,
1709 "Using %d TX descriptors instead of %d!\n",
c1a8a339 1710 IGB_DEFAULT_TXD, ntxd);
91b8700a 1711 txr->num_tx_desc = IGB_DEFAULT_TXD;
1f7e3916 1712 } else {
c1a8a339 1713 txr->num_tx_desc = ntxd;
1f7e3916
SZ
1714 }
1715
1716 /*
1717 * Allocate TX descriptor ring
1718 */
91b8700a 1719 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1f7e3916
SZ
1720 IGB_DBA_ALIGN);
1721 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1722 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1723 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1724 if (txr->txdma.dma_vaddr == NULL) {
1725 device_printf(txr->sc->dev,
1726 "Unable to allocate TX Descriptor memory\n");
1727 return ENOMEM;
1728 }
1729 txr->tx_base = txr->txdma.dma_vaddr;
1730 bzero(txr->tx_base, tsize);
1731
e2a02a4c
SZ
1732 tsize = __VM_CACHELINE_ALIGN(
1733 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1734 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1f7e3916
SZ
1735
1736 /*
b6220144
SZ
1737 * Allocate TX head write-back buffer
1738 */
1739 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1740 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1741 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1742 if (txr->tx_hdr == NULL) {
1743 device_printf(txr->sc->dev,
1744 "Unable to allocate TX head write-back buffer\n");
1745 return ENOMEM;
1746 }
1747
1748 /*
1f7e3916
SZ
1749 * Create DMA tag for TX buffers
1750 */
1751 error = bus_dma_tag_create(txr->sc->parent_tag,
1752 1, 0, /* alignment, bounds */
1753 BUS_SPACE_MAXADDR, /* lowaddr */
1754 BUS_SPACE_MAXADDR, /* highaddr */
1755 NULL, NULL, /* filter, filterarg */
1756 IGB_TSO_SIZE, /* maxsize */
1757 IGB_MAX_SCATTER, /* nsegments */
1758 PAGE_SIZE, /* maxsegsize */
1759 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1760 BUS_DMA_ONEBPAGE, /* flags */
1761 &txr->tx_tag);
1762 if (error) {
1763 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1764 kfree(txr->tx_buf, M_DEVBUF);
1765 txr->tx_buf = NULL;
1766 return error;
1767 }
1768
1769 /*
1770 * Create DMA maps for TX buffers
1771 */
91b8700a 1772 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1773 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1774
1775 error = bus_dmamap_create(txr->tx_tag,
1776 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1777 if (error) {
1778 device_printf(txr->sc->dev,
1779 "Unable to create TX DMA map\n");
1780 igb_destroy_tx_ring(txr, i);
1781 return error;
1782 }
1783 }
b6220144 1784
81b8cfc6
SZ
1785 if (txr->sc->hw.mac.type == e1000_82575)
1786 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1787
b6220144
SZ
1788 /*
1789 * Initialize various watermark
1790 */
1791 txr->spare_desc = IGB_TX_SPARE;
91b8700a 1792 txr->intr_nsegs = txr->num_tx_desc / 16;
5a612d02 1793 txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
91b8700a
SZ
1794 txr->oact_hi_desc = txr->num_tx_desc / 2;
1795 txr->oact_lo_desc = txr->num_tx_desc / 8;
b6220144
SZ
1796 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1797 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1798 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1799 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1800
1f7e3916
SZ
1801 return 0;
1802}
1803
1804static void
1805igb_free_tx_ring(struct igb_tx_ring *txr)
1806{
1807 int i;
1808
91b8700a 1809 for (i = 0; i < txr->num_tx_desc; ++i) {
1f7e3916
SZ
1810 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1811
1812 if (txbuf->m_head != NULL) {
1813 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1814 m_freem(txbuf->m_head);
1815 txbuf->m_head = NULL;
1816 }
1817 }
1818}
1819
1820static void
1821igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1822{
1823 int i;
1824
1825 if (txr->txdma.dma_vaddr != NULL) {
1826 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1827 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1828 txr->txdma.dma_map);
1829 bus_dma_tag_destroy(txr->txdma.dma_tag);
1830 txr->txdma.dma_vaddr = NULL;
1831 }
1832
b6220144
SZ
1833 if (txr->tx_hdr != NULL) {
1834 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1835 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1836 txr->tx_hdr_dmap);
1837 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1838 txr->tx_hdr = NULL;
1839 }
1840
1f7e3916
SZ
1841 if (txr->tx_buf == NULL)
1842 return;
1843
1844 for (i = 0; i < ndesc; ++i) {
1845 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1846
1847 KKASSERT(txbuf->m_head == NULL);
1848 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1849 }
1850 bus_dma_tag_destroy(txr->tx_tag);
1851
1852 kfree(txr->tx_buf, M_DEVBUF);
1853 txr->tx_buf = NULL;
1854}
1855
1856static void
1857igb_init_tx_ring(struct igb_tx_ring *txr)
1858{
1f7e3916
SZ
1859 /* Clear the old descriptor contents */
1860 bzero(txr->tx_base,
91b8700a 1861 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1f7e3916 1862
b6220144
SZ
1863 /* Clear TX head write-back buffer */
1864 *(txr->tx_hdr) = 0;
1865
1f7e3916
SZ
1866 /* Reset indices */
1867 txr->next_avail_desc = 0;
1868 txr->next_to_clean = 0;
b6220144 1869 txr->tx_nsegs = 0;
1f7e3916
SZ
1870
1871 /* Set number of descriptors available */
91b8700a 1872 txr->tx_avail = txr->num_tx_desc;
ddaf4d42
SZ
1873
1874 /* Enable this TX ring */
1875 txr->tx_flags |= IGB_TXFLAG_ENABLED;
1f7e3916
SZ
1876}
1877
1878static void
1879igb_init_tx_unit(struct igb_softc *sc)
1880{
1881 struct e1000_hw *hw = &sc->hw;
1882 uint32_t tctl;
1883 int i;
1884
1885 /* Setup the Tx Descriptor Rings */
d802cc67 1886 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1f7e3916
SZ
1887 struct igb_tx_ring *txr = &sc->tx_rings[i];
1888 uint64_t bus_addr = txr->txdma.dma_paddr;
c3162c4e 1889 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1f7e3916 1890 uint32_t txdctl = 0;
b6220144 1891 uint32_t dca_txctrl;
1f7e3916
SZ
1892
1893 E1000_WRITE_REG(hw, E1000_TDLEN(i),
91b8700a 1894 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1f7e3916
SZ
1895 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1896 (uint32_t)(bus_addr >> 32));
1897 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1898 (uint32_t)bus_addr);
1899
1900 /* Setup the HW Tx Head and Tail descriptor pointers */
1901 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1902 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1903
b6220144
SZ
1904 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1905 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1906 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1907
54691ff1
SZ
1908 /*
1909 * Don't set WB_on_EITR:
1910 * - 82575 does not have it
1911 * - It almost has no effect on 82576, see:
1912 * 82576 specification update errata #26
1913 * - It causes unnecessary bus traffic
1914 */
b6220144 1915 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
c3162c4e 1916 (uint32_t)(hdr_paddr >> 32));
b6220144 1917 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
c3162c4e 1918 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
c7c6ca44
SZ
1919
1920 /*
1921 * WTHRESH is ignored by the hardware, since header
1922 * write back mode is used.
1923 */
1924 txdctl |= IGB_TX_PTHRESH;
1925 txdctl |= IGB_TX_HTHRESH << 8;
1926 txdctl |= IGB_TX_WTHRESH << 16;
1927 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1928 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1f7e3916
SZ
1929 }
1930
1931 if (sc->vf_ifp)
1932 return;
1933
1934 e1000_config_collision_dist(hw);
1935
1936 /* Program the Transmit Control Register */
1937 tctl = E1000_READ_REG(hw, E1000_TCTL);
1938 tctl &= ~E1000_TCTL_CT;
1939 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1940 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1941
1942 /* This write will effectively turn on the transmit unit. */
1943 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1944}
1945
1946static boolean_t
48faa653 1947igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1f7e3916
SZ
1948{
1949 struct e1000_adv_tx_context_desc *TXD;
1f7e3916 1950 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1f7e3916 1951 int ehdrlen, ctxd, ip_hlen = 0;
1f7e3916
SZ
1952 boolean_t offload = TRUE;
1953
1954 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1955 offload = FALSE;
1956
1957 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
48faa653 1958
1f7e3916 1959 ctxd = txr->next_avail_desc;
1f7e3916
SZ
1960 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1961
1962 /*
1963 * In advanced descriptors the vlan tag must
1964 * be placed into the context descriptor, thus
1965 * we need to be here just for that setup.
1966 */
1967 if (mp->m_flags & M_VLANTAG) {
23f6ffe4
SZ
1968 uint16_t vlantag;
1969
1f7e3916
SZ
1970 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1971 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1972 } else if (!offload) {
1973 return FALSE;
1974 }
1975
48faa653
SZ
1976 ehdrlen = mp->m_pkthdr.csum_lhlen;
1977 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1f7e3916
SZ
1978
1979 /* Set the ether header length */
1980 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
48faa653
SZ
1981 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1982 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1983 ip_hlen = mp->m_pkthdr.csum_iphlen;
1984 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1f7e3916 1985 }
1f7e3916 1986 vlan_macip_lens |= ip_hlen;
1f7e3916 1987
23f6ffe4 1988 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1f7e3916
SZ
1989 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1990 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1991 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1992 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1993
1994 /* 82575 needs the queue index added */
1995 if (txr->sc->hw.mac.type == e1000_82575)
1996 mss_l4len_idx = txr->me << 4;
1997
1998 /* Now copy bits into descriptor */
1999 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
2000 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
2001 TXD->seqnum_seed = htole32(0);
2002 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
2003
1f7e3916 2004 /* We've consumed the first desc, adjust counters */
91b8700a 2005 if (++ctxd == txr->num_tx_desc)
1f7e3916
SZ
2006 ctxd = 0;
2007 txr->next_avail_desc = ctxd;
2008 --txr->tx_avail;
2009
2010 return offload;
2011}
2012
2013static void
2014igb_txeof(struct igb_tx_ring *txr)
2015{
2016 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
b6220144 2017 int first, hdr, avail;
1f7e3916 2018
91b8700a 2019 if (txr->tx_avail == txr->num_tx_desc)
1f7e3916
SZ
2020 return;
2021
2022 first = txr->next_to_clean;
b6220144 2023 hdr = *(txr->tx_hdr);
1f7e3916 2024
b6220144
SZ
2025 if (first == hdr)
2026 return;
1f7e3916 2027
b6220144
SZ
2028 avail = txr->tx_avail;
2029 while (first != hdr) {
2030 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1f7e3916 2031
b6220144
SZ
2032 ++avail;
2033 if (txbuf->m_head) {
2034 bus_dmamap_unload(txr->tx_tag, txbuf->map);
2035 m_freem(txbuf->m_head);
2036 txbuf->m_head = NULL;
2037 ++ifp->if_opackets;
1f7e3916 2038 }
91b8700a 2039 if (++first == txr->num_tx_desc)
b6220144 2040 first = 0;
1f7e3916
SZ
2041 }
2042 txr->next_to_clean = first;
b6220144 2043 txr->tx_avail = avail;
1f7e3916
SZ
2044
2045 /*
9ed293e0 2046 * If we have a minimum free, clear OACTIVE
1f7e3916
SZ
2047 * to tell the stack that it is OK to send packets.
2048 */
b6220144 2049 if (IGB_IS_NOT_OACTIVE(txr)) {
f0a26983 2050 ifsq_clr_oactive(txr->ifsq);
1f7e3916 2051
1f7e3916
SZ
2052 /*
2053 * We have enough TX descriptors, turn off
b6220144
SZ
2054 * the watchdog. We allow small amount of
2055 * packets (roughly intr_nsegs) pending on
2056 * the transmit ring.
1f7e3916 2057 */
16109efc 2058 txr->tx_watchdog.wd_timer = 0;
1f7e3916
SZ
2059 }
2060}
2061
2062static int
2063igb_create_rx_ring(struct igb_rx_ring *rxr)
2064{
c1a8a339 2065 int rsize, i, error, nrxd;
1f7e3916
SZ
2066
2067 /*
2068 * Validate number of receive descriptors. It must not exceed
2069 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2070 */
c1a8a339
SZ
2071 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2072 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2073 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
1f7e3916
SZ
2074 device_printf(rxr->sc->dev,
2075 "Using %d RX descriptors instead of %d!\n",
c1a8a339 2076 IGB_DEFAULT_RXD, nrxd);
91b8700a 2077 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1f7e3916 2078 } else {
c1a8a339 2079 rxr->num_rx_desc = nrxd;
1f7e3916
SZ
2080 }
2081
2082 /*
2083 * Allocate RX descriptor ring
2084 */
91b8700a 2085 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1f7e3916
SZ
2086 IGB_DBA_ALIGN);
2087 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2088 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2089 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2090 &rxr->rxdma.dma_paddr);
2091 if (rxr->rxdma.dma_vaddr == NULL) {
2092 device_printf(rxr->sc->dev,
2093 "Unable to allocate RxDescriptor memory\n");
2094 return ENOMEM;
2095 }
2096 rxr->rx_base = rxr->rxdma.dma_vaddr;
2097 bzero(rxr->rx_base, rsize);
2098
e2a02a4c
SZ
2099 rsize = __VM_CACHELINE_ALIGN(
2100 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2101 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
1f7e3916
SZ
2102
2103 /*
2104 * Create DMA tag for RX buffers
2105 */
2106 error = bus_dma_tag_create(rxr->sc->parent_tag,
2107 1, 0, /* alignment, bounds */
2108 BUS_SPACE_MAXADDR, /* lowaddr */
2109 BUS_SPACE_MAXADDR, /* highaddr */
2110 NULL, NULL, /* filter, filterarg */
2111 MCLBYTES, /* maxsize */
2112 1, /* nsegments */
2113 MCLBYTES, /* maxsegsize */
2114 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2115 &rxr->rx_tag);
2116 if (error) {
2117 device_printf(rxr->sc->dev,
2118 "Unable to create RX payload DMA tag\n");
2119 kfree(rxr->rx_buf, M_DEVBUF);
2120 rxr->rx_buf = NULL;
2121 return error;
2122 }
2123
2124 /*
2125 * Create spare DMA map for RX buffers
2126 */
2127 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2128 &rxr->rx_sparemap);
2129 if (error) {
2130 device_printf(rxr->sc->dev,
2131 "Unable to create spare RX DMA maps\n");
2132 bus_dma_tag_destroy(rxr->rx_tag);
2133 kfree(rxr->rx_buf, M_DEVBUF);
2134 rxr->rx_buf = NULL;
2135 return error;
2136 }
2137
2138 /*
2139 * Create DMA maps for RX buffers
2140 */
91b8700a 2141 for (i = 0; i < rxr->num_rx_desc; i++) {
1f7e3916
SZ
2142 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2143
2144 error = bus_dmamap_create(rxr->rx_tag,
2145 BUS_DMA_WAITOK, &rxbuf->map);
2146 if (error) {
2147 device_printf(rxr->sc->dev,
2148 "Unable to create RX DMA maps\n");
2149 igb_destroy_rx_ring(rxr, i);
2150 return error;
2151 }
2152 }
b56e8196
SZ
2153
2154 /*
2155 * Initialize various watermark
2156 */
5a612d02 2157 rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
b56e8196 2158
1f7e3916
SZ
2159 return 0;
2160}
2161
2162static void
2163igb_free_rx_ring(struct igb_rx_ring *rxr)
2164{
2165 int i;
2166
91b8700a 2167 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2168 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2169
2170 if (rxbuf->m_head != NULL) {
2171 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2172 m_freem(rxbuf->m_head);
2173 rxbuf->m_head = NULL;
2174 }
2175 }
2176
2177 if (rxr->fmp != NULL)
2178 m_freem(rxr->fmp);
2179 rxr->fmp = NULL;
2180 rxr->lmp = NULL;
2181}
2182
2183static void
2184igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2185{
2186 int i;
2187
2188 if (rxr->rxdma.dma_vaddr != NULL) {
2189 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2190 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2191 rxr->rxdma.dma_map);
2192 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2193 rxr->rxdma.dma_vaddr = NULL;
2194 }
2195
2196 if (rxr->rx_buf == NULL)
2197 return;
2198
2199 for (i = 0; i < ndesc; ++i) {
2200 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2201
2202 KKASSERT(rxbuf->m_head == NULL);
2203 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2204 }
2205 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2206 bus_dma_tag_destroy(rxr->rx_tag);
2207
2208 kfree(rxr->rx_buf, M_DEVBUF);
2209 rxr->rx_buf = NULL;
2210}
2211
2212static void
2213igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2214{
2215 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2216 rxd->wb.upper.status_error = 0;
2217}
2218
2219static int
2220igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2221{
2222 struct mbuf *m;
2223 bus_dma_segment_t seg;
2224 bus_dmamap_t map;
2225 struct igb_rx_buf *rxbuf;
2226 int error, nseg;
2227
2228 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2229 if (m == NULL) {
2230 if (wait) {
2231 if_printf(&rxr->sc->arpcom.ac_if,
2232 "Unable to allocate RX mbuf\n");
2233 }
2234 return ENOBUFS;
2235 }
2236 m->m_len = m->m_pkthdr.len = MCLBYTES;
2237
2238 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2239 m_adj(m, ETHER_ALIGN);
2240
2241 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2242 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2243 if (error) {
2244 m_freem(m);
2245 if (wait) {
2246 if_printf(&rxr->sc->arpcom.ac_if,
2247 "Unable to load RX mbuf\n");
2248 }
2249 return error;
2250 }
2251
2252 rxbuf = &rxr->rx_buf[i];
2253 if (rxbuf->m_head != NULL)
2254 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2255
2256 map = rxbuf->map;
2257 rxbuf->map = rxr->rx_sparemap;
2258 rxr->rx_sparemap = map;
2259
2260 rxbuf->m_head = m;
2261 rxbuf->paddr = seg.ds_addr;
2262
2263 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2264 return 0;
2265}
2266
2267static int
2268igb_init_rx_ring(struct igb_rx_ring *rxr)
2269{
2270 int i;
2271
2272 /* Clear the ring contents */
2273 bzero(rxr->rx_base,
91b8700a 2274 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
1f7e3916
SZ
2275
2276 /* Now replenish the ring mbufs */
91b8700a 2277 for (i = 0; i < rxr->num_rx_desc; ++i) {
1f7e3916
SZ
2278 int error;
2279
2280 error = igb_newbuf(rxr, i, TRUE);
2281 if (error)
2282 return error;
2283 }
2284
2285 /* Setup our descriptor indices */
2286 rxr->next_to_check = 0;
2287
2288 rxr->fmp = NULL;
2289 rxr->lmp = NULL;
2290 rxr->discard = FALSE;
2291
2292 return 0;
2293}
2294
2295static void
2296igb_init_rx_unit(struct igb_softc *sc)
2297{
2298 struct ifnet *ifp = &sc->arpcom.ac_if;
2299 struct e1000_hw *hw = &sc->hw;
2300 uint32_t rctl, rxcsum, srrctl = 0;
2301 int i;
2302
2303 /*
2304 * Make sure receives are disabled while setting
2305 * up the descriptor ring
2306 */
2307 rctl = E1000_READ_REG(hw, E1000_RCTL);
2308 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2309
2310#if 0
2311 /*
2312 ** Set up for header split
2313 */
2314 if (igb_header_split) {
2315 /* Use a standard mbuf for the header */
2316 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2317 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2318 } else
2319#endif
2320 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2321
2322 /*
2323 ** Set up for jumbo frames
2324 */
2325 if (ifp->if_mtu > ETHERMTU) {
2326 rctl |= E1000_RCTL_LPE;
2327#if 0
2328 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2329 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2330 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2331 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2332 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2333 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2334 }
2335 /* Set maximum packet len */
2336 psize = adapter->max_frame_size;
2337 /* are we on a vlan? */
2338 if (adapter->ifp->if_vlantrunk != NULL)
2339 psize += VLAN_TAG_SIZE;
2340 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2341#else
2342 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2343 rctl |= E1000_RCTL_SZ_2048;
2344#endif
2345 } else {
2346 rctl &= ~E1000_RCTL_LPE;
2347 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2348 rctl |= E1000_RCTL_SZ_2048;
2349 }
2350
2351 /* Setup the Base and Length of the Rx Descriptor Rings */
be922da6 2352 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2353 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2354 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2355 uint32_t rxdctl;
2356
2357 E1000_WRITE_REG(hw, E1000_RDLEN(i),
91b8700a 2358 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
1f7e3916
SZ
2359 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2360 (uint32_t)(bus_addr >> 32));
2361 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2362 (uint32_t)bus_addr);
2363 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2364 /* Enable this Queue */
2365 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2366 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2367 rxdctl &= 0xFFF00000;
2368 rxdctl |= IGB_RX_PTHRESH;
2369 rxdctl |= IGB_RX_HTHRESH << 8;
54691ff1
SZ
2370 /*
2371 * Don't set WTHRESH to a value above 1 on 82576, see:
2372 * 82576 specification update errata #26
2373 */
1f7e3916
SZ
2374 rxdctl |= IGB_RX_WTHRESH << 16;
2375 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2376 }
2377
8d6600da
SZ
2378 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2379 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2380
1f7e3916 2381 /*
8d6600da
SZ
2382 * Receive Checksum Offload for TCP and UDP
2383 *
2384 * Checksum offloading is also enabled if multiple receive
2385 * queue is to be supported, since we need it to figure out
2386 * fragments.
1f7e3916 2387 */
8d6600da
SZ
2388 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2389 /*
2390 * NOTE:
2391 * PCSD must be enabled to enable multiple
2392 * receive queues.
2393 */
2394 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2395 E1000_RXCSUM_PCSD;
2396 } else {
2397 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2398 E1000_RXCSUM_PCSD);
2399 }
2400 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2401
2402 if (IGB_ENABLE_HWRSS(sc)) {
2403 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
d1218435
SZ
2404 uint32_t reta_shift;
2405 int j, r;
8d6600da
SZ
2406
2407 /*
2408 * NOTE:
2409 * When we reach here, RSS has already been disabled
2410 * in igb_stop(), so we could safely configure RSS key
2411 * and redirect table.
2412 */
2413
2414 /*
2415 * Configure RSS key
2416 */
2417 toeplitz_get_key(key, sizeof(key));
2418 for (i = 0; i < IGB_NRSSRK; ++i) {
2419 uint32_t rssrk;
2420
2421 rssrk = IGB_RSSRK_VAL(key, i);
2422 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2423
2424 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
1f7e3916 2425 }
1f7e3916
SZ
2426
2427 /*
8d6600da
SZ
2428 * Configure RSS redirect table in following fashion:
2429 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2430 */
2431 reta_shift = IGB_RETA_SHIFT;
2432 if (hw->mac.type == e1000_82575)
2433 reta_shift = IGB_RETA_SHIFT_82575;
8d6600da 2434
d1218435
SZ
2435 r = 0;
2436 for (j = 0; j < IGB_NRETA; ++j) {
2437 uint32_t reta = 0;
8d6600da 2438
d1218435
SZ
2439 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2440 uint32_t q;
2441
be922da6 2442 q = (r % sc->rx_ring_inuse) << reta_shift;
d1218435
SZ
2443 reta |= q << (8 * i);
2444 ++r;
2445 }
2446 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2447 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2448 }
8d6600da
SZ
2449
2450 /*
2451 * Enable multiple receive queues.
2452 * Enable IPv4 RSS standard hash functions.
2453 * Disable RSS interrupt on 82575
2454 */
2455 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2456 E1000_MRQC_ENABLE_RSS_4Q |
2457 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2458 E1000_MRQC_RSS_FIELD_IPV4);
1f7e3916 2459 }
1f7e3916
SZ
2460
2461 /* Setup the Receive Control Register */
2462 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2463 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2464 E1000_RCTL_RDMTS_HALF |
2465 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2466 /* Strip CRC bytes. */
2467 rctl |= E1000_RCTL_SECRC;
2468 /* Make sure VLAN Filters are off */
2469 rctl &= ~E1000_RCTL_VFE;
2470 /* Don't store bad packets */
2471 rctl &= ~E1000_RCTL_SBP;
2472
2473 /* Enable Receives */
2474 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2475
2476 /*
2477 * Setup the HW Rx Head and Tail Descriptor Pointers
2478 * - needs to be after enable
2479 */
be922da6 2480 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1f7e3916
SZ
2481 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2482
2483 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
91b8700a 2484 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
1f7e3916
SZ
2485 }
2486}
2487
2488static void
b56e8196
SZ
2489igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2490{
2491 if (--i < 0)
2492 i = rxr->num_rx_desc - 1;
2493 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2494}
2495
2496static void
1f7e3916
SZ
2497igb_rxeof(struct igb_rx_ring *rxr, int count)
2498{
2499 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2500 union e1000_adv_rx_desc *cur;
2501 uint32_t staterr;
b56e8196 2502 int i, ncoll = 0;
1f7e3916
SZ
2503
2504 i = rxr->next_to_check;
2505 cur = &rxr->rx_base[i];
2506 staterr = le32toh(cur->wb.upper.status_error);
2507
2508 if ((staterr & E1000_RXD_STAT_DD) == 0)
2509 return;
2510
2511 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
8d6600da 2512 struct pktinfo *pi = NULL, pi0;
1f7e3916
SZ
2513 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2514 struct mbuf *m = NULL;
2515 boolean_t eop;
2516
2517 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2518 if (eop)
2519 --count;
2520
b56e8196 2521 ++ncoll;
1f7e3916
SZ
2522 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2523 !rxr->discard) {
2524 struct mbuf *mp = rxbuf->m_head;
8d6600da 2525 uint32_t hash, hashtype;
1f7e3916
SZ
2526 uint16_t vlan;
2527 int len;
2528
2529 len = le16toh(cur->wb.upper.length);
2530 if (rxr->sc->hw.mac.type == e1000_i350 &&
2531 (staterr & E1000_RXDEXT_STATERR_LB))
2532 vlan = be16toh(cur->wb.upper.vlan);
2533 else
2534 vlan = le16toh(cur->wb.upper.vlan);
2535
8d6600da
SZ
2536 hash = le32toh(cur->wb.lower.hi_dword.rss);
2537 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2538 E1000_RXDADV_RSSTYPE_MASK;
2539
2540 IGB_RSS_DPRINTF(rxr->sc, 10,
2541 "ring%d, hash 0x%08x, hashtype %u\n",
2542 rxr->me, hash, hashtype);
2543
1f7e3916
SZ
2544 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2545 BUS_DMASYNC_POSTREAD);
2546
2547 if (igb_newbuf(rxr, i, FALSE) != 0) {
2548 ifp->if_iqdrops++;
2549 goto discard;
2550 }
2551
2552 mp->m_len = len;
2553 if (rxr->fmp == NULL) {
2554 mp->m_pkthdr.len = len;
2555 rxr->fmp = mp;
2556 rxr->lmp = mp;
2557 } else {
2558 rxr->lmp->m_next = mp;
2559 rxr->lmp = rxr->lmp->m_next;
2560 rxr->fmp->m_pkthdr.len += len;
2561 }
2562
2563 if (eop) {
2564 m = rxr->fmp;
2565 rxr->fmp = NULL;
2566 rxr->lmp = NULL;
2567
2568 m->m_pkthdr.rcvif = ifp;
2569 ifp->if_ipackets++;
2570
2571 if (ifp->if_capenable & IFCAP_RXCSUM)
2572 igb_rxcsum(staterr, m);
2573
2574 if (staterr & E1000_RXD_STAT_VP) {
2575 m->m_pkthdr.ether_vlantag = vlan;
2576 m->m_flags |= M_VLANTAG;
2577 }
2578
1f7e3916 2579 if (ifp->if_capenable & IFCAP_RSS) {
8d6600da
SZ
2580 pi = igb_rssinfo(m, &pi0,
2581 hash, hashtype, staterr);
1f7e3916 2582 }
8d6600da
SZ
2583#ifdef IGB_RSS_DEBUG
2584 rxr->rx_packets++;
1f7e3916
SZ
2585#endif
2586 }
2587 } else {
2588 ifp->if_ierrors++;
2589discard:
2590 igb_setup_rxdesc(cur, rxbuf);
2591 if (!eop)
2592 rxr->discard = TRUE;
2593 else
2594 rxr->discard = FALSE;
2595 if (rxr->fmp != NULL) {
2596 m_freem(rxr->fmp);
2597 rxr->fmp = NULL;
2598 rxr->lmp = NULL;
2599 }
2600 m = NULL;
2601 }
2602
2603 if (m != NULL)
8d6600da 2604 ether_input_pkt(ifp, m, pi);
1f7e3916
SZ
2605
2606 /* Advance our pointers to the next descriptor. */
91b8700a 2607 if (++i == rxr->num_rx_desc)
1f7e3916
SZ
2608 i = 0;
2609
9d8e892a 2610 if (ncoll >= rxr->wreg_nsegs) {
b56e8196
SZ
2611 igb_rx_refresh(rxr, i);
2612 ncoll = 0;
2613 }
2614
1f7e3916
SZ
2615 cur = &rxr->rx_base[i];
2616 staterr = le32toh(cur->wb.upper.status_error);
2617 }
2618 rxr->next_to_check = i;
2619
b56e8196
SZ
2620 if (ncoll > 0)
2621 igb_rx_refresh(rxr, i);
1f7e3916
SZ
2622}
2623
2624
2625static void
2626igb_set_vlan(struct igb_softc *sc)
2627{
2628 struct e1000_hw *hw = &sc->hw;
2629 uint32_t reg;
2630#if 0
2631 struct ifnet *ifp = sc->arpcom.ac_if;
2632#endif
2633
2634 if (sc->vf_ifp) {
2635 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2636 return;
2637 }
2638
2639 reg = E1000_READ_REG(hw, E1000_CTRL);
2640 reg |= E1000_CTRL_VME;
2641 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2642
2643#if 0
2644 /* Enable the Filter Table */
2645 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2646 reg = E1000_READ_REG(hw, E1000_RCTL);
2647 reg &= ~E1000_RCTL_CFIEN;
2648 reg |= E1000_RCTL_VFE;
2649 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650 }
2651#endif
2652
2653 /* Update the frame size */
2654 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2655 sc->max_frame_size + VLAN_TAG_SIZE);
2656
2657#if 0
2658 /* Don't bother with table if no vlans */
2659 if ((adapter->num_vlans == 0) ||
2660 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2661 return;
2662 /*
2663 ** A soft reset zero's out the VFTA, so
2664 ** we need to repopulate it now.
2665 */
2666 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2667 if (adapter->shadow_vfta[i] != 0) {
2668 if (adapter->vf_ifp)
2669 e1000_vfta_set_vf(hw,
2670 adapter->shadow_vfta[i], TRUE);
2671 else
2672 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2673 i, adapter->shadow_vfta[i]);
2674 }
2675#endif
2676}
2677
2678static void
2679igb_enable_intr(struct igb_softc *sc)
2680{
9c0ecdcc
SZ
2681 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2682 lwkt_serialize_handler_enable(&sc->main_serialize);
2683 } else {
2684 int i;
2685
2686 for (i = 0; i < sc->msix_cnt; ++i) {
2687 lwkt_serialize_handler_enable(
2688 sc->msix_data[i].msix_serialize);
2689 }
2690 }
1f7e3916 2691
f6167a56 2692 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
9c0ecdcc
SZ
2693 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2694 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2695 else
2696 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56
SZ
2697 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2698 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
1f7e3916
SZ
2699 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2700 } else {
2701 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2702 }
2703 E1000_WRITE_FLUSH(&sc->hw);
2704}
2705
2706static void
2707igb_disable_intr(struct igb_softc *sc)
2708{
f6167a56 2709 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
1f7e3916
SZ
2710 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2711 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
f6167a56 2712 }
1f7e3916
SZ
2713 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2714 E1000_WRITE_FLUSH(&sc->hw);
2715
9c0ecdcc
SZ
2716 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2717 lwkt_serialize_handler_disable(&sc->main_serialize);
2718 } else {
2719 int i;
2720
2721 for (i = 0; i < sc->msix_cnt; ++i) {
2722 lwkt_serialize_handler_disable(
2723 sc->msix_data[i].msix_serialize);
2724 }
2725 }
1f7e3916
SZ
2726}
2727
2728/*
2729 * Bit of a misnomer, what this really means is
2730 * to enable OS management of the system... aka
2731 * to disable special hardware management features
2732 */
2733static void
2734igb_get_mgmt(struct igb_softc *sc)
2735{
396b7048 2736 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2737 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2738 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2739
2740 /* disable hardware interception of ARP */
2741 manc &= ~E1000_MANC_ARP_EN;
2742
2743 /* enable receiving management packets to the host */
2744 manc |= E1000_MANC_EN_MNG2HOST;
2745 manc2h |= 1 << 5; /* Mng Port 623 */
2746 manc2h |= 1 << 6; /* Mng Port 664 */
2747 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2748 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2749 }
2750}
2751
2752/*
2753 * Give control back to hardware management controller
2754 * if there is one.
2755 */
2756static void
2757igb_rel_mgmt(struct igb_softc *sc)
2758{
396b7048 2759 if (sc->flags & IGB_FLAG_HAS_MGMT) {
1f7e3916
SZ
2760 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2761
2762 /* Re-enable hardware interception of ARP */
2763 manc |= E1000_MANC_ARP_EN;
2764 manc &= ~E1000_MANC_EN_MNG2HOST;
2765
2766 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2767 }
2768}
2769
2770/*
2771 * Sets CTRL_EXT:DRV_LOAD bit.
2772 *
2773 * For ASF and Pass Through versions of f/w this means that
2774 * the driver is loaded.
2775 */
2776static void
2777igb_get_hw_control(struct igb_softc *sc)
2778{
2779 uint32_t ctrl_ext;
2780
2781 if (sc->vf_ifp)
2782 return;
2783
2784 /* Let firmware know the driver has taken over */
2785 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2786 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2787 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2788}
2789
2790/*
2791 * Resets CTRL_EXT:DRV_LOAD bit.
2792 *
2793 * For ASF and Pass Through versions of f/w this means that the
2794 * driver is no longer loaded.
2795 */
2796static void
2797igb_rel_hw_control(struct igb_softc *sc)
2798{
2799 uint32_t ctrl_ext;
2800
2801 if (sc->vf_ifp)
2802 return;
2803
2804 /* Let firmware taken over control of h/w */
2805 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2806 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2807 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2808}
2809
2810static int
2811igb_is_valid_ether_addr(const uint8_t *addr)
2812{
2813 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2814
2815 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2816 return FALSE;
2817 return TRUE;
2818}
2819
2820/*
2821 * Enable PCI Wake On Lan capability
2822 */
2823static void
2824igb_enable_wol(device_t dev)
2825{
2826 uint16_t cap, status;
2827 uint8_t id;
2828
2829 /* First find the capabilities pointer*/
2830 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2831
2832 /* Read the PM Capabilities */
2833 id = pci_read_config(dev, cap, 1);
2834 if (id != PCIY_PMG) /* Something wrong */
2835 return;
2836
2837 /*
2838 * OK, we have the power capabilities,
2839 * so now get the status register
2840 */
2841 cap += PCIR_POWER_STATUS;
2842 status = pci_read_config(dev, cap, 2);
2843 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2844 pci_write_config(dev, cap, status, 2);
2845}
2846
2847static void
2848igb_update_stats_counters(struct igb_softc *sc)
2849{
2850 struct e1000_hw *hw = &sc->hw;
2851 struct e1000_hw_stats *stats;
2852 struct ifnet *ifp = &sc->arpcom.ac_if;
2853
2854 /*
2855 * The virtual function adapter has only a
2856 * small controlled set of stats, do only
2857 * those and return.
2858 */
2859 if (sc->vf_ifp) {
2860 igb_update_vf_stats_counters(sc);
2861 return;
2862 }
2863 stats = sc->stats;
2864
2865 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2866 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2867 stats->symerrs +=
2868 E1000_READ_REG(hw,E1000_SYMERRS);
2869 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2870 }
2871
2872 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2873 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2874 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2875 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2876
2877 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2878 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2879 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2880 stats->dc += E1000_READ_REG(hw, E1000_DC);
2881 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2882 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2883 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2884
2885 /*
2886 * For watchdog management we need to know if we have been
2887 * paused during the last interval, so capture that here.
2888 */
2889 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2890 stats->xoffrxc += sc->pause_frames;
2891 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2892 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2893 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2894 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2895 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2896 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2897 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2898 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2899 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2900 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2901 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2902 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2903
2904 /* For the 64-bit byte counters the low dword must be read first. */
2905 /* Both registers clear on the read of the high dword */
2906
2907 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2908 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2909 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2910 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2911
2912 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2913 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2914 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2915 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2916 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2917
2918 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2919 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2920
2921 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2922 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2923 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2924 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2925 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2926 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2927 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2928 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2929 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2930 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2931
2932 /* Interrupt Counts */
2933
2934 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2935 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2936 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2937 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2938 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2939 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2940 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2941 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2942 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2943
2944 /* Host to Card Statistics */
2945
2946 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2947 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2948 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2949 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2950 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2951 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2952 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2953 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2954 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2955 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2956 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2957 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2958 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2959 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2960
2961 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2962 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2963 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2964 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2965 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2966 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2967
2968 ifp->if_collisions = stats->colc;
2969
2970 /* Rx Errors */
2971 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2972 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2973
2974 /* Tx Errors */
2975 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2976
2977 /* Driver specific counters */
2978 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2979 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2980 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2981 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2982 sc->packet_buf_alloc_tx =
2983 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2984 sc->packet_buf_alloc_rx =
2985 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2986}
2987
2988static void
2989igb_vf_init_stats(struct igb_softc *sc)
2990{
2991 struct e1000_hw *hw = &sc->hw;
2992 struct e1000_vf_stats *stats;
2993
2994 stats = sc->stats;
2995 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2996 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2997 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2998 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2999 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
3000}
3001
3002static void
3003igb_update_vf_stats_counters(struct igb_softc *sc)
3004{
3005 struct e1000_hw *hw = &sc->hw;
3006 struct e1000_vf_stats *stats;
3007
3008 if (sc->link_speed == 0)
3009 return;
3010
3011 stats = sc->stats;
3012 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3013 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3014 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3015 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3016 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3017}
3018
d0f59cad 3019#ifdef IFPOLL_ENABLE
1f7e3916
SZ
3020
3021static void
2f00683b 3022igb_npoll_status(struct ifnet *ifp)
1f7e3916
SZ
3023{
3024 struct igb_softc *sc = ifp->if_softc;
3025 uint32_t reg_icr;
3026
d0f59cad 3027 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916 3028
d0f59cad
SZ
3029 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3030 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3031 sc->hw.mac.get_link_status = 1;
3032 igb_update_link_status(sc);
3033 }
3034}
7d235eb5 3035
d0f59cad
SZ
3036static void
3037igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3038{
3039 struct igb_tx_ring *txr = arg;
7d235eb5 3040
d0f59cad 3041 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3042
d0f59cad 3043 igb_txeof(txr);
f0a26983
SZ
3044 if (!ifsq_is_empty(txr->ifsq))
3045 ifsq_devstart(txr->ifsq);
d0f59cad
SZ
3046}
3047
3048static void
3049igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3050{
3051 struct igb_rx_ring *rxr = arg;
3052
3053 ASSERT_SERIALIZED(&rxr->rx_serialize);
3054
3055 igb_rxeof(rxr, cycle);
3056}
3057
3058static void
3059igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3060{
3061 struct igb_softc *sc = ifp->if_softc;
d802cc67 3062 int i, txr_cnt, rxr_cnt;
d0f59cad
SZ
3063
3064 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3065
3066 if (info) {
f0a26983 3067 int off;
d0f59cad
SZ
3068
3069 info->ifpi_status.status_func = igb_npoll_status;
3070 info->ifpi_status.serializer = &sc->main_serialize;
3071
d802cc67 3072 txr_cnt = igb_get_txring_inuse(sc, TRUE);
d0f59cad 3073 off = sc->tx_npoll_off;
d802cc67 3074 for (i = 0; i < txr_cnt; ++i) {
f0a26983
SZ
3075 struct igb_tx_ring *txr = &sc->tx_rings[i];
3076 int idx = i + off;
3077
3078 KKASSERT(idx < ncpus2);
3079 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3080 info->ifpi_tx[idx].arg = txr;
3081 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3082 ifsq_set_cpuid(txr->ifsq, idx);
3083 }
d0f59cad 3084
d802cc67 3085 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
d0f59cad 3086 off = sc->rx_npoll_off;
d802cc67 3087 for (i = 0; i < rxr_cnt; ++i) {
d0f59cad
SZ
3088 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3089 int idx = i + off;
3090
3091 KKASSERT(idx < ncpus2);
3092 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3093 info->ifpi_rx[idx].arg = rxr;
3094 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
1f7e3916 3095 }
d0f59cad
SZ
3096
3097 if (ifp->if_flags & IFF_RUNNING) {
d802cc67
SZ
3098 if (rxr_cnt == sc->rx_ring_inuse &&
3099 txr_cnt == sc->tx_ring_inuse)
d0f59cad
SZ
3100 igb_disable_intr(sc);
3101 else
3102 igb_init(sc);
3103 }
d0f59cad 3104 } else {
343c1194
SZ
3105 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3106 struct igb_tx_ring *txr = &sc->tx_rings[i];
3107
3108 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3109 }
3110
d0f59cad 3111 if (ifp->if_flags & IFF_RUNNING) {
d802cc67
SZ
3112 txr_cnt = igb_get_txring_inuse(sc, FALSE);
3113 rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3114
3115 if (rxr_cnt == sc->rx_ring_inuse &&
3116 txr_cnt == sc->tx_ring_inuse)
d0f59cad
SZ
3117 igb_enable_intr(sc);
3118 else
3119 igb_init(sc);
3120 }
1f7e3916
SZ
3121 }
3122}
3123
d0f59cad 3124#endif /* IFPOLL_ENABLE */
1f7e3916
SZ
3125
3126static void
3127igb_intr(void *xsc)
3128{
3129 struct igb_softc *sc = xsc;
3130 struct ifnet *ifp = &sc->arpcom.ac_if;
f6167a56
SZ
3131 uint32_t eicr;
3132
7d235eb5 3133 ASSERT_SERIALIZED(&sc->main_serialize);
f6167a56
SZ
3134
3135 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3136
3137 if (eicr == 0)
3138 return;
3139
3140 if (ifp->if_flags & IFF_RUNNING) {
f0a26983 3141 struct igb_tx_ring *txr = &sc->tx_rings[0];
7d235eb5 3142 int i;
f6167a56 3143
be922da6 3144 for (i = 0; i < sc->rx_ring_inuse; ++i) {
7d235eb5
SZ
3145 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3146
3147 if (eicr & rxr->rx_intr_mask) {
3148 lwkt_serialize_enter(&rxr->rx_serialize);
3149 igb_rxeof(rxr, -1);
3150 lwkt_serialize_exit(&rxr->rx_serialize);
3151 }
3152 }
3153
7d235eb5
SZ
3154 if (eicr & txr->tx_intr_mask) {
3155 lwkt_serialize_enter(&txr->tx_serialize);
3156 igb_txeof(txr);
f0a26983
SZ
3157 if (!ifsq_is_empty(txr->ifsq))
3158 ifsq_devstart(txr->ifsq);
7d235eb5 3159 lwkt_serialize_exit(&txr->tx_serialize);
f6167a56
SZ
3160 }
3161 }
3162
3163 if (eicr & E1000_EICR_OTHER) {
3164 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3165
3166 /* Link status change */
3167 if (icr & E1000_ICR_LSC) {
3168 sc->hw.mac.get_link_status = 1;
3169 igb_update_link_status(sc);
3170 }
3171 }
3172
3173 /*
3174 * Reading EICR has the side effect to clear interrupt mask,
3175 * so all interrupts need to be enabled here.
3176 */
3177 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3178}
3179
3180static void
9c0ecdcc 3181igb_intr_shared(void *xsc)
f6167a56
SZ
3182{
3183 struct igb_softc *sc = xsc;
3184 struct ifnet *ifp = &sc->arpcom.ac_if;
1f7e3916
SZ
3185 uint32_t reg_icr;
3186
7d235eb5 3187 ASSERT_SERIALIZED(&sc->main_serialize);
1f7e3916
SZ
3188
3189 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3190
3191 /* Hot eject? */
3192 if (reg_icr == 0xffffffff)
3193 return;
3194
3195 /* Definitely not our interrupt. */
3196 if (reg_icr == 0x0)
3197 return;
3198
3199 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3200 return;
3201
3202 if (ifp->if_flags & IFF_RUNNING) {
71b8b086
SZ
3203 if (reg_icr &
3204 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3205 int i;
7d235eb5 3206
71b8b086
SZ
3207 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3208 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1f7e3916 3209
71b8b086
SZ
3210 lwkt_serialize_enter(&rxr->rx_serialize);
3211 igb_rxeof(rxr, -1);
3212 lwkt_serialize_exit(&rxr->rx_serialize);
3213 }
7d235eb5
SZ
3214 }
3215
71b8b086
SZ
3216 if (reg_icr & E1000_ICR_TXDW) {
3217 struct igb_tx_ring *txr = &sc->tx_rings[0];
3218
3219 lwkt_serialize_enter(&txr->tx_serialize);
3220 igb_txeof(txr);
f0a26983
SZ
3221 if (!ifsq_is_empty(txr->ifsq))
3222 ifsq_devstart(txr->ifsq);
71b8b086
SZ
3223 lwkt_serialize_exit(&txr->tx_serialize);
3224 }
1f7e3916
SZ
3225 }
3226
3227 /* Link status change */
3228 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3229 sc->hw.mac.get_link_status = 1;
3230 igb_update_link_status(sc);
3231 }
3232
3233 if (reg_icr & E1000_ICR_RXO)
3234 sc->rx_overruns++;
3235}
3236
3237static int
871c0e2b
SZ
3238igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3239 int *segs_used, int *idx)
1f7e3916
SZ
3240{
3241 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3242 bus_dmamap_t map;
3243 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3244 union e1000_adv_tx_desc *txd = NULL;
3245 struct mbuf *m_head = *m_headp;
b6220144 3246 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
07e9f7c0 3247 int maxsegs, nsegs, i, j, error;
1f7e3916
SZ
3248 uint32_t hdrlen = 0;
3249
23f6ffe4
SZ
3250 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3251 error = igb_tso_pullup(txr, m_headp);
3252 if (error)
3253 return error;
3254 m_head = *m_headp;
3255 }
3256
1f7e3916
SZ
3257 /* Set basic descriptor constants */
3258 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3259 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3260 if (m_head->m_flags & M_VLANTAG)
3261 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3262
3263 /*
3264 * Map the packet for DMA.
1f7e3916 3265 */
b6220144 3266 tx_buf = &txr->tx_buf[txr->next_avail_desc];
1f7e3916
SZ
3267 tx_buf_mapped = tx_buf;
3268 map = tx_buf->map;
3269
b6220144
SZ
3270 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3271 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
1f7e3916
SZ
3272 if (maxsegs > IGB_MAX_SCATTER)
3273 maxsegs = IGB_MAX_SCATTER;
3274
3275 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3276 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3277 if (error) {
3278 if (error == ENOBUFS)
3279 txr->sc->mbuf_defrag_failed++;
3280 else
3281 txr->sc->no_tx_dma_setup++;
3282
3283 m_freem(*m_headp);
3284 *m_headp = NULL;
3285 return error;
3286 }
3287 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3288
3289 m_head = *m_headp;
3290
1f7e3916 3291 /*
66c68b4b
SZ
3292 * Set up the TX context descriptor, if any hardware offloading is
3293 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3294 * TX descriptor.
3295 *
3296 * Unlike these chips' predecessors (em/emx), TX context descriptor
3297 * will _not_ interfere TX data fetching pipelining.
1f7e3916
SZ
3298 */
3299 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
23f6ffe4
SZ
3300 igb_tso_ctx(txr, m_head, &hdrlen);
3301 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3302 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3303 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3304 txr->tx_nsegs++;
871c0e2b 3305 (*segs_used)++;
23f6ffe4 3306 } else if (igb_txcsum_ctx(txr, m_head)) {
48faa653
SZ
3307 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3308 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
1f7e3916
SZ
3309 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3310 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
b6220144 3311 txr->tx_nsegs++;
871c0e2b 3312 (*segs_used)++;
1f7e3916 3313 }
1f7e3916 3314
871c0e2b 3315 *segs_used += nsegs;
b6220144
SZ
3316 txr->tx_nsegs += nsegs;
3317 if (txr->tx_nsegs >= txr->intr_nsegs) {
3318 /*
3319 * Report Status (RS) is turned on every intr_nsegs
3320 * descriptors (roughly).
3321 */
3322 txr->tx_nsegs = 0;
3323 cmd_rs = E1000_ADVTXD_DCMD_RS;
3324 }
3325
1f7e3916
SZ
3326 /* Calculate payload length */
3327 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3328 << E1000_ADVTXD_PAYLEN_SHIFT);
3329
3330 /* 82575 needs the queue index added */
3331 if (txr->sc->hw.mac.type == e1000_82575)
3332 olinfo_status |= txr->me << 4;
3333
3334 /* Set up our transmit descriptors */
3335 i = txr->next_avail_desc;
3336 for (j = 0; j < nsegs; j++) {
3337 bus_size_t seg_len;
3338 bus_addr_t seg_addr;
3339
3340 tx_buf = &txr->tx_buf[i];
3341 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3342 seg_addr = segs[j].ds_addr;
3343 seg_len = segs[j].ds_len;
3344
3345 txd->read.buffer_addr = htole64(seg_addr);
3346 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3347 txd->read.olinfo_status = htole32(olinfo_status);
91b8700a 3348 if (++i == txr->num_tx_desc)
1f7e3916
SZ
3349 i = 0;
3350 tx_buf->m_head = NULL;
1f7e3916
SZ
3351 }
3352
3353 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3354 txr->next_avail_desc = i;
3355 txr->tx_avail -= nsegs;
3356
3357 tx_buf->m_head = m_head;
3358 tx_buf_mapped->map = tx_buf->map;
3359 tx_buf->map = map;
3360
3361 /*
b6220144 3362 * Last Descriptor of Packet needs End Of Packet (EOP)
1f7e3916 3363 */
b6220144 3364 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
1f7e3916
SZ
3365
3366 /*
5d94c328 3367 * Defer TDT updating, until enough descrptors are setup
1f7e3916 3368 */
871c0e2b 3369 *idx = i;
5d1c889d 3370#ifdef IGB_TSS_DEBUG
1f7e3916 3371 ++txr->tx_packets;
5d1c889d 3372#endif
1f7e3916
SZ
3373
3374 return 0;
3375}
3376
3377static void
f0a26983 3378igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1f7e3916
SZ
3379{
3380 struct igb_softc *sc = ifp->if_softc;
f0a26983 3381 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
1f7e3916 3382 struct mbuf *m_head;
871c0e2b 3383 int idx = -1, nsegs = 0;
1f7e3916 3384
f0a26983 3385 KKASSERT(txr->ifsq == ifsq);
7d235eb5 3386 ASSERT_SERIALIZED(&txr->tx_serialize);
1f7e3916 3387
f0a26983 3388 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1f7e3916
SZ
3389 return;
3390
ddaf4d42 3391 if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
f0a26983 3392 ifsq_purge(ifsq);
1f7e3916
SZ
3393 return;
3394 }
3395
b6220144 3396 if (!IGB_IS_NOT_OACTIVE(txr))
1f7e3916
SZ
3397 igb_txeof(txr);
3398
f0a26983 3399 while (!ifsq_is_empty(ifsq)) {
b6220144 3400 if (IGB_IS_OACTIVE(txr)) {
f0a26983 3401 ifsq_set_oactive(ifsq);
1f7e3916 3402 /* Set watchdog on */
16109efc 3403 txr->tx_watchdog.wd_timer = 5;
1f7e3916
SZ
3404 break;
3405 }
3406
f0a26983 3407 m_head = ifsq_dequeue(ifsq, NULL);
1f7e3916
SZ
3408 if (m_head == NULL)
3409 break;
3410
871c0e2b 3411 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
1f7e3916
SZ
3412 ifp->if_oerrors++;
3413 continue;
3414 }
3415
871c0e2b
SZ
3416 if (nsegs >= txr->wreg_nsegs) {
3417 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3418 idx = -1;
3419 nsegs = 0;
3420 }
3421
1f7e3916
SZ
3422 /* Send a copy of the frame to the BPF listener */
3423 ETHER_BPF_MTAP(ifp, m_head);
3424 }
871c0e2b
SZ
3425 if (idx >= 0)
3426 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
1f7e3916
SZ
3427}
3428
3429static void
16109efc 3430igb_watchdog(struct ifaltq_subque *ifsq)
1f7e3916 3431{
16109efc
SZ
3432 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3433 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1f7e3916 3434 struct igb_softc *sc = ifp->if_softc;
73397ddb 3435 int i;
1f7e3916 3436
16109efc 3437 KKASSERT(txr->ifsq == ifsq);
1f7e3916
SZ
3438 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3439
3440 /*
3441 * If flow control has paused us since last checking
3442 * it invalidates the watchdog timing, so dont run it.
3443 */
3444 if (sc->pause_frames) {
3445 sc->pause_frames = 0;
16109efc 3446 txr->tx_watchdog.wd_timer = 5;
1f7e3916
SZ
3447 return;
3448 }
3449
3450 if_printf(ifp, "Watchdog timeout -- resetting\n");
3451 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3452 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3453 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3454 if_printf(ifp, "TX(%d) desc avail = %d, "
3455 "Next TX to Clean = %d\n",
3456 txr->me, txr->tx_avail, txr->next_to_clean);
3457
3458 ifp->if_oerrors++;
3459 sc->watchdog_events++;
3460
3461 igb_init(sc);
d802cc67 3462 for (i = 0; i < sc->tx_ring_inuse; ++i)
73397ddb 3463 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
1f7e3916
SZ
3464}
3465
3466static void
9c0ecdcc 3467igb_set_eitr(struct igb_softc *sc, int idx, int rate)
1f7e3916 3468{
9c0ecdcc 3469 uint32_t eitr = 0;
1f7e3916 3470
9c0ecdcc 3471 if (rate > 0) {
1f7e3916 3472 if (sc->hw.mac.type == e1000_82575) {
9c0ecdcc 3473 eitr = 1000000000 / 256 / rate;
1f7e3916
SZ
3474 /*
3475 * NOTE:
3476 * Document is wrong on the 2 bits left shift
3477 */
3478 } else {
9c0ecdcc 3479 eitr = 1000000 / rate;
d4beffa9
SZ
3480 eitr <<= IGB_EITR_INTVL_SHIFT;
3481 }
3482
3483 if (eitr == 0) {
3484 /* Don't disable it */
3485 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3486 } else if (eitr > IGB_EITR_INTVL_MASK) {
3487 /* Don't allow it to be too large */
3488 eitr = IGB_EITR_INTVL_MASK;
1f7e3916 3489 }
1f7e3916
SZ
3490 }
3491 if (sc->hw.mac.type == e1000_82575)
9c0ecdcc 3492 eitr |= eitr << 16;
1f7e3916 3493 else
9c0ecdcc
SZ
3494 eitr |= E1000_EITR_CNT_IGNR;
3495 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
1f7e3916
SZ
3496}
3497
3498static int
3499igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3500{
3501 struct igb_softc *sc = (void *)arg1;
3502 struct ifnet *ifp = &sc->arpcom.ac_if;
3503 int error, intr_rate;
3504
3505 intr_rate = sc->intr_rate;
3506 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3507 if (error || req->newptr == NULL)
3508 return error;
3509 if (intr_rate < 0)
3510 return EINVAL;
3511
3512 ifnet_serialize_all(ifp);
3513
3514 sc->intr_rate = intr_rate;
3515 if (ifp->if_flags & IFF_RUNNING)
9c0ecdcc
SZ
3516 igb_set_eitr(sc, 0, sc->intr_rate);
3517
3518 if (bootverbose)
3519 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
1f7e3916
SZ
3520
3521 ifnet_deserialize_all(ifp);
3522
9c0ecdcc
SZ
3523 return 0;
3524}
3525
3526static int
3527igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3528{
3529 struct igb_msix_data *msix = (void *)arg1;
3530 struct igb_softc *sc = msix->msix_sc;
3531 struct ifnet *ifp = &sc->arpcom.ac_if;
3532 int error, msix_rate;
3533
3534 msix_rate = msix->msix_rate;
3535 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3536 if (error || req->newptr == NULL)
3537 return error;
3538 if (msix_rate < 0)
3539 return EINVAL;
3540
3541 lwkt_serialize_enter(msix->msix_serialize);
3542
3543 msix->msix_rate = msix_rate;
3544 if (ifp->if_flags & IFF_RUNNING)
3545 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3546
3547 if (bootverbose) {
3548 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3549 msix->msix_rate);
3550 }
3551
3552 lwkt_serialize_exit(msix->msix_serialize);
3553
1f7e3916
SZ
3554 return 0;
3555}
b6220144
SZ
3556
3557static int
3558igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3559{
3560 struct igb_softc *sc = (void *)arg1;
3561 struct ifnet *ifp = &sc->arpcom.ac_if;
27866bf1 3562 struct igb_tx_ring *txr = &sc->tx_rings[0];
b6220144
SZ
3563 int error, nsegs;
3564
3565 nsegs = txr->intr_nsegs;
3566 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3567 if (error || req->newptr == NULL)
3568 return error;
3569 if (nsegs <= 0)
3570 return EINVAL;
3571
3572 ifnet_serialize_all(ifp);
3573
91b8700a 3574 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
b6220144
SZ
3575 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3576 error = EINVAL;
3577 } else {
708575bb
SZ
3578 int i;
3579
b6220144 3580 error = 0;
708575bb
SZ
3581 for (i = 0; i < sc->tx_ring_cnt; ++i)
3582 sc->tx_rings[i].intr_nsegs = nsegs;
b6220144
SZ
3583 }
3584
3585 ifnet_deserialize_all(ifp);
3586
3587 return error;
3588}
f6167a56 3589
9d8e892a
SZ
3590static int
3591igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3592{
3593 struct igb_softc *sc = (void *)arg1;
3594 struct ifnet *ifp = &sc->arpcom.ac_if;
3595 int error, nsegs, i;
3596
3597 nsegs = sc->rx_rings[0].wreg_nsegs;
3598 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3599 if (error || req->newptr == NULL)
3600 return error;
3601
3602 ifnet_serialize_all(ifp);
3603 for (i = 0; i < sc->rx_ring_cnt; ++i)
3604 sc->rx_rings[i].wreg_nsegs =nsegs;
3605 ifnet_deserialize_all(ifp);
3606
3607 return 0;
3608}
3609
708575bb
SZ
3610static int
3611igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3612{
3613 struct igb_softc *sc = (void *)arg1;
3614 struct ifnet *ifp = &sc->arpcom.ac_if;
3615 int error, nsegs, i;
3616
3617 nsegs = sc->tx_rings[0].wreg_nsegs;
3618 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3619 if (error || req->newptr == NULL)
3620 return error;
3621
3622 ifnet_serialize_all(ifp);
3623 for (i = 0; i < sc->tx_ring_cnt; ++i)
3624 sc->tx_rings[i].wreg_nsegs =nsegs;
3625 ifnet_deserialize_all(ifp);
3626
3627 return 0;
3628}
3629
d0f59cad
SZ
3630#ifdef IFPOLL_ENABLE
3631
3632static int
3633igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3634{
3635 struct igb_softc *sc = (void *)arg1;
3636 struct ifnet *ifp = &sc->arpcom.ac_if;
3637 int error, off;
3638
3639 off = sc->rx_npoll_off;
3640 error = sysctl_handle_int(oidp, &off, 0, req);
3641 if (error || req->newptr == NULL)
3642 return error;
3643 if (off < 0)
3644 return EINVAL;
3645
3646 ifnet_serialize_all(ifp);
3647 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3648 error = EINVAL;
3649 } else {
3650 error = 0;
3651 sc->rx_npoll_off = off;
3652 }
3653 ifnet_deserialize_all(ifp);
3654
3655 return error;
3656}
3657
3658static int
3659igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3660{
3661 struct igb_softc *sc = (void *)arg1;
3662 struct ifnet *ifp = &sc->arpcom.ac_if;
3663 int error, off;
3664
3665 off = sc->tx_npoll_off;
3666 error = sysctl_handle_int(oidp, &off, 0, req);
3667 if (error || req->newptr == NULL)
3668 return error;
3669 if (off < 0)
3670 return EINVAL;
3671
3672 ifnet_serialize_all(ifp);
d802cc67 3673 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
d0f59cad
SZ
3674 error = EINVAL;
3675 } else {
3676 error = 0;
3677 sc->tx_npoll_off = off;
3678 }
3679 ifnet_deserialize_all(ifp);
3680
3681 return error;
3682}
3683
3684#endif /* IFPOLL_ENABLE */
3685
f6167a56
SZ
3686static void
3687igb_init_intr(struct igb_softc *sc)
3688{
be922da6 3689 igb_set_intr_mask(sc);
9c0ecdcc
SZ
3690
3691 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
f6167a56 3692 igb_init_unshared_intr(sc);
9c0ecdcc
SZ
3693
3694 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3695 igb_set_eitr(sc, 0, sc->intr_rate);
3696 } else {
3697 int i;
3698
3699 for (i = 0; i < sc->msix_cnt; ++i)
3700 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3701 }
f6167a56
SZ
3702}
3703
3704static void
3705igb_init_unshared_intr(struct igb_softc *sc)
3706{
3707 struct e1000_hw *hw = &sc->hw;
3708 const struct igb_rx_ring *rxr;
3709 const struct igb_tx_ring *txr;
3710 uint32_t ivar, index;
3711 int i;
3712
3713 /*
3714 * Enable extended mode
3715 */
3716 if (sc->hw.mac.type != e1000_82575) {
9c0ecdcc
SZ
3717 uint32_t gpie;
3718 int ivar_max;
3719
3720 gpie = E1000_GPIE_NSICR;
3721 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3722 gpie |= E1000_GPIE_MSIX_MODE |
3723 E1000_GPIE_EIAME |
3724 E1000_GPIE_PBA;
3725 }
3726 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3727
3728 /*
3729 * Clear IVARs
3730 */
3731 switch (sc->hw.mac.type) {
3732 case e1000_82580:
3733 ivar_max = IGB_MAX_IVAR_82580;
3734 break;
3735
3736 case e1000_i350:
3737 ivar_max = IGB_MAX_IVAR_I350;
3738 break;
3739
3740 case e1000_vfadapt:
3741 case e1000_vfadapt_i350:
3742 ivar_max = IGB_MAX_IVAR_VF;
3743 break;
3744
3745 case e1000_82576:
3746 ivar_max = IGB_MAX_IVAR_82576;
3747 break;
3748
3749 default:
3750 panic("unknown mac type %d\n", sc->hw.mac.type);
3751 }
3752 for (i = 0; i < ivar_max; ++i)
3753 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3754 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
f6167a56
SZ
3755 } else {
3756 uint32_t tmp;
3757
9c0ecdcc
SZ
3758 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3759 ("82575 w/ MSI-X"));
f6167a56
SZ
3760 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3761