igb: Add per-TX ring enable flag.
[dragonfly.git] / sys / dev / netif / igb / if_igb.h
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1/*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _IF_IGB_H_
33#define _IF_IGB_H_
34
35/* Tunables */
36
37/*
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38 * Max ring count
39 */
40#define IGB_MAX_RING_82575 4
41#define IGB_MAX_RING_I350 8
42#define IGB_MAX_RING_82580 8
43#define IGB_MAX_RING_82576 16
44#define IGB_MIN_RING 1
be922da6 45#define IGB_MIN_RING_RSS 2
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46
47/*
48 * Max TX/RX interrupt bits
49 */
50#define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
51#define IGB_MAX_TXRXINT_I350 8
52#define IGB_MAX_TXRXINT_82580 8
53#define IGB_MAX_TXRXINT_82576 16
54#define IGB_MIN_TXRXINT 2 /* XXX VF? */
55
56/*
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57 * Max IVAR count
58 */
59#define IGB_MAX_IVAR_I350 4
60#define IGB_MAX_IVAR_82580 4
61#define IGB_MAX_IVAR_82576 8
62#define IGB_MAX_IVAR_VF 1
63
64/*
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65 * Default number of segments received before writing to RX related registers
66 */
67#define IGB_DEF_RXWREG_NSEGS 32
68
69/*
70 * Default number of segments sent before writing to RX related registers
71 */
72#define IGB_DEF_TXWREG_NSEGS 8
73
74/*
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75 * IGB_TXD: Maximum number of Transmit Descriptors
76 *
77 * This value is the number of transmit descriptors allocated by the driver.
78 * Increasing this value allows the driver to queue more transmits. Each
79 * descriptor is 16 bytes.
80 * Since TDLEN should be multiple of 128bytes, the number of transmit
81 * desscriptors should meet the following condition.
82 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
83 */
84#define IGB_MIN_TXD 256
85#define IGB_DEFAULT_TXD 1024
86#define IGB_MAX_TXD 4096
87
88/*
89 * IGB_RXD: Maximum number of Transmit Descriptors
90 *
91 * This value is the number of receive descriptors allocated by the driver.
92 * Increasing this value allows the driver to buffer more incoming packets.
93 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
94 * descriptor. The maximum MTU size is 16110.
95 * Since TDLEN should be multiple of 128bytes, the number of transmit
96 * desscriptors should meet the following condition.
97 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
98 */
99#define IGB_MIN_RXD 256
e7c14703 100#define IGB_DEFAULT_RXD 512
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101#define IGB_MAX_RXD 4096
102
103/*
104 * This parameter controls when the driver calls the routine to reclaim
105 * transmit descriptors. Cleaning earlier seems a win.
106 */
107#define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
108
109/*
110 * This parameter controls whether or not autonegotation is enabled.
111 * 0 - Disable autonegotiation
112 * 1 - Enable autonegotiation
113 */
114#define DO_AUTO_NEG 1
115
116/*
117 * This parameter control whether or not the driver will wait for
118 * autonegotiation to complete.
119 * 1 - Wait for autonegotiation to complete
120 * 0 - Don't wait for autonegotiation to complete
121 */
122#define WAIT_FOR_AUTO_NEG_DEFAULT 0
123
124/* Tunables -- End */
125
126#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
127 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
128 ADVERTISE_1000_FULL)
129
130#define AUTO_ALL_MODES 0
131
132/* PHY master/slave setting */
133#define IGB_MASTER_SLAVE e1000_ms_hw_default
134
135/*
136 * Micellaneous constants
137 */
138#define IGB_VENDOR_ID 0x8086
139
140#define IGB_JUMBO_PBA 0x00000028
141#define IGB_DEFAULT_PBA 0x00000030
142#define IGB_SMARTSPEED_DOWNSHIFT 3
143#define IGB_SMARTSPEED_MAX 15
144#define IGB_MAX_LOOP 10
145
146#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
147#define IGB_RX_HTHRESH 8
148#define IGB_RX_WTHRESH 1
149
150#define IGB_TX_PTHRESH 8
151#define IGB_TX_HTHRESH 1
396b7048 152#define IGB_TX_WTHRESH 16
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153
154#define MAX_NUM_MULTICAST_ADDRESSES 128
155#define IGB_FC_PAUSE_TIME 0x0680
156
c2d84054 157#define IGB_INTR_RATE 6000
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158#define IGB_MSIX_RX_RATE 6000
159#define IGB_MSIX_TX_RATE 4000
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160
161/*
162 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
163 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
164 * also optimize cache line size effect. H/W supports up to cache line size 128.
165 */
166#define IGB_DBA_ALIGN 128
167
168/* PCI Config defines */
169#define IGB_MSIX_BAR 3
170
171#define IGB_MAX_SCATTER 64
172#define IGB_VFTA_SIZE 128
23f6ffe4 173#define IGB_TSO_SIZE (IP_MAXPACKET + \
1f7e3916 174 sizeof(struct ether_vlan_header))
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175#define IGB_HDR_BUF 128
176#define IGB_PKTTYPE_MASK 0x0000FFF0
177
178#define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
179#define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
180#define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
181 IGB_IPVHL_SIZE)
182
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183/* One for TX csum offloading desc, the other 2 are reserved */
184#define IGB_TX_RESERVED 3
185
186/* Large enough for 64K TSO */
23f6ffe4 187#define IGB_TX_SPARE 33
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188
189#define IGB_TX_OACTIVE_MAX 64
190
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191/* main + 16x RX + 16x TX */
192#define IGB_NSERIALIZE 33
193
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194#define IGB_NRSSRK 10
195#define IGB_RSSRK_SIZE 4
196#define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \
197 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
198 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
199 key[(i) * IGB_RSSRK_SIZE + 3] << 24)
200
201#define IGB_NRETA 32
202#define IGB_RETA_SIZE 4
203#define IGB_RETA_SHIFT 0
204#define IGB_RETA_SHIFT_82575 6
205
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206#define IGB_EITR_INTVL_MASK 0x7ffc
207#define IGB_EITR_INTVL_SHIFT 2
208
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209struct igb_softc;
210
211/*
212 * Bus dma information structure
213 */
214struct igb_dma {
215 bus_addr_t dma_paddr;
216 void *dma_vaddr;
217 bus_dma_tag_t dma_tag;
218 bus_dmamap_t dma_map;
219};
220
221/*
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222 * Transmit ring: one per queue
223 */
224struct igb_tx_ring {
7d235eb5 225 struct lwkt_serialize tx_serialize;
1f7e3916 226 struct igb_softc *sc;
f0a26983 227 struct ifaltq_subque *ifsq;
1f7e3916 228 uint32_t me;
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229 uint32_t tx_flags;
230#define IGB_TXFLAG_TSO_IPLEN0 0x1
ddaf4d42 231#define IGB_TXFLAG_ENABLED 0x2
1f7e3916 232 struct e1000_tx_desc *tx_base;
91b8700a 233 int num_tx_desc;
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234 uint32_t next_avail_desc;
235 uint32_t next_to_clean;
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236 uint32_t *tx_hdr;
237 int tx_avail;
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238 struct igb_tx_buf *tx_buf;
239 bus_dma_tag_t tx_tag;
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240 int tx_nsegs;
241 int spare_desc;
242 int oact_lo_desc;
243 int oact_hi_desc;
244 int intr_nsegs;
871c0e2b 245 int wreg_nsegs;
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246 int tx_intr_bit;
247 uint32_t tx_intr_mask;
16109efc 248 struct ifsubq_watchdog tx_watchdog;
1f7e3916 249
791a0338 250 /* Soft stats */
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251 u_long no_desc_avail;
252 u_long tx_packets;
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253
254 struct igb_dma txdma;
255 bus_dma_tag_t tx_hdr_dtag;
256 bus_dmamap_t tx_hdr_dmap;
257 bus_addr_t tx_hdr_paddr;
0e23628a 258 int tx_intr_cpuid;
ff230ec8 259} __cachealign;
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260
261/*
262 * Receive ring: one per queue
263 */
264struct igb_rx_ring {
7d235eb5 265 struct lwkt_serialize rx_serialize;
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266 struct igb_softc *sc;
267 uint32_t me;
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268 union e1000_adv_rx_desc *rx_base;
269 boolean_t discard;
91b8700a 270 int num_rx_desc;
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271 uint32_t next_to_check;
272 struct igb_rx_buf *rx_buf;
273 bus_dma_tag_t rx_tag;
274 bus_dmamap_t rx_sparemap;
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275 int rx_intr_bit;
276 uint32_t rx_intr_mask;
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277
278 /*
279 * First/last mbuf pointers, for
280 * collecting multisegment RX packets.
281 */
282 struct mbuf *fmp;
283 struct mbuf *lmp;
9d8e892a 284 int wreg_nsegs;
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285
286 /* Soft stats */
287 u_long rx_packets;
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288
289 struct igb_dma rxdma;
ff230ec8 290} __cachealign;
1f7e3916 291
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292struct igb_msix_data {
293 struct lwkt_serialize *msix_serialize;
294 struct lwkt_serialize msix_serialize0;
295 struct igb_softc *msix_sc;
296 uint32_t msix_mask;
297 struct igb_rx_ring *msix_rx;
298 struct igb_tx_ring *msix_tx;
299
300 driver_intr_t *msix_func;
301 void *msix_arg;
302
303 int msix_cpuid;
304 char msix_desc[32];
305 int msix_rid;
306 struct resource *msix_res;
307 void *msix_handle;
308 u_int msix_vector;
309 int msix_rate;
310 char msix_rate_desc[32];
ff230ec8 311} __cachealign;
9c0ecdcc 312
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313struct igb_softc {
314 struct arpcom arpcom;
315 struct e1000_hw hw;
316
317 struct e1000_osdep osdep;
318 device_t dev;
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319 uint32_t flags;
320#define IGB_FLAG_SHARED_INTR 0x1
396b7048 321#define IGB_FLAG_HAS_MGMT 0x2
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322
323 bus_dma_tag_t parent_tag;
324
325 int mem_rid;
326 struct resource *mem_res;
327
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328 struct ifmedia media;
329 struct callout timer;
7b61c9f2 330 int timer_cpuid;
1f7e3916 331
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332 int intr_type;
333 int intr_rid;
334 struct resource *intr_res;
335 void *intr_tag;
336
337 int if_flags;
338 int max_frame_size;
1f7e3916 339 int pause_frames;
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340 uint16_t vf_ifp; /* a VF interface */
341
342 /* Management and WOL features */
343 int wol;
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344
345 /* Info about the interface */
346 uint8_t link_active;
347 uint16_t link_speed;
348 uint16_t link_duplex;
349 uint32_t smartspeed;
350 uint32_t dma_coalesce;
351
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352 /* Multicast array pointer */
353 uint8_t *mta;
354
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355 int rx_npoll_off;
356 int tx_npoll_off;
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357 int serialize_cnt;
358 int tx_serialize;
359 int rx_serialize;
360 struct lwkt_serialize *serializes[IGB_NSERIALIZE];
361 struct lwkt_serialize main_serialize;
362
1f7e3916 363 int intr_rate;
f6167a56 364 uint32_t intr_mask;
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365 int sts_intr_bit;
366 uint32_t sts_intr_mask;
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367
368 /*
369 * Transmit rings
370 */
27866bf1 371 int tx_ring_cnt;
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372 int tx_ring_msix;
373 int tx_ring_inuse;
1f7e3916 374 struct igb_tx_ring *tx_rings;
1f7e3916 375
396b7048 376 /*
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377 * Receive rings
378 */
8d6600da 379 int rss_debug;
27866bf1 380 int rx_ring_cnt;
9c0ecdcc 381 int rx_ring_msix;
be922da6 382 int rx_ring_inuse;
1f7e3916 383 struct igb_rx_ring *rx_rings;
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384
385 /* Misc stats maintained by the driver */
386 u_long dropped_pkts;
387 u_long mbuf_defrag_failed;
388 u_long no_tx_dma_setup;
389 u_long watchdog_events;
390 u_long rx_overruns;
391 u_long device_control;
392 u_long rx_control;
393 u_long int_mask;
394 u_long eint_mask;
395 u_long packet_buf_alloc_rx;
396 u_long packet_buf_alloc_tx;
397
398 /* sysctl tree glue */
399 struct sysctl_ctx_list sysctl_ctx;
400 struct sysctl_oid *sysctl_tree;
401
402 void *stats;
9c0ecdcc 403
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404 int msix_mem_rid;
405 struct resource *msix_mem_res;
406 int msix_cnt;
407 struct igb_msix_data *msix_data;
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408};
409
8d6600da 410#define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
d802cc67 411#define IGB_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1)
8d6600da 412
1f7e3916 413struct igb_tx_buf {
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414 struct mbuf *m_head;
415 bus_dmamap_t map; /* bus_dma map for packet */
416};
417
418struct igb_rx_buf {
419 struct mbuf *m_head;
420 bus_dmamap_t map; /* bus_dma map for packet */
421 bus_addr_t paddr;
422};
423
424#define UPDATE_VF_REG(reg, last, cur) \
425{ \
426 uint32_t new = E1000_READ_REG(hw, reg); \
427 if (new < last) \
428 cur += 0x100000000LL; \
429 last = new; \
430 cur &= 0xFFFFFFFF00000000LL; \
431 cur |= new; \
432}
433
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434#define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
435#define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
436
1f7e3916 437#endif /* _IF_IGB_H_ */