pci: Put back header gardian in header files
[dragonfly.git] / sys / bus / pci / pcivar.h
CommitLineData
4d28e78f 1/*-
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2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
4d28e78f 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
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27 *
28 */
29
30#ifndef _PCIVAR_H_
4d28e78f 31#define _PCIVAR_H_
984263bc 32
e2c4df7c 33#ifndef _SYS_QUEUE_H_
984263bc 34#include <sys/queue.h>
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35#endif
36
4d28e78f 37#include <bus/pci/pcireg.h>
e2c4df7c 38
4d28e78f 39extern const char *pcib_owner; /* arbitrate who owns the pci device arch */
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40
41/* some PCI bus constants */
42
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43#define PCI_DOMAINMAX 65535 /* highest supported domain number */
44#define PCI_BUSMAX 255 /* highest supported bus number */
45#define PCI_SLOTMAX 31 /* highest supported slot number */
46#define PCI_FUNCMAX 7 /* highest supported function number */
47#define PCI_REGMAX 255 /* highest supported config register addr. */
984263bc 48
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49#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
50#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
51#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
984263bc 52
4d28e78f 53typedef uint64_t pci_addr_t;
984263bc 54
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55/* Interesting values for PCI power management */
56struct pcicfg_pp {
57 uint16_t pp_cap; /* PCI power management capabilities */
58 uint8_t pp_status; /* config space address of PCI power status reg */
59 uint8_t pp_pmcsr; /* config space address of PMCSR reg */
60 uint8_t pp_data; /* config space address of PCI power data reg */
1f7d9fe0 61};
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62
63struct vpd_readonly {
64 char keyword[2];
65 char *value;
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66};
67
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68struct vpd_write {
69 char keyword[2];
70 char *value;
71 int start;
72 int len;
73};
638744c5 74
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75struct pcicfg_vpd {
76 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
77 char vpd_cached;
78 char *vpd_ident; /* string identifier */
79 int vpd_rocnt;
80 struct vpd_readonly *vpd_ros;
81 int vpd_wcnt;
82 struct vpd_write *vpd_w;
83};
984263bc 84
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85/* Interesting values for PCI MSI */
86struct pcicfg_msi {
87 uint16_t msi_ctrl; /* Message Control */
88 uint8_t msi_location; /* Offset of MSI capability registers. */
89 uint8_t msi_msgnum; /* Number of messages */
90 int msi_alloc; /* Number of allocated messages. */
91 uint64_t msi_addr; /* Contents of address register. */
92 uint16_t msi_data; /* Contents of data register. */
93 u_int msi_handlers;
94};
984263bc 95
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96/* Interesting values for PCI MSI-X */
97struct msix_vector {
98 uint64_t mv_address; /* Contents of address register. */
99 uint32_t mv_data; /* Contents of data register. */
100 int mv_irq;
101};
984263bc 102
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103struct msix_table_entry {
104 u_int mte_vector; /* 1-based index into msix_vectors array. */
105 u_int mte_handlers;
106};
984263bc 107
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108struct pcicfg_msix {
109 uint16_t msix_ctrl; /* Message Control */
110 uint16_t msix_msgnum; /* Number of messages */
111 uint8_t msix_location; /* Offset of MSI-X capability registers. */
112 uint8_t msix_table_bar; /* BAR containing vector table. */
113 uint8_t msix_pba_bar; /* BAR containing PBA. */
114 uint32_t msix_table_offset;
115 uint32_t msix_pba_offset;
116 int msix_alloc; /* Number of allocated vectors. */
117 int msix_table_len; /* Length of virtual table. */
118 struct msix_table_entry *msix_table; /* Virtual table. */
119 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
120 struct resource *msix_table_res; /* Resource containing vector table. */
121 struct resource *msix_pba_res; /* Resource containing PBA. */
122};
984263bc 123
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124/* Interesting values for HyperTransport */
125struct pcicfg_ht {
126 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
127 uint16_t ht_msictrl; /* MSI mapping control */
128 uint64_t ht_msiaddr; /* MSI mapping base address */
129};
984263bc 130
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131/* config header information common to all header types */
132typedef struct pcicfg {
133 struct device *dev; /* device which owns this */
984263bc 134
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135 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
136 uint32_t bios; /* BIOS mapping */
984263bc 137
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138 uint16_t subvendor; /* card vendor ID */
139 uint16_t subdevice; /* card device ID, assigned by card vendor */
140 uint16_t vendor; /* chip vendor ID */
141 uint16_t device; /* chip device ID, assigned by chip vendor */
142
143 uint16_t cmdreg; /* disable/enable chip and PCI options */
144 uint16_t statreg; /* supported PCI features and error state */
145
146 uint8_t baseclass; /* chip PCI class */
147 uint8_t subclass; /* chip PCI subclass */
148 uint8_t progif; /* chip PCI programming interface */
149 uint8_t revid; /* chip revision ID */
150
151 uint8_t hdrtype; /* chip config header type */
152 uint8_t cachelnsz; /* cache line size in 4byte units */
153 uint8_t intpin; /* PCI interrupt pin */
154 uint8_t intline; /* interrupt line (IRQ for PC arch) */
155
156 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
157 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
158 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
159
160 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
161 uint8_t nummaps; /* actual number of PCI maps used */
162
163 uint32_t domain; /* PCI domain */
164 uint8_t bus; /* config space bus address */
165 uint8_t slot; /* config space slot address */
166 uint8_t func; /* config space function number */
167
168 struct pcicfg_pp pp; /* pci power management */
169 struct pcicfg_vpd vpd; /* pci vital product data */
170 struct pcicfg_msi msi; /* pci msi */
171 struct pcicfg_msix msix; /* pci msi-x */
172 struct pcicfg_ht ht; /* HyperTransport */
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173} pcicfgregs;
174
175/* additional type 1 device config header information (PCI to PCI bridge) */
176
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177#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
178#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
179#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
180#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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181
182typedef struct {
183 pci_addr_t pmembase; /* base address of prefetchable memory */
184 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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185 uint32_t membase; /* base address of memory window */
186 uint32_t memlimit; /* topmost address of memory window */
187 uint32_t iobase; /* base address of port window */
188 uint32_t iolimit; /* topmost address of port window */
189 uint16_t secstat; /* secondary bus status register */
190 uint16_t bridgectl; /* bridge control register */
191 uint8_t seclat; /* CardBus latency timer */
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192} pcih1cfgregs;
193
194/* additional type 2 device config header information (CardBus bridge) */
195
196typedef struct {
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197 uint32_t membase0; /* base address of memory window */
198 uint32_t memlimit0; /* topmost address of memory window */
199 uint32_t membase1; /* base address of memory window */
200 uint32_t memlimit1; /* topmost address of memory window */
201 uint32_t iobase0; /* base address of port window */
202 uint32_t iolimit0; /* topmost address of port window */
203 uint32_t iobase1; /* base address of port window */
204 uint32_t iolimit1; /* topmost address of port window */
205 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
206 uint16_t secstat; /* secondary bus status register */
207 uint16_t bridgectl; /* bridge control register */
208 uint8_t seclat; /* CardBus latency timer */
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209} pcih2cfgregs;
210
4d28e78f 211extern uint32_t pci_numdevs;
984263bc 212
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213/* Only if the prerequisites are present */
214#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
215struct pci_devinfo {
216 STAILQ_ENTRY(pci_devinfo) pci_links;
217 struct resource_list resources;
218 pcicfgregs cfg;
219 struct pci_conf conf;
220};
221#endif
984263bc 222
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223#ifdef _SYS_BUS_H_
224
225#include "pci_if.h"
226
227/*
228 * Define pci-specific resource flags for accessing memory via dense
229 * or bwx memory spaces. These flags are ignored on i386.
230 */
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231#define PCI_RF_DENSE 0x10000
232#define PCI_RF_BWX 0x20000
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233
234enum pci_device_ivars {
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235 PCI_IVAR_SUBVENDOR,
236 PCI_IVAR_SUBDEVICE,
237 PCI_IVAR_VENDOR,
238 PCI_IVAR_DEVICE,
239 PCI_IVAR_DEVID,
240 PCI_IVAR_CLASS,
241 PCI_IVAR_SUBCLASS,
242 PCI_IVAR_PROGIF,
243 PCI_IVAR_REVID,
244 PCI_IVAR_INTPIN,
245 PCI_IVAR_IRQ,
246 PCI_IVAR_DOMAIN,
247 PCI_IVAR_BUS,
248 PCI_IVAR_SLOT,
249 PCI_IVAR_FUNCTION,
250 PCI_IVAR_ETHADDR,
251 PCI_IVAR_CMDREG,
252 PCI_IVAR_CACHELNSZ,
253 PCI_IVAR_MINGNT,
254 PCI_IVAR_MAXLAT,
255 PCI_IVAR_LATTIMER,
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256};
257
258/*
259 * Simplified accessors for pci devices
260 */
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261#define PCI_ACCESSOR(var, ivar, type) \
262 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
263
264PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
265PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
266PCI_ACCESSOR(vendor, VENDOR, uint16_t)
267PCI_ACCESSOR(device, DEVICE, uint16_t)
268PCI_ACCESSOR(devid, DEVID, uint32_t)
269PCI_ACCESSOR(class, CLASS, uint8_t)
270PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
271PCI_ACCESSOR(progif, PROGIF, uint8_t)
272PCI_ACCESSOR(revid, REVID, uint8_t)
273PCI_ACCESSOR(intpin, INTPIN, uint8_t)
274PCI_ACCESSOR(irq, IRQ, uint8_t)
275PCI_ACCESSOR(domain, DOMAIN, uint32_t)
276PCI_ACCESSOR(bus, BUS, uint8_t)
277PCI_ACCESSOR(slot, SLOT, uint8_t)
278PCI_ACCESSOR(function, FUNCTION, uint8_t)
f72d3d23 279PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
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280PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
281PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
282PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
283PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
284PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
984263bc 285
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286#undef PCI_ACCESSOR
287
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288/*
289 * Operations on configuration space.
290 */
291static __inline uint32_t
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292pci_read_config(device_t dev, int reg, int width)
293{
294 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
295}
296
297static __inline void
4d28e78f 298pci_write_config(device_t dev, int reg, uint32_t val, int width)
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299{
300 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
301}
302
303/*
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304 * Ivars for pci bridges.
305 */
306
307/*typedef enum pci_device_ivars pcib_device_ivars;*/
308enum pcib_device_ivars {
309 PCIB_IVAR_DOMAIN,
310 PCIB_IVAR_BUS
311};
312
313#define PCIB_ACCESSOR(var, ivar, type) \
314 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
315
316PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
317PCIB_ACCESSOR(bus, BUS, uint32_t)
318
319#undef PCIB_ACCESSOR
320
321/*
322 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
323 * on i386 or other platforms should be mapped out in the MD pcireadconf
324 * code and not here, since the only MI invalid IRQ is 255.
325 */
326#define PCI_INVALID_IRQ 255
327#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
328
329/*
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330 * Convenience functions.
331 *
332 * These should be used in preference to manually manipulating
333 * configuration space.
334 */
4d28e78f 335static __inline int
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336pci_enable_busmaster(device_t dev)
337{
4d28e78f 338 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
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339}
340
4d28e78f 341static __inline int
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342pci_disable_busmaster(device_t dev)
343{
4d28e78f 344 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
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345}
346
4d28e78f 347static __inline int
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348pci_enable_io(device_t dev, int space)
349{
4d28e78f 350 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
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351}
352
4d28e78f 353static __inline int
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354pci_disable_io(device_t dev, int space)
355{
4d28e78f 356 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
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357}
358
c7e4e7eb 359static __inline int
4d28e78f 360pci_get_vpd_ident(device_t dev, const char **identptr)
c7e4e7eb 361{
4d28e78f 362 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
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363}
364
365static __inline int
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366pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
367{
368 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
369}
370
371/*
372 * Check if the address range falls within the VGA defined address range(s)
373 */
374static __inline int
375pci_is_vga_ioport_range(u_long start, u_long end)
376{
377
378 return (((start >= 0x3b0 && end <= 0x3bb) ||
379 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
380}
381
382static __inline int
383pci_is_vga_memory_range(u_long start, u_long end)
c7e4e7eb 384{
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385
386 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
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387}
388
4d28e78f 389void pcie_set_max_readrq(device_t, uint16_t);
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390/*
391 * PCI power states are as defined by ACPI:
392 *
393 * D0 State in which device is on and running. It is receiving full
394 * power from the system and delivering full functionality to the user.
395 * D1 Class-specific low-power state in which device context may or may not
396 * be lost. Buses in D1 cannot do anything to the bus that would force
4d28e78f 397 * devices on that bus to lose context.
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398 * D2 Class-specific low-power state in which device context may or may
399 * not be lost. Attains greater power savings than D1. Buses in D2
4d28e78f 400 * can cause devices on that bus to lose some context. Devices in D2
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401 * must be prepared for the bus to be in D2 or higher.
402 * D3 State in which the device is off and not running. Device context is
403 * lost. Power can be removed from the device.
404 */
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405#define PCI_POWERSTATE_D0 0
406#define PCI_POWERSTATE_D1 1
407#define PCI_POWERSTATE_D2 2
408#define PCI_POWERSTATE_D3 3
409#define PCI_POWERSTATE_UNKNOWN -1
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410
411static __inline int
412pci_set_powerstate(device_t dev, int state)
413{
414 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
415}
416
417static __inline int
418pci_get_powerstate(device_t dev)
419{
420 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
421}
422
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423static __inline int
424pci_find_extcap(device_t dev, int capability, int *capreg)
425{
426 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
427}
428
429static __inline int
430pci_is_pcie(device_t dev)
431{
432 int reg;
433 return (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0);
434}
984263bc 435
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436static __inline int
437pci_is_pcix(device_t dev)
438{
439 int reg;
440 return (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0);
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441}
442
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443#warning "this code is probably incorrect"
444static __inline int*
445pci_get_vpdcap_ptr(device_t dev)
446{
447 int *reg;
448 pci_find_extcap(dev, PCIY_VPD, reg);
449 return reg;
450}
984263bc 451
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452static __inline int*
453pci_get_pciecap_ptr(device_t dev)
454{
455 int *reg;
456 pci_find_extcap(dev, PCIY_EXPRESS, reg);
457 return reg;
458}
27c23c6b 459
984263bc 460
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461static __inline int*
462pci_get_pcixcap_ptr(device_t dev)
463{
464 int *reg;
465 pci_find_extcap(dev, PCIY_PCIX, reg);
466 return reg;
467}
dc5a7bd2 468
984263bc 469
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470static __inline int
471pci_alloc_msi(device_t dev, int *count)
472{
473 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
474}
475
476static __inline int
477pci_alloc_msix(device_t dev, int *count)
478{
479 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
480}
984263bc 481
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482static __inline int
483pci_remap_msix(device_t dev, int count, const u_int *vectors)
484{
485 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
486}
984263bc 487
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488static __inline int
489pci_release_msi(device_t dev)
490{
491 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
492}
984263bc 493
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494static __inline int
495pci_msi_count(device_t dev)
496{
497 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
498}
984263bc 499
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500static __inline int
501pci_msix_count(device_t dev)
502{
503 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
504}
984263bc 505
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506device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
507device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
508device_t pci_find_device(uint16_t, uint16_t);
509
510/*
511 * Can be used by MD code to request the PCI bus to re-map an MSI or
512 * MSI-X message.
513 */
514int pci_remap_msi_irq(device_t dev, u_int irq);
515
516/* Can be used by drivers to manage the MSI-X table. */
517int pci_pending_msix(device_t dev, u_int index);
518
519int pci_msi_device_blacklisted(device_t dev);
520
521void pci_ht_map_msi(device_t dev, uint64_t addr);
522
523#endif /* _SYS_BUS_H_ */
524
525/*
526 * cdev switch for control device, initialised in generic PCI code
527 */
528extern struct cdevsw pcicdev;
529
530/*
531 * List of all PCI devices, generation count for the list.
532 */
533STAILQ_HEAD(devlist, pci_devinfo);
534
535extern struct devlist pci_devq;
536extern uint32_t pci_generation;
984263bc 537
984263bc 538#endif /* _PCIVAR_H_ */