Rename printf -> kprintf in sys/ and add some defines where necessary
[dragonfly.git] / sys / dev / disk / advansys / advansys.c
CommitLineData
984263bc
MD
1/*
2 * Generic driver for the Advanced Systems Inc. SCSI controllers
3 * Product specific probe and attach routines can be found in:
4 *
5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852
6 * i386/eisa/adv_eisa.c ABP742, ABP752
7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U,
8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA,
9 * ABP970, ABP970U
10 *
11 * Copyright (c) 1996-2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification, immediately at the beginning of the file.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/advansys/advansys.c,v 1.14.2.4 2002/01/06 21:21:42 dwmalone Exp $
e3869ec7 36 * $DragonFly: src/sys/dev/disk/advansys/advansys.c,v 1.11 2006/12/22 23:26:15 swildner Exp $
984263bc
MD
37 */
38/*
39 * Ported from:
40 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
41 *
42 * Copyright (c) 1995-1997 Advanced System Products, Inc.
43 * All Rights Reserved.
44 *
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that redistributions of source
47 * code retain the above copyright notice and this comment without
48 * modification.
49 */
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/malloc.h>
54#include <sys/kernel.h>
c1139c5e 55#include <sys/thread2.h>
984263bc
MD
56#include <sys/bus.h>
57#include <sys/rman.h>
58
1f2de5d4
MD
59#include <bus/cam/cam.h>
60#include <bus/cam/cam_ccb.h>
61#include <bus/cam/cam_sim.h>
62#include <bus/cam/cam_xpt_sim.h>
63#include <bus/cam/cam_xpt_periph.h>
64#include <bus/cam/cam_debug.h>
984263bc 65
1f2de5d4
MD
66#include <bus/cam/scsi/scsi_all.h>
67#include <bus/cam/scsi/scsi_message.h>
984263bc
MD
68
69#include <vm/vm.h>
70#include <vm/vm_param.h>
71#include <vm/pmap.h>
72
1f2de5d4 73#include "advansys.h"
984263bc
MD
74
75static void adv_action(struct cam_sim *sim, union ccb *ccb);
76static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
77 int nsegments, int error);
78static void adv_poll(struct cam_sim *sim);
79static void adv_run_doneq(struct adv_softc *adv);
80static struct adv_ccb_info *
81 adv_alloc_ccb_info(struct adv_softc *adv);
82static void adv_destroy_ccb_info(struct adv_softc *adv,
83 struct adv_ccb_info *cinfo);
84static __inline struct adv_ccb_info *
85 adv_get_ccb_info(struct adv_softc *adv);
86static __inline void adv_free_ccb_info(struct adv_softc *adv,
87 struct adv_ccb_info *cinfo);
88static __inline void adv_set_state(struct adv_softc *adv, adv_state state);
89static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb);
90static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb);
91
92static __inline struct adv_ccb_info *
93adv_get_ccb_info(struct adv_softc *adv)
94{
95 struct adv_ccb_info *cinfo;
984263bc 96
c1139c5e 97 crit_enter();
984263bc
MD
98 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
99 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
100 } else {
101 cinfo = adv_alloc_ccb_info(adv);
102 }
c1139c5e 103 crit_exit();
984263bc
MD
104
105 return (cinfo);
106}
107
108static __inline void
109adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
c1139c5e
EN
110{
111 crit_enter();
984263bc
MD
112 cinfo->state = ACCB_FREE;
113 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links);
c1139c5e 114 crit_exit();
984263bc
MD
115}
116
117static __inline void
118adv_set_state(struct adv_softc *adv, adv_state state)
119{
120 if (adv->state == 0)
121 xpt_freeze_simq(adv->sim, /*count*/1);
122 adv->state |= state;
123}
124
125static __inline void
126adv_clear_state(struct adv_softc *adv, union ccb* ccb)
127{
128 if (adv->state != 0)
129 adv_clear_state_really(adv, ccb);
130}
131
132static void
133adv_clear_state_really(struct adv_softc *adv, union ccb* ccb)
134{
135 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0)
136 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK);
137 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) {
138 int openings;
139
140 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q;
141 if (openings >= adv->openings_needed) {
142 adv->state &= ~ADV_RESOURCE_SHORTAGE;
143 adv->openings_needed = 0;
144 }
145 }
146
147 if ((adv->state & ADV_IN_TIMEOUT) != 0) {
148 struct adv_ccb_info *cinfo;
149
150 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
151 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) {
152 struct ccb_hdr *ccb_h;
153
154 /*
155 * We now traverse our list of pending CCBs
156 * and reinstate their timeouts.
157 */
158 ccb_h = LIST_FIRST(&adv->pending_ccbs);
159 while (ccb_h != NULL) {
ddcafce9
JS
160 callout_reset(&ccb_h->timeout_ch,
161 (ccb_h->timeout * hz) / 1000,
162 adv_timeout, ccb_h);
984263bc
MD
163 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
164 }
165 adv->state &= ~ADV_IN_TIMEOUT;
e3869ec7 166 kprintf("%s: No longer in timeout\n", adv_name(adv));
984263bc
MD
167 }
168 }
169 if (adv->state == 0)
170 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
171}
172
173void
174adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
175{
176 bus_addr_t* physaddr;
177
178 physaddr = (bus_addr_t*)arg;
179 *physaddr = segs->ds_addr;
180}
181
182char *
183adv_name(struct adv_softc *adv)
184{
185 static char name[10];
186
f8c7a42d 187 ksnprintf(name, sizeof(name), "adv%d", adv->unit);
984263bc
MD
188 return (name);
189}
190
191static void
192adv_action(struct cam_sim *sim, union ccb *ccb)
193{
194 struct adv_softc *adv;
195
196 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n"));
197
198 adv = (struct adv_softc *)cam_sim_softc(sim);
199
200 switch (ccb->ccb_h.func_code) {
201 /* Common cases first */
202 case XPT_SCSI_IO: /* Execute the requested I/O operation */
203 {
204 struct ccb_hdr *ccb_h;
205 struct ccb_scsiio *csio;
206 struct adv_ccb_info *cinfo;
207
208 ccb_h = &ccb->ccb_h;
209 csio = &ccb->csio;
210 cinfo = adv_get_ccb_info(adv);
211 if (cinfo == NULL)
212 panic("XXX Handle CCB info error!!!");
213
214 ccb_h->ccb_cinfo_ptr = cinfo;
215 cinfo->ccb = ccb;
216
217 /* Only use S/G if there is a transfer */
218 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
219 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
220 /*
221 * We've been given a pointer
222 * to a single buffer
223 */
224 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
984263bc
MD
225 int error;
226
c1139c5e 227 crit_enter();
984263bc
MD
228 error =
229 bus_dmamap_load(adv->buffer_dmat,
230 cinfo->dmamap,
231 csio->data_ptr,
232 csio->dxfer_len,
233 adv_execute_ccb,
234 csio, /*flags*/0);
235 if (error == EINPROGRESS) {
236 /*
237 * So as to maintain ordering,
238 * freeze the controller queue
239 * until our mapping is
240 * returned.
241 */
242 adv_set_state(adv,
243 ADV_BUSDMA_BLOCK);
244 }
c1139c5e 245 crit_exit();
984263bc
MD
246 } else {
247 struct bus_dma_segment seg;
248
249 /* Pointer to physical buffer */
250 seg.ds_addr =
251 (bus_addr_t)csio->data_ptr;
252 seg.ds_len = csio->dxfer_len;
253 adv_execute_ccb(csio, &seg, 1, 0);
254 }
255 } else {
256 struct bus_dma_segment *segs;
257 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
258 panic("adv_setup_data - Physical "
259 "segment pointers unsupported");
260
261 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
262 panic("adv_setup_data - Virtual "
263 "segment addresses unsupported");
264
265 /* Just use the segments provided */
266 segs = (struct bus_dma_segment *)csio->data_ptr;
267 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0);
268 }
269 } else {
270 adv_execute_ccb(ccb, NULL, 0, 0);
271 }
272 break;
273 }
274 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
275 case XPT_TARGET_IO: /* Execute target I/O request */
276 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
277 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
278 case XPT_EN_LUN: /* Enable LUN as a target */
279 case XPT_ABORT: /* Abort the specified CCB */
280 /* XXX Implement */
281 ccb->ccb_h.status = CAM_REQ_INVALID;
282 xpt_done(ccb);
283 break;
284 case XPT_SET_TRAN_SETTINGS:
285 {
286 struct ccb_trans_settings *cts;
287 target_bit_vector targ_mask;
288 struct adv_transinfo *tconf;
289 u_int update_type;
984263bc
MD
290
291 cts = &ccb->cts;
292 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
293 update_type = 0;
294
295 /*
296 * The user must specify which type of settings he wishes
297 * to change.
298 */
299 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
300 && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) {
301 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
302 update_type |= ADV_TRANS_GOAL;
303 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
304 && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) {
305 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
306 update_type |= ADV_TRANS_USER;
307 } else {
308 ccb->ccb_h.status = CAM_REQ_INVALID;
309 break;
310 }
984263bc 311
c1139c5e 312 crit_enter();
984263bc
MD
313 if ((update_type & ADV_TRANS_GOAL) != 0) {
314 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
315 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
316 adv->disc_enable |= targ_mask;
317 else
318 adv->disc_enable &= ~targ_mask;
319 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B,
320 adv->disc_enable);
321 }
322
323 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
324 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
325 adv->cmd_qng_enabled |= targ_mask;
326 else
327 adv->cmd_qng_enabled &= ~targ_mask;
328 }
329 }
330
331 if ((update_type & ADV_TRANS_USER) != 0) {
332 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
333 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
334 adv->user_disc_enable |= targ_mask;
335 else
336 adv->user_disc_enable &= ~targ_mask;
337 }
338
339 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
340 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
341 adv->user_cmd_qng_enabled |= targ_mask;
342 else
343 adv->user_cmd_qng_enabled &= ~targ_mask;
344 }
345 }
346
347 /*
348 * If the user specifies either the sync rate, or offset,
349 * but not both, the unspecified parameter defaults to its
350 * current value in transfer negotiations.
351 */
352 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
353 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
354 /*
355 * If the user provided a sync rate but no offset,
356 * use the current offset.
357 */
358 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0)
359 cts->sync_offset = tconf->offset;
360
361 /*
362 * If the user provided an offset but no sync rate,
363 * use the current sync rate.
364 */
365 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0)
366 cts->sync_period = tconf->period;
367
368 adv_period_offset_to_sdtr(adv, &cts->sync_period,
369 &cts->sync_offset,
370 cts->ccb_h.target_id);
371
372 adv_set_syncrate(adv, /*struct cam_path */NULL,
373 cts->ccb_h.target_id, cts->sync_period,
374 cts->sync_offset, update_type);
375 }
376
c1139c5e 377 crit_exit();
984263bc
MD
378 ccb->ccb_h.status = CAM_REQ_CMP;
379 xpt_done(ccb);
380 break;
381 }
382 case XPT_GET_TRAN_SETTINGS:
383 /* Get default/user set transfer settings for the target */
384 {
385 struct ccb_trans_settings *cts;
386 struct adv_transinfo *tconf;
387 target_bit_vector target_mask;
984263bc
MD
388
389 cts = &ccb->cts;
390 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
391
392 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
393
c1139c5e 394 crit_enter();
984263bc
MD
395 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
396 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
397 if ((adv->disc_enable & target_mask) != 0)
398 cts->flags |= CCB_TRANS_DISC_ENB;
399 if ((adv->cmd_qng_enabled & target_mask) != 0)
400 cts->flags |= CCB_TRANS_TAG_ENB;
401 } else {
402 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
403 if ((adv->user_disc_enable & target_mask) != 0)
404 cts->flags |= CCB_TRANS_DISC_ENB;
405 if ((adv->user_cmd_qng_enabled & target_mask) != 0)
406 cts->flags |= CCB_TRANS_TAG_ENB;
407 }
408
409 cts->sync_period = tconf->period;
410 cts->sync_offset = tconf->offset;
c1139c5e 411 crit_exit();
984263bc
MD
412
413 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
414 cts->valid = CCB_TRANS_SYNC_RATE_VALID
415 | CCB_TRANS_SYNC_OFFSET_VALID
416 | CCB_TRANS_BUS_WIDTH_VALID
417 | CCB_TRANS_DISC_VALID
418 | CCB_TRANS_TQ_VALID;
419 ccb->ccb_h.status = CAM_REQ_CMP;
420 xpt_done(ccb);
421 break;
422 }
423 case XPT_CALC_GEOMETRY:
424 {
425 struct ccb_calc_geometry *ccg;
426 u_int32_t size_mb;
427 u_int32_t secs_per_cylinder;
428 int extended;
429
430 ccg = &ccb->ccg;
431 size_mb = ccg->volume_size
432 / ((1024L * 1024L) / ccg->block_size);
433 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0;
434
435 if (size_mb > 1024 && extended) {
436 ccg->heads = 255;
437 ccg->secs_per_track = 63;
438 } else {
439 ccg->heads = 64;
440 ccg->secs_per_track = 32;
441 }
442 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
443 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
444 ccb->ccb_h.status = CAM_REQ_CMP;
445 xpt_done(ccb);
446 break;
447 }
448 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
449 {
c1139c5e 450 crit_enter();
984263bc
MD
451 adv_stop_execution(adv);
452 adv_reset_bus(adv, /*initiate_reset*/TRUE);
453 adv_start_execution(adv);
c1139c5e 454 crit_exit();
984263bc
MD
455
456 ccb->ccb_h.status = CAM_REQ_CMP;
457 xpt_done(ccb);
458 break;
459 }
460 case XPT_TERM_IO: /* Terminate the I/O process */
461 /* XXX Implement */
462 ccb->ccb_h.status = CAM_REQ_INVALID;
463 xpt_done(ccb);
464 break;
465 case XPT_PATH_INQ: /* Path routing inquiry */
466 {
467 struct ccb_pathinq *cpi = &ccb->cpi;
468
469 cpi->version_num = 1; /* XXX??? */
470 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
471 cpi->target_sprt = 0;
472 cpi->hba_misc = 0;
473 cpi->hba_eng_cnt = 0;
474 cpi->max_target = 7;
475 cpi->max_lun = 7;
476 cpi->initiator_id = adv->scsi_id;
477 cpi->bus_id = cam_sim_bus(sim);
478 cpi->base_transfer_speed = 3300;
479 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
480 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN);
481 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
482 cpi->unit_number = cam_sim_unit(sim);
483 cpi->ccb_h.status = CAM_REQ_CMP;
484 xpt_done(ccb);
485 break;
486 }
487 default:
488 ccb->ccb_h.status = CAM_REQ_INVALID;
489 xpt_done(ccb);
490 break;
491 }
492}
493
494/*
495 * Currently, the output of bus_dmammap_load suits our needs just
496 * fine, but should it change, we'd need to do something here.
497 */
498#define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs)
499
500static void
501adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
502 int nsegments, int error)
503{
504 struct ccb_scsiio *csio;
505 struct ccb_hdr *ccb_h;
506 struct cam_sim *sim;
507 struct adv_softc *adv;
508 struct adv_ccb_info *cinfo;
509 struct adv_scsi_q scsiq;
510 struct adv_sg_head sghead;
984263bc
MD
511
512 csio = (struct ccb_scsiio *)arg;
513 ccb_h = &csio->ccb_h;
514 sim = xpt_path_sim(ccb_h->path);
515 adv = (struct adv_softc *)cam_sim_softc(sim);
516 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr;
517
518 /*
519 * Setup our done routine to release the simq on
520 * the next ccb that completes.
521 */
522 if ((adv->state & ADV_BUSDMA_BLOCK) != 0)
523 adv->state |= ADV_BUSDMA_BLOCK_CLEARED;
524
525 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
526 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) {
527 /* XXX Need phystovirt!!!! */
528 /* How about pmap_kenter??? */
529 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
530 } else {
531 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
532 }
533 } else {
534 scsiq.cdbptr = csio->cdb_io.cdb_bytes;
535 }
536 /*
537 * Build up the request
538 */
539 scsiq.q1.status = 0;
540 scsiq.q1.q_no = 0;
541 scsiq.q1.cntl = 0;
542 scsiq.q1.sg_queue_cnt = 0;
543 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id);
544 scsiq.q1.target_lun = ccb_h->target_lun;
545 scsiq.q1.sense_len = csio->sense_len;
546 scsiq.q1.extra_bytes = 0;
547 scsiq.q2.ccb_index = cinfo - adv->ccb_infos;
548 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id,
549 ccb_h->target_lun);
550 scsiq.q2.flag = 0;
551 scsiq.q2.cdb_len = csio->cdb_len;
552 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0)
553 scsiq.q2.tag_code = csio->tag_action;
554 else
555 scsiq.q2.tag_code = 0;
556 scsiq.q2.vm_id = 0;
557
558 if (nsegments != 0) {
559 bus_dmasync_op_t op;
560
561 scsiq.q1.data_addr = dm_segs->ds_addr;
562 scsiq.q1.data_cnt = dm_segs->ds_len;
563 if (nsegments > 1) {
564 scsiq.q1.cntl |= QC_SG_HEAD;
565 sghead.entry_cnt
566 = sghead.entry_to_copy
567 = nsegments;
568 sghead.res = 0;
569 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs);
570 scsiq.sg_head = &sghead;
571 } else {
572 scsiq.sg_head = NULL;
573 }
574 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN)
575 op = BUS_DMASYNC_PREREAD;
576 else
577 op = BUS_DMASYNC_PREWRITE;
578 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
579 } else {
580 scsiq.q1.data_addr = 0;
581 scsiq.q1.data_cnt = 0;
582 scsiq.sg_head = NULL;
583 }
584
984263bc 585
c1139c5e 586 crit_enter();
984263bc
MD
587 /*
588 * Last time we need to check if this SCB needs to
589 * be aborted.
590 */
591 if (ccb_h->status != CAM_REQ_INPROG) {
592 if (nsegments != 0)
593 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
594 adv_clear_state(adv, (union ccb *)csio);
595 adv_free_ccb_info(adv, cinfo);
596 xpt_done((union ccb *)csio);
c1139c5e 597 crit_exit();
984263bc
MD
598 return;
599 }
600
601 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) {
602 /* Temporary resource shortage */
603 adv_set_state(adv, ADV_RESOURCE_SHORTAGE);
604 if (nsegments != 0)
605 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
606 csio->ccb_h.status = CAM_REQUEUE_REQ;
607 adv_clear_state(adv, (union ccb *)csio);
608 adv_free_ccb_info(adv, cinfo);
609 xpt_done((union ccb *)csio);
c1139c5e 610 crit_exit();
984263bc
MD
611 return;
612 }
613 cinfo->state |= ACCB_ACTIVE;
614 ccb_h->status |= CAM_SIM_QUEUED;
615 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le);
616 /* Schedule our timeout */
ddcafce9
JS
617 callout_reset(&ccb_h->timeout_ch, (ccb_h->timeout * hz)/1000,
618 adv_timeout, csio);
c1139c5e 619 crit_exit();
984263bc
MD
620}
621
622static struct adv_ccb_info *
623adv_alloc_ccb_info(struct adv_softc *adv)
624{
625 int error;
626 struct adv_ccb_info *cinfo;
627
628 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated];
629 cinfo->state = ACCB_FREE;
630 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0,
631 &cinfo->dmamap);
632 if (error != 0) {
e3869ec7 633 kprintf("%s: Unable to allocate CCB info "
984263bc
MD
634 "dmamap - error %d\n", adv_name(adv), error);
635 return (NULL);
636 }
637 adv->ccb_infos_allocated++;
638 return (cinfo);
639}
640
641static void
642adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
643{
644 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap);
645}
646
647void
648adv_timeout(void *arg)
649{
984263bc
MD
650 union ccb *ccb;
651 struct adv_softc *adv;
652 struct adv_ccb_info *cinfo;
653
654 ccb = (union ccb *)arg;
655 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc;
656 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
657
658 xpt_print_path(ccb->ccb_h.path);
e3869ec7 659 kprintf("Timed out\n");
984263bc 660
c1139c5e 661 crit_enter();
984263bc
MD
662 /* Have we been taken care of already?? */
663 if (cinfo == NULL || cinfo->state == ACCB_FREE) {
c1139c5e 664 crit_exit();
984263bc
MD
665 return;
666 }
667
668 adv_stop_execution(adv);
669
670 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) {
671 struct ccb_hdr *ccb_h;
672
673 /*
674 * In order to simplify the recovery process, we ask the XPT
675 * layer to halt the queue of new transactions and we traverse
676 * the list of pending CCBs and remove their timeouts. This
677 * means that the driver attempts to clear only one error
678 * condition at a time. In general, timeouts that occur
679 * close together are related anyway, so there is no benefit
680 * in attempting to handle errors in parrallel. Timeouts will
681 * be reinstated when the recovery process ends.
682 */
683 adv_set_state(adv, ADV_IN_TIMEOUT);
684
685 /* This CCB is the CCB representing our recovery actions */
686 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED;
687
688 ccb_h = LIST_FIRST(&adv->pending_ccbs);
689 while (ccb_h != NULL) {
ddcafce9 690 callout_stop(&ccb_h->timeout_ch);
984263bc
MD
691 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
692 }
693
694 /* XXX Should send a BDR */
695 /* Attempt an abort as our first tact */
696 xpt_print_path(ccb->ccb_h.path);
e3869ec7 697 kprintf("Attempting abort\n");
984263bc
MD
698 adv_abort_ccb(adv, ccb->ccb_h.target_id,
699 ccb->ccb_h.target_lun, ccb,
700 CAM_CMD_TIMEOUT, /*queued_only*/FALSE);
ddcafce9 701 callout_reset(&ccb->ccb_h.timeout_ch, 2 * hz, adv_timeout, ccb);
984263bc
MD
702 } else {
703 /* Our attempt to perform an abort failed, go for a reset */
704 xpt_print_path(ccb->ccb_h.path);
e3869ec7 705 kprintf("Resetting bus\n");
984263bc
MD
706 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
707 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
708 adv_reset_bus(adv, /*initiate_reset*/TRUE);
709 }
710 adv_start_execution(adv);
c1139c5e 711 crit_exit();
984263bc
MD
712}
713
714struct adv_softc *
715adv_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh)
716{
717 struct adv_softc *adv = device_get_softc(dev);
718
719 /*
720 * Allocate a storage area for us
721 */
722 LIST_INIT(&adv->pending_ccbs);
723 SLIST_INIT(&adv->free_ccb_infos);
724 adv->dev = dev;
725 adv->unit = device_get_unit(dev);
726 adv->tag = tag;
727 adv->bsh = bsh;
728
729 return(adv);
730}
731
732void
733adv_free(struct adv_softc *adv)
734{
735 switch (adv->init_level) {
736 case 6:
737 {
738 struct adv_ccb_info *cinfo;
739
740 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
741 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
742 adv_destroy_ccb_info(adv, cinfo);
743 }
744
745 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap);
746 }
747 case 5:
748 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers,
749 adv->sense_dmamap);
750 case 4:
751 bus_dma_tag_destroy(adv->sense_dmat);
752 case 3:
753 bus_dma_tag_destroy(adv->buffer_dmat);
754 case 2:
755 bus_dma_tag_destroy(adv->parent_dmat);
756 case 1:
757 if (adv->ccb_infos != NULL)
efda3bd0 758 kfree(adv->ccb_infos, M_DEVBUF);
984263bc
MD
759 case 0:
760 break;
761 }
762}
763
764int
765adv_init(struct adv_softc *adv)
766{
767 struct adv_eeprom_config eeprom_config;
768 int checksum, i;
769 int max_sync;
770 u_int16_t config_lsw;
771 u_int16_t config_msw;
772
773 adv_lib_init(adv);
774
775 /*
776 * Stop script execution.
777 */
778 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE);
779 adv_stop_execution(adv);
780 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) {
e3869ec7 781 kprintf("adv%d: Unable to halt adapter. Initialization"
984263bc
MD
782 "failed\n", adv->unit);
783 return (1);
784 }
785 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
786 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
e3869ec7 787 kprintf("adv%d: Unable to set program counter. Initialization"
984263bc
MD
788 "failed\n", adv->unit);
789 return (1);
790 }
791
792 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
793 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
794
795 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) {
796 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
797 /*
798 * XXX The Linux code flags this as an error,
799 * but what should we report to the user???
800 * It seems that clearing the config register
801 * makes this error recoverable.
802 */
803 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
804 }
805
806 /* Suck in the configuration from the EEProm */
807 checksum = adv_get_eeprom_config(adv, &eeprom_config);
808
809 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) {
810 /*
811 * XXX The Linux code sets a warning level for this
812 * condition, yet nothing of meaning is printed to
813 * the user. What does this mean???
814 */
815 if (adv->chip_version == 3) {
816 if (eeprom_config.cfg_lsw != config_lsw)
817 eeprom_config.cfg_lsw = config_lsw;
818 if (eeprom_config.cfg_msw != config_msw) {
819 eeprom_config.cfg_msw = config_msw;
820 }
821 }
822 }
823 if (checksum == eeprom_config.chksum) {
824
825 /* Range/Sanity checking */
826 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) {
827 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG;
828 }
829 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) {
830 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG;
831 }
832 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) {
833 eeprom_config.max_tag_qng = eeprom_config.max_total_qng;
834 }
835 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) {
836 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC;
837 }
838 adv->max_openings = eeprom_config.max_total_qng;
839 adv->user_disc_enable = eeprom_config.disc_enable;
840 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng;
841 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config);
842 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID;
843 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id);
844 adv->control = eeprom_config.cntl;
845 for (i = 0; i <= ADV_MAX_TID; i++) {
846 u_int8_t sync_data;
847
848 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0)
849 sync_data = 0;
850 else
851 sync_data = eeprom_config.sdtr_data[i];
852 adv_sdtr_to_period_offset(adv,
853 sync_data,
854 &adv->tinfo[i].user.period,
855 &adv->tinfo[i].user.offset,
856 i);
857 }
858 config_lsw = eeprom_config.cfg_lsw;
859 eeprom_config.cfg_msw = config_msw;
860 } else {
861 u_int8_t sync_data;
862
e3869ec7 863 kprintf("adv%d: Warning EEPROM Checksum mismatch. "
984263bc
MD
864 "Using default device parameters\n", adv->unit);
865
866 /* Set reasonable defaults since we can't read the EEPROM */
867 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1;
868 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG;
869 adv->disc_enable = TARGET_BIT_VECTOR_SET;
870 adv->user_disc_enable = TARGET_BIT_VECTOR_SET;
871 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
872 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
873 adv->scsi_id = 7;
874 adv->control = 0xFFFF;
875
876 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
877 /* Default to no Ultra to support the 3030 */
878 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA;
879 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4);
880 for (i = 0; i <= ADV_MAX_TID; i++) {
881 adv_sdtr_to_period_offset(adv, sync_data,
882 &adv->tinfo[i].user.period,
883 &adv->tinfo[i].user.offset,
884 i);
885 }
886 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON;
887 }
888 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
889 config_lsw |= ADV_CFG_LSW_HOST_INT_ON;
890 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)
891 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0)
892 /* 25ns or 10MHz */
893 max_sync = 25;
894 else
895 /* Unlimited */
896 max_sync = 0;
897 for (i = 0; i <= ADV_MAX_TID; i++) {
898 if (adv->tinfo[i].user.period < max_sync)
899 adv->tinfo[i].user.period = max_sync;
900 }
901
902 if (adv_test_external_lram(adv) == 0) {
903 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) {
904 eeprom_config.max_total_qng =
905 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
906 eeprom_config.max_tag_qng =
907 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG;
908 } else {
909 eeprom_config.cfg_msw |= 0x0800;
910 config_msw |= 0x0800;
911 eeprom_config.max_total_qng =
912 ADV_MAX_PCI_INRAM_TOTAL_QNG;
913 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG;
914 }
915 adv->max_openings = eeprom_config.max_total_qng;
916 }
917 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
918 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw);
919#if 0
920 /*
921 * Don't write the eeprom data back for now.
922 * I'd rather not mess up the user's card. We also don't
923 * fully sanitize the eeprom settings above for the write-back
924 * to be 100% correct.
925 */
926 if (adv_set_eeprom_config(adv, &eeprom_config) != 0)
e3869ec7 927 kprintf("%s: WARNING! Failure writing to EEPROM.\n",
984263bc
MD
928 adv_name(adv));
929#endif
930
931 adv_set_chip_scsiid(adv, adv->scsi_id);
932 if (adv_init_lram_and_mcode(adv))
933 return (1);
934
935 adv->disc_enable = adv->user_disc_enable;
936
937 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
938 for (i = 0; i <= ADV_MAX_TID; i++) {
939 /*
940 * Start off in async mode.
941 */
942 adv_set_syncrate(adv, /*struct cam_path */NULL,
943 i, /*period*/0, /*offset*/0,
944 ADV_TRANS_CUR);
945 /*
946 * Enable the use of tagged commands on all targets.
947 * This allows the kernel driver to make up it's own mind
948 * as it sees fit to tag queue instead of having the
949 * firmware try and second guess the tag_code settins.
950 */
951 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i,
952 adv->max_openings);
953 }
954 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
955 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
e3869ec7 956 kprintf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n",
984263bc
MD
957 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0)
958 ? "Ultra SCSI" : "SCSI",
959 adv->scsi_id, adv->max_openings);
960 return (0);
961}
962
963void
964adv_intr(void *arg)
965{
966 struct adv_softc *adv;
967 u_int16_t chipstat;
968 u_int16_t saved_ram_addr;
969 u_int8_t ctrl_reg;
970 u_int8_t saved_ctrl_reg;
971 u_int8_t host_flag;
972
973 adv = (struct adv_softc *)arg;
974
975 chipstat = ADV_INW(adv, ADV_CHIP_STATUS);
976
977 /* Is it for us? */
978 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0)
979 return;
980
981 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL);
982 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET |
983 ADV_CC_SINGLE_STEP | ADV_CC_DIAG |
984 ADV_CC_TEST));
985
986 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) {
e3869ec7 987 kprintf("Detected Bus Reset\n");
984263bc
MD
988 adv_reset_bus(adv, /*initiate_reset*/FALSE);
989 return;
990 }
991
992 if ((chipstat & ADV_CSW_INT_PENDING) != 0) {
993
994 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR);
995 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
996 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
997 host_flag | ADV_HOST_FLAG_IN_ISR);
998
999 adv_ack_interrupt(adv);
1000
1001 if ((chipstat & ADV_CSW_HALTED) != 0
1002 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) {
1003 adv_isr_chip_halted(adv);
1004 saved_ctrl_reg &= ~ADV_CC_HALT;
1005 } else {
1006 adv_run_doneq(adv);
1007 }
1008 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr);
1009#ifdef DIAGNOSTIC
1010 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr)
1011 panic("adv_intr: Unable to set LRAM addr");
1012#endif
1013 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
1014 }
1015
1016 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg);
1017}
1018
1019void
1020adv_run_doneq(struct adv_softc *adv)
1021{
1022 struct adv_q_done_info scsiq;
1023 u_int doneq_head;
1024 u_int done_qno;
1025
1026 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF;
1027 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head)
1028 + ADV_SCSIQ_B_FWD);
1029 while (done_qno != ADV_QLINK_END) {
1030 union ccb* ccb;
1031 struct adv_ccb_info *cinfo;
1032 u_int done_qaddr;
1033 u_int sg_queue_cnt;
1034 int aborted;
1035
1036 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1037
1038 /* Pull status from this request */
1039 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq,
1040 adv->max_dma_count);
1041
1042 /* Mark it as free */
1043 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS,
1044 scsiq.q_status & ~(QS_READY|QS_ABORTED));
1045
1046 /* Process request based on retrieved info */
1047 if ((scsiq.cntl & QC_SG_HEAD) != 0) {
1048 u_int i;
1049
1050 /*
1051 * S/G based request. Free all of the queue
1052 * structures that contained S/G information.
1053 */
1054 for (i = 0; i < sg_queue_cnt; i++) {
1055 done_qno = adv_read_lram_8(adv, done_qaddr
1056 + ADV_SCSIQ_B_FWD);
1057
1058#ifdef DIAGNOSTIC
1059 if (done_qno == ADV_QLINK_END) {
1060 panic("adv_qdone: Corrupted SG "
1061 "list encountered");
1062 }
1063#endif
1064 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1065
1066 /* Mark SG queue as free */
1067 adv_write_lram_8(adv, done_qaddr
1068 + ADV_SCSIQ_B_STATUS, QS_FREE);
1069 }
1070 } else
1071 sg_queue_cnt = 0;
1072#ifdef DIAGNOSTIC
1073 if (adv->cur_active < (sg_queue_cnt + 1))
1074 panic("adv_qdone: Attempting to free more "
1075 "queues than are active");
1076#endif
1077 adv->cur_active -= sg_queue_cnt + 1;
1078
1079 aborted = (scsiq.q_status & QS_ABORTED) != 0;
1080
1081 if ((scsiq.q_status != QS_DONE)
1082 && (scsiq.q_status & QS_ABORTED) == 0)
1083 panic("adv_qdone: completed scsiq with unknown status");
1084
1085 scsiq.remain_bytes += scsiq.extra_bytes;
1086
1087 if ((scsiq.d3.done_stat == QD_WITH_ERROR) &&
1088 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) {
1089 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) {
1090 scsiq.d3.done_stat = QD_NO_ERROR;
1091 scsiq.d3.host_stat = QHSTA_NO_ERROR;
1092 }
1093 }
1094
1095 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index];
1096 ccb = cinfo->ccb;
1097 ccb->csio.resid = scsiq.remain_bytes;
1098 adv_done(adv, ccb,
1099 scsiq.d3.done_stat, scsiq.d3.host_stat,
1100 scsiq.d3.scsi_stat, scsiq.q_no);
1101
1102 doneq_head = done_qno;
1103 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD);
1104 }
1105 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head);
1106}
1107
1108
1109void
1110adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat,
1111 u_int host_stat, u_int scsi_status, u_int q_no)
1112{
1113 struct adv_ccb_info *cinfo;
1114
1115 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
1116 LIST_REMOVE(&ccb->ccb_h, sim_links.le);
ddcafce9 1117 callout_stop(&ccb->ccb_h.timeout_ch);
984263bc
MD
1118 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1119 bus_dmasync_op_t op;
1120
1121 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1122 op = BUS_DMASYNC_POSTREAD;
1123 else
1124 op = BUS_DMASYNC_POSTWRITE;
1125 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
1126 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
1127 }
1128
1129 switch (done_stat) {
1130 case QD_NO_ERROR:
1131 if (host_stat == QHSTA_NO_ERROR) {
1132 ccb->ccb_h.status = CAM_REQ_CMP;
1133 break;
1134 }
1135 xpt_print_path(ccb->ccb_h.path);
e3869ec7 1136 kprintf("adv_done - queue done without error, "
984263bc
MD
1137 "but host status non-zero(%x)\n", host_stat);
1138 /*FALLTHROUGH*/
1139 case QD_WITH_ERROR:
1140 switch (host_stat) {
1141 case QHSTA_M_TARGET_STATUS_BUSY:
1142 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY:
1143 /*
1144 * Assume that if we were a tagged transaction
1145 * the target reported queue full. Otherwise,
1146 * report busy. The firmware really should just
1147 * pass the original status back up to us even
1148 * if it thinks the target was in error for
1149 * returning this status as no other transactions
1150 * from this initiator are in effect, but this
1151 * ignores multi-initiator setups and there is
1152 * evidence that the firmware gets its per-device
1153 * transaction counts screwed up occassionally.
1154 */
1155 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1156 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
1157 && host_stat != QHSTA_M_TARGET_STATUS_BUSY)
1158 scsi_status = SCSI_STATUS_QUEUE_FULL;
1159 else
1160 scsi_status = SCSI_STATUS_BUSY;
1161 adv_abort_ccb(adv, ccb->ccb_h.target_id,
1162 ccb->ccb_h.target_lun,
1163 /*ccb*/NULL, CAM_REQUEUE_REQ,
1164 /*queued_only*/TRUE);
1165 /*FALLTHROUGH*/
1166 case QHSTA_M_NO_AUTO_REQ_SENSE:
1167 case QHSTA_NO_ERROR:
1168 ccb->csio.scsi_status = scsi_status;
1169 switch (scsi_status) {
1170 case SCSI_STATUS_CHECK_COND:
1171 case SCSI_STATUS_CMD_TERMINATED:
1172 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1173 /* Structure copy */
1174 ccb->csio.sense_data =
1175 adv->sense_buffers[q_no - 1];
1176 /* FALLTHROUGH */
1177 case SCSI_STATUS_BUSY:
1178 case SCSI_STATUS_RESERV_CONFLICT:
1179 case SCSI_STATUS_QUEUE_FULL:
1180 case SCSI_STATUS_COND_MET:
1181 case SCSI_STATUS_INTERMED:
1182 case SCSI_STATUS_INTERMED_COND_MET:
1183 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1184 break;
1185 case SCSI_STATUS_OK:
1186 ccb->ccb_h.status |= CAM_REQ_CMP;
1187 break;
1188 }
1189 break;
1190 case QHSTA_M_SEL_TIMEOUT:
1191 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1192 break;
1193 case QHSTA_M_DATA_OVER_RUN:
1194 ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1195 break;
1196 case QHSTA_M_UNEXPECTED_BUS_FREE:
1197 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1198 break;
1199 case QHSTA_M_BAD_BUS_PHASE_SEQ:
1200 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1201 break;
1202 case QHSTA_M_BAD_CMPL_STATUS_IN:
1203 /* No command complete after a status message */
1204 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1205 break;
1206 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT:
1207 case QHSTA_M_WTM_TIMEOUT:
1208 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET:
1209 /* The SCSI bus hung in a phase */
1210 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1211 adv_reset_bus(adv, /*initiate_reset*/TRUE);
1212 break;
1213 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1214 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1215 break;
1216 case QHSTA_D_QDONE_SG_LIST_CORRUPTED:
1217 case QHSTA_D_ASC_DVC_ERROR_CODE_SET:
1218 case QHSTA_D_HOST_ABORT_FAILED:
1219 case QHSTA_D_EXE_SCSI_Q_FAILED:
1220 case QHSTA_D_ASPI_NO_BUF_POOL:
1221 case QHSTA_M_BAD_TAG_CODE:
1222 case QHSTA_D_LRAM_CMP_ERROR:
1223 case QHSTA_M_MICRO_CODE_ERROR_HALT:
1224 default:
1225 panic("%s: Unhandled Host status error %x",
1226 adv_name(adv), host_stat);
1227 /* NOTREACHED */
1228 }
1229 break;
1230
1231 case QD_ABORTED_BY_HOST:
1232 /* Don't clobber any, more explicit, error codes we've set */
1233 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1234 ccb->ccb_h.status = CAM_REQ_ABORTED;
1235 break;
1236
1237 default:
1238 xpt_print_path(ccb->ccb_h.path);
e3869ec7 1239 kprintf("adv_done - queue done with unknown status %x:%x\n",
984263bc
MD
1240 done_stat, host_stat);
1241 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1242 break;
1243 }
1244 adv_clear_state(adv, ccb);
1245 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP
1246 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
1247 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1248 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1249 }
1250 adv_free_ccb_info(adv, cinfo);
1251 /*
1252 * Null this out so that we catch driver bugs that cause a
1253 * ccb to be completed twice.
1254 */
1255 ccb->ccb_h.ccb_cinfo_ptr = NULL;
1256 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
1257 xpt_done(ccb);
1258}
1259
1260/*
1261 * Function to poll for command completion when
1262 * interrupts are disabled (crash dumps)
1263 */
1264static void
1265adv_poll(struct cam_sim *sim)
1266{
1267 adv_intr(cam_sim_softc(sim));
1268}
1269
1270/*
1271 * Attach all the sub-devices we can find
1272 */
1273int
1274adv_attach(adv)
1275 struct adv_softc *adv;
1276{
1277 struct ccb_setasync csa;
984263bc
MD
1278 int max_sg;
1279
1280 /*
1281 * Allocate an array of ccb mapping structures. We put the
1282 * index of the ccb_info structure into the queue representing
1283 * a transaction and use it for mapping the queue to the
1284 * upper level SCSI transaction it represents.
1285 */
efda3bd0 1286 adv->ccb_infos = kmalloc(sizeof(*adv->ccb_infos) * adv->max_openings,
3aed1355 1287 M_DEVBUF, M_WAITOK);
984263bc
MD
1288 adv->init_level++;
1289
1290 /*
1291 * Create our DMA tags. These tags define the kinds of device
1292 * accessible memory allocations and memory mappings we will
1293 * need to perform during normal operation.
1294 *
1295 * Unless we need to further restrict the allocation, we rely
1296 * on the restrictions of the parent dmat, hence the common
1297 * use of MAXADDR and MAXSIZE.
1298 *
1299 * The ASC boards use chains of "queues" (the transactional
1300 * resources on the board) to represent long S/G lists.
1301 * The first queue represents the command and holds a
1302 * single address and data pair. The queues that follow
1303 * can each hold ADV_SG_LIST_PER_Q entries. Given the
1304 * total number of queues, we can express the largest
1305 * transaction we can map. We reserve a few queues for
1306 * error recovery. Take those into account as well.
1307 *
1308 * There is a way to take an interrupt to download the
1309 * next batch of S/G entries if there are more than 255
1310 * of them (the counter in the queue structure is a u_int8_t).
1311 * We don't use this feature, so limit the S/G list size
1312 * accordingly.
1313 */
1314 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q;
1315 if (max_sg > 255)
1316 max_sg = 255;
1317
1318 /* DMA tag for mapping buffers into device visible space. */
1319 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1320 /*lowaddr*/BUS_SPACE_MAXADDR,
1321 /*highaddr*/BUS_SPACE_MAXADDR,
1322 /*filter*/NULL, /*filterarg*/NULL,
1323 /*maxsize*/MAXPHYS,
1324 /*nsegments*/max_sg,
1325 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1326 /*flags*/BUS_DMA_ALLOCNOW,
1327 &adv->buffer_dmat) != 0) {
1328 return (ENXIO);
1329 }
1330 adv->init_level++;
1331
1332 /* DMA tag for our sense buffers */
1333 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1334 /*lowaddr*/BUS_SPACE_MAXADDR,
1335 /*highaddr*/BUS_SPACE_MAXADDR,
1336 /*filter*/NULL, /*filterarg*/NULL,
1337 sizeof(struct scsi_sense_data)*adv->max_openings,
1338 /*nsegments*/1,
1339 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1340 /*flags*/0, &adv->sense_dmat) != 0) {
1341 return (ENXIO);
1342 }
1343
1344 adv->init_level++;
1345
1346 /* Allocation for our sense buffers */
1347 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers,
1348 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) {
1349 return (ENOMEM);
1350 }
1351
1352 adv->init_level++;
1353
1354 /* And permanently map them */
1355 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap,
1356 adv->sense_buffers,
1357 sizeof(struct scsi_sense_data)*adv->max_openings,
1358 adv_map, &adv->sense_physbase, /*flags*/0);
1359
1360 adv->init_level++;
1361
1362 /*
1363 * Fire up the chip
1364 */
1365 if (adv_start_chip(adv) != 1) {
e3869ec7 1366 kprintf("adv%d: Unable to start on board processor. Aborting.\n",
984263bc
MD
1367 adv->unit);
1368 return (ENXIO);
1369 }
1370
984263bc
MD
1371 /*
1372 * Construct our SIM entry.
1373 */
1374 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit,
3aed1355 1375 1, adv->max_openings, NULL);
984263bc
MD
1376 if (adv->sim == NULL)
1377 return (ENOMEM);
1378
1379 /*
1380 * Register the bus.
1381 *
1382 * XXX Twin Channel EISA Cards???
1383 */
1384 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) {
3aed1355 1385 cam_sim_free(adv->sim);
984263bc
MD
1386 return (ENXIO);
1387 }
1388
1389 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim),
1390 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1391 != CAM_REQ_CMP) {
1392 xpt_bus_deregister(cam_sim_path(adv->sim));
3aed1355 1393 cam_sim_free(adv->sim);
984263bc
MD
1394 return (ENXIO);
1395 }
1396
1397 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5);
1398 csa.ccb_h.func_code = XPT_SASYNC_CB;
1399 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
1400 csa.callback = advasync;
1401 csa.callback_arg = adv;
1402 xpt_action((union ccb *)&csa);
1403 return (0);
1404}