Rename printf -> kprintf in sys/ and add some defines where necessary
[dragonfly.git] / sys / dev / disk / sym / sym_hipd.c
CommitLineData
984263bc
MD
1/*
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58/* $FreeBSD: src/sys/dev/sym/sym_hipd.c,v 1.6.2.12 2001/12/02 19:01:10 groudier Exp $ */
e3869ec7 59/* $DragonFly: src/sys/dev/disk/sym/sym_hipd.c,v 1.20 2006/12/22 23:26:17 swildner Exp $ */
984263bc
MD
60
61#define SYM_DRIVER_NAME "sym-1.6.5-20000902"
62
63/* #define SYM_DEBUG_GENERIC_SUPPORT */
64/* #define CAM_NEW_TRAN_CODE */
65
1f2de5d4 66#include "use_pci.h"
984263bc
MD
67#include <sys/param.h>
68
69/*
70 * Only use the BUS stuff for PCI under FreeBSD 4 and later versions.
71 * Note that the old BUS stuff also works for FreeBSD 4 and spares
72 * about 1 KB for the driver object file.
73 */
84754cd0 74#if defined(__DragonFly__) || __FreeBSD_version >= 400000
984263bc
MD
75#define FreeBSD_Bus_Dma_Abstraction
76#define FreeBSD_Bus_Io_Abstraction
77#define FreeBSD_Bus_Space_Abstraction
78#endif
79
80/*
81 * Driver configuration options.
82 */
83#include "opt_sym.h"
1f2de5d4 84#include "sym_conf.h"
984263bc
MD
85
86#ifndef FreeBSD_Bus_Io_Abstraction
1f2de5d4 87#include "use_ncr.h" /* To know if the ncr has been configured */
984263bc
MD
88#endif
89
90#include <sys/systm.h>
91#include <sys/malloc.h>
92#include <sys/kernel.h>
93#ifdef FreeBSD_Bus_Io_Abstraction
94#include <sys/module.h>
95#include <sys/bus.h>
1f7ab7c9 96#include <sys/rman.h>
984263bc 97#endif
2c9868e4 98#include <sys/thread2.h>
984263bc
MD
99
100#include <sys/proc.h>
101
1f2de5d4
MD
102#include <bus/pci/pcireg.h>
103#include <bus/pci/pcivar.h>
984263bc 104
984263bc
MD
105#include <machine/clock.h>
106
1f2de5d4
MD
107#include <bus/cam/cam.h>
108#include <bus/cam/cam_ccb.h>
109#include <bus/cam/cam_sim.h>
110#include <bus/cam/cam_xpt_sim.h>
111#include <bus/cam/cam_debug.h>
984263bc 112
1f2de5d4
MD
113#include <bus/cam/scsi/scsi_all.h>
114#include <bus/cam/scsi/scsi_message.h>
984263bc
MD
115
116#include <vm/vm.h>
117#include <vm/vm_param.h>
118#include <vm/pmap.h>
119
120/* Short and quite clear integer types */
121typedef int8_t s8;
122typedef int16_t s16;
123typedef int32_t s32;
124typedef u_int8_t u8;
125typedef u_int16_t u16;
126typedef u_int32_t u32;
127
128/*
129 * From 'cam.error_recovery_diffs.20010313.context' patch.
130 */
131#ifdef CAM_NEW_TRAN_CODE
132#define FreeBSD_New_Tran_Settings
133#endif /* CAM_NEW_TRAN_CODE */
134
135/*
136 * Driver definitions.
137 */
1f2de5d4
MD
138#include "sym_defs.h"
139#include "sym_fw.h"
984263bc
MD
140
141/*
142 * IA32 architecture does not reorder STORES and prevents
143 * LOADS from passing STORES. It is called `program order'
144 * by Intel and allows device drivers to deal with memory
145 * ordering by only ensuring that the code is not reordered
146 * by the compiler when ordering is required.
147 * Other architectures implement a weaker ordering that
148 * requires memory barriers (and also IO barriers when they
149 * make sense) to be used.
150 */
151
152#if defined __i386__
153#define MEMORY_BARRIER() do { ; } while(0)
984263bc
MD
154#elif defined __powerpc__
155#define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
156#elif defined __ia64__
157#define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
158#elif defined __sparc64__
159#define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory")
160#else
161#error "Not supported platform"
162#endif
163
164/*
165 * Portable but silly implemented byte order primitives.
166 * We define the primitives we need, since FreeBSD doesn't
167 * seem to have them yet.
168 */
169#if BYTE_ORDER == BIG_ENDIAN
170
171#define __revb16(x) ( (((u16)(x) & (u16)0x00ffU) << 8) | \
172 (((u16)(x) & (u16)0xff00U) >> 8) )
173#define __revb32(x) ( (((u32)(x) & 0x000000ffU) << 24) | \
174 (((u32)(x) & 0x0000ff00U) << 8) | \
175 (((u32)(x) & 0x00ff0000U) >> 8) | \
176 (((u32)(x) & 0xff000000U) >> 24) )
177
178#define __htole16(v) __revb16(v)
179#define __htole32(v) __revb32(v)
180#define __le16toh(v) __htole16(v)
181#define __le32toh(v) __htole32(v)
182
183static __inline u16 _htole16(u16 v) { return __htole16(v); }
184static __inline u32 _htole32(u32 v) { return __htole32(v); }
185#define _le16toh _htole16
186#define _le32toh _htole32
187
188#else /* LITTLE ENDIAN */
189
190#define __htole16(v) (v)
191#define __htole32(v) (v)
192#define __le16toh(v) (v)
193#define __le32toh(v) (v)
194
195#define _htole16(v) (v)
196#define _htole32(v) (v)
197#define _le16toh(v) (v)
198#define _le32toh(v) (v)
199
200#endif /* BYTE_ORDER */
201
202/*
203 * A la VMS/CAM-3 queue management.
204 */
205
206typedef struct sym_quehead {
207 struct sym_quehead *flink; /* Forward pointer */
208 struct sym_quehead *blink; /* Backward pointer */
209} SYM_QUEHEAD;
210
211#define sym_que_init(ptr) do { \
212 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \
213} while (0)
214
215static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head)
216{
217 return (head->flink == head) ? 0 : head->flink;
218}
219
220static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head)
221{
222 return (head->blink == head) ? 0 : head->blink;
223}
224
225static __inline void __sym_que_add(struct sym_quehead * new,
226 struct sym_quehead * blink,
227 struct sym_quehead * flink)
228{
229 flink->blink = new;
230 new->flink = flink;
231 new->blink = blink;
232 blink->flink = new;
233}
234
235static __inline void __sym_que_del(struct sym_quehead * blink,
236 struct sym_quehead * flink)
237{
238 flink->blink = blink;
239 blink->flink = flink;
240}
241
242static __inline int sym_que_empty(struct sym_quehead *head)
243{
244 return head->flink == head;
245}
246
247static __inline void sym_que_splice(struct sym_quehead *list,
248 struct sym_quehead *head)
249{
250 struct sym_quehead *first = list->flink;
251
252 if (first != list) {
253 struct sym_quehead *last = list->blink;
254 struct sym_quehead *at = head->flink;
255
256 first->blink = head;
257 head->flink = first;
258
259 last->flink = at;
260 at->blink = last;
261 }
262}
263
264#define sym_que_entry(ptr, type, member) \
265 ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member)))
266
267
268#define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
269
270#define sym_remque(el) __sym_que_del((el)->blink, (el)->flink)
271
272#define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink)
273
274static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head)
275{
276 struct sym_quehead *elem = head->flink;
277
278 if (elem != head)
279 __sym_que_del(head, elem->flink);
280 else
281 elem = 0;
282 return elem;
283}
284
285#define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head)
286
287static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head)
288{
289 struct sym_quehead *elem = head->blink;
290
291 if (elem != head)
292 __sym_que_del(elem->blink, head);
293 else
294 elem = 0;
295 return elem;
296}
297
298/*
299 * This one may be useful.
300 */
301#define FOR_EACH_QUEUED_ELEMENT(head, qp) \
302 for (qp = (head)->flink; qp != (head); qp = qp->flink)
303/*
304 * FreeBSD does not offer our kind of queue in the CAM CCB.
305 * So, we have to cast.
306 */
307#define sym_qptr(p) ((struct sym_quehead *) (p))
308
309/*
310 * Simple bitmap operations.
311 */
312#define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))
313#define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))
314#define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))
315
316/*
317 * Number of tasks per device we want to handle.
318 */
319#if SYM_CONF_MAX_TAG_ORDER > 8
320#error "more than 256 tags per logical unit not allowed."
321#endif
322#define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER)
323
324/*
325 * Donnot use more tasks that we can handle.
326 */
327#ifndef SYM_CONF_MAX_TAG
328#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
329#endif
330#if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK
331#undef SYM_CONF_MAX_TAG
332#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
333#endif
334
335/*
336 * This one means 'NO TAG for this job'
337 */
338#define NO_TAG (256)
339
340/*
341 * Number of SCSI targets.
342 */
343#if SYM_CONF_MAX_TARGET > 16
344#error "more than 16 targets not allowed."
345#endif
346
347/*
348 * Number of logical units per target.
349 */
350#if SYM_CONF_MAX_LUN > 64
351#error "more than 64 logical units per target not allowed."
352#endif
353
354/*
355 * Asynchronous pre-scaler (ns). Shall be 40 for
356 * the SCSI timings to be compliant.
357 */
358#define SYM_CONF_MIN_ASYNC (40)
359
360/*
361 * Number of entries in the START and DONE queues.
362 *
363 * We limit to 1 PAGE in order to succeed allocation of
364 * these queues. Each entry is 8 bytes long (2 DWORDS).
365 */
366#ifdef SYM_CONF_MAX_START
367#define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2)
368#else
369#define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2)
370#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
371#endif
372
373#if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8
374#undef SYM_CONF_MAX_QUEUE
375#define SYM_CONF_MAX_QUEUE PAGE_SIZE/8
376#undef SYM_CONF_MAX_START
377#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
378#endif
379
380/*
381 * For this one, we want a short name :-)
382 */
383#define MAX_QUEUE SYM_CONF_MAX_QUEUE
384
984263bc
MD
385/*
386 * Active debugging tags and verbosity.
387 */
388#define DEBUG_ALLOC (0x0001)
389#define DEBUG_PHASE (0x0002)
390#define DEBUG_POLL (0x0004)
391#define DEBUG_QUEUE (0x0008)
392#define DEBUG_RESULT (0x0010)
393#define DEBUG_SCATTER (0x0020)
394#define DEBUG_SCRIPT (0x0040)
395#define DEBUG_TINY (0x0080)
396#define DEBUG_TIMING (0x0100)
397#define DEBUG_NEGO (0x0200)
398#define DEBUG_TAGS (0x0400)
399#define DEBUG_POINTER (0x0800)
400
401#if 0
402static int sym_debug = 0;
403 #define DEBUG_FLAGS sym_debug
404#else
405/* #define DEBUG_FLAGS (0x0631) */
406 #define DEBUG_FLAGS (0x0000)
407
408#endif
409#define sym_verbose (np->verbose)
410
411/*
412 * Insert a delay in micro-seconds and milli-seconds.
413 */
414static void UDELAY(int us) { DELAY(us); }
415static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
416
417/*
418 * Simple power of two buddy-like allocator.
419 *
420 * This simple code is not intended to be fast, but to
421 * provide power of 2 aligned memory allocations.
422 * Since the SCRIPTS processor only supplies 8 bit arithmetic,
423 * this allocator allows simple and fast address calculations
424 * from the SCRIPTS code. In addition, cache line alignment
425 * is guaranteed for power of 2 cache line size.
426 *
427 * This allocator has been developped for the Linux sym53c8xx
428 * driver, since this O/S does not provide naturally aligned
429 * allocations.
430 * It has the advantage of allowing the driver to use private
431 * pages of memory that will be useful if we ever need to deal
432 * with IO MMUs for PCI.
433 */
434
435#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
436#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
437#if 0
438#define MEMO_FREE_UNUSED /* Free unused pages immediately */
439#endif
440#define MEMO_WARN 1
441#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
442#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
443#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
444
efda3bd0
MD
445#define get_pages() kmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_INTWAIT)
446#define free_pages(p) kfree((p), M_DEVBUF)
984263bc
MD
447
448typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
449
450typedef struct m_link { /* Link between free memory chunks */
451 struct m_link *next;
452} m_link_s;
453
454#ifdef FreeBSD_Bus_Dma_Abstraction
455typedef struct m_vtob { /* Virtual to Bus address translation */
456 struct m_vtob *next;
457 bus_dmamap_t dmamap; /* Map for this chunk */
458 m_addr_t vaddr; /* Virtual address */
459 m_addr_t baddr; /* Bus physical address */
460} m_vtob_s;
461/* Hash this stuff a bit to speed up translations */
462#define VTOB_HASH_SHIFT 5
463#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
464#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
465#define VTOB_HASH_CODE(m) \
466 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
467#endif
468
469typedef struct m_pool { /* Memory pool of a given kind */
470#ifdef FreeBSD_Bus_Dma_Abstraction
471 bus_dma_tag_t dev_dmat; /* Identifies the pool */
472 bus_dma_tag_t dmat; /* Tag for our fixed allocations */
473 m_addr_t (*getp)(struct m_pool *);
474#ifdef MEMO_FREE_UNUSED
475 void (*freep)(struct m_pool *, m_addr_t);
476#endif
477#define M_GETP() mp->getp(mp)
478#define M_FREEP(p) mp->freep(mp, p)
479 int nump;
480 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
481 struct m_pool *next;
482#else
483#define M_GETP() get_pages()
484#define M_FREEP(p) free_pages(p)
485#endif /* FreeBSD_Bus_Dma_Abstraction */
486 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1];
487} m_pool_s;
488
489static void *___sym_malloc(m_pool_s *mp, int size)
490{
491 int i = 0;
492 int s = (1 << MEMO_SHIFT);
493 int j;
494 m_addr_t a;
495 m_link_s *h = mp->h;
496
497 if (size > MEMO_CLUSTER_SIZE)
498 return 0;
499
500 while (size > s) {
501 s <<= 1;
502 ++i;
503 }
504
505 j = i;
506 while (!h[j].next) {
507 if (s == MEMO_CLUSTER_SIZE) {
508 h[j].next = (m_link_s *) M_GETP();
509 if (h[j].next)
510 h[j].next->next = 0;
511 break;
512 }
513 ++j;
514 s <<= 1;
515 }
516 a = (m_addr_t) h[j].next;
517 if (a) {
518 h[j].next = h[j].next->next;
519 while (j > i) {
520 j -= 1;
521 s >>= 1;
522 h[j].next = (m_link_s *) (a+s);
523 h[j].next->next = 0;
524 }
525 }
526#ifdef DEBUG
e3869ec7 527 kprintf("___sym_malloc(%d) = %p\n", size, (void *) a);
984263bc
MD
528#endif
529 return (void *) a;
530}
531
532static void ___sym_mfree(m_pool_s *mp, void *ptr, int size)
533{
534 int i = 0;
535 int s = (1 << MEMO_SHIFT);
536 m_link_s *q;
537 m_addr_t a, b;
538 m_link_s *h = mp->h;
539
540#ifdef DEBUG
e3869ec7 541 kprintf("___sym_mfree(%p, %d)\n", ptr, size);
984263bc
MD
542#endif
543
544 if (size > MEMO_CLUSTER_SIZE)
545 return;
546
547 while (size > s) {
548 s <<= 1;
549 ++i;
550 }
551
552 a = (m_addr_t) ptr;
553
554 while (1) {
555#ifdef MEMO_FREE_UNUSED
556 if (s == MEMO_CLUSTER_SIZE) {
557 M_FREEP(a);
558 break;
559 }
560#endif
561 b = a ^ s;
562 q = &h[i];
563 while (q->next && q->next != (m_link_s *) b) {
564 q = q->next;
565 }
566 if (!q->next) {
567 ((m_link_s *) a)->next = h[i].next;
568 h[i].next = (m_link_s *) a;
569 break;
570 }
571 q->next = q->next->next;
572 a = a & b;
573 s <<= 1;
574 ++i;
575 }
576}
577
578static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags)
579{
580 void *p;
581
582 p = ___sym_malloc(mp, size);
583
584 if (DEBUG_FLAGS & DEBUG_ALLOC)
e3869ec7 585 kprintf ("new %-10s[%4d] @%p.\n", name, size, p);
984263bc
MD
586
587 if (p)
588 bzero(p, size);
589 else if (uflags & MEMO_WARN)
e3869ec7 590 kprintf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size);
984263bc
MD
591
592 return p;
593}
594
595#define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN)
596
597static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name)
598{
599 if (DEBUG_FLAGS & DEBUG_ALLOC)
e3869ec7 600 kprintf ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
984263bc
MD
601
602 ___sym_mfree(mp, ptr, size);
603
604}
605
606/*
607 * Default memory pool we donnot need to involve in DMA.
608 */
609#ifndef FreeBSD_Bus_Dma_Abstraction
610/*
611 * Without the `bus dma abstraction', all the memory is assumed
612 * DMAable and a single pool is all what we need.
613 */
614static m_pool_s mp0;
615
616#else
617/*
618 * With the `bus dma abstraction', we use a separate pool for
619 * memory we donnot need to involve in DMA.
620 */
621static m_addr_t ___mp0_getp(m_pool_s *mp)
622{
623 m_addr_t m = (m_addr_t) get_pages();
624 if (m)
625 ++mp->nump;
626 return m;
627}
628
629#ifdef MEMO_FREE_UNUSED
630static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
631{
632 free_pages(m);
633 --mp->nump;
634}
635#endif
636
637#ifdef MEMO_FREE_UNUSED
638static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep};
639#else
640static m_pool_s mp0 = {0, 0, ___mp0_getp};
641#endif
642
643#endif /* FreeBSD_Bus_Dma_Abstraction */
644
645/*
646 * Actual memory allocation routine for non-DMAed memory.
647 */
648static void *sym_calloc(int size, char *name)
649{
650 void *m;
651 /* Lock */
652 m = __sym_calloc(&mp0, size, name);
653 /* Unlock */
654 return m;
655}
656
657/*
658 * Actual memory allocation routine for non-DMAed memory.
659 */
660static void sym_mfree(void *ptr, int size, char *name)
661{
662 /* Lock */
663 __sym_mfree(&mp0, ptr, size, name);
664 /* Unlock */
665}
666
667/*
668 * DMAable pools.
669 */
670#ifndef FreeBSD_Bus_Dma_Abstraction
671/*
672 * Without `bus dma abstraction', all the memory is DMAable, and
673 * only a single pool is needed (vtophys() is our friend).
674 */
675#define __sym_calloc_dma(b, s, n) sym_calloc(s, n)
676#define __sym_mfree_dma(b, p, s, n) sym_mfree(p, s, n)
984263bc 677#define __vtobus(b, p) vtophys(p)
984263bc
MD
678
679#else
680/*
681 * With `bus dma abstraction', we use a separate pool per parent
682 * BUS handle. A reverse table (hashed) is maintained for virtual
683 * to BUS address translation.
684 */
685static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
686{
687 bus_addr_t *baddr;
688 baddr = (bus_addr_t *)arg;
689 *baddr = segs->ds_addr;
690}
691
692static m_addr_t ___dma_getp(m_pool_s *mp)
693{
694 m_vtob_s *vbp;
695 void *vaddr = 0;
696 bus_addr_t baddr = 0;
697
698 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB");
699 if (!vbp)
700 goto out_err;
701
702 if (bus_dmamem_alloc(mp->dmat, &vaddr,
703 BUS_DMA_NOWAIT, &vbp->dmamap))
704 goto out_err;
705 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr,
706 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0);
707 if (baddr) {
708 int hc = VTOB_HASH_CODE(vaddr);
709 vbp->vaddr = (m_addr_t) vaddr;
710 vbp->baddr = (m_addr_t) baddr;
711 vbp->next = mp->vtob[hc];
712 mp->vtob[hc] = vbp;
713 ++mp->nump;
714 return (m_addr_t) vaddr;
715 }
716out_err:
717 if (baddr)
718 bus_dmamap_unload(mp->dmat, vbp->dmamap);
719 if (vaddr)
720 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap);
721 if (vbp->dmamap)
722 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
723 if (vbp)
724 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
725 return 0;
726}
727
728#ifdef MEMO_FREE_UNUSED
729static void ___dma_freep(m_pool_s *mp, m_addr_t m)
730{
731 m_vtob_s **vbpp, *vbp;
732 int hc = VTOB_HASH_CODE(m);
733
734 vbpp = &mp->vtob[hc];
735 while (*vbpp && (*vbpp)->vaddr != m)
736 vbpp = &(*vbpp)->next;
737 if (*vbpp) {
738 vbp = *vbpp;
739 *vbpp = (*vbpp)->next;
740 bus_dmamap_unload(mp->dmat, vbp->dmamap);
741 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap);
742 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
743 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
744 --mp->nump;
745 }
746}
747#endif
748
749static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat)
750{
751 m_pool_s *mp;
752 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next);
753 return mp;
754}
755
756static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat)
757{
758 m_pool_s *mp = 0;
759
760 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL");
761 if (mp) {
762 mp->dev_dmat = dev_dmat;
763 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE,
764 BUS_SPACE_MAXADDR_32BIT,
765 BUS_SPACE_MAXADDR_32BIT,
766 NULL, NULL, MEMO_CLUSTER_SIZE, 1,
767 MEMO_CLUSTER_SIZE, 0, &mp->dmat)) {
768 mp->getp = ___dma_getp;
769#ifdef MEMO_FREE_UNUSED
770 mp->freep = ___dma_freep;
771#endif
772 mp->next = mp0.next;
773 mp0.next = mp;
774 return mp;
775 }
776 }
777 if (mp)
778 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL");
779 return 0;
780}
781
782#ifdef MEMO_FREE_UNUSED
783static void ___del_dma_pool(m_pool_s *p)
784{
785 struct m_pool **pp = &mp0.next;
786
787 while (*pp && *pp != p)
788 pp = &(*pp)->next;
789 if (*pp) {
790 *pp = (*pp)->next;
791 bus_dma_tag_destroy(p->dmat);
792 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL");
793 }
794}
795#endif
796
797static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name)
798{
799 struct m_pool *mp;
800 void *m = 0;
801
802 /* Lock */
803 mp = ___get_dma_pool(dev_dmat);
804 if (!mp)
805 mp = ___cre_dma_pool(dev_dmat);
806 if (mp)
807 m = __sym_calloc(mp, size, name);
808#ifdef MEMO_FREE_UNUSED
809 if (mp && !mp->nump)
810 ___del_dma_pool(mp);
811#endif
812 /* Unlock */
813
814 return m;
815}
816
817static void
818__sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name)
819{
820 struct m_pool *mp;
821
822 /* Lock */
823 mp = ___get_dma_pool(dev_dmat);
824 if (mp)
825 __sym_mfree(mp, m, size, name);
826#ifdef MEMO_FREE_UNUSED
827 if (mp && !mp->nump)
828 ___del_dma_pool(mp);
829#endif
830 /* Unlock */
831}
832
833static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m)
834{
835 m_pool_s *mp;
836 int hc = VTOB_HASH_CODE(m);
837 m_vtob_s *vp = 0;
838 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
839
840 /* Lock */
841 mp = ___get_dma_pool(dev_dmat);
842 if (mp) {
843 vp = mp->vtob[hc];
844 while (vp && (m_addr_t) vp->vaddr != a)
845 vp = vp->next;
846 }
847 /* Unlock */
848 if (!vp)
849 panic("sym: VTOBUS FAILED!\n");
850 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
851}
852
853#endif /* FreeBSD_Bus_Dma_Abstraction */
854
855/*
856 * Verbs for DMAable memory handling.
857 * The _uvptv_ macro avoids a nasty warning about pointer to volatile
858 * being discarded.
859 */
860#define _uvptv_(p) ((void *)((vm_offset_t)(p)))
861#define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n)
862#define _sym_mfree_dma(np, p, s, n) \
863 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n)
864#define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n)
865#define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n)
866#define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p))
867#define vtobus(p) _vtobus(np, p)
868
869
870/*
871 * Print a buffer in hexadecimal format.
872 */
873static void sym_printb_hex (u_char *p, int n)
874{
875 while (n-- > 0)
e3869ec7 876 kprintf (" %x", *p++);
984263bc
MD
877}
878
879/*
880 * Same with a label at beginning and .\n at end.
881 */
882static void sym_printl_hex (char *label, u_char *p, int n)
883{
e3869ec7 884 kprintf ("%s", label);
984263bc 885 sym_printb_hex (p, n);
e3869ec7 886 kprintf (".\n");
984263bc
MD
887}
888
889/*
890 * Return a string for SCSI BUS mode.
891 */
892static char *sym_scsi_bus_mode(int mode)
893{
894 switch(mode) {
895 case SMODE_HVD: return "HVD";
896 case SMODE_SE: return "SE";
897 case SMODE_LVD: return "LVD";
898 }
899 return "??";
900}
901
902/*
903 * Some poor and bogus sync table that refers to Tekram NVRAM layout.
904 */
905#ifdef SYM_CONF_NVRAM_SUPPORT
906static u_char Tekram_sync[16] =
907 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10};
908#endif
909
910/*
911 * Union of supported NVRAM formats.
912 */
913struct sym_nvram {
914 int type;
915#define SYM_SYMBIOS_NVRAM (1)
916#define SYM_TEKRAM_NVRAM (2)
917#ifdef SYM_CONF_NVRAM_SUPPORT
918 union {
919 Symbios_nvram Symbios;
920 Tekram_nvram Tekram;
921 } data;
922#endif
923};
924
925/*
926 * This one is hopefully useless, but actually useful. :-)
927 */
928#ifndef assert
929#define assert(expression) { \
930 if (!(expression)) { \
931 (void)panic( \
932 "assertion \"%s\" failed: file \"%s\", line %d\n", \
933 #expression, \
934 __FILE__, __LINE__); \
935 } \
936}
937#endif
938
939/*
940 * Some provision for a possible big endian mode supported by
941 * Symbios chips (never seen, by the way).
942 * For now, this stuff does not deserve any comments. :)
943 */
944
945#define sym_offb(o) (o)
946#define sym_offw(o) (o)
947
948/*
949 * Some provision for support for BIG ENDIAN CPU.
950 * Btw, FreeBSD does not seem to be ready yet for big endian.
951 */
952
953#if BYTE_ORDER == BIG_ENDIAN
954#define cpu_to_scr(dw) _htole32(dw)
955#define scr_to_cpu(dw) _le32toh(dw)
956#else
957#define cpu_to_scr(dw) (dw)
958#define scr_to_cpu(dw) (dw)
959#endif
960
961/*
962 * Access to the chip IO registers and on-chip RAM.
963 * We use the `bus space' interface under FreeBSD-4 and
964 * later kernel versions.
965 */
966
967#ifdef FreeBSD_Bus_Space_Abstraction
968
969#if defined(SYM_CONF_IOMAPPED)
970
971#define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o)
972#define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o)
973#define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o)
974
975#define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v))
976#define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v))
977#define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v))
978
979#else /* Memory mapped IO */
980
981#define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o)
982#define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o)
983#define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o)
984
985#define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v))
986#define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v))
987#define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v))
988
989#endif /* SYM_CONF_IOMAPPED */
990
991#define OUTRAM_OFF(o, a, l) \
992 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l))
993
994#else /* not defined FreeBSD_Bus_Space_Abstraction */
995
996#if BYTE_ORDER == BIG_ENDIAN
997#error "BIG ENDIAN support requires bus space kernel interface"
998#endif
999
1000/*
1001 * Access to the chip IO registers and on-chip RAM.
1002 * We use legacy MMIO and IO interface for FreeBSD 3.X versions.
1003 */
1004
1005/*
1006 * Define some understable verbs for IO and MMIO.
1007 */
1008#define io_read8(p) scr_to_cpu(inb((p)))
1009#define io_read16(p) scr_to_cpu(inw((p)))
1010#define io_read32(p) scr_to_cpu(inl((p)))
1011#define io_write8(p, v) outb((p), cpu_to_scr(v))
1012#define io_write16(p, v) outw((p), cpu_to_scr(v))
1013#define io_write32(p, v) outl((p), cpu_to_scr(v))
1014
984263bc
MD
1015#define mmio_read8(a) scr_to_cpu((*(volatile unsigned char *) (a)))
1016#define mmio_read16(a) scr_to_cpu((*(volatile unsigned short *) (a)))
1017#define mmio_read32(a) scr_to_cpu((*(volatile unsigned int *) (a)))
1018#define mmio_write8(a, b) (*(volatile unsigned char *) (a)) = cpu_to_scr(b)
1019#define mmio_write16(a, b) (*(volatile unsigned short *) (a)) = cpu_to_scr(b)
1020#define mmio_write32(a, b) (*(volatile unsigned int *) (a)) = cpu_to_scr(b)
1021#define memcpy_to_pci(d, s, n) bcopy((s), (void *)(d), (n))
1022
984263bc
MD
1023/*
1024 * Normal IO
1025 */
1026#if defined(SYM_CONF_IOMAPPED)
1027
1028#define INB_OFF(o) io_read8(np->io_port + sym_offb(o))
1029#define OUTB_OFF(o, v) io_write8(np->io_port + sym_offb(o), (v))
1030
1031#define INW_OFF(o) io_read16(np->io_port + sym_offw(o))
1032#define OUTW_OFF(o, v) io_write16(np->io_port + sym_offw(o), (v))
1033
1034#define INL_OFF(o) io_read32(np->io_port + (o))
1035#define OUTL_OFF(o, v) io_write32(np->io_port + (o), (v))
1036
1037#else /* Memory mapped IO */
1038
1039#define INB_OFF(o) mmio_read8(np->mmio_va + sym_offb(o))
1040#define OUTB_OFF(o, v) mmio_write8(np->mmio_va + sym_offb(o), (v))
1041
1042#define INW_OFF(o) mmio_read16(np->mmio_va + sym_offw(o))
1043#define OUTW_OFF(o, v) mmio_write16(np->mmio_va + sym_offw(o), (v))
1044
1045#define INL_OFF(o) mmio_read32(np->mmio_va + (o))
1046#define OUTL_OFF(o, v) mmio_write32(np->mmio_va + (o), (v))
1047
1048#endif
1049
1050#define OUTRAM_OFF(o, a, l) memcpy_to_pci(np->ram_va + (o), (a), (l))
1051
1052#endif /* FreeBSD_Bus_Space_Abstraction */
1053
1054/*
1055 * Common definitions for both bus space and legacy IO methods.
1056 */
1057#define INB(r) INB_OFF(offsetof(struct sym_reg,r))
1058#define INW(r) INW_OFF(offsetof(struct sym_reg,r))
1059#define INL(r) INL_OFF(offsetof(struct sym_reg,r))
1060
1061#define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v))
1062#define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v))
1063#define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v))
1064
1065#define OUTONB(r, m) OUTB(r, INB(r) | (m))
1066#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
1067#define OUTONW(r, m) OUTW(r, INW(r) | (m))
1068#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
1069#define OUTONL(r, m) OUTL(r, INL(r) | (m))
1070#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
1071
1072/*
1073 * We normally want the chip to have a consistent view
1074 * of driver internal data structures when we restart it.
1075 * Thus these macros.
1076 */
1077#define OUTL_DSP(v) \
1078 do { \
1079 MEMORY_BARRIER(); \
1080 OUTL (nc_dsp, (v)); \
1081 } while (0)
1082
1083#define OUTONB_STD() \
1084 do { \
1085 MEMORY_BARRIER(); \
1086 OUTONB (nc_dcntl, (STD|NOCOM)); \
1087 } while (0)
1088
1089/*
1090 * Command control block states.
1091 */
1092#define HS_IDLE (0)
1093#define HS_BUSY (1)
1094#define HS_NEGOTIATE (2) /* sync/wide data transfer*/
1095#define HS_DISCONNECT (3) /* Disconnected by target */
1096#define HS_WAIT (4) /* waiting for resource */
1097
1098#define HS_DONEMASK (0x80)
1099#define HS_COMPLETE (4|HS_DONEMASK)
1100#define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
1101#define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */
1102#define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */
1103
1104/*
1105 * Software Interrupt Codes
1106 */
1107#define SIR_BAD_SCSI_STATUS (1)
1108#define SIR_SEL_ATN_NO_MSG_OUT (2)
1109#define SIR_MSG_RECEIVED (3)
1110#define SIR_MSG_WEIRD (4)
1111#define SIR_NEGO_FAILED (5)
1112#define SIR_NEGO_PROTO (6)
1113#define SIR_SCRIPT_STOPPED (7)
1114#define SIR_REJECT_TO_SEND (8)
1115#define SIR_SWIDE_OVERRUN (9)
1116#define SIR_SODL_UNDERRUN (10)
1117#define SIR_RESEL_NO_MSG_IN (11)
1118#define SIR_RESEL_NO_IDENTIFY (12)
1119#define SIR_RESEL_BAD_LUN (13)
1120#define SIR_TARGET_SELECTED (14)
1121#define SIR_RESEL_BAD_I_T_L (15)
1122#define SIR_RESEL_BAD_I_T_L_Q (16)
1123#define SIR_ABORT_SENT (17)
1124#define SIR_RESEL_ABORTED (18)
1125#define SIR_MSG_OUT_DONE (19)
1126#define SIR_COMPLETE_ERROR (20)
1127#define SIR_DATA_OVERRUN (21)
1128#define SIR_BAD_PHASE (22)
1129#define SIR_MAX (22)
1130
1131/*
1132 * Extended error bit codes.
1133 * xerr_status field of struct sym_ccb.
1134 */
1135#define XE_EXTRA_DATA (1) /* unexpected data phase */
1136#define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */
1137#define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */
1138#define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */
1139#define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */
1140
1141/*
1142 * Negotiation status.
1143 * nego_status field of struct sym_ccb.
1144 */
1145#define NS_SYNC (1)
1146#define NS_WIDE (2)
1147#define NS_PPR (3)
1148
1149/*
1150 * A CCB hashed table is used to retrieve CCB address
1151 * from DSA value.
1152 */
1153#define CCB_HASH_SHIFT 8
1154#define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT)
1155#define CCB_HASH_MASK (CCB_HASH_SIZE-1)
1156#define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK)
1157
1158/*
1159 * Device flags.
1160 */
1161#define SYM_DISC_ENABLED (1)
1162#define SYM_TAGS_ENABLED (1<<1)
1163#define SYM_SCAN_BOOT_DISABLED (1<<2)
1164#define SYM_SCAN_LUNS_DISABLED (1<<3)
1165
1166/*
1167 * Host adapter miscellaneous flags.
1168 */
1169#define SYM_AVOID_BUS_RESET (1)
1170#define SYM_SCAN_TARGETS_HILO (1<<1)
1171
1172/*
1173 * Device quirks.
1174 * Some devices, for example the CHEETAH 2 LVD, disconnects without
1175 * saving the DATA POINTER then reselects and terminates the IO.
1176 * On reselection, the automatic RESTORE DATA POINTER makes the
1177 * CURRENT DATA POINTER not point at the end of the IO.
1178 * This behaviour just breaks our calculation of the residual.
1179 * For now, we just force an AUTO SAVE on disconnection and will
1180 * fix that in a further driver version.
1181 */
1182#define SYM_QUIRK_AUTOSAVE 1
1183
1184/*
1185 * Misc.
1186 */
1187#define SYM_SNOOP_TIMEOUT (10000000)
1188#define SYM_PCI_IO PCIR_MAPS
1189#define SYM_PCI_MMIO (PCIR_MAPS + 4)
1190#define SYM_PCI_RAM (PCIR_MAPS + 8)
1191#define SYM_PCI_RAM64 (PCIR_MAPS + 12)
1192
1193/*
1194 * Back-pointer from the CAM CCB to our data structures.
1195 */
1196#define sym_hcb_ptr spriv_ptr0
1197/* #define sym_ccb_ptr spriv_ptr1 */
1198
1199/*
1200 * We mostly have to deal with pointers.
1201 * Thus these typedef's.
1202 */
1203typedef struct sym_tcb *tcb_p;
1204typedef struct sym_lcb *lcb_p;
1205typedef struct sym_ccb *ccb_p;
1206typedef struct sym_hcb *hcb_p;
1207
1208/*
1209 * Gather negotiable parameters value
1210 */
1211struct sym_trans {
1212#ifdef FreeBSD_New_Tran_Settings
1213 u8 scsi_version;
1214 u8 spi_version;
1215#endif
1216 u8 period;
1217 u8 offset;
1218 u8 width;
1219 u8 options; /* PPR options */
1220};
1221
1222struct sym_tinfo {
1223 struct sym_trans current;
1224 struct sym_trans goal;
1225 struct sym_trans user;
1226};
1227
1228#define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT
1229#define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT
1230
1231/*
1232 * Global TCB HEADER.
1233 *
1234 * Due to lack of indirect addressing on earlier NCR chips,
1235 * this substructure is copied from the TCB to a global
1236 * address after selection.
1237 * For SYMBIOS chips that support LOAD/STORE this copy is
1238 * not needed and thus not performed.
1239 */
1240struct sym_tcbh {
1241 /*
1242 * Scripts bus addresses of LUN table accessed from scripts.
1243 * LUN #0 is a special case, since multi-lun devices are rare,
1244 * and we we want to speed-up the general case and not waste
1245 * resources.
1246 */
1247 u32 luntbl_sa; /* bus address of this table */
1248 u32 lun0_sa; /* bus address of LCB #0 */
1249 /*
1250 * Actual SYNC/WIDE IO registers value for this target.
1251 * 'sval', 'wval' and 'uval' are read from SCRIPTS and
1252 * so have alignment constraints.
1253 */
1254/*0*/ u_char uval; /* -> SCNTL4 register */
1255/*1*/ u_char sval; /* -> SXFER io register */
1256/*2*/ u_char filler1;
1257/*3*/ u_char wval; /* -> SCNTL3 io register */
1258};
1259
1260/*
1261 * Target Control Block
1262 */
1263struct sym_tcb {
1264 /*
1265 * TCB header.
1266 * Assumed at offset 0.
1267 */
1268/*0*/ struct sym_tcbh head;
1269
1270 /*
1271 * LUN table used by the SCRIPTS processor.
1272 * An array of bus addresses is used on reselection.
1273 */
1274 u32 *luntbl; /* LCBs bus address table */
1275
1276 /*
1277 * LUN table used by the C code.
1278 */
1279 lcb_p lun0p; /* LCB of LUN #0 (usual case) */
1280#if SYM_CONF_MAX_LUN > 1
1281 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */
1282#endif
1283
1284 /*
1285 * Bitmap that tells about LUNs that succeeded at least
1286 * 1 IO and therefore assumed to be a real device.
1287 * Avoid useless allocation of the LCB structure.
1288 */
1289 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];
1290
1291 /*
1292 * Bitmap that tells about LUNs that haven't yet an LCB
1293 * allocated (not discovered or LCB allocation failed).
1294 */
1295 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];
1296
1297 /*
1298 * Transfer capabilities (SIP)
1299 */
1300 struct sym_tinfo tinfo;
1301
1302 /*
1303 * Keep track of the CCB used for the negotiation in order
1304 * to ensure that only 1 negotiation is queued at a time.
1305 */
1306 ccb_p nego_cp; /* CCB used for the nego */
1307
1308 /*
1309 * Set when we want to reset the device.
1310 */
1311 u_char to_reset;
1312
1313 /*
1314 * Other user settable limits and options.
1315 * These limits are read from the NVRAM if present.
1316 */
1317 u_char usrflags;
1318 u_short usrtags;
1319};
1320
1321/*
1322 * Global LCB HEADER.
1323 *
1324 * Due to lack of indirect addressing on earlier NCR chips,
1325 * this substructure is copied from the LCB to a global
1326 * address after selection.
1327 * For SYMBIOS chips that support LOAD/STORE this copy is
1328 * not needed and thus not performed.
1329 */
1330struct sym_lcbh {
1331 /*
1332 * SCRIPTS address jumped by SCRIPTS on reselection.
1333 * For not probed logical units, this address points to
1334 * SCRIPTS that deal with bad LU handling (must be at
1335 * offset zero of the LCB for that reason).
1336 */
1337/*0*/ u32 resel_sa;
1338
1339 /*
1340 * Task (bus address of a CCB) read from SCRIPTS that points
1341 * to the unique ITL nexus allowed to be disconnected.
1342 */
1343 u32 itl_task_sa;
1344
1345 /*
1346 * Task table bus address (read from SCRIPTS).
1347 */
1348 u32 itlq_tbl_sa;
1349};
1350
1351/*
1352 * Logical Unit Control Block
1353 */
1354struct sym_lcb {
1355 /*
1356 * TCB header.
1357 * Assumed at offset 0.
1358 */
1359/*0*/ struct sym_lcbh head;
1360
1361 /*
1362 * Task table read from SCRIPTS that contains pointers to
1363 * ITLQ nexuses. The bus address read from SCRIPTS is
1364 * inside the header.
1365 */
1366 u32 *itlq_tbl; /* Kernel virtual address */
1367
1368 /*
1369 * Busy CCBs management.
1370 */
1371 u_short busy_itlq; /* Number of busy tagged CCBs */
1372 u_short busy_itl; /* Number of busy untagged CCBs */
1373
1374 /*
1375 * Circular tag allocation buffer.
1376 */
1377 u_short ia_tag; /* Tag allocation index */
1378 u_short if_tag; /* Tag release index */
1379 u_char *cb_tags; /* Circular tags buffer */
1380
1381 /*
1382 * Set when we want to clear all tasks.
1383 */
1384 u_char to_clear;
1385
1386 /*
1387 * Capabilities.
1388 */
1389 u_char user_flags;
1390 u_char current_flags;
1391};
1392
1393/*
1394 * Action from SCRIPTS on a task.
1395 * Is part of the CCB, but is also used separately to plug
1396 * error handling action to perform from SCRIPTS.
1397 */
1398struct sym_actscr {
1399 u32 start; /* Jumped by SCRIPTS after selection */
1400 u32 restart; /* Jumped by SCRIPTS on relection */
1401};
1402
1403/*
1404 * Phase mismatch context.
1405 *
1406 * It is part of the CCB and is used as parameters for the
1407 * DATA pointer. We need two contexts to handle correctly the
1408 * SAVED DATA POINTER.
1409 */
1410struct sym_pmc {
1411 struct sym_tblmove sg; /* Updated interrupted SG block */
1412 u32 ret; /* SCRIPT return address */
1413};
1414
1415/*
1416 * LUN control block lookup.
1417 * We use a direct pointer for LUN #0, and a table of
1418 * pointers which is only allocated for devices that support
1419 * LUN(s) > 0.
1420 */
1421#if SYM_CONF_MAX_LUN <= 1
1422#define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0
1423#else
1424#define sym_lp(np, tp, lun) \
1425 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0
1426#endif
1427
1428/*
1429 * Status are used by the host and the script processor.
1430 *
1431 * The last four bytes (status[4]) are copied to the
1432 * scratchb register (declared as scr0..scr3) just after the
1433 * select/reselect, and copied back just after disconnecting.
1434 * Inside the script the XX_REG are used.
1435 */
1436
1437/*
1438 * Last four bytes (script)
1439 */
1440#define QU_REG scr0
1441#define HS_REG scr1
1442#define HS_PRT nc_scr1
1443#define SS_REG scr2
1444#define SS_PRT nc_scr2
1445#define HF_REG scr3
1446#define HF_PRT nc_scr3
1447
1448/*
1449 * Last four bytes (host)
1450 */
1451#define actualquirks phys.head.status[0]
1452#define host_status phys.head.status[1]
1453#define ssss_status phys.head.status[2]
1454#define host_flags phys.head.status[3]
1455
1456/*
1457 * Host flags
1458 */
1459#define HF_IN_PM0 1u
1460#define HF_IN_PM1 (1u<<1)
1461#define HF_ACT_PM (1u<<2)
1462#define HF_DP_SAVED (1u<<3)
1463#define HF_SENSE (1u<<4)
1464#define HF_EXT_ERR (1u<<5)
1465#define HF_DATA_IN (1u<<6)
1466#ifdef SYM_CONF_IARB_SUPPORT
1467#define HF_HINT_IARB (1u<<7)
1468#endif
1469
1470/*
1471 * Global CCB HEADER.
1472 *
1473 * Due to lack of indirect addressing on earlier NCR chips,
1474 * this substructure is copied from the ccb to a global
1475 * address after selection (or reselection) and copied back
1476 * before disconnect.
1477 * For SYMBIOS chips that support LOAD/STORE this copy is
1478 * not needed and thus not performed.
1479 */
1480
1481struct sym_ccbh {
1482 /*
1483 * Start and restart SCRIPTS addresses (must be at 0).
1484 */
1485/*0*/ struct sym_actscr go;
1486
1487 /*
1488 * SCRIPTS jump address that deal with data pointers.
1489 * 'savep' points to the position in the script responsible
1490 * for the actual transfer of data.
1491 * It's written on reception of a SAVE_DATA_POINTER message.
1492 */
1493 u32 savep; /* Jump address to saved data pointer */
1494 u32 lastp; /* SCRIPTS address at end of data */
1495 u32 goalp; /* Not accessed for now from SCRIPTS */
1496
1497 /*
1498 * Status fields.
1499 */
1500 u8 status[4];
1501};
1502
1503/*
1504 * Data Structure Block
1505 *
1506 * During execution of a ccb by the script processor, the
1507 * DSA (data structure address) register points to this
1508 * substructure of the ccb.
1509 */
1510struct sym_dsb {
1511 /*
1512 * CCB header.
1513 * Also assumed at offset 0 of the sym_ccb structure.
1514 */
1515/*0*/ struct sym_ccbh head;
1516
1517 /*
1518 * Phase mismatch contexts.
1519 * We need two to handle correctly the SAVED DATA POINTER.
1520 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic
1521 * for address calculation from SCRIPTS.
1522 */
1523 struct sym_pmc pm0;
1524 struct sym_pmc pm1;
1525
1526 /*
1527 * Table data for Script
1528 */
1529 struct sym_tblsel select;
1530 struct sym_tblmove smsg;
1531 struct sym_tblmove smsg_ext;
1532 struct sym_tblmove cmd;
1533 struct sym_tblmove sense;
1534 struct sym_tblmove wresid;
1535 struct sym_tblmove data [SYM_CONF_MAX_SG];
1536};
1537
1538/*
1539 * Our Command Control Block
1540 */
1541struct sym_ccb {
1542 /*
1543 * This is the data structure which is pointed by the DSA
1544 * register when it is executed by the script processor.
1545 * It must be the first entry.
1546 */
1547 struct sym_dsb phys;
1548
1549 /*
1550 * Pointer to CAM ccb and related stuff.
1551 */
1552 union ccb *cam_ccb; /* CAM scsiio ccb */
1553 u8 cdb_buf[16]; /* Copy of CDB */
1554 u8 *sns_bbuf; /* Bounce buffer for sense data */
1555#define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data)
1556 int data_len; /* Total data length */
1557 int segments; /* Number of SG segments */
1558
1559 /*
1560 * Miscellaneous status'.
1561 */
1562 u_char nego_status; /* Negotiation status */
1563 u_char xerr_status; /* Extended error flags */
1564 u32 extra_bytes; /* Extraneous bytes transferred */
1565
1566 /*
1567 * Message areas.
1568 * We prepare a message to be sent after selection.
1569 * We may use a second one if the command is rescheduled
1570 * due to CHECK_CONDITION or COMMAND TERMINATED.
1571 * Contents are IDENTIFY and SIMPLE_TAG.
1572 * While negotiating sync or wide transfer,
1573 * a SDTR or WDTR message is appended.
1574 */
1575 u_char scsi_smsg [12];
1576 u_char scsi_smsg2[12];
1577
1578 /*
1579 * Auto request sense related fields.
1580 */
1581 u_char sensecmd[6]; /* Request Sense command */
1582 u_char sv_scsi_status; /* Saved SCSI status */
1583 u_char sv_xerr_status; /* Saved extended status */
1584 int sv_resid; /* Saved residual */
1585
1586 /*
1587 * Map for the DMA of user data.
1588 */
1589#ifdef FreeBSD_Bus_Dma_Abstraction
1590 void *arg; /* Argument for some callback */
1591 bus_dmamap_t dmamap; /* DMA map for user data */
1592 u_char dmamapped;
1593#define SYM_DMA_NONE 0
1594#define SYM_DMA_READ 1
1595#define SYM_DMA_WRITE 2
1596#endif
1597 /*
1598 * Other fields.
1599 */
1600 u32 ccb_ba; /* BUS address of this CCB */
1601 u_short tag; /* Tag for this transfer */
1602 /* NO_TAG means no tag */
1603 u_char target;
1604 u_char lun;
1605 ccb_p link_ccbh; /* Host adapter CCB hash chain */
1606 SYM_QUEHEAD
1607 link_ccbq; /* Link to free/busy CCB queue */
1608 u32 startp; /* Initial data pointer */
1609 int ext_sg; /* Extreme data pointer, used */
1610 int ext_ofs; /* to calculate the residual. */
1611 u_char to_abort; /* Want this IO to be aborted */
1612};
1613
1614#define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl))
1615
1616/*
1617 * Host Control Block
1618 */
1619struct sym_hcb {
1620 /*
1621 * Global headers.
1622 * Due to poorness of addressing capabilities, earlier
1623 * chips (810, 815, 825) copy part of the data structures
1624 * (CCB, TCB and LCB) in fixed areas.
1625 */
1626#ifdef SYM_CONF_GENERIC_SUPPORT
1627 struct sym_ccbh ccb_head;
1628 struct sym_tcbh tcb_head;
1629 struct sym_lcbh lcb_head;
1630#endif
1631 /*
1632 * Idle task and invalid task actions and
1633 * their bus addresses.
1634 */
1635 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1636 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1637
1638 /*
1639 * Dummy lun table to protect us against target
1640 * returning bad lun number on reselection.
1641 */
1642 u32 *badluntbl; /* Table physical address */
1643 u32 badlun_sa; /* SCRIPT handler BUS address */
1644
1645 /*
1646 * Bus address of this host control block.
1647 */
1648 u32 hcb_ba;
1649
1650 /*
1651 * Bit 32-63 of the on-chip RAM bus address in LE format.
1652 * The START_RAM64 script loads the MMRS and MMWS from this
1653 * field.
1654 */
1655 u32 scr_ram_seg;
1656
1657 /*
1658 * Chip and controller indentification.
1659 */
1660#ifdef FreeBSD_Bus_Io_Abstraction
1661 device_t device;
1662#else
1663 pcici_t pci_tag;
1664#endif
1665 int unit;
1666 char inst_name[8];
1667
1668 /*
1669 * Initial value of some IO register bits.
1670 * These values are assumed to have been set by BIOS, and may
1671 * be used to probe adapter implementation differences.
1672 */
1673 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1674 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1675 sv_stest1;
1676
1677 /*
1678 * Actual initial value of IO register bits used by the
1679 * driver. They are loaded at initialisation according to
1680 * features that are to be enabled/disabled.
1681 */
1682 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1683 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1684
1685 /*
1686 * Target data.
1687 */
1688 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1689
1690 /*
1691 * Target control block bus address array used by the SCRIPT
1692 * on reselection.
1693 */
1694 u32 *targtbl;
1695 u32 targtbl_ba;
1696
1697 /*
1698 * CAM SIM information for this instance.
1699 */
1700 struct cam_sim *sim;
1701 struct cam_path *path;
1702
1703 /*
1704 * Allocated hardware resources.
1705 */
1706#ifdef FreeBSD_Bus_Io_Abstraction
1707 struct resource *irq_res;
1708 struct resource *io_res;
1709 struct resource *mmio_res;
1710 struct resource *ram_res;
1711 int ram_id;
1712 void *intr;
1713#endif
1714
1715 /*
1716 * Bus stuff.
1717 *
1718 * My understanding of PCI is that all agents must share the
1719 * same addressing range and model.
1720 * But some hardware architecture guys provide complex and
1721 * brain-deaded stuff that makes shit.
1722 * This driver only support PCI compliant implementations and
1723 * deals with part of the BUS stuff complexity only to fit O/S
1724 * requirements.
1725 */
1726#ifdef FreeBSD_Bus_Io_Abstraction
1727 bus_space_handle_t io_bsh;
1728 bus_space_tag_t io_tag;
1729 bus_space_handle_t mmio_bsh;
1730 bus_space_tag_t mmio_tag;
1731 bus_space_handle_t ram_bsh;
1732 bus_space_tag_t ram_tag;
1733#endif
1734
1735 /*
1736 * DMA stuff.
1737 */
1738#ifdef FreeBSD_Bus_Dma_Abstraction
1739 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1740 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1741#endif
1742 /*
1743 * Virtual and physical bus addresses of the chip.
1744 */
1745 vm_offset_t mmio_va; /* MMIO kernel virtual address */
1746 vm_offset_t mmio_pa; /* MMIO CPU physical address */
1747 vm_offset_t mmio_ba; /* MMIO BUS address */
1748 int mmio_ws; /* MMIO Window size */
1749
1750 vm_offset_t ram_va; /* RAM kernel virtual address */
1751 vm_offset_t ram_pa; /* RAM CPU physical address */
1752 vm_offset_t ram_ba; /* RAM BUS address */
1753 int ram_ws; /* RAM window size */
1754 u32 io_port; /* IO port address */
1755
1756 /*
1757 * SCRIPTS virtual and physical bus addresses.
1758 * 'script' is loaded in the on-chip RAM if present.
1759 * 'scripth' stays in main memory for all chips except the
1760 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM.
1761 */
1762 u_char *scripta0; /* Copies of script and scripth */
1763 u_char *scriptb0; /* Copies of script and scripth */
1764 vm_offset_t scripta_ba; /* Actual script and scripth */
1765 vm_offset_t scriptb_ba; /* bus addresses. */
1766 vm_offset_t scriptb0_ba;
1767 u_short scripta_sz; /* Actual size of script A */
1768 u_short scriptb_sz; /* Actual size of script B */
1769
1770 /*
1771 * Bus addresses, setup and patch methods for
1772 * the selected firmware.
1773 */
1774 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1775 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1776 void (*fw_setup)(hcb_p np, struct sym_fw *fw);
1777 void (*fw_patch)(hcb_p np);
1778 char *fw_name;
1779
1780 /*
1781 * General controller parameters and configuration.
1782 */
1783 u_short device_id; /* PCI device id */
1784 u_char revision_id; /* PCI device revision id */
1785 u_int features; /* Chip features map */
1786 u_char myaddr; /* SCSI id of the adapter */
1787 u_char maxburst; /* log base 2 of dwords burst */
1788 u_char maxwide; /* Maximum transfer width */
1789 u_char minsync; /* Min sync period factor (ST) */
1790 u_char maxsync; /* Max sync period factor (ST) */
1791 u_char maxoffs; /* Max scsi offset (ST) */
1792 u_char minsync_dt; /* Min sync period factor (DT) */
1793 u_char maxsync_dt; /* Max sync period factor (DT) */
1794 u_char maxoffs_dt; /* Max scsi offset (DT) */
1795 u_char multiplier; /* Clock multiplier (1,2,4) */
1796 u_char clock_divn; /* Number of clock divisors */
1797 u32 clock_khz; /* SCSI clock frequency in KHz */
1798 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1799 /*
1800 * Start queue management.
1801 * It is filled up by the host processor and accessed by the
1802 * SCRIPTS processor in order to start SCSI commands.
1803 */
1804 volatile /* Prevent code optimizations */
1805 u32 *squeue; /* Start queue virtual address */
1806 u32 squeue_ba; /* Start queue BUS address */
1807 u_short squeueput; /* Next free slot of the queue */
1808 u_short actccbs; /* Number of allocated CCBs */
1809
1810 /*
1811 * Command completion queue.
1812 * It is the same size as the start queue to avoid overflow.
1813 */
1814 u_short dqueueget; /* Next position to scan */
1815 volatile /* Prevent code optimizations */
1816 u32 *dqueue; /* Completion (done) queue */
1817 u32 dqueue_ba; /* Done queue BUS address */
1818
1819 /*
1820 * Miscellaneous buffers accessed by the scripts-processor.
1821 * They shall be DWORD aligned, because they may be read or
1822 * written with a script command.
1823 */
1824 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1825 u_char msgin [8]; /* Buffer for MESSAGE IN */
1826 u32 lastmsg; /* Last SCSI message sent */
1827 u_char scratch; /* Scratch for SCSI receive */
1828
1829 /*
1830 * Miscellaneous configuration and status parameters.
1831 */
1832 u_char usrflags; /* Miscellaneous user flags */
1833 u_char scsi_mode; /* Current SCSI BUS mode */
1834 u_char verbose; /* Verbosity for this controller*/
1835 u32 cache; /* Used for cache test at init. */
1836
1837 /*
1838 * CCB lists and queue.
1839 */
1840 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1841 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1842 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1843
1844 /*
1845 * During error handling and/or recovery,
1846 * active CCBs that are to be completed with
1847 * error or requeued are moved from the busy_ccbq
1848 * to the comp_ccbq prior to completion.
1849 */
1850 SYM_QUEHEAD comp_ccbq;
1851
1852 /*
1853 * CAM CCB pending queue.
1854 */
1855 SYM_QUEHEAD cam_ccbq;
1856
1857 /*
1858 * IMMEDIATE ARBITRATION (IARB) control.
1859 *
1860 * We keep track in 'last_cp' of the last CCB that has been
1861 * queued to the SCRIPTS processor and clear 'last_cp' when
1862 * this CCB completes. If last_cp is not zero at the moment
1863 * we queue a new CCB, we set a flag in 'last_cp' that is
1864 * used by the SCRIPTS as a hint for setting IARB.
1865 * We donnot set more than 'iarb_max' consecutive hints for
1866 * IARB in order to leave devices a chance to reselect.
1867 * By the way, any non zero value of 'iarb_max' is unfair. :)
1868 */
1869#ifdef SYM_CONF_IARB_SUPPORT
1870 u_short iarb_max; /* Max. # consecutive IARB hints*/
1871 u_short iarb_count; /* Actual # of these hints */
1872 ccb_p last_cp;
1873#endif
1874
1875 /*
1876 * Command abort handling.
1877 * We need to synchronize tightly with the SCRIPTS
1878 * processor in order to handle things correctly.
1879 */
1880 u_char abrt_msg[4]; /* Message to send buffer */
1881 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */
1882 struct sym_tblsel abrt_sel; /* Sync params for selection */
1883 u_char istat_sem; /* Tells the chip to stop (SEM) */
1884};
1885
1886#define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl))
1887
1888/*
1889 * Return the name of the controller.
1890 */
1891static __inline char *sym_name(hcb_p np)
1892{
1893 return np->inst_name;
1894}
1895
1896/*--------------------------------------------------------------------------*/
1897/*------------------------------ FIRMWARES ---------------------------------*/
1898/*--------------------------------------------------------------------------*/
1899
1900/*
1901 * This stuff will be moved to a separate source file when
1902 * the driver will be broken into several source modules.
1903 */
1904
1905/*
1906 * Macros used for all firmwares.
1907 */
1908#define SYM_GEN_A(s, label) ((short) offsetof(s, label)),
1909#define SYM_GEN_B(s, label) ((short) offsetof(s, label)),
1910#define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label)
1911#define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label)
1912
1913
1914#ifdef SYM_CONF_GENERIC_SUPPORT
1915/*
1916 * Allocate firmware #1 script area.
1917 */
1918#define SYM_FWA_SCR sym_fw1a_scr
1919#define SYM_FWB_SCR sym_fw1b_scr
1f2de5d4 1920#include "sym_fw1.h"
984263bc
MD
1921struct sym_fwa_ofs sym_fw1a_ofs = {
1922 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1923};
1924struct sym_fwb_ofs sym_fw1b_ofs = {
1925 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1926};
1927#undef SYM_FWA_SCR
1928#undef SYM_FWB_SCR
1929#endif /* SYM_CONF_GENERIC_SUPPORT */
1930
1931/*
1932 * Allocate firmware #2 script area.
1933 */
1934#define SYM_FWA_SCR sym_fw2a_scr
1935#define SYM_FWB_SCR sym_fw2b_scr
1f2de5d4 1936#include "sym_fw2.h"
984263bc
MD
1937struct sym_fwa_ofs sym_fw2a_ofs = {
1938 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1939};
1940struct sym_fwb_ofs sym_fw2b_ofs = {
1941 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1942 SYM_GEN_B(struct SYM_FWB_SCR, start64)
1943 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle)
1944};
1945#undef SYM_FWA_SCR
1946#undef SYM_FWB_SCR
1947
1948#undef SYM_GEN_A
1949#undef SYM_GEN_B
1950#undef PADDR_A
1951#undef PADDR_B
1952
1953#ifdef SYM_CONF_GENERIC_SUPPORT
1954/*
1955 * Patch routine for firmware #1.
1956 */
1957static void
1958sym_fw1_patch(hcb_p np)
1959{
1960 struct sym_fw1a_scr *scripta0;
1961 struct sym_fw1b_scr *scriptb0;
1962
1963 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1964 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1965
1966 /*
1967 * Remove LED support if not needed.
1968 */
1969 if (!(np->features & FE_LED0)) {
1970 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1971 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1972 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1973 }
1974
1975#ifdef SYM_CONF_IARB_SUPPORT
1976 /*
1977 * If user does not want to use IMMEDIATE ARBITRATION
1978 * when we are reselected while attempting to arbitrate,
1979 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1980 */
1981 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1982 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1983#endif
1984 /*
1985 * Patch some data in SCRIPTS.
1986 * - start and done queue initial bus address.
1987 * - target bus address table bus address.
1988 */
1989 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1990 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1991 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1992}
1993#endif /* SYM_CONF_GENERIC_SUPPORT */
1994
1995/*
1996 * Patch routine for firmware #2.
1997 */
1998static void
1999sym_fw2_patch(hcb_p np)
2000{
2001 struct sym_fw2a_scr *scripta0;
2002 struct sym_fw2b_scr *scriptb0;
2003
2004 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
2005 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
2006
2007 /*
2008 * Remove LED support if not needed.
2009 */
2010 if (!(np->features & FE_LED0)) {
2011 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
2012 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
2013 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
2014 }
2015
2016#ifdef SYM_CONF_IARB_SUPPORT
2017 /*
2018 * If user does not want to use IMMEDIATE ARBITRATION
2019 * when we are reselected while attempting to arbitrate,
2020 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
2021 */
2022 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
2023 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
2024#endif
2025 /*
2026 * Patch some variable in SCRIPTS.
2027 * - start and done queue initial bus address.
2028 * - target bus address table bus address.
2029 */
2030 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
2031 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
2032 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
2033
2034 /*
2035 * Remove the load of SCNTL4 on reselection if not a C10.
2036 */
2037 if (!(np->features & FE_C10)) {
2038 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP);
2039 scripta0->resel_scntl4[1] = cpu_to_scr(0);
2040 }
2041
2042 /*
2043 * Remove a couple of work-arounds specific to C1010 if
2044 * they are not desirable. See `sym_fw2.h' for more details.
2045 */
2046 if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
2047 np->revision_id < 0x1 &&
2048 np->pciclk_khz < 60000)) {
2049 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
2050 scripta0->datao_phase[1] = cpu_to_scr(0);
2051 }
2052 if (!(np->device_id == PCI_ID_LSI53C1010 &&
2053 /* np->revision_id < 0xff */ 1)) {
2054 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
2055 scripta0->sel_done[1] = cpu_to_scr(0);
2056 }
2057
2058 /*
2059 * Patch some other variables in SCRIPTS.
2060 * These ones are loaded by the SCRIPTS processor.
2061 */
2062 scriptb0->pm0_data_addr[0] =
2063 cpu_to_scr(np->scripta_ba +
2064 offsetof(struct sym_fw2a_scr, pm0_data));
2065 scriptb0->pm1_data_addr[0] =
2066 cpu_to_scr(np->scripta_ba +
2067 offsetof(struct sym_fw2a_scr, pm1_data));
2068}
2069
2070/*
2071 * Fill the data area in scripts.
2072 * To be done for all firmwares.
2073 */
2074static void
2075sym_fw_fill_data (u32 *in, u32 *out)
2076{
2077 int i;
2078
2079 for (i = 0; i < SYM_CONF_MAX_SG; i++) {
2080 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN;
2081 *in++ = offsetof (struct sym_dsb, data[i]);
2082 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT;
2083 *out++ = offsetof (struct sym_dsb, data[i]);
2084 }
2085}
2086
2087/*
2088 * Setup useful script bus addresses.
2089 * To be done for all firmwares.
2090 */
2091static void
2092sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw)
2093{
2094 u32 *pa;
2095 u_short *po;
2096 int i;
2097
2098 /*
2099 * Build the bus address table for script A
2100 * from the script A offset table.
2101 */
2102 po = (u_short *) fw->a_ofs;
2103 pa = (u32 *) &np->fwa_bas;
2104 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)
2105 pa[i] = np->scripta_ba + po[i];
2106
2107 /*
2108 * Same for script B.
2109 */
2110 po = (u_short *) fw->b_ofs;
2111 pa = (u32 *) &np->fwb_bas;
2112 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)
2113 pa[i] = np->scriptb_ba + po[i];
2114}
2115
2116#ifdef SYM_CONF_GENERIC_SUPPORT
2117/*
2118 * Setup routine for firmware #1.
2119 */
2120static void
2121sym_fw1_setup(hcb_p np, struct sym_fw *fw)
2122{
2123 struct sym_fw1a_scr *scripta0;
2124 struct sym_fw1b_scr *scriptb0;
2125
2126 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
2127 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
2128
2129 /*
2130 * Fill variable parts in scripts.
2131 */
2132 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2133
2134 /*
2135 * Setup bus addresses used from the C code..
2136 */
2137 sym_fw_setup_bus_addresses(np, fw);
2138}
2139#endif /* SYM_CONF_GENERIC_SUPPORT */
2140
2141/*
2142 * Setup routine for firmware #2.
2143 */
2144static void
2145sym_fw2_setup(hcb_p np, struct sym_fw *fw)
2146{
2147 struct sym_fw2a_scr *scripta0;
2148 struct sym_fw2b_scr *scriptb0;
2149
2150 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
2151 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
2152
2153 /*
2154 * Fill variable parts in scripts.
2155 */
2156 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2157
2158 /*
2159 * Setup bus addresses used from the C code..
2160 */
2161 sym_fw_setup_bus_addresses(np, fw);
2162}
2163
2164/*
2165 * Allocate firmware descriptors.
2166 */
2167#ifdef SYM_CONF_GENERIC_SUPPORT
2168static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic");
2169#endif /* SYM_CONF_GENERIC_SUPPORT */
2170static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based");
2171
2172/*
2173 * Find the most appropriate firmware for a chip.
2174 */
2175static struct sym_fw *
2176sym_find_firmware(struct sym_pci_chip *chip)
2177{
2178 if (chip->features & FE_LDSTR)
2179 return &sym_fw2;
2180#ifdef SYM_CONF_GENERIC_SUPPORT
2181 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
2182 return &sym_fw1;
2183#endif
2184 else
2185 return 0;
2186}
2187
2188/*
2189 * Bind a script to physical addresses.
2190 */
2191static void sym_fw_bind_script (hcb_p np, u32 *start, int len)
2192{
2193 u32 opcode, new, old, tmp1, tmp2;
2194 u32 *end, *cur;
2195 int relocs;
2196
2197 cur = start;
2198 end = start + len/4;
2199
2200 while (cur < end) {
2201
2202 opcode = *cur;
2203
2204 /*
2205 * If we forget to change the length
2206 * in scripts, a field will be
2207 * padded with 0. This is an illegal
2208 * command.
2209 */
2210 if (opcode == 0) {
e3869ec7 2211 kprintf ("%s: ERROR0 IN SCRIPT at %d.\n",
984263bc
MD
2212 sym_name(np), (int) (cur-start));
2213 MDELAY (10000);
2214 ++cur;
2215 continue;
2216 };
2217
2218 /*
2219 * We use the bogus value 0xf00ff00f ;-)
2220 * to reserve data area in SCRIPTS.
2221 */
2222 if (opcode == SCR_DATA_ZERO) {
2223 *cur++ = 0;
2224 continue;
2225 }
2226
2227 if (DEBUG_FLAGS & DEBUG_SCRIPT)
e3869ec7 2228 kprintf ("%d: <%x>\n", (int) (cur-start),
984263bc
MD
2229 (unsigned)opcode);
2230
2231 /*
2232 * We don't have to decode ALL commands
2233 */
2234 switch (opcode >> 28) {
2235 case 0xf:
2236 /*
2237 * LOAD / STORE DSA relative, don't relocate.
2238 */
2239 relocs = 0;
2240 break;
2241 case 0xe:
2242 /*
2243 * LOAD / STORE absolute.
2244 */
2245 relocs = 1;
2246 break;
2247 case 0xc:
2248 /*
2249 * COPY has TWO arguments.
2250 */
2251 relocs = 2;
2252 tmp1 = cur[1];
2253 tmp2 = cur[2];
2254 if ((tmp1 ^ tmp2) & 3) {
e3869ec7 2255 kprintf ("%s: ERROR1 IN SCRIPT at %d.\n",
984263bc
MD
2256 sym_name(np), (int) (cur-start));
2257 MDELAY (10000);
2258 }
2259 /*
2260 * If PREFETCH feature not enabled, remove
2261 * the NO FLUSH bit if present.
2262 */
2263 if ((opcode & SCR_NO_FLUSH) &&
2264 !(np->features & FE_PFEN)) {
2265 opcode = (opcode & ~SCR_NO_FLUSH);
2266 }
2267 break;
2268 case 0x0:
2269 /*
2270 * MOVE/CHMOV (absolute address)
2271 */
2272 if (!(np->features & FE_WIDE))
2273 opcode = (opcode | OPC_MOVE);
2274 relocs = 1;
2275 break;
2276 case 0x1:
2277 /*
2278 * MOVE/CHMOV (table indirect)
2279 */
2280 if (!(np->features & FE_WIDE))
2281 opcode = (opcode | OPC_MOVE);
2282 relocs = 0;
2283 break;
2284 case 0x8:
2285 /*
2286 * JUMP / CALL
2287 * dont't relocate if relative :-)
2288 */
2289 if (opcode & 0x00800000)
2290 relocs = 0;
2291 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/
2292 relocs = 2;
2293 else
2294 relocs = 1;
2295 break;
2296 case 0x4:
2297 case 0x5:
2298 case 0x6:
2299 case 0x7:
2300 relocs = 1;
2301 break;
2302 default:
2303 relocs = 0;
2304 break;
2305 };
2306
2307 /*
2308 * Scriptify:) the opcode.
2309 */
2310 *cur++ = cpu_to_scr(opcode);
2311
2312 /*
2313 * If no relocation, assume 1 argument
2314 * and just scriptize:) it.
2315 */
2316 if (!relocs) {
2317 *cur = cpu_to_scr(*cur);
2318 ++cur;
2319 continue;
2320 }
2321
2322 /*
2323 * Otherwise performs all needed relocations.
2324 */
2325 while (relocs--) {
2326 old = *cur;
2327
2328 switch (old & RELOC_MASK) {
2329 case RELOC_REGISTER:
2330 new = (old & ~RELOC_MASK) + np->mmio_ba;
2331 break;
2332 case RELOC_LABEL_A:
2333 new = (old & ~RELOC_MASK) + np->scripta_ba;
2334 break;
2335 case RELOC_LABEL_B:
2336 new = (old & ~RELOC_MASK) + np->scriptb_ba;
2337 break;
2338 case RELOC_SOFTC:
2339 new = (old & ~RELOC_MASK) + np->hcb_ba;
2340 break;
2341 case 0:
2342 /*
2343 * Don't relocate a 0 address.
2344 * They are mostly used for patched or
2345 * script self-modified areas.
2346 */
2347 if (old == 0) {
2348 new = old;
2349 break;
2350 }
2351 /* fall through */
2352 default:
2353 new = 0;
2354 panic("sym_fw_bind_script: "
2355 "weird relocation %x\n", old);
2356 break;
2357 }
2358
2359 *cur++ = cpu_to_scr(new);
2360 }
2361 };
2362}
2363
2364/*--------------------------------------------------------------------------*/
2365/*--------------------------- END OF FIRMARES -----------------------------*/
2366/*--------------------------------------------------------------------------*/
2367
2368/*
2369 * Function prototypes.
2370 */
2371static void sym_save_initial_setting (hcb_p np);
2372static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram);
2373static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr);
2374static void sym_put_start_queue (hcb_p np, ccb_p cp);
2375static void sym_chip_reset (hcb_p np);
2376static void sym_soft_reset (hcb_p np);
2377static void sym_start_reset (hcb_p np);
2378static int sym_reset_scsi_bus (hcb_p np, int enab_int);
2379static int sym_wakeup_done (hcb_p np);
2380static void sym_flush_busy_queue (hcb_p np, int cam_status);
2381static void sym_flush_comp_queue (hcb_p np, int cam_status);
2382static void sym_init (hcb_p np, int reason);
2383static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp,
2384 u_char *fakp);
2385static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per,
2386 u_char div, u_char fak);
2387static void sym_setwide (hcb_p np, ccb_p cp, u_char wide);
2388static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2389 u_char per, u_char wide, u_char div, u_char fak);
2390static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2391 u_char per, u_char wide, u_char div, u_char fak);
2392static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat);
2393static void sym_intr (void *arg);
2394static void sym_poll (struct cam_sim *sim);
2395static void sym_recover_scsi_int (hcb_p np, u_char hsts);
2396static void sym_int_sto (hcb_p np);
2397static void sym_int_udc (hcb_p np);
2398static void sym_int_sbmc (hcb_p np);
2399static void sym_int_par (hcb_p np, u_short sist);
2400static void sym_int_ma (hcb_p np);
2401static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun,
2402 int task);
2403static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp);
2404static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task);
2405static void sym_sir_task_recovery (hcb_p np, int num);
2406static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);
2407static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs);
2408static int sym_compute_residual (hcb_p np, ccb_p cp);
2409static int sym_show_msg (u_char * msg);
2410static void sym_print_msg (ccb_p cp, char *label, u_char *msg);
2411static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp);
2412static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp);
2413static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp);
2414static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp);
2415static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp);
2416static void sym_int_sir (hcb_p np);
2417static void sym_free_ccb (hcb_p np, ccb_p cp);
2418static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
2419static ccb_p sym_alloc_ccb (hcb_p np);
2420static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
2421static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
2422static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
2423static int sym_snooptest (hcb_p np);
2424static void sym_selectclock(hcb_p np, u_char scntl3);
2425static void sym_getclock (hcb_p np, int mult);
2426static int sym_getpciclock (hcb_p np);
2427static void sym_complete_ok (hcb_p np, ccb_p cp);
2428static void sym_complete_error (hcb_p np, ccb_p cp);
2429static void sym_timeout (void *arg);
2430static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out);
2431static void sym_reset_dev (hcb_p np, union ccb *ccb);
2432static void sym_action (struct cam_sim *sim, union ccb *ccb);
2433static void sym_action1 (struct cam_sim *sim, union ccb *ccb);
2434static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp);
2435static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio,
2436 ccb_p cp);
2437#ifdef FreeBSD_Bus_Dma_Abstraction
2438static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
2439 bus_dma_segment_t *psegs, int nsegs);
2440#else
2441static int sym_scatter_virtual (hcb_p np, ccb_p cp, vm_offset_t vaddr,
2442 vm_size_t len);
2443static int sym_scatter_sg_virtual (hcb_p np, ccb_p cp,
2444 bus_dma_segment_t *psegs, int nsegs);
2445static int sym_scatter_physical (hcb_p np, ccb_p cp, vm_offset_t paddr,
2446 vm_size_t len);
2447#endif
2448static int sym_scatter_sg_physical (hcb_p np, ccb_p cp,
2449 bus_dma_segment_t *psegs, int nsegs);
2450static void sym_action2 (struct cam_sim *sim, union ccb *ccb);
2451static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip,
2452 struct ccb_trans_settings *cts);
2453static void sym_update_dflags(hcb_p np, u_char *flags,
2454 struct ccb_trans_settings *cts);
2455
2456#ifdef FreeBSD_Bus_Io_Abstraction
2457static struct sym_pci_chip *sym_find_pci_chip (device_t dev);
2458static int sym_pci_probe (device_t dev);
2459static int sym_pci_attach (device_t dev);
2460#else
2461static struct sym_pci_chip *sym_find_pci_chip (pcici_t tag);
2462static const char *sym_pci_probe (pcici_t tag, pcidi_t type);
2463static void sym_pci_attach (pcici_t tag, int unit);
2464static int sym_pci_attach2 (pcici_t tag, int unit);
2465#endif
2466
2467static void sym_pci_free (hcb_p np);
2468static int sym_cam_attach (hcb_p np);
2469static void sym_cam_free (hcb_p np);
2470
2471static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram);
2472static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp);
2473static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp);
2474
2475/*
2476 * Print something which allows to retrieve the controler type,
2477 * unit, target, lun concerned by a kernel message.
2478 */
2479static void PRINT_TARGET (hcb_p np, int target)
2480{
e3869ec7 2481 kprintf ("%s:%d:", sym_name(np), target);
984263bc
MD
2482}
2483
2484static void PRINT_LUN(hcb_p np, int target, int lun)
2485{
e3869ec7 2486 kprintf ("%s:%d:%d:", sym_name(np), target, lun);
984263bc
MD
2487}
2488
2489static void PRINT_ADDR (ccb_p cp)
2490{
2491 if (cp && cp->cam_ccb)
2492 xpt_print_path(cp->cam_ccb->ccb_h.path);
2493}
2494
2495/*
2496 * Take into account this ccb in the freeze count.
2497 */
2498static void sym_freeze_cam_ccb(union ccb *ccb)
2499{
2500 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) {
2501 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2502 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2503 xpt_freeze_devq(ccb->ccb_h.path, 1);
2504 }
2505 }
2506}
2507
2508/*
2509 * Set the status field of a CAM CCB.
2510 */
2511static __inline void sym_set_cam_status(union ccb *ccb, cam_status status)
2512{
2513 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2514 ccb->ccb_h.status |= status;
2515}
2516
2517/*
2518 * Get the status field of a CAM CCB.
2519 */
2520static __inline int sym_get_cam_status(union ccb *ccb)
2521{
2522 return ccb->ccb_h.status & CAM_STATUS_MASK;
2523}
2524
2525/*
2526 * Enqueue a CAM CCB.
2527 */
2528static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb)
2529{
2530 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED));
2531 ccb->ccb_h.status = CAM_REQ_INPROG;
2532
ddcafce9
JS
2533 callout_reset(&ccb->ccb_h.timeout_ch, ccb->ccb_h.timeout*hz/1000,
2534 sym_timeout, ccb);
984263bc
MD
2535 ccb->ccb_h.status |= CAM_SIM_QUEUED;
2536 ccb->ccb_h.sym_hcb_ptr = np;
2537
2538 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq);
2539}
2540
2541/*
2542 * Complete a pending CAM CCB.
2543 */
2544static void sym_xpt_done(hcb_p np, union ccb *ccb)
2545{
2546 if (ccb->ccb_h.status & CAM_SIM_QUEUED) {
ddcafce9 2547 callout_stop(&ccb->ccb_h.timeout_ch);
984263bc
MD
2548 sym_remque(sym_qptr(&ccb->ccb_h.sim_links));
2549 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2550 ccb->ccb_h.sym_hcb_ptr = 0;
2551 }
2552 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE)
2553 sym_freeze_cam_ccb(ccb);
2554 xpt_done(ccb);
2555}
2556
2557static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
2558{
2559 sym_set_cam_status(ccb, cam_status);
2560 sym_xpt_done(np, ccb);
2561}
2562
2563/*
2564 * SYMBIOS chip clock divisor table.
2565 *
2566 * Divisors are multiplied by 10,000,000 in order to make
2567 * calculations more simple.
2568 */
2569#define _5M 5000000
2570static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
2571
2572/*
2573 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
2574 * 128 transfers. All chips support at least 16 transfers
2575 * bursts. The 825A, 875 and 895 chips support bursts of up
2576 * to 128 transfers and the 895A and 896 support bursts of up
2577 * to 64 transfers. All other chips support up to 16
2578 * transfers bursts.
2579 *
2580 * For PCI 32 bit data transfers each transfer is a DWORD.
2581 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
2582 *
2583 * We use log base 2 (burst length) as internal code, with
2584 * value 0 meaning "burst disabled".
2585 */
2586
2587/*
2588 * Burst length from burst code.
2589 */
2590#define burst_length(bc) (!(bc))? 0 : 1 << (bc)
2591
2592/*
2593 * Burst code from io register bits.
2594 */
2595#define burst_code(dmode, ctest4, ctest5) \
2596 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
2597
2598/*
2599 * Set initial io register bits from burst code.
2600 */
2601static __inline void sym_init_burst(hcb_p np, u_char bc)
2602{
2603 np->rv_ctest4 &= ~0x80;
2604 np->rv_dmode &= ~(0x3 << 6);
2605 np->rv_ctest5 &= ~0x4;
2606
2607 if (!bc) {
2608 np->rv_ctest4 |= 0x80;
2609 }
2610 else {
2611 --bc;
2612 np->rv_dmode |= ((bc & 0x3) << 6);
2613 np->rv_ctest5 |= (bc & 0x4);
2614 }
2615}
2616
2617
2618/*
2619 * Print out the list of targets that have some flag disabled by user.
2620 */
2621static void sym_print_targets_flag(hcb_p np, int mask, char *msg)
2622{
2623 int cnt;
2624 int i;
2625
2626 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2627 if (i == np->myaddr)
2628 continue;
2629 if (np->target[i].usrflags & mask) {
2630 if (!cnt++)
e3869ec7 2631 kprintf("%s: %s disabled for targets",
984263bc 2632 sym_name(np), msg);
e3869ec7 2633 kprintf(" %d", i);
984263bc
MD
2634 }
2635 }
2636 if (cnt)
e3869ec7 2637 kprintf(".\n");
984263bc
MD
2638}
2639
2640/*
2641 * Save initial settings of some IO registers.
2642 * Assumed to have been set by BIOS.
2643 * We cannot reset the chip prior to reading the
2644 * IO registers, since informations will be lost.
2645 * Since the SCRIPTS processor may be running, this
2646 * is not safe on paper, but it seems to work quite
2647 * well. :)
2648 */
2649static void sym_save_initial_setting (hcb_p np)
2650{
2651 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
2652 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
2653 np->sv_dmode = INB(nc_dmode) & 0xce;
2654 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
2655 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
2656 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
2657 np->sv_gpcntl = INB(nc_gpcntl);
2658 np->sv_stest1 = INB(nc_stest1);
2659 np->sv_stest2 = INB(nc_stest2) & 0x20;
2660 np->sv_stest4 = INB(nc_stest4);
2661 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
2662 np->sv_scntl4 = INB(nc_scntl4);
2663 np->sv_ctest5 = INB(nc_ctest5) & 0x04;
2664 }
2665 else
2666 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
2667}
2668
2669/*
2670 * Prepare io register values used by sym_init() according
2671 * to selected and supported features.
2672 */
2673static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
2674{
2675 u_char burst_max;
2676 u32 period;
2677 int i;
2678
2679 /*
2680 * Wide ?
2681 */
2682 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
2683
2684 /*
2685 * Get the frequency of the chip's clock.
2686 */
2687 if (np->features & FE_QUAD)
2688 np->multiplier = 4;
2689 else if (np->features & FE_DBLR)
2690 np->multiplier = 2;
2691 else
2692 np->multiplier = 1;
2693
2694 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000;
2695 np->clock_khz *= np->multiplier;
2696
2697 if (np->clock_khz != 40000)
2698 sym_getclock(np, np->multiplier);
2699
2700 /*
2701 * Divisor to be used for async (timer pre-scaler).
2702 */
2703 i = np->clock_divn - 1;
2704 while (--i >= 0) {
2705 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
2706 ++i;
2707 break;
2708 }
2709 }
2710 np->rv_scntl3 = i+1;
2711
2712 /*
2713 * The C1010 uses hardwired divisors for async.
2714 * So, we just throw away, the async. divisor.:-)
2715 */
2716 if (np->features & FE_C10)
2717 np->rv_scntl3 = 0;
2718
2719 /*
2720 * Minimum synchronous period factor supported by the chip.
2721 * Btw, 'period' is in tenths of nanoseconds.
2722 */
2723 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
2724 if (period <= 250) np->minsync = 10;
2725 else if (period <= 303) np->minsync = 11;
2726 else if (period <= 500) np->minsync = 12;
2727 else np->minsync = (period + 40 - 1) / 40;
2728
2729 /*
2730 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
2731 */
2732 if (np->minsync < 25 &&
2733 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
2734 np->minsync = 25;
2735 else if (np->minsync < 12 &&
2736 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
2737 np->minsync = 12;
2738
2739 /*
2740 * Maximum synchronous period factor supported by the chip.
2741 */
2742 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
2743 np->maxsync = period > 2540 ? 254 : period / 10;
2744
2745 /*
2746 * If chip is a C1010, guess the sync limits in DT mode.
2747 */
2748 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
2749 if (np->clock_khz == 160000) {
2750 np->minsync_dt = 9;
2751 np->maxsync_dt = 50;
2752 np->maxoffs_dt = 62;
2753 }
2754 }
2755
2756 /*
2757 * 64 bit addressing (895A/896/1010) ?
2758 */
2759 if (np->features & FE_DAC)
2760#if BITS_PER_LONG > 32
2761 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
2762#else
2763 np->rv_ccntl1 |= (DDAC);
2764#endif
2765
2766 /*
2767 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
2768 */
2769 if (np->features & FE_NOPM)
2770 np->rv_ccntl0 |= (ENPMJ);
2771
2772 /*
2773 * C1010 Errata.
2774 * In dual channel mode, contention occurs if internal cycles
2775 * are used. Disable internal cycles.
2776 */
2777 if (np->device_id == PCI_ID_LSI53C1010 &&
2778 np->revision_id < 0x2)
2779 np->rv_ccntl0 |= DILS;
2780
2781 /*
2782 * Select burst length (dwords)
2783 */
2784 burst_max = SYM_SETUP_BURST_ORDER;
2785 if (burst_max == 255)
2786 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
2787 np->sv_ctest5);
2788 if (burst_max > 7)
2789 burst_max = 7;
2790 if (burst_max > np->maxburst)
2791 burst_max = np->maxburst;
2792
2793 /*
2794 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
2795 * This chip and the 860 Rev 1 may wrongly use PCI cache line
2796 * based transactions on LOAD/STORE instructions. So we have
2797 * to prevent these chips from using such PCI transactions in
2798 * this driver. The generic ncr driver that does not use
2799 * LOAD/STORE instructions does not need this work-around.
2800 */
2801 if ((np->device_id == PCI_ID_SYM53C810 &&
2802 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
2803 (np->device_id == PCI_ID_SYM53C860 &&
2804 np->revision_id <= 0x1))
2805 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
2806
2807 /*
2808 * Select all supported special features.
2809 * If we are using on-board RAM for scripts, prefetch (PFEN)
2810 * does not help, but burst op fetch (BOF) does.
2811 * Disabling PFEN makes sure BOF will be used.
2812 */
2813 if (np->features & FE_ERL)
2814 np->rv_dmode |= ERL; /* Enable Read Line */
2815 if (np->features & FE_BOF)
2816 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
2817 if (np->features & FE_ERMP)
2818 np->rv_dmode |= ERMP; /* Enable Read Multiple */
2819#if 1
2820 if ((np->features & FE_PFEN) && !np->ram_ba)
2821#else
2822 if (np->features & FE_PFEN)
2823#endif
2824 np->rv_dcntl |= PFEN; /* Prefetch Enable */
2825 if (np->features & FE_CLSE)
2826 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
2827 if (np->features & FE_WRIE)
2828 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
2829 if (np->features & FE_DFS)
2830 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
2831
2832 /*
2833 * Select some other
2834 */
2835 if (SYM_SETUP_PCI_PARITY)
2836 np->rv_ctest4 |= MPEE; /* Master parity checking */
2837 if (SYM_SETUP_SCSI_PARITY)
2838 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
2839
2840 /*
2841 * Get parity checking, host ID and verbose mode from NVRAM
2842 */
2843 np->myaddr = 255;
2844 sym_nvram_setup_host (np, nvram);
2845
2846 /*
2847 * Get SCSI addr of host adapter (set by bios?).
2848 */
2849 if (np->myaddr == 255) {
2850 np->myaddr = INB(nc_scid) & 0x07;
2851 if (!np->myaddr)
2852 np->myaddr = SYM_SETUP_HOST_ID;
2853 }
2854
2855 /*
2856 * Prepare initial io register bits for burst length
2857 */
2858 sym_init_burst(np, burst_max);
2859
2860 /*
2861 * Set SCSI BUS mode.
2862 * - LVD capable chips (895/895A/896/1010) report the
2863 * current BUS mode through the STEST4 IO register.
2864 * - For previous generation chips (825/825A/875),
2865 * user has to tell us how to check against HVD,
2866 * since a 100% safe algorithm is not possible.
2867 */
2868 np->scsi_mode = SMODE_SE;
2869 if (np->features & (FE_ULTRA2|FE_ULTRA3))
2870 np->scsi_mode = (np->sv_stest4 & SMODE);
2871 else if (np->features & FE_DIFF) {
2872 if (SYM_SETUP_SCSI_DIFF == 1) {
2873 if (np->sv_scntl3) {
2874 if (np->sv_stest2 & 0x20)
2875 np->scsi_mode = SMODE_HVD;
2876 }
2877 else if (nvram->type == SYM_SYMBIOS_NVRAM) {
2878 if (!(INB(nc_gpreg) & 0x08))
2879 np->scsi_mode = SMODE_HVD;
2880 }
2881 }
2882 else if (SYM_SETUP_SCSI_DIFF == 2)
2883 np->scsi_mode = SMODE_HVD;
2884 }
2885 if (np->scsi_mode == SMODE_HVD)
2886 np->rv_stest2 |= 0x20;
2887
2888 /*
2889 * Set LED support from SCRIPTS.
2890 * Ignore this feature for boards known to use a
2891 * specific GPIO wiring and for the 895A, 896
2892 * and 1010 that drive the LED directly.
2893 */
2894 if ((SYM_SETUP_SCSI_LED ||
2895 (nvram->type == SYM_SYMBIOS_NVRAM ||
2896 (nvram->type == SYM_TEKRAM_NVRAM &&
2897 np->device_id == PCI_ID_SYM53C895))) &&
2898 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
2899 np->features |= FE_LED0;
2900
2901 /*
2902 * Set irq mode.
2903 */
2904 switch(SYM_SETUP_IRQ_MODE & 3) {
2905 case 2:
2906 np->rv_dcntl |= IRQM;
2907 break;
2908 case 1:
2909 np->rv_dcntl |= (np->sv_dcntl & IRQM);
2910 break;
2911 default:
2912 break;
2913 }
2914
2915 /*
2916 * Configure targets according to driver setup.
2917 * If NVRAM present get targets setup from NVRAM.
2918 */
2919 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2920 tcb_p tp = &np->target[i];
2921
2922#ifdef FreeBSD_New_Tran_Settings
2923 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2;
2924 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2;
2925#endif
2926 tp->tinfo.user.period = np->minsync;
2927 tp->tinfo.user.offset = np->maxoffs;
2928 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT;
2929 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
2930 tp->usrtags = SYM_SETUP_MAX_TAG;
2931
2932 sym_nvram_setup_target (np, i, nvram);
2933
2934 /*
2935 * For now, guess PPR/DT support from the period
2936 * and BUS width.
2937 */
2938 if (np->features & FE_ULTRA3) {
2939 if (tp->tinfo.user.period <= 9 &&
2940 tp->tinfo.user.width == BUS_16_BIT) {
2941 tp->tinfo.user.options |= PPR_OPT_DT;
2942 tp->tinfo.user.offset = np->maxoffs_dt;
2943#ifdef FreeBSD_New_Tran_Settings
2944 tp->tinfo.user.spi_version = 3;
2945#endif
2946 }
2947 }
2948
2949 if (!tp->usrtags)
2950 tp->usrflags &= ~SYM_TAGS_ENABLED;
2951 }
2952
2953 /*
2954 * Let user know about the settings.
2955 */
2956 i = nvram->type;
e3869ec7 2957 kprintf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np),
984263bc
MD
2958 i == SYM_SYMBIOS_NVRAM ? "Symbios" :
2959 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"),
2960 np->myaddr,
2961 (np->features & FE_ULTRA3) ? 80 :
2962 (np->features & FE_ULTRA2) ? 40 :
2963 (np->features & FE_ULTRA) ? 20 : 10,
2964 sym_scsi_bus_mode(np->scsi_mode),
2965 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
2966 /*
2967 * Tell him more on demand.
2968 */
2969 if (sym_verbose) {
e3869ec7 2970 kprintf("%s: %s IRQ line driver%s\n",
984263bc
MD
2971 sym_name(np),
2972 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
2973 np->ram_ba ? ", using on-chip SRAM" : "");
e3869ec7 2974 kprintf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
984263bc 2975 if (np->features & FE_NOPM)
e3869ec7 2976 kprintf("%s: handling phase mismatch from SCRIPTS.\n",
984263bc
MD
2977 sym_name(np));
2978 }
2979 /*
2980 * And still more.
2981 */
2982 if (sym_verbose > 1) {
e3869ec7 2983 kprintf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
984263bc
MD
2984 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2985 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
2986 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
2987
e3869ec7 2988 kprintf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
984263bc
MD
2989 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2990 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
2991 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
2992 }
2993 /*
2994 * Let user be aware of targets that have some disable flags set.
2995 */
2996 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT");
2997 if (sym_verbose)
2998 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED,
2999 "SCAN FOR LUNS");
3000
3001 return 0;
3002}
3003
3004/*
3005 * Prepare the next negotiation message if needed.
3006 *
3007 * Fill in the part of message buffer that contains the
3008 * negotiation and the nego_status field of the CCB.
3009 * Returns the size of the message in bytes.
3010 */
3011
3012static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr)
3013{
3014 tcb_p tp = &np->target[cp->target];
3015 int msglen = 0;
3016
3017 /*
3018 * Early C1010 chips need a work-around for DT
3019 * data transfer to work.
3020 */
3021 if (!(np->features & FE_U3EN))
3022 tp->tinfo.goal.options = 0;
3023 /*
3024 * negotiate using PPR ?
3025 */
3026 if (tp->tinfo.goal.options & PPR_OPT_MASK)
3027 nego = NS_PPR;
3028 /*
3029 * negotiate wide transfers ?
3030 */
3031 else if (tp->tinfo.current.width != tp->tinfo.goal.width)
3032 nego = NS_WIDE;
3033 /*
3034 * negotiate synchronous transfers?
3035 */
3036 else if (tp->tinfo.current.period != tp->tinfo.goal.period ||
3037 tp->tinfo.current.offset != tp->tinfo.goal.offset)
3038 nego = NS_SYNC;
3039
3040 switch (nego) {
3041 case NS_SYNC:
3042 msgptr[msglen++] = M_EXTENDED;
3043 msgptr[msglen++] = 3;
3044 msgptr[msglen++] = M_X_SYNC_REQ;
3045 msgptr[msglen++] = tp->tinfo.goal.period;
3046 msgptr[msglen++] = tp->tinfo.goal.offset;
3047 break;
3048 case NS_WIDE:
3049 msgptr[msglen++] = M_EXTENDED;
3050 msgptr[msglen++] = 2;
3051 msgptr[msglen++] = M_X_WIDE_REQ;
3052 msgptr[msglen++] = tp->tinfo.goal.width;
3053 break;
3054 case NS_PPR:
3055 msgptr[msglen++] = M_EXTENDED;
3056 msgptr[msglen++] = 6;
3057 msgptr[msglen++] = M_X_PPR_REQ;
3058 msgptr[msglen++] = tp->tinfo.goal.period;
3059 msgptr[msglen++] = 0;
3060 msgptr[msglen++] = tp->tinfo.goal.offset;
3061 msgptr[msglen++] = tp->tinfo.goal.width;
3062 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT;
3063 break;
3064 };
3065
3066 cp->nego_status = nego;
3067
3068 if (nego) {
3069 tp->nego_cp = cp; /* Keep track a nego will be performed */
3070 if (DEBUG_FLAGS & DEBUG_NEGO) {
3071 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" :
3072 nego == NS_WIDE ? "wide msgout" :
3073 "ppr msgout", msgptr);
3074 };
3075 };
3076
3077 return msglen;
3078}
3079
3080/*
3081 * Insert a job into the start queue.
3082 */
3083static void sym_put_start_queue(hcb_p np, ccb_p cp)
3084{
3085 u_short qidx;
3086
3087#ifdef SYM_CONF_IARB_SUPPORT
3088 /*
3089 * If the previously queued CCB is not yet done,
3090 * set the IARB hint. The SCRIPTS will go with IARB
3091 * for this job when starting the previous one.
3092 * We leave devices a chance to win arbitration by
3093 * not using more than 'iarb_max' consecutive
3094 * immediate arbitrations.
3095 */
3096 if (np->last_cp && np->iarb_count < np->iarb_max) {
3097 np->last_cp->host_flags |= HF_HINT_IARB;
3098 ++np->iarb_count;
3099 }
3100 else
3101 np->iarb_count = 0;
3102 np->last_cp = cp;
3103#endif
3104
3105 /*
3106 * Insert first the idle task and then our job.
3107 * The MB should ensure proper ordering.
3108 */
3109 qidx = np->squeueput + 2;
3110 if (qidx >= MAX_QUEUE*2) qidx = 0;
3111
3112 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
3113 MEMORY_BARRIER();
3114 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
3115
3116 np->squeueput = qidx;
3117
3118 if (DEBUG_FLAGS & DEBUG_QUEUE)
e3869ec7 3119 kprintf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
984263bc
MD
3120
3121 /*
3122 * Script processor may be waiting for reselect.
3123 * Wake it up.
3124 */
3125 MEMORY_BARRIER();
3126 OUTB (nc_istat, SIGP|np->istat_sem);
3127}
3128
3129
3130/*
3131 * Soft reset the chip.
3132 *
3133 * Raising SRST when the chip is running may cause
3134 * problems on dual function chips (see below).
3135 * On the other hand, LVD devices need some delay
3136 * to settle and report actual BUS mode in STEST4.
3137 */
3138static void sym_chip_reset (hcb_p np)
3139{
3140 OUTB (nc_istat, SRST);
3141 UDELAY (10);
3142 OUTB (nc_istat, 0);
3143 UDELAY(2000); /* For BUS MODE to settle */
3144}
3145
3146/*
3147 * Soft reset the chip.
3148 *
3149 * Some 896 and 876 chip revisions may hang-up if we set
3150 * the SRST (soft reset) bit at the wrong time when SCRIPTS
3151 * are running.
3152 * So, we need to abort the current operation prior to
3153 * soft resetting the chip.
3154 */
3155static void sym_soft_reset (hcb_p np)
3156{
3157 u_char istat;
3158 int i;
3159
3160 OUTB (nc_istat, CABRT);
3161 for (i = 1000000 ; i ; --i) {
3162 istat = INB (nc_istat);
3163 if (istat & SIP) {
3164 INW (nc_sist);
3165 continue;
3166 }
3167 if (istat & DIP) {
3168 OUTB (nc_istat, 0);
3169 INB (nc_dstat);
3170 break;
3171 }
3172 }
3173 if (!i)
e3869ec7 3174 kprintf("%s: unable to abort current chip operation.\n",
984263bc
MD
3175 sym_name(np));
3176 sym_chip_reset (np);
3177}
3178
3179/*
3180 * Start reset process.
3181 *
3182 * The interrupt handler will reinitialize the chip.
3183 */
3184static void sym_start_reset(hcb_p np)
3185{
3186 (void) sym_reset_scsi_bus(np, 1);
3187}
3188
3189static int sym_reset_scsi_bus(hcb_p np, int enab_int)
3190{
3191 u32 term;
3192 int retv = 0;
3193
3194 sym_soft_reset(np); /* Soft reset the chip */
3195 if (enab_int)
3196 OUTW (nc_sien, RST);
3197 /*
3198 * Enable Tolerant, reset IRQD if present and
3199 * properly set IRQ mode, prior to resetting the bus.
3200 */
3201 OUTB (nc_stest3, TE);
3202 OUTB (nc_dcntl, (np->rv_dcntl & IRQM));
3203 OUTB (nc_scntl1, CRST);
3204 UDELAY (200);
3205
3206 if (!SYM_SETUP_SCSI_BUS_CHECK)
3207 goto out;
3208 /*
3209 * Check for no terminators or SCSI bus shorts to ground.
3210 * Read SCSI data bus, data parity bits and control signals.
3211 * We are expecting RESET to be TRUE and other signals to be
3212 * FALSE.
3213 */
3214 term = INB(nc_sstat0);
3215 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
3216 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
3217 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
3218 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
3219 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
3220
3221 if (!(np->features & FE_WIDE))
3222 term &= 0x3ffff;
3223
3224 if (term != (2<<7)) {
e3869ec7 3225 kprintf("%s: suspicious SCSI data while resetting the BUS.\n",
984263bc 3226 sym_name(np));
e3869ec7 3227 kprintf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
984263bc
MD
3228 "0x%lx, expecting 0x%lx\n",
3229 sym_name(np),
3230 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
3231 (u_long)term, (u_long)(2<<7));
3232 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
3233 retv = 1;
3234 }
3235out:
3236 OUTB (nc_scntl1, 0);
3237 /* MDELAY(100); */
3238 return retv;
3239}
3240
3241/*
3242 * The chip may have completed jobs. Look at the DONE QUEUE.
3243 *
3244 * On architectures that may reorder LOAD/STORE operations,
3245 * a memory barrier may be needed after the reading of the
3246 * so-called `flag' and prior to dealing with the data.
3247 */
3248static int sym_wakeup_done (hcb_p np)
3249{
3250 ccb_p cp;
3251 int i, n;
3252 u32 dsa;
3253
3254 n = 0;
3255 i = np->dqueueget;
3256 while (1) {
3257 dsa = scr_to_cpu(np->dqueue[i]);
3258 if (!dsa)
3259 break;
3260 np->dqueue[i] = 0;
3261 if ((i = i+2) >= MAX_QUEUE*2)
3262 i = 0;
3263
3264 cp = sym_ccb_from_dsa(np, dsa);
3265 if (cp) {
3266 MEMORY_BARRIER();
3267 sym_complete_ok (np, cp);
3268 ++n;
3269 }
3270 else
e3869ec7 3271 kprintf ("%s: bad DSA (%x) in done queue.\n",
984263bc
MD
3272 sym_name(np), (u_int) dsa);
3273 }
3274 np->dqueueget = i;
3275
3276 return n;
3277}
3278
3279/*
3280 * Complete all active CCBs with error.
3281 * Used on CHIP/SCSI RESET.
3282 */
3283static void sym_flush_busy_queue (hcb_p np, int cam_status)
3284{
3285 /*
3286 * Move all active CCBs to the COMP queue
3287 * and flush this queue.
3288 */
3289 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
3290 sym_que_init(&np->busy_ccbq);
3291 sym_flush_comp_queue(np, cam_status);
3292}
3293
3294/*
3295 * Start chip.
3296 *
3297 * 'reason' means:
3298 * 0: initialisation.
3299 * 1: SCSI BUS RESET delivered or received.
3300 * 2: SCSI BUS MODE changed.
3301 */
3302static void sym_init (hcb_p np, int reason)
3303{
3304 int i;
3305 u32 phys;
3306
3307 /*
3308 * Reset chip if asked, otherwise just clear fifos.
3309 */
3310 if (reason == 1)
3311 sym_soft_reset(np);
3312 else {
3313 OUTB (nc_stest3, TE|CSF);
3314 OUTONB (nc_ctest3, CLF);
3315 }
3316
3317 /*
3318 * Clear Start Queue
3319 */
3320 phys = np->squeue_ba;
3321 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3322 np->squeue[i] = cpu_to_scr(np->idletask_ba);
3323 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
3324 }
3325 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3326
3327 /*
3328 * Start at first entry.
3329 */
3330 np->squeueput = 0;
3331
3332 /*
3333 * Clear Done Queue
3334 */
3335 phys = np->dqueue_ba;
3336 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3337 np->dqueue[i] = 0;
3338 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
3339 }
3340 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3341
3342 /*
3343 * Start at first entry.
3344 */
3345 np->dqueueget = 0;
3346
3347 /*
3348 * Install patches in scripts.
3349 * This also let point to first position the start
3350 * and done queue pointers used from SCRIPTS.
3351 */
3352 np->fw_patch(np);
3353
3354 /*
3355 * Wakeup all pending jobs.
3356 */
3357 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);
3358
3359 /*
3360 * Init chip.
3361 */
3362 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */
3363 UDELAY (2000); /* The 895 needs time for the bus mode to settle */
3364
3365 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
3366 /* full arb., ena parity, par->ATN */
3367 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
3368
3369 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
3370
3371 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
3372 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
3373 OUTB (nc_istat , SIGP ); /* Signal Process */
3374 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
3375 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
3376
3377 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
3378 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
3379 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
3380
3381 /* Extended Sreq/Sack filtering not supported on the C10 */
3382 if (np->features & FE_C10)
3383 OUTB (nc_stest2, np->rv_stest2);
3384 else
3385 OUTB (nc_stest2, EXT|np->rv_stest2);
3386
3387 OUTB (nc_stest3, TE); /* TolerANT enable */
3388 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
3389
3390 /*
3391 * For now, disable AIP generation on C1010-66.
3392 */
3393 if (np->device_id == PCI_ID_LSI53C1010_2)
3394 OUTB (nc_aipcntl1, DISAIP);
3395
3396 /*
3397 * C10101 Errata.
3398 * Errant SGE's when in narrow. Write bits 4 & 5 of
3399 * STEST1 register to disable SGE. We probably should do
3400 * that from SCRIPTS for each selection/reselection, but
3401 * I just don't want. :)
3402 */
3403 if (np->device_id == PCI_ID_LSI53C1010 &&
3404 /* np->revision_id < 0xff */ 1)
3405 OUTB (nc_stest1, INB(nc_stest1) | 0x30);
3406
3407 /*
3408 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
3409 * Disable overlapped arbitration for some dual function devices,
3410 * regardless revision id (kind of post-chip-design feature. ;-))
3411 */
3412 if (np->device_id == PCI_ID_SYM53C875)
3413 OUTB (nc_ctest0, (1<<5));
3414 else if (np->device_id == PCI_ID_SYM53C896)
3415 np->rv_ccntl0 |= DPR;
3416
3417 /*
3418 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
3419 * and/or hardware phase mismatch, since only such chips
3420 * seem to support those IO registers.
3421 */
3422 if (np->features & (FE_DAC|FE_NOPM)) {
3423 OUTB (nc_ccntl0, np->rv_ccntl0);
3424 OUTB (nc_ccntl1, np->rv_ccntl1);
3425 }
3426
3427 /*
3428 * If phase mismatch handled by scripts (895A/896/1010),
3429 * set PM jump addresses.
3430 */
3431 if (np->features & FE_NOPM) {
3432 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle));
3433 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle));
3434 }
3435
3436 /*
3437 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
3438 * Also set GPIO5 and clear GPIO6 if hardware LED control.
3439 */
3440 if (np->features & FE_LED0)
3441 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01);
3442 else if (np->features & FE_LEDC)
3443 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20);
3444
3445 /*
3446 * enable ints
3447 */
3448 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
3449 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID);
3450
3451 /*
3452 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
3453 * Try to eat the spurious SBMC interrupt that may occur when
3454 * we reset the chip but not the SCSI BUS (at initialization).
3455 */
3456 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
3457 OUTONW (nc_sien, SBMC);
3458 if (reason == 0) {
3459 MDELAY(100);
3460 INW (nc_sist);
3461 }
3462 np->scsi_mode = INB (nc_stest4) & SMODE;
3463 }
3464
3465 /*
3466 * Fill in target structure.
3467 * Reinitialize usrsync.
3468 * Reinitialize usrwide.
3469 * Prepare sync negotiation according to actual SCSI bus mode.
3470 */
3471 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
3472 tcb_p tp = &np->target[i];
3473
3474 tp->to_reset = 0;
3475 tp->head.sval = 0;
3476 tp->head.wval = np->rv_scntl3;
3477 tp->head.uval = 0;
3478
3479 tp->tinfo.current.period = 0;
3480 tp->tinfo.current.offset = 0;
3481 tp->tinfo.current.width = BUS_8_BIT;
3482 tp->tinfo.current.options = 0;
3483 }
3484
3485 /*
3486 * Download SCSI SCRIPTS to on-chip RAM if present,
3487 * and start script processor.
3488 */
3489 if (np->ram_ba) {
3490 if (sym_verbose > 1)
e3869ec7 3491 kprintf ("%s: Downloading SCSI SCRIPTS.\n",
984263bc
MD
3492 sym_name(np));
3493 if (np->ram_ws == 8192) {
3494 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz);
3495 OUTL (nc_mmws, np->scr_ram_seg);
3496 OUTL (nc_mmrs, np->scr_ram_seg);
3497 OUTL (nc_sfs, np->scr_ram_seg);
3498 phys = SCRIPTB_BA (np, start64);
3499 }
3500 else
3501 phys = SCRIPTA_BA (np, init);
3502 OUTRAM_OFF(0, np->scripta0, np->scripta_sz);
3503 }
3504 else
3505 phys = SCRIPTA_BA (np, init);
3506
3507 np->istat_sem = 0;
3508
3509 OUTL (nc_dsa, np->hcb_ba);
3510 OUTL_DSP (phys);
3511
3512 /*
3513 * Notify the XPT about the RESET condition.
3514 */
3515 if (reason != 0)
3516 xpt_async(AC_BUS_RESET, np->path, NULL);
3517}
3518
3519/*
3520 * Get clock factor and sync divisor for a given
3521 * synchronous factor period.
3522 */
3523static int
3524sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
3525{
3526 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
3527 int div = np->clock_divn; /* Number of divisors supported */
3528 u32 fak; /* Sync factor in sxfer */
3529 u32 per; /* Period in tenths of ns */
3530 u32 kpc; /* (per * clk) */
3531 int ret;
3532
3533 /*
3534 * Compute the synchronous period in tenths of nano-seconds
3535 */
3536 if (dt && sfac <= 9) per = 125;
3537 else if (sfac <= 10) per = 250;
3538 else if (sfac == 11) per = 303;
3539 else if (sfac == 12) per = 500;
3540 else per = 40 * sfac;
3541 ret = per;
3542
3543 kpc = per * clk;
3544 if (dt)
3545 kpc <<= 1;
3546
3547 /*
3548 * For earliest C10 revision 0, we cannot use extra
3549 * clocks for the setting of the SCSI clocking.
3550 * Note that this limits the lowest sync data transfer
3551 * to 5 Mega-transfers per second and may result in
3552 * using higher clock divisors.
3553 */
3554#if 1
3555 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
3556 /*
3557 * Look for the lowest clock divisor that allows an
3558 * output speed not faster than the period.
3559 */
3560 while (div > 0) {
3561 --div;
3562 if (kpc > (div_10M[div] << 2)) {
3563 ++div;
3564 break;
3565 }
3566 }
3567 fak = 0; /* No extra clocks */
3568 if (div == np->clock_divn) { /* Are we too fast ? */
3569 ret = -1;
3570 }
3571 *divp = div;
3572 *fakp = fak;
3573 return ret;
3574 }
3575#endif
3576
3577 /*
3578 * Look for the greatest clock divisor that allows an
3579 * input speed faster than the period.
3580 */
3581 while (div-- > 0)
3582 if (kpc >= (div_10M[div] << 2)) break;
3583
3584 /*
3585 * Calculate the lowest clock factor that allows an output
3586 * speed not faster than the period, and the max output speed.
3587 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
3588 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
3589 */
3590 if (dt) {
3591 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
3592 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
3593 }
3594 else {
3595 fak = (kpc - 1) / div_10M[div] + 1 - 4;
3596 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
3597 }
3598
3599 /*
3600 * Check against our hardware limits, or bugs :).
3601 */
3602 if (fak < 0) {fak = 0; ret = -1;}
3603 if (fak > 2) {fak = 2; ret = -1;}
3604
3605 /*
3606 * Compute and return sync parameters.
3607 */
3608 *divp = div;
3609 *fakp = fak;
3610
3611 return ret;
3612}
3613
3614/*
3615 * Tell the SCSI layer about the new transfer parameters.
3616 */
3617static void
3618sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid)
3619{
3620 struct ccb_trans_settings cts;
3621 struct cam_path *path;
3622 int sts;
3623 tcb_p tp = &np->target[target];
3624
3625 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target,
3626 CAM_LUN_WILDCARD);
3627 if (sts != CAM_REQ_CMP)
3628 return;
3629
3630 bzero(&cts, sizeof(cts));
3631
3632#ifdef FreeBSD_New_Tran_Settings
3633#define cts__scsi (cts.proto_specific.scsi)
3634#define cts__spi (cts.xport_specific.spi)
3635
3636 cts.type = CTS_TYPE_CURRENT_SETTINGS;
3637 cts.protocol = PROTO_SCSI;
3638 cts.transport = XPORT_SPI;
3639 cts.protocol_version = tp->tinfo.current.scsi_version;
3640 cts.transport_version = tp->tinfo.current.spi_version;
3641
3642 cts__spi.valid = spi_valid;
3643 if (spi_valid & CTS_SPI_VALID_SYNC_RATE)
3644 cts__spi.sync_period = tp->tinfo.current.period;
3645 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET)
3646 cts__spi.sync_offset = tp->tinfo.current.offset;
3647 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH)
3648 cts__spi.bus_width = tp->tinfo.current.width;
3649 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS)
3650 cts__spi.ppr_options = tp->tinfo.current.options;
3651#undef cts__spi
3652#undef cts__scsi
3653#else
3654 cts.valid = spi_valid;
3655 if (spi_valid & CCB_TRANS_SYNC_RATE_VALID)
3656 cts.sync_period = tp->tinfo.current.period;
3657 if (spi_valid & CCB_TRANS_SYNC_OFFSET_VALID)
3658 cts.sync_offset = tp->tinfo.current.offset;
3659 if (spi_valid & CCB_TRANS_BUS_WIDTH_VALID)
3660 cts.bus_width = tp->tinfo.current.width;
3661#endif
3662 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1);
3663 xpt_async(AC_TRANSFER_NEG, path, &cts);
3664 xpt_free_path(path);
3665}
3666
3667#ifdef FreeBSD_New_Tran_Settings
3668#define SYM_SPI_VALID_WDTR \
3669 CTS_SPI_VALID_BUS_WIDTH | \
3670 CTS_SPI_VALID_SYNC_RATE | \
3671 CTS_SPI_VALID_SYNC_OFFSET
3672#define SYM_SPI_VALID_SDTR \
3673 CTS_SPI_VALID_SYNC_RATE | \
3674 CTS_SPI_VALID_SYNC_OFFSET
3675#define SYM_SPI_VALID_PPR \
3676 CTS_SPI_VALID_PPR_OPTIONS | \
3677 CTS_SPI_VALID_BUS_WIDTH | \
3678 CTS_SPI_VALID_SYNC_RATE | \
3679 CTS_SPI_VALID_SYNC_OFFSET
3680#else
3681#define SYM_SPI_VALID_WDTR \
3682 CCB_TRANS_BUS_WIDTH_VALID | \
3683 CCB_TRANS_SYNC_RATE_VALID | \
3684 CCB_TRANS_SYNC_OFFSET_VALID
3685#define SYM_SPI_VALID_SDTR \
3686 CCB_TRANS_SYNC_RATE_VALID | \
3687 CCB_TRANS_SYNC_OFFSET_VALID
3688#define SYM_SPI_VALID_PPR \
3689 CCB_TRANS_BUS_WIDTH_VALID | \
3690 CCB_TRANS_SYNC_RATE_VALID | \
3691 CCB_TRANS_SYNC_OFFSET_VALID
3692#endif
3693
3694/*
3695 * We received a WDTR.
3696 * Let everything be aware of the changes.
3697 */
3698static void sym_setwide(hcb_p np, ccb_p cp, u_char wide)
3699{
3700 tcb_p tp = &np->target[cp->target];
3701
3702 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0);
3703
3704 /*
3705 * Tell the SCSI layer about the new transfer parameters.
3706 */
3707 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3708 tp->tinfo.current.offset = 0;
3709 tp->tinfo.current.period = 0;
3710 tp->tinfo.current.options = 0;
3711
3712 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR);
3713}
3714
3715/*
3716 * We received a SDTR.
3717 * Let everything be aware of the changes.
3718 */
3719static void
3720sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
3721{
3722 tcb_p tp = &np->target[cp->target];
3723 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0;
3724
3725 sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
3726
3727 /*
3728 * Tell the SCSI layer about the new transfer parameters.
3729 */
3730 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3731 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3732 tp->tinfo.goal.options = tp->tinfo.current.options = 0;
3733
3734 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR);
3735}
3736
3737/*
3738 * We received a PPR.
3739 * Let everything be aware of the changes.
3740 */
3741static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3742 u_char per, u_char wide, u_char div, u_char fak)
3743{
3744 tcb_p tp = &np->target[cp->target];
3745
3746 sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
3747
3748 /*
3749 * Tell the SCSI layer about the new transfer parameters.
3750 */
3751 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3752 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3753 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3754 tp->tinfo.goal.options = tp->tinfo.current.options = dt;
3755
3756 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR);
3757}
3758
3759/*
3760 * Switch trans mode for current job and it's target.
3761 */
3762static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3763 u_char per, u_char wide, u_char div, u_char fak)
3764{
3765 SYM_QUEHEAD *qp;
3766 union ccb *ccb;
3767 tcb_p tp;
3768 u_char target = INB (nc_sdid) & 0x0f;
3769 u_char sval, wval, uval;
3770
3771 assert (cp);
3772 if (!cp) return;
3773 ccb = cp->cam_ccb;
3774 assert (ccb);
3775 if (!ccb) return;
3776 assert (target == (cp->target & 0xf));
3777 tp = &np->target[target];
3778
3779 sval = tp->head.sval;
3780 wval = tp->head.wval;
3781 uval = tp->head.uval;
3782
3783#if 0
e3869ec7 3784 kprintf("XXXX sval=%x wval=%x uval=%x (%x)\n",
984263bc
MD
3785 sval, wval, uval, np->rv_scntl3);
3786#endif
3787 /*
3788 * Set the offset.
3789 */
3790 if (!(np->features & FE_C10))
3791 sval = (sval & ~0x1f) | ofs;
3792 else
3793 sval = (sval & ~0x3f) | ofs;
3794
3795 /*
3796 * Set the sync divisor and extra clock factor.
3797 */
3798 if (ofs != 0) {
3799 wval = (wval & ~0x70) | ((div+1) << 4);
3800 if (!(np->features & FE_C10))
3801 sval = (sval & ~0xe0) | (fak << 5);
3802 else {
3803 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
3804 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
3805 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
3806 }
3807 }
3808
3809 /*
3810 * Set the bus width.
3811 */
3812 wval = wval & ~EWS;
3813 if (wide != 0)
3814 wval |= EWS;
3815
3816 /*
3817 * Set misc. ultra enable bits.
3818 */
3819 if (np->features & FE_C10) {
3820 uval = uval & ~(U3EN|AIPCKEN);
3821 if (dt) {
3822 assert(np->features & FE_U3EN);
3823 uval |= U3EN;
3824 }
3825 }
3826 else {
3827 wval = wval & ~ULTRA;
3828 if (per <= 12) wval |= ULTRA;
3829 }
3830
3831 /*
3832 * Stop there if sync parameters are unchanged.
3833 */
3834 if (tp->head.sval == sval &&
3835 tp->head.wval == wval &&
3836 tp->head.uval == uval)
3837 return;
3838 tp->head.sval = sval;
3839 tp->head.wval = wval;
3840 tp->head.uval = uval;
3841
3842 /*
3843 * Disable extended Sreq/Sack filtering if per < 50.
3844 * Not supported on the C1010.
3845 */
3846 if (per < 50 && !(np->features & FE_C10))
3847 OUTOFFB (nc_stest2, EXT);
3848
3849 /*
3850 * set actual value and sync_status
3851 */
3852 OUTB (nc_sxfer, tp->head.sval);
3853 OUTB (nc_scntl3, tp->head.wval);
3854
3855 if (np->features & FE_C10) {
3856 OUTB (nc_scntl4, tp->head.uval);
3857 }
3858
3859 /*
3860 * patch ALL busy ccbs of this target.
3861 */
3862 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3863 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3864 if (cp->target != target)
3865 continue;
3866 cp->phys.select.sel_scntl3 = tp->head.wval;
3867 cp->phys.select.sel_sxfer = tp->head.sval;
3868 if (np->features & FE_C10) {
3869 cp->phys.select.sel_scntl4 = tp->head.uval;
3870 }
3871 }
3872}
3873
3874/*
3875 * log message for real hard errors
3876 *
3877 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc).
3878 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
3879 *
3880 * exception register:
3881 * ds: dstat
3882 * si: sist
3883 *
3884 * SCSI bus lines:
3885 * so: control lines as driven by chip.
3886 * si: control lines as seen by chip.
3887 * sd: scsi data lines as seen by chip.
3888 *
3889 * wide/fastmode:
3890 * sxfer: (see the manual)
3891 * scntl3: (see the manual)
3892 *
3893 * current script command:
3894 * dsp: script adress (relative to start of script).
3895 * dbc: first word of script command.
3896 *
3897 * First 24 register of the chip:
3898 * r0..rf
3899 */
3900static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat)
3901{
3902 u32 dsp;
3903 int script_ofs;
3904 int script_size;
3905 char *script_name;
3906 u_char *script_base;
3907 int i;
3908
3909 dsp = INL (nc_dsp);
3910
3911 if (dsp > np->scripta_ba &&
3912 dsp <= np->scripta_ba + np->scripta_sz) {
3913 script_ofs = dsp - np->scripta_ba;
3914 script_size = np->scripta_sz;
3915 script_base = (u_char *) np->scripta0;
3916 script_name = "scripta";
3917 }
3918 else if (np->scriptb_ba < dsp &&
3919 dsp <= np->scriptb_ba + np->scriptb_sz) {
3920 script_ofs = dsp - np->scriptb_ba;
3921 script_size = np->scriptb_sz;
3922 script_base = (u_char *) np->scriptb0;
3923 script_name = "scriptb";
3924 } else {
3925 script_ofs = dsp;
3926 script_size = 0;
3927 script_base = 0;
3928 script_name = "mem";
3929 }
3930
e3869ec7 3931 kprintf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
984263bc
MD
3932 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
3933 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl),
3934 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer),
3935 (unsigned)INB (nc_scntl3), script_name, script_ofs,
3936 (unsigned)INL (nc_dbc));
3937
3938 if (((script_ofs & 3) == 0) &&
3939 (unsigned)script_ofs < script_size) {
e3869ec7 3940 kprintf ("%s: script cmd = %08x\n", sym_name(np),
984263bc
MD
3941 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
3942 }
3943
e3869ec7 3944 kprintf ("%s: regdump:", sym_name(np));
984263bc 3945 for (i=0; i<24;i++)
e3869ec7
SW
3946 kprintf (" %02x", (unsigned)INB_OFF(i));
3947 kprintf (".\n");
984263bc
MD
3948
3949 /*
3950 * PCI BUS error, read the PCI ststus register.
3951 */
3952 if (dstat & (MDPE|BF)) {
3953 u_short pci_sts;
3954#ifdef FreeBSD_Bus_Io_Abstraction
3955 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2);
3956#else
3957 pci_sts = pci_cfgread(np->pci_tag, PCIR_STATUS, 2);
3958#endif
3959 if (pci_sts & 0xf900) {
3960#ifdef FreeBSD_Bus_Io_Abstraction
3961 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2);
3962#else
3963 pci_cfgwrite(np->pci_tag, PCIR_STATUS, pci_sts, 2);
3964#endif
e3869ec7