Rename printf -> kprintf in sys/ and add some defines where necessary
[dragonfly.git] / sys / dev / netif / rtw / rtw.c
CommitLineData
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1/*
2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $NetBSD: rtw.c,v 1.72 2006/03/28 00:48:10 dyoung Exp $
e3869ec7 35 * $DragonFly: src/sys/dev/netif/rtw/rtw.c,v 1.5 2006/12/22 23:26:21 swildner Exp $
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36 */
37
38/*
39 * Copyright (c) 2004, 2005 David Young. All rights reserved.
40 *
41 * Programmed for NetBSD by David Young.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. The name of David Young may not be used to endorse or promote
52 * products derived from this software without specific prior
53 * written permission.
54 *
55 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
57 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
58 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
59 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
60 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
61 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
63 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
66 * OF SUCH DAMAGE.
67 */
68
69/*
70 * Device driver for the Realtek RTL8180 802.11 MAC/BBP.
71 */
72
73#include <sys/param.h>
74#include <sys/bus.h>
75#include <sys/endian.h>
76#include <sys/kernel.h>
77#include <sys/rman.h>
78#include <sys/socket.h>
79#include <sys/sockio.h>
80#include <sys/serialize.h>
81#include <sys/sysctl.h>
82
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83#include <net/if.h>
84#include <net/if_arp.h>
85#include <net/if_dl.h>
86#include <net/if_media.h>
87#include <net/ifq_var.h>
88#include <net/ethernet.h>
89#include <net/bpf.h>
90
91#include <netproto/802_11/ieee80211_var.h>
92#include <netproto/802_11/ieee80211_radiotap.h>
93
94#include "rtwbitop.h"
95#include "rtwreg.h"
96#include "rtwvar.h"
97#include "rtwphyio.h"
98#include "rtwphy.h"
99#include "smc93cx6var.h"
100
101/* XXX */
102#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
103#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
104#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
105#define IEEE80211_DUR_DS_FAST_PLCPHDR 24
106#define IEEE80211_DUR_DS_SLOW_ACK 112
107#define IEEE80211_DUR_DS_SLOW_CTS 112
108#define IEEE80211_DUR_DS_SIFS 10
109
110struct rtw_txsegs {
111 int nseg;
112 bus_dma_segment_t segs[RTW_MAXPKTSEGS];
113};
114
115devclass_t rtw_devclass;
116
117static const struct ieee80211_rateset rtw_rates_11b = { 4, { 2, 4, 11, 22 } };
118
119SYSCTL_NODE(_hw, OID_AUTO, rtw, CTLFLAG_RD, 0,
120 "Realtek RTL818x 802.11 controls");
121
122/* [0, SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)] */
123static int rtw_rfprog_fallback = 0;
124SYSCTL_INT(_hw_rtw, OID_AUTO, rfprog_fallback, CTLFLAG_RW,
125 &rtw_rfprog_fallback, 0, "fallback RF programming method");
126
127static int rtw_host_rfio = 0; /* 0/1 */
128SYSCTL_INT(_hw_rtw, OID_AUTO, host_rfio, CTLFLAG_RW,
129 &rtw_host_rfio, 0, "enable host control of RF I/O");
130
131#ifdef RTW_DEBUG
132int rtw_debug = 0; /* [0, RTW_DEBUG_MAX] */
133SYSCTL_INT(_hw_rtw, OID_AUTO, debug, CTLFLAG_RW, &rtw_debug, 0, "debug level");
134
135static int rtw_rxbufs_limit = RTW_RXQLEN; /* [0, RTW_RXQLEN] */
136SYSCTL_INT(_hw_rtw, OID_AUTO, rxbufs_limit, CTLFLAG_RW, &rtw_rxbufs_limit, 0,
137 "rx buffers limit");
138#endif /* RTW_DEBUG */
139
140#if 0
141static int rtw_xmtr_restart = 0;
142SYSCTL_INT(_hw_rtw, OID_AUTO, xmtr_restart, CTLFLAG_RW, &rtw_xmtr_restart, 0,
143 "gratuitously reset xmtr on rcvr error");
144
145static int rtw_ring_reset = 0;
146SYSCTL_INT(_hw_rtw, OID_AUTO, ring_reset, CTLFLAG_RW, &rtw_ring_reset, 0,
147 "reset ring pointers on rcvr error");
148#endif
149
150static int rtw_do_chip_reset = 0;
151SYSCTL_INT(_hw_rtw, OID_AUTO, chip_reset, CTLFLAG_RW, &rtw_do_chip_reset, 0,
152 "gratuitously reset chip on rcvr error");
153
154int rtw_dwelltime = 200; /* milliseconds */
155
156/* XXX */
157static struct ieee80211_cipher rtw_cipher_wep;
158
159static void rtw_led_init(struct rtw_softc *);
160static void rtw_led_newstate(struct rtw_softc *, enum ieee80211_state);
161static void rtw_led_slowblink(void *);
162static void rtw_led_fastblink(void *);
163static void rtw_led_set(struct rtw_softc *);
164
165static void rtw_init(void *);
166static void rtw_start(struct ifnet *);
167static int rtw_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
168static void rtw_watchdog(struct ifnet *);
169static void rtw_intr(void *);
170
171static void rtw_intr_rx(struct rtw_softc *, uint16_t);
172static void rtw_intr_tx(struct rtw_softc *, uint16_t);
173static void rtw_intr_beacon(struct rtw_softc *, uint16_t);
174static void rtw_intr_atim(struct rtw_softc *);
175static void rtw_intr_ioerror(struct rtw_softc *, uint16_t);
176static void rtw_intr_timeout(struct rtw_softc *);
177
178static int rtw_dequeue(struct ifnet *, struct rtw_txsoft_blk **,
179 struct rtw_txdesc_blk **, struct mbuf **,
180 struct ieee80211_node **);
181static struct mbuf *rtw_load_txbuf(struct rtw_softc *, struct rtw_txsoft *,
182 struct rtw_txsegs *, int, struct mbuf *);
183
184static void rtw_idle(struct rtw_softc *);
185static void rtw_txring_fixup(struct rtw_softc *);
186static void rtw_rxring_fixup(struct rtw_softc *);
187static int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *);
188static void rtw_reset_oactive(struct rtw_softc *);
189
190static int rtw_enable(struct rtw_softc *);
191static void rtw_disable(struct rtw_softc *);
192static void rtw_io_enable(struct rtw_softc *, uint8_t, int);
193static int rtw_pwrstate(struct rtw_softc *, enum rtw_pwrstate);
194static void rtw_set_access(struct rtw_softc *, enum rtw_access);
195
196static void rtw_continuous_tx_enable(struct rtw_softc *, int);
197static void rtw_txdac_enable(struct rtw_softc *, int);
198static void rtw_anaparm_enable(struct rtw_regs *, int);
199static void rtw_config0123_enable(struct rtw_regs *, int);
200
201static void rtw_transmit_config(struct rtw_regs *);
202static void rtw_set_rfprog(struct rtw_softc *);
203static void rtw_enable_interrupts(struct rtw_softc *);
204static void rtw_pktfilt_load(struct rtw_softc *);
205static void rtw_wep_setkeys(struct rtw_softc *);
206static void rtw_resume_ticks(struct rtw_softc *);
207static void rtw_set_nettype(struct rtw_softc *, enum ieee80211_opmode);
208
209static int rtw_reset(struct rtw_softc *);
210static int rtw_chip_reset(struct rtw_softc *);
211static int rtw_recall_eeprom(struct rtw_softc *);
212static int rtw_srom_read(struct rtw_softc *);
213static int rtw_srom_parse(struct rtw_softc *);
214static struct rtw_rf *rtw_rf_attach(struct rtw_softc *, enum rtw_rfchipid, int);
215
216static uint8_t rtw_check_phydelay(struct rtw_regs *, uint32_t);
217static void rtw_identify_country(struct rtw_softc *);
218static int rtw_identify_sta(struct rtw_softc *);
219
220static int rtw_swring_setup(struct rtw_softc *);
221static void rtw_hwring_setup(struct rtw_softc *);
222
223static int rtw_desc_blk_alloc(struct rtw_softc *);
224static void rtw_desc_blk_free(struct rtw_softc *);
225static int rtw_soft_blk_alloc(struct rtw_softc *);
226static void rtw_soft_blk_free(struct rtw_softc *);
227
228static void rtw_txdesc_blk_init_all(struct rtw_softc *);
229static void rtw_txsoft_blk_init_all(struct rtw_softc *);
230static void rtw_rxdesc_blk_init_all(struct rtw_softc *);
231static int rtw_rxsoft_blk_init_all(struct rtw_softc *);
232
233static void rtw_txdesc_blk_reset_all(struct rtw_softc *);
234
235static int rtw_rxsoft_alloc(struct rtw_softc *, struct rtw_rxsoft *, int);
236static void rtw_rxdesc_init(struct rtw_softc *, int idx, int);
237
238#ifdef RTW_DEBUG
239static void rtw_print_txdesc(struct rtw_softc *, const char *,
240 struct rtw_txsoft *, struct rtw_txdesc_blk *,
241 int);
242#endif /* RTW_DEBUG */
243
244static int rtw_newstate(struct ieee80211com *, enum ieee80211_state, int);
245static void rtw_next_scan(void *);
246
247static int rtw_key_delete(struct ieee80211com *,
248 const struct ieee80211_key *);
249static int rtw_key_set(struct ieee80211com *,
250 const struct ieee80211_key *,
251 const u_int8_t[IEEE80211_ADDR_LEN]);
252static void rtw_key_update_end(struct ieee80211com *);
253static void rtw_key_update_begin(struct ieee80211com *);
254static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int);
255
256static int rtw_compute_duration1(int, int, uint32_t, int,
257 struct rtw_duration *);
258static int rtw_compute_duration(const struct ieee80211_frame_min *,
259 const struct ieee80211_key *, int,
260 uint32_t, int, int,
261 struct rtw_duration *,
262 struct rtw_duration *, int *, int);
263
264#ifdef RTW_DEBUG
265static void
266rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
267{
268#define PRINTREG32(sc, reg) \
269 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
270 ("%s: reg[ " #reg " / %03x ] = %08x\n", \
271 dvname, reg, RTW_READ(regs, reg)))
272
273#define PRINTREG16(sc, reg) \
274 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
275 ("%s: reg[ " #reg " / %03x ] = %04x\n", \
276 dvname, reg, RTW_READ16(regs, reg)))
277
278#define PRINTREG8(sc, reg) \
279 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
280 ("%s: reg[ " #reg " / %03x ] = %02x\n", \
281 dvname, reg, RTW_READ8(regs, reg)))
282
283 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where));
284
285 PRINTREG32(regs, RTW_IDR0);
286 PRINTREG32(regs, RTW_IDR1);
287 PRINTREG32(regs, RTW_MAR0);
288 PRINTREG32(regs, RTW_MAR1);
289 PRINTREG32(regs, RTW_TSFTRL);
290 PRINTREG32(regs, RTW_TSFTRH);
291 PRINTREG32(regs, RTW_TLPDA);
292 PRINTREG32(regs, RTW_TNPDA);
293 PRINTREG32(regs, RTW_THPDA);
294 PRINTREG32(regs, RTW_TCR);
295 PRINTREG32(regs, RTW_RCR);
296 PRINTREG32(regs, RTW_TINT);
297 PRINTREG32(regs, RTW_TBDA);
298 PRINTREG32(regs, RTW_ANAPARM);
299 PRINTREG32(regs, RTW_BB);
300 PRINTREG32(regs, RTW_PHYCFG);
301 PRINTREG32(regs, RTW_WAKEUP0L);
302 PRINTREG32(regs, RTW_WAKEUP0H);
303 PRINTREG32(regs, RTW_WAKEUP1L);
304 PRINTREG32(regs, RTW_WAKEUP1H);
305 PRINTREG32(regs, RTW_WAKEUP2LL);
306 PRINTREG32(regs, RTW_WAKEUP2LH);
307 PRINTREG32(regs, RTW_WAKEUP2HL);
308 PRINTREG32(regs, RTW_WAKEUP2HH);
309 PRINTREG32(regs, RTW_WAKEUP3LL);
310 PRINTREG32(regs, RTW_WAKEUP3LH);
311 PRINTREG32(regs, RTW_WAKEUP3HL);
312 PRINTREG32(regs, RTW_WAKEUP3HH);
313 PRINTREG32(regs, RTW_WAKEUP4LL);
314 PRINTREG32(regs, RTW_WAKEUP4LH);
315 PRINTREG32(regs, RTW_WAKEUP4HL);
316 PRINTREG32(regs, RTW_WAKEUP4HH);
317 PRINTREG32(regs, RTW_DK0);
318 PRINTREG32(regs, RTW_DK1);
319 PRINTREG32(regs, RTW_DK2);
320 PRINTREG32(regs, RTW_DK3);
321 PRINTREG32(regs, RTW_RETRYCTR);
322 PRINTREG32(regs, RTW_RDSAR);
323 PRINTREG32(regs, RTW_FER);
324 PRINTREG32(regs, RTW_FEMR);
325 PRINTREG32(regs, RTW_FPSR);
326 PRINTREG32(regs, RTW_FFER);
327
328 /* 16-bit registers */
329 PRINTREG16(regs, RTW_BRSR);
330 PRINTREG16(regs, RTW_IMR);
331 PRINTREG16(regs, RTW_ISR);
332 PRINTREG16(regs, RTW_BCNITV);
333 PRINTREG16(regs, RTW_ATIMWND);
334 PRINTREG16(regs, RTW_BINTRITV);
335 PRINTREG16(regs, RTW_ATIMTRITV);
336 PRINTREG16(regs, RTW_CRC16ERR);
337 PRINTREG16(regs, RTW_CRC0);
338 PRINTREG16(regs, RTW_CRC1);
339 PRINTREG16(regs, RTW_CRC2);
340 PRINTREG16(regs, RTW_CRC3);
341 PRINTREG16(regs, RTW_CRC4);
342 PRINTREG16(regs, RTW_CWR);
343
344 /* 8-bit registers */
345 PRINTREG8(regs, RTW_CR);
346 PRINTREG8(regs, RTW_9346CR);
347 PRINTREG8(regs, RTW_CONFIG0);
348 PRINTREG8(regs, RTW_CONFIG1);
349 PRINTREG8(regs, RTW_CONFIG2);
350 PRINTREG8(regs, RTW_MSR);
351 PRINTREG8(regs, RTW_CONFIG3);
352 PRINTREG8(regs, RTW_CONFIG4);
353 PRINTREG8(regs, RTW_TESTR);
354 PRINTREG8(regs, RTW_PSR);
355 PRINTREG8(regs, RTW_SCR);
356 PRINTREG8(regs, RTW_PHYDELAY);
357 PRINTREG8(regs, RTW_CRCOUNT);
358 PRINTREG8(regs, RTW_PHYADDR);
359 PRINTREG8(regs, RTW_PHYDATAW);
360 PRINTREG8(regs, RTW_PHYDATAR);
361 PRINTREG8(regs, RTW_CONFIG5);
362 PRINTREG8(regs, RTW_TPPOLL);
363
364 PRINTREG16(regs, RTW_BSSID16);
365 PRINTREG32(regs, RTW_BSSID32);
366#undef PRINTREG32
367#undef PRINTREG16
368#undef PRINTREG8
369}
370#endif /* RTW_DEBUG */
371
372static void
373rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
374{
375 struct rtw_regs *regs = &sc->sc_regs;
376 uint32_t tcr;
377
378 tcr = RTW_READ(regs, RTW_TCR);
379 tcr &= ~RTW_TCR_LBK_MASK;
380 if (enable)
381 tcr |= RTW_TCR_LBK_CONT;
382 else
383 tcr |= RTW_TCR_LBK_NORMAL;
384 RTW_WRITE(regs, RTW_TCR, tcr);
385 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
386 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
387 rtw_txdac_enable(sc, !enable);
388 rtw_set_access(sc, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
389 rtw_set_access(sc, RTW_ACCESS_NONE);
390}
391
392#ifdef RTW_DEBUG
393static const char *
394rtw_access_string(enum rtw_access access)
395{
396 switch (access) {
397 case RTW_ACCESS_NONE:
398 return "none";
399 case RTW_ACCESS_CONFIG:
400 return "config";
401 case RTW_ACCESS_ANAPARM:
402 return "anaparm";
403 default:
404 return "unknown";
405 }
406}
407#endif /* RTW_DEBUG */
408
409static void
410rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
411{
412 KKASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM);
413 KKASSERT(regs->r_access >= RTW_ACCESS_NONE &&
414 regs->r_access <= RTW_ACCESS_ANAPARM);
415
416 if (naccess == regs->r_access)
417 return;
418
419 switch (naccess) {
420 case RTW_ACCESS_NONE:
421 switch (regs->r_access) {
422 case RTW_ACCESS_ANAPARM:
423 rtw_anaparm_enable(regs, 0);
424 /*FALLTHROUGH*/
425 case RTW_ACCESS_CONFIG:
426 rtw_config0123_enable(regs, 0);
427 /*FALLTHROUGH*/
428 case RTW_ACCESS_NONE:
429 break;
430 }
431 break;
432 case RTW_ACCESS_CONFIG:
433 switch (regs->r_access) {
434 case RTW_ACCESS_NONE:
435 rtw_config0123_enable(regs, 1);
436 /*FALLTHROUGH*/
437 case RTW_ACCESS_CONFIG:
438 break;
439 case RTW_ACCESS_ANAPARM:
440 rtw_anaparm_enable(regs, 0);
441 break;
442 }
443 break;
444 case RTW_ACCESS_ANAPARM:
445 switch (regs->r_access) {
446 case RTW_ACCESS_NONE:
447 rtw_config0123_enable(regs, 1);
448 /*FALLTHROUGH*/
449 case RTW_ACCESS_CONFIG:
450 rtw_anaparm_enable(regs, 1);
451 /*FALLTHROUGH*/
452 case RTW_ACCESS_ANAPARM:
453 break;
454 }
455 break;
456 }
457}
458
459static void
460rtw_set_access(struct rtw_softc *sc, enum rtw_access access)
461{
462 struct rtw_regs *regs = &sc->sc_regs;
463
464 rtw_set_access1(regs, access);
465 RTW_DPRINTF(RTW_DEBUG_ACCESS,
466 ("%s: access %s -> %s\n", sc->sc_ic.ic_if.if_xname,
467 rtw_access_string(regs->r_access),
468 rtw_access_string(access)));
469 regs->r_access = access;
470}
471
472/*
473 * Enable registers, switch register banks.
474 */
475static void
476rtw_config0123_enable(struct rtw_regs *regs, int enable)
477{
478 uint8_t ecr;
479
480 ecr = RTW_READ8(regs, RTW_9346CR);
481 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);
482 if (enable) {
483 ecr |= RTW_9346CR_EEM_CONFIG;
484 } else {
485 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
486 ecr |= RTW_9346CR_EEM_NORMAL;
487 }
488 RTW_WRITE8(regs, RTW_9346CR, ecr);
489 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
490}
491
492/* requires rtw_config0123_enable(, 1) */
493static void
494rtw_anaparm_enable(struct rtw_regs *regs, int enable)
495{
496 uint8_t cfg3;
497
498 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
499 cfg3 |= RTW_CONFIG3_CLKRUNEN;
500 if (enable)
501 cfg3 |= RTW_CONFIG3_PARMEN;
502 else
503 cfg3 &= ~RTW_CONFIG3_PARMEN;
504 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
505 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
506}
507
508/* requires rtw_anaparm_enable(, 1) */
509static void
510rtw_txdac_enable(struct rtw_softc *sc, int enable)
511{
512 uint32_t anaparm;
513 struct rtw_regs *regs = &sc->sc_regs;
514
515 anaparm = RTW_READ(regs, RTW_ANAPARM);
516 if (enable)
517 anaparm &= ~RTW_ANAPARM_TXDACOFF;
518 else
519 anaparm |= RTW_ANAPARM_TXDACOFF;
520 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
521 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
522}
523
524static int
525rtw_chip_reset1(struct rtw_softc *sc)
526{
527 struct rtw_regs *regs = &sc->sc_regs;
528 uint8_t cr;
529 int i;
530
531 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
532
533 RTW_WBR(regs, RTW_CR, RTW_CR);
534
535 for (i = 0; i < 1000; i++) {
536 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
537 RTW_DPRINTF(RTW_DEBUG_RESET,
538 ("%s: reset in %dus\n",
539 sc->sc_ic.ic_if.if_xname, i));
540 return 0;
541 }
542 RTW_RBR(regs, RTW_CR, RTW_CR);
543 DELAY(10); /* 10us */
544 }
545
546 if_printf(&sc->sc_ic.ic_if, "reset failed\n");
547 return ETIMEDOUT;
548}
549
550static int
551rtw_chip_reset(struct rtw_softc *sc)
552{
553 struct rtw_regs *regs = &sc->sc_regs;
554 uint32_t tcr;
555
556 /* from Linux driver */
557 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 |
558 SHIFTIN(7, RTW_TCR_SRL_MASK) | SHIFTIN(7, RTW_TCR_LRL_MASK);
559
560 RTW_WRITE(regs, RTW_TCR, tcr);
561
562 RTW_WBW(regs, RTW_CR, RTW_TCR);
563
564 return rtw_chip_reset1(sc);
565}
566
567static int
568rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen)
569{
570 struct ieee80211_key keycopy;
571 const struct ieee80211_cipher *wep_cipher;
572
573 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__));
574
575 keycopy = *k;
576 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT;
577
578 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
579 KKASSERT(wep_cipher != NULL);
580
581 return wep_cipher->ic_decap(&keycopy, m, hdrlen);
582}
583
584static int
585rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
586{
587 struct rtw_softc *sc = ic->ic_ifp->if_softc;
588 u_int keyix = k->wk_keyix;
589
590 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix));
591
592 if (keyix >= IEEE80211_WEP_NKID)
593 return 0;
594 if (k->wk_keylen != 0)
595 sc->sc_flags &= ~RTW_F_DK_VALID;
596 return 1;
597}
598
599static int
600rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
601 const u_int8_t mac[IEEE80211_ADDR_LEN])
602{
603 struct rtw_softc *sc = ic->ic_ifp->if_softc;
604
605 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix));
606
607 if (k->wk_keyix >= IEEE80211_WEP_NKID)
608 return 0;
609
610 sc->sc_flags &= ~RTW_F_DK_VALID;
611 return 1;
612}
613
614static void
615rtw_key_update_begin(struct ieee80211com *ic)
616{
617#ifdef RTW_DEBUG
618 struct ifnet *ifp = ic->ic_ifp;
619 struct rtw_softc *sc = ifp->if_softc;
620#endif
621
622 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
623}
624
625static void
626rtw_key_update_end(struct ieee80211com *ic)
627{
628 struct ifnet *ifp = ic->ic_ifp;
629 struct rtw_softc *sc = ifp->if_softc;
630
631 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
632
633 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 ||
634 (sc->sc_flags & RTW_F_ENABLED) == 0 ||
635 (sc->sc_flags & RTW_F_INVALID) != 0)
636 return;
637
638 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
639 rtw_wep_setkeys(sc);
640 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE,
641 (ifp->if_flags & IFF_RUNNING) != 0);
642}
643
644static __inline int
645rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k)
646{
647 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
648 return 0;
649
650 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) ||
651 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13);
652}
653
654static void
655rtw_wep_setkeys(struct rtw_softc *sc)
656{
657 struct ieee80211com *ic = &sc->sc_ic;
658 struct ieee80211_key *wk = ic->ic_nw_keys;
659 const struct ieee80211_cipher *wep_cipher;
660 struct rtw_regs *regs = &sc->sc_regs;
661 union rtw_keys *rk = &sc->sc_keys;
662 uint8_t psr, scr;
663 int i, keylen;
664
665 memset(rk->rk_keys, 0, sizeof(rk->rk_keys));
666
667 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
668 KKASSERT(wep_cipher != NULL);
669
670 /* Temporarily use software crypto for all keys. */
671 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
672 if (wk[i].wk_cipher == &rtw_cipher_wep)
673 wk[i].wk_cipher = wep_cipher;
674 }
675
676 rtw_set_access(sc, RTW_ACCESS_CONFIG);
677
678 psr = RTW_READ8(regs, RTW_PSR);
679 scr = RTW_READ8(regs, RTW_SCR);
680 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON);
681
682 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
683 goto out;
684
685 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) {
686 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i]))
687 continue;
688 if (i == ic->ic_def_txkey) {
689 keylen = wk[i].wk_keylen;
690 break;
691 }
692 keylen = MAX(keylen, wk[i].wk_keylen);
693 }
694
695 if (keylen == 5)
696 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON;
697 else if (keylen == 13)
698 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON;
699
700 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
701 if (wk[i].wk_keylen != keylen ||
702 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
703 continue;
704 /* h/w will decrypt, s/w still strips headers */
705 wk[i].wk_cipher = &rtw_cipher_wep;
706 memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen);
707 }
708out:
709 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN);
710
711 bus_space_write_region_4(regs->r_bt, regs->r_bh, RTW_DK0, rk->rk_words,
712 sizeof(rk->rk_words) / sizeof(rk->rk_words[0]));
713
714 RTW_WBW(regs, RTW_DK0, RTW_PSR);
715 RTW_WRITE8(regs, RTW_PSR, psr);
716 RTW_WBW(regs, RTW_PSR, RTW_SCR);
717 RTW_WRITE8(regs, RTW_SCR, scr);
718 RTW_SYNC(regs, RTW_SCR, RTW_SCR);
719 rtw_set_access(sc, RTW_ACCESS_NONE);
720 sc->sc_flags |= RTW_F_DK_VALID;
721}
722
723static int
724rtw_recall_eeprom(struct rtw_softc *sc)
725{
726 struct rtw_regs *regs = &sc->sc_regs;
727 int i;
728 uint8_t ecr;
729
730 ecr = RTW_READ8(regs, RTW_9346CR);
731 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;
732 RTW_WRITE8(regs, RTW_9346CR, ecr);
733
734 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
735
736 /* wait 25ms for completion */
737 for (i = 0; i < 250; i++) {
738 ecr = RTW_READ8(regs, RTW_9346CR);
739 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {
740 RTW_DPRINTF(RTW_DEBUG_RESET,
741 ("%s: recall EEPROM in %dus\n",
742 sc->sc_ic.ic_if.if_xname, i * 100));
743 return 0;
744 }
745 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
746 DELAY(100);
747 }
748 if_printf(&sc->sc_ic.ic_if, "recall EEPROM failed\n");
749 return ETIMEDOUT;
750}
751
752static int
753rtw_reset(struct rtw_softc *sc)
754{
755 struct rtw_regs *regs = &sc->sc_regs;
756 uint8_t config1;
757 int rc;
758
759 sc->sc_flags &= ~RTW_F_DK_VALID;
760
761 rc = rtw_chip_reset(sc);
762 if (rc)
763 return rc;
764
765 rtw_recall_eeprom(sc); /* ignore err */
766
767 config1 = RTW_READ8(regs, RTW_CONFIG1);
768 RTW_WRITE8(regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN);
769 /* TBD turn off maximum power saving? */
770 return 0;
771}
772
773static int
774rtw_srom_parse(struct rtw_softc *sc)
775{
776 struct rtw_srom *sr = &sc->sc_srom;
777 char scratch[sizeof("unknown 0xXX")];
778 uint8_t mac[IEEE80211_ADDR_LEN];
779 const char *rfname, *paname;
780 uint16_t srom_version;
781 int i;
782
783 sc->sc_flags &= ~(RTW_F_DIGPHY | RTW_F_DFLANTB | RTW_F_ANTDIV);
784 sc->sc_rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
785
786 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION);
787 if_printf(&sc->sc_ic.ic_if, "SROM version %d.%d",
788 srom_version >> 8, srom_version & 0xff);
789
790 if (srom_version <= 0x0101) {
e3869ec7 791 kprintf(" is not understood, limping along with defaults\n");
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792
793 /* Default values */
794 sc->sc_flags |= (RTW_F_DIGPHY | RTW_F_ANTDIV);
795 sc->sc_csthr = RTW_SR_ENERGYDETTHR_DEFAULT;
796 sc->sc_rcr |= RTW_RCR_ENCS1;
797 sc->sc_rfchipid = RTW_RFCHIPID_PHILIPS;
798 return 0;
799 }
e3869ec7 800 kprintf("\n");
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801
802 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
803 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);
804
805 RTW_DPRINTF(RTW_DEBUG_ATTACH,
806 ("%s: EEPROM MAC %6D\n", sc->sc_ic.ic_if.if_xname, mac, ":"));
807
808 sc->sc_csthr = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);
809
810 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)
811 sc->sc_flags |= RTW_F_ANTDIV;
812
813 /*
814 * Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems
815 * to be reversed.
816 */
817 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)
818 sc->sc_flags |= RTW_F_DIGPHY;
819 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)
820 sc->sc_flags |= RTW_F_DFLANTB;
821
822 sc->sc_rcr |= SHIFTIN(SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
823 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);
824
825 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0)
826 sc->sc_flags |= RTW_C_RXWEP_104;
827
828 sc->sc_flags |= RTW_C_RXWEP_40; /* XXX */
829
830 sc->sc_rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);
831 switch (sc->sc_rfchipid) {
832 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */
833 rfname = "GCT GRF5101";
834 paname = "Winspring WS9901";
835 break;
836 case RTW_RFCHIPID_MAXIM:
837 rfname = "Maxim MAX2820"; /* guess */
838 paname = "Maxim MAX2422"; /* guess */
839 break;
840 case RTW_RFCHIPID_INTERSIL:
841 rfname = "Intersil HFA3873"; /* guess */
842 paname = "Intersil <unknown>";
843 break;
844 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */
845 rfname = "Philips SA2400A";
846 paname = "Philips SA2411";
847 break;
848 case RTW_RFCHIPID_RFMD:
849 /* this is the same front-end as an atw(4)! */
850 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */
851 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */
852 "SYN: Silicon Labs Si4126"; /* inferred from
853 * reference driver
854 */
855 paname = "RFMD RF2189"; /* mentioned in Realtek docs */
856 break;
857 case RTW_RFCHIPID_RESERVED:
858 rfname = paname = "reserved";
859 break;
860 default:
f8c7a42d 861 ksnprintf(scratch, sizeof(scratch), "unknown 0x%02x",
44db266b
SZ
862 sc->sc_rfchipid);
863 rfname = paname = scratch;
864 }
865 if_printf(&sc->sc_ic.ic_if, "RF: %s, PA: %s\n", rfname, paname);
866
867 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {
868 case RTW_CONFIG0_GL_USA:
869 case _RTW_CONFIG0_GL_USA:
870 sc->sc_locale = RTW_LOCALE_USA;
871 break;
872 case RTW_CONFIG0_GL_EUROPE:
873 sc->sc_locale = RTW_LOCALE_EUROPE;
874 break;
875 case RTW_CONFIG0_GL_JAPAN:
876 sc->sc_locale = RTW_LOCALE_JAPAN;
877 break;
878 default:
879 sc->sc_locale = RTW_LOCALE_UNKNOWN;
880 break;
881 }
882 return 0;
883}
884
885static int
886rtw_srom_read(struct rtw_softc *sc)
887{
888 struct rtw_regs *regs = &sc->sc_regs;
889 struct rtw_srom *sr = &sc->sc_srom;
890 struct seeprom_descriptor sd;
891 uint8_t ecr;
892 int rc;
893
894 memset(&sd, 0, sizeof(sd));
895
896 ecr = RTW_READ8(regs, RTW_9346CR);
897
898 if ((sc->sc_flags & RTW_F_9356SROM) != 0) {
899 RTW_DPRINTF(RTW_DEBUG_ATTACH,
900 ("%s: 93c56 SROM\n", sc->sc_ic.ic_if.if_xname));
901 sr->sr_size = 256;
902 sd.sd_chip = C56_66;
903 } else {
904 RTW_DPRINTF(RTW_DEBUG_ATTACH,
905 ("%s: 93c46 SROM\n", sc->sc_ic.ic_if.if_xname));
906 sr->sr_size = 128;
907 sd.sd_chip = C46;
908 }
909
910 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
911 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
912 ecr |= RTW_9346CR_EEM_PROGRAM;
913
914 RTW_WRITE8(regs, RTW_9346CR, ecr);
915
efda3bd0 916 sr->sr_content = kmalloc(sr->sr_size, M_DEVBUF, M_WAITOK | M_ZERO);
44db266b
SZ
917
918 /*
919 * RTL8180 has a single 8-bit register for controlling the
920 * 93cx6 SROM. There is no "ready" bit. The RTL8180
921 * input/output sense is the reverse of read_seeprom's.
922 */
923 sd.sd_tag = regs->r_bt;
924 sd.sd_bsh = regs->r_bh;
925 sd.sd_regsize = 1;
926 sd.sd_control_offset = RTW_9346CR;
927 sd.sd_status_offset = RTW_9346CR;
928 sd.sd_dataout_offset = RTW_9346CR;
929 sd.sd_CK = RTW_9346CR_EESK;
930 sd.sd_CS = RTW_9346CR_EECS;
931 sd.sd_DI = RTW_9346CR_EEDO;
932 sd.sd_DO = RTW_9346CR_EEDI;
933 /* make read_seeprom enter EEPROM read/write mode */
934 sd.sd_MS = ecr;
935 sd.sd_RDY = 0;
936
937 /* TBD bus barriers */
938 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size / 2)) {
939 if_printf(&sc->sc_ic.ic_if, "could not read SROM\n");
efda3bd0 940 kfree(sr->sr_content, M_DEVBUF);
44db266b
SZ
941 sr->sr_content = NULL;
942 return EIO; /* XXX */
943 }
944
945 /* end EEPROM read/write mode */
946 RTW_WRITE8(regs, RTW_9346CR,
947 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);
948 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
949
950 rc = rtw_recall_eeprom(sc);
951 if (rc)
952 return rc;
953
954#ifdef RTW_DEBUG
955 {
956 int i;
957 RTW_DPRINTF(RTW_DEBUG_ATTACH,
958 ("\n%s: serial ROM:\n\t", sc->sc_ic.ic_if.if_xname));
959 for (i = 0; i < sr->sr_size/2; i++) {
960 if (((i % 8) == 0) && (i != 0))
961 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t"));
962 RTW_DPRINTF(RTW_DEBUG_ATTACH,
963 (" %04x", sr->sr_content[i]));
964 }
965 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n"));
966 }
967#endif /* RTW_DEBUG */
968 return 0;
969}
970
971static void
972rtw_set_rfprog(struct rtw_softc *sc)
973{
974 struct rtw_regs *regs = &sc->sc_regs;
975 const char *method;
976 uint8_t cfg4;
977
978 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
979
980 switch (sc->sc_rfchipid) {
981 default:
982 cfg4 |= SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
983 method = "fallback";
984 break;
985 case RTW_RFCHIPID_INTERSIL:
986 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;
987 method = "Intersil";
988 break;
989 case RTW_RFCHIPID_PHILIPS:
990 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;
991 method = "Philips";
992 break;
993 case RTW_RFCHIPID_GCT: /* XXX a guess */
994 case RTW_RFCHIPID_RFMD:
995 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;
996 method = "RFMD";
997 break;
998 }
999
1000 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
1001
1002 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
1003
1004 RTW_DPRINTF(RTW_DEBUG_INIT,
1005 ("%s: %s RF programming method, %#02x\n",
1006 sc->sc_ic.ic_if.if_xname, method,
1007 RTW_READ8(regs, RTW_CONFIG4)));
1008}
1009
1010static __inline void
1011rtw_init_channels(struct rtw_softc *sc)
1012{
1013 const char *name = NULL;
1014 struct ieee80211_channel *chans = sc->sc_ic.ic_channels;
1015 int i;
1016#define ADD_CHANNEL(_chans, _chan) do { \
1017 _chans[_chan].ic_flags = IEEE80211_CHAN_B; \
1018 _chans[_chan].ic_freq = \
1019 ieee80211_ieee2mhz(_chan, _chans[_chan].ic_flags); \
1020} while (0)
1021
1022 switch (sc->sc_locale) {
1023 case RTW_LOCALE_USA: /* 1-11 */
1024 name = "USA";
1025 for (i = 1; i <= 11; i++)
1026 ADD_CHANNEL(chans, i);
1027 break;
1028 case RTW_LOCALE_JAPAN: /* 1-14 */
1029 name = "Japan";
1030 ADD_CHANNEL(chans, 14);
1031 for (i = 1; i <= 14; i++)
1032 ADD_CHANNEL(chans, i);
1033 break;
1034 case RTW_LOCALE_EUROPE: /* 1-13 */
1035 name = "Europe";
1036 for (i = 1; i <= 13; i++)
1037 ADD_CHANNEL(chans, i);
1038 break;
1039 default: /* 10-11 allowed by most countries */
1040 name = "<unknown>";
1041 for (i = 10; i <= 11; i++)
1042 ADD_CHANNEL(chans, i);
1043 break;
1044 }
1045 if_printf(&sc->sc_ic.ic_if, "Geographic Location %s\n", name);
1046#undef ADD_CHANNEL
1047}
1048
1049
1050static void
1051rtw_identify_country(struct rtw_softc *sc)
1052{
1053 uint8_t cfg0;
1054
1055 cfg0 = RTW_READ8(&sc->sc_regs, RTW_CONFIG0);
1056 switch (cfg0 & RTW_CONFIG0_GL_MASK) {
1057 case RTW_CONFIG0_GL_USA:
1058 case _RTW_CONFIG0_GL_USA:
1059 sc->sc_locale = RTW_LOCALE_USA;
1060 break;
1061 case RTW_CONFIG0_GL_JAPAN:
1062 sc->sc_locale = RTW_LOCALE_JAPAN;
1063 break;
1064 case RTW_CONFIG0_GL_EUROPE:
1065 sc->sc_locale = RTW_LOCALE_EUROPE;
1066 break;
1067 default:
1068 sc->sc_locale = RTW_LOCALE_UNKNOWN;
1069 break;
1070 }
1071}
1072
1073static int
1074rtw_identify_sta(struct rtw_softc *sc)
1075{
1076 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
1077 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1078 };
1079 struct rtw_regs *regs = &sc->sc_regs;
1080 uint8_t *addr = sc->sc_ic.ic_myaddr;
1081 uint32_t idr0, idr1;
1082
1083 idr0 = RTW_READ(regs, RTW_IDR0);
1084 idr1 = RTW_READ(regs, RTW_IDR1);
1085
1086 addr[0] = SHIFTOUT(idr0, __BITS(0, 7));
1087 addr[1] = SHIFTOUT(idr0, __BITS(8, 15));
1088 addr[2] = SHIFTOUT(idr0, __BITS(16, 23));
1089 addr[3] = SHIFTOUT(idr0, __BITS(24 ,31));
1090
1091 addr[4] = SHIFTOUT(idr1, __BITS(0, 7));
1092 addr[5] = SHIFTOUT(idr1, __BITS(8, 15));
1093
1094 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) {
1095 if_printf(&sc->sc_ic.ic_if, "could not get mac address\n");
1096 return ENXIO;
1097 }
1098 return 0;
1099}
1100
1101static uint8_t
1102rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,
1103 struct ieee80211_channel *chan)
1104{
1105 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;
1106
1107 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14,
1108 ("%s: channel %d out of range", __func__,
1109 idx - RTW_SR_TXPOWER1 + 1));
1110 return RTW_SR_GET(sr, idx);
1111}
1112
1113static void
1114rtw_txdesc_blk_init_all(struct rtw_softc *sc)
1115{
1116 /* nfree: the number of free descriptors in each ring.
1117 * The beacon ring is a special case: I do not let the
1118 * driver use all of the descriptors on the beacon ring.
1119 * The reasons are two-fold:
1120 *
1121 * (1) A BEACON descriptor's OWN bit is (apparently) not
1122 * updated, so the driver cannot easily know if the descriptor
1123 * belongs to it, or if it is racing the NIC. If the NIC
1124 * does not OWN every descriptor, then the driver can safely
1125 * update the descriptors when RTW_TBDA points at tdb_next.
1126 *
1127 * (2) I hope that the NIC will process more than one BEACON
1128 * descriptor in a single beacon interval, since that will
1129 * enable multiple-BSS support. Since the NIC does not
1130 * clear the OWN bit, there is no natural place for it to
1131 * stop processing BEACON desciptors. Maybe it will *not*
1132 * stop processing them! I do not want to chance the NIC
1133 * looping around and around a saturated beacon ring, so
1134 * I will leave one descriptor unOWNed at all times.
1135 */
1136 int nfree[RTW_NTXPRI] = {
1137 RTW_NTXDESCLO,
1138 RTW_NTXDESCMD,
1139 RTW_NTXDESCHI,
1140 RTW_NTXDESCBCN - 1
1141 };
1142 struct rtw_txdesc_blk *tdb;
1143 int pri;
1144
1145 for (tdb = sc->sc_txdesc_blk, pri = 0; pri < RTW_NTXPRI; tdb++, pri++) {
1146 tdb->tdb_nfree = nfree[pri];
1147 tdb->tdb_next = 0;
1148
1149 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1150 BUS_DMASYNC_PREWRITE);
1151 }
1152}
1153
1154static void
1155rtw_txsoft_blk_init_all(struct rtw_softc *sc)
1156{
1157 struct rtw_txsoft_blk *tsb;
1158 int pri;
1159
1160 for (tsb = sc->sc_txsoft_blk, pri = 0; pri < RTW_NTXPRI; tsb++, pri++) {
1161 int i;
1162
1163 STAILQ_INIT(&tsb->tsb_dirtyq);
1164 STAILQ_INIT(&tsb->tsb_freeq);
1165 for (i = 0; i < tsb->tsb_ndesc; i++) {
1166 struct rtw_txsoft *ts;
1167
1168 ts = &tsb->tsb_desc[i];
1169 ts->ts_mbuf = NULL;
1170 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1171 }
1172 tsb->tsb_tx_timer = 0;
1173 }
1174}
1175
1176static void
1177rtw_rxbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
1178 bus_size_t mapsize, int error)
1179{
1180 if (error)
1181 return;
1182
1183 KASSERT(nseg == 1, ("too many rx mbuf seg\n"));
1184
1185 *((bus_addr_t *)arg) = seg->ds_addr;
1186}
1187
1188static int
1189rtw_rxsoft_alloc(struct rtw_softc *sc, struct rtw_rxsoft *rs, int waitok)
1190{
1191 bus_addr_t paddr;
1192 bus_dmamap_t map;
1193 struct mbuf *m;
1194 int rc;
1195
1196 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1197 if (m == NULL)
1198 return ENOBUFS;
1199
1200 m->m_pkthdr.len = m->m_len = MCLBYTES;
1201
1202 rc = bus_dmamap_load_mbuf(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap, m,
1203 rtw_rxbuf_dma_map, &paddr,
1204 waitok ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1205 if (rc) {
1206 if_printf(&sc->sc_ic.ic_if, "can't load rx mbuf\n");
1207 m_freem(m);
1208 return rc;
1209 }
1210
1211 if (rs->rs_mbuf != NULL)
1212 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
1213
1214 /* Swap DMA map */
1215 map = rs->rs_dmamap;
1216 rs->rs_dmamap = sc->sc_rxsoft_dmamap;
1217 sc->sc_rxsoft_dmamap = map;
1218
1219 rs->rs_mbuf = m;
1220 rs->rs_phyaddr = paddr;
1221
1222 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap, BUS_DMASYNC_PREREAD);
1223 return 0;
1224}
1225
1226static int
1227rtw_rxsoft_blk_init_all(struct rtw_softc *sc)
1228{
1229 int i, rc = 0;
1230
1231 for (i = 0; i < RTW_RXQLEN; i++) {
1232 struct rtw_rxsoft *rs;
1233
1234 rs = &sc->sc_rxsoft[i];
1235 /* we're in rtw_init, so there should be no mbufs allocated */
1236 KKASSERT(rs->rs_mbuf == NULL);
1237#ifdef RTW_DEBUG
1238 if (i == rtw_rxbufs_limit) {
1239 if_printf(&sc->sc_ic.ic_if,
1240 "TEST hit %d-buffer limit\n", i);
1241 rc = ENOBUFS;
1242 break;
1243 }
1244#endif /* RTW_DEBUG */
1245 rc = rtw_rxsoft_alloc(sc, rs, 1);
1246 if (rc)
1247 break;
1248 }
1249 return rc;
1250}
1251
1252static void
1253rtw_rxdesc_init(struct rtw_softc *sc, int idx, int kick)
1254{
1255 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1256 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx];
1257 struct rtw_rxsoft *rs = &sc->sc_rxsoft[idx];
1258 uint32_t ctl;
1259
1260#ifdef RTW_DEBUG
1261 uint32_t octl, obuf;
1262
1263 obuf = rd->rd_buf;
1264 octl = rd->rd_ctl;
1265#endif /* RTW_DEBUG */
1266
1267 rd->rd_buf = htole32(rs->rs_phyaddr);
1268
1269 ctl = SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
1270 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS;
1271
1272 if (idx == rdb->rdb_ndesc - 1)
1273 ctl |= RTW_RXCTL_EOR;
1274
1275 rd->rd_ctl = htole32(ctl);
1276
1277 RTW_DPRINTF(kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK)
1278 : RTW_DEBUG_RECV_DESC,
1279 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n",
1280 sc->sc_ic.ic_if.if_xname, rd, le32toh(obuf),
1281 le32toh(rd->rd_buf), le32toh(octl), le32toh(rd->rd_ctl)));
1282}
1283
1284static void
1285rtw_rxdesc_blk_init_all(struct rtw_softc *sc)
1286{
1287 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1288 int i;
1289
1290 for (i = 0; i < rdb->rdb_ndesc; i++)
1291 rtw_rxdesc_init(sc, i, 1);
1292
1293 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_PREWRITE);
1294}
1295
1296static void
1297rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable)
1298{
1299 struct rtw_regs *regs = &sc->sc_regs;
1300 uint8_t cr;
1301
1302 RTW_DPRINTF(RTW_DEBUG_IOSTATE,
1303 ("%s: %s 0x%02x\n", sc->sc_ic.ic_if.if_xname,
1304 enable ? "enable" : "disable", flags));
1305
1306 cr = RTW_READ8(regs, RTW_CR);
1307
1308 /* XXX reference source does not enable MULRW */
1309#if 0
1310 /* enable PCI Read/Write Multiple */
1311 cr |= RTW_CR_MULRW;
1312#endif
1313
1314 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
1315 if (enable)
1316 cr |= flags;
1317 else
1318 cr &= ~flags;
1319 RTW_WRITE8(regs, RTW_CR, cr);
1320 RTW_SYNC(regs, RTW_CR, RTW_CR);
1321}
1322
1323static void
1324rtw_intr_rx(struct rtw_softc *sc, uint16_t isr)
1325{
1326#define IS_BEACON(__fc0) \
1327 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\
1328 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON))
1329
1330 /*
1331 * convert rates:
1332 * hardware -> net80211
1333 */
1334 static const int ratetbl[4] = { 2, 4, 11, 22 };
1335 struct ifnet *ifp = &sc->sc_if;
1336 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1337 int next, nproc = 0, sync = 0;
1338
1339 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1340
1341 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_POSTREAD);
1342
1343 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) {
1344 struct ieee80211_node *ni;
1345 struct ieee80211_frame_min *wh;
1346 struct rtw_rxdesc *rd;
1347 struct rtw_rxsoft *rs;
1348 struct mbuf *m;
1349 int hwrate, len, rate, rssi, sq, error;
1350 uint32_t hrssi, hstat, htsfth, htsftl;
1351
1352 rd = &rdb->rdb_desc[next];
1353 rs = &sc->sc_rxsoft[next];
1354
1355 hstat = le32toh(rd->rd_stat);
1356 hrssi = le32toh(rd->rd_rssi);
1357 htsfth = le32toh(rd->rd_tsfth);
1358 htsftl = le32toh(rd->rd_tsftl);
1359
1360 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1361 ("%s: rxdesc[%d] hstat %08x hrssi %08x "
1362 "htsft %08x%08x\n", ifp->if_xname,
1363 next, hstat, hrssi, htsfth, htsftl));
1364
1365 ++nproc;
1366
1367 /* still belongs to NIC */
1368 if (hstat & RTW_RXSTAT_OWN) {
1369 if (nproc > 1)
1370 break;
1371
1372 /* sometimes the NIC skips to the 0th descriptor */
1373 rd = &rdb->rdb_desc[0];
1374 if (rd->rd_stat & htole32(RTW_RXSTAT_OWN))
1375 break;
1376 RTW_DPRINTF(RTW_DEBUG_BUGS,
1377 ("%s: NIC skipped from rxdesc[%u] "
1378 "to rxdesc[0]\n", ifp->if_xname, next));
1379 next = rdb->rdb_ndesc - 1;
1380 continue;
1381 }
1382
1383#ifdef RTW_DEBUG
1384#define PRINTSTAT(flag) do { \
1385 if ((hstat & flag) != 0) { \
e3869ec7 1386 kprintf("%s" #flag, delim); \
44db266b
SZ
1387 delim = ","; \
1388 } \
1389} while (0)
1390 if (rtw_debug & RTW_DEBUG_RECV_DESC) {
1391 const char *delim = "<";
1392
1393 if_printf(ifp, "%s", "");
1394 if ((hstat & RTW_RXSTAT_DEBUG) != 0) {
e3869ec7 1395 kprintf("status %08x", hstat);
44db266b
SZ
1396 PRINTSTAT(RTW_RXSTAT_SPLCP);
1397 PRINTSTAT(RTW_RXSTAT_MAR);
1398 PRINTSTAT(RTW_RXSTAT_PAR);
1399 PRINTSTAT(RTW_RXSTAT_BAR);
1400 PRINTSTAT(RTW_RXSTAT_PWRMGT);
1401 PRINTSTAT(RTW_RXSTAT_CRC32);
1402 PRINTSTAT(RTW_RXSTAT_ICV);
e3869ec7 1403 kprintf(">, ");
44db266b
SZ
1404 }
1405 }
1406#endif /* RTW_DEBUG */
1407
1408 if (hstat & RTW_RXSTAT_IOERROR) {
1409 if_printf(ifp, "DMA error/FIFO overflow %08x, "
1410 "rx descriptor %d\n",
1411 hstat & RTW_RXSTAT_IOERROR, next);
1412 ifp->if_ierrors++;
1413 goto next;
1414 }
1415
1416 len = SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);
1417 if (len < IEEE80211_MIN_LEN) {
1418 sc->sc_ic.ic_stats.is_rx_tooshort++;
1419 goto next;
1420 }
1421
1422 /* CRC is included with the packet; trim it off. */
1423 len -= IEEE80211_CRC_LEN;
1424
1425 hwrate = SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);
1426 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) {
1427 if_printf(ifp, "unknown rate #%d\n",
1428 SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));
1429 ifp->if_ierrors++;
1430 goto next;
1431 }
1432 rate = ratetbl[hwrate];
1433
1434#ifdef RTW_DEBUG
1435 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1436 ("%s rate %d.%d Mb/s, time %08x%08x\n",
1437 ifp->if_xname, (rate * 5) / 10,
1438 (rate * 5) % 10, htsfth, htsftl));
1439#endif /* RTW_DEBUG */
1440
1441 if ((hstat & RTW_RXSTAT_RES) &&
1442 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
1443 goto next;
1444
1445 /* if bad flags, skip descriptor */
1446 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) {
1447 if_printf(ifp, "too many rx segments\n");
1448 goto next;
1449 }
1450
1451 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
1452 BUS_DMASYNC_POSTREAD);
1453
1454 m = rs->rs_mbuf;
1455
1456 /* if temporarily out of memory, re-use mbuf */
1457 error = rtw_rxsoft_alloc(sc, rs, 0);
1458 if (error) {
1459 if_printf(ifp, "%s: rtw_rxsoft_alloc(, %d) failed, "
1460 "dropping packet\n", ifp->if_xname, next);
1461 goto next;
1462 }
1463
1464 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) {
1465 rssi = SHIFTOUT(hrssi, RTW_RXRSSI_RSSI);
1466 } else {
1467 rssi = SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI);
1468 /* TBD find out each front-end's LNA gain in the
1469 * front-end's units
1470 */
1471 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0)
1472 rssi |= 0x80;
1473 }
1474 sq = SHIFTOUT(hrssi, RTW_RXRSSI_SQ);
1475
1476 /*
1477 * Note well: now we cannot recycle the rs_mbuf unless
1478 * we restore its original length.
1479 */
1480 m->m_pkthdr.rcvif = ifp;
1481 m->m_pkthdr.len = m->m_len = len;
1482
1483 wh = mtod(m, struct ieee80211_frame_min *);
1484
1485 if (!IS_BEACON(wh->i_fc[0]))
1486 sc->sc_led_state.ls_event |= RTW_LED_S_RX;
1487
1488 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */
1489 ni = ieee80211_find_rxnode(&sc->sc_ic, wh);
1490
1491 sc->sc_tsfth = htsfth;
1492
1493#ifdef RTW_DEBUG
1494 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
1495 (IFF_DEBUG | IFF_LINK2)) {
1496 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len,
1497 rate, rssi);
1498 }
1499#endif /* RTW_DEBUG */
1500
1501 if (sc->sc_radiobpf != NULL) {
1502 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
1503
1504 rr->rr_tsft =
1505 htole64(((uint64_t)htsfth << 32) | htsftl);
1506
1507 if ((hstat & RTW_RXSTAT_SPLCP) != 0)
1508 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE;
1509
1510 rr->rr_flags = 0;
1511 rr->rr_rate = rate;
1512 rr->rr_antsignal = rssi;
1513 rr->rr_barker_lock = htole16(sq);
1514
1515 bpf_ptap(sc->sc_radiobpf, m, rr, sizeof(sc->sc_rxtapu));
1516 }
1517
1518 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl);
1519 ieee80211_free_node(ni);
1520next:
1521 rtw_rxdesc_init(sc, next, 0);
1522 sync = 1;
1523 }
1524
1525 if (sync) {
1526 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1527 BUS_DMASYNC_PREWRITE);
1528 }
1529
1530 rdb->rdb_next = next;
1531 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1532#undef IS_BEACON
1533}
1534
1535static __inline void
1536rtw_txsoft_release(bus_dma_tag_t dmat, struct rtw_txsoft *ts,
1537 int data_retry, int rts_retry, int error, int ratectl)
1538{
1539 struct mbuf *m;
1540 struct ieee80211_node *ni;
1541
1542 if (!ts->ts_ratectl)
1543 ratectl = 0;
1544
1545 m = ts->ts_mbuf;
1546 ni = ts->ts_ni;
1547 KKASSERT(m != NULL);
1548 KKASSERT(ni != NULL);
1549 ts->ts_mbuf = NULL;
1550 ts->ts_ni = NULL;
1551
1552 if (ratectl) {
1553 struct ieee80211_ratectl_res rc_res;
1554
1555 rc_res.rc_res_rateidx = ts->ts_rateidx;
1556 rc_res.rc_res_tries = data_retry + rts_retry + 1;
1557
1558 ieee80211_ratectl_tx_complete(ni, m->m_pkthdr.len,
1559 &rc_res, 1,
1560 data_retry, rts_retry,
1561 error);
1562 }
1563
1564 bus_dmamap_sync(dmat, ts->ts_dmamap, BUS_DMASYNC_POSTWRITE);
1565 bus_dmamap_unload(dmat, ts->ts_dmamap);
1566 m_freem(m);
1567 ieee80211_free_node(ni);
1568}
1569
1570static __inline void
1571rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb,
1572 struct rtw_txsoft *ts, int ndesc)
1573{
1574 uint32_t hstat;
1575 int data_retry, rts_retry, error;
1576 struct rtw_txdesc *tdn;
1577 const char *condstring;
1578 struct ifnet *ifp = &sc->sc_if;
1579
1580 tdb->tdb_nfree += ndesc;
1581
1582 tdn = &tdb->tdb_desc[ts->ts_last];
1583
1584 hstat = le32toh(tdn->td_stat);
1585 rts_retry = SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);
1586 data_retry = SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);
1587
1588 ifp->if_collisions += rts_retry + data_retry;
1589
1590 if ((hstat & RTW_TXSTAT_TOK) != 0) {
1591 condstring = "ok";
1592 error = 0;
1593 } else {
1594 ifp->if_oerrors++;
1595 condstring = "error";
1596 error = 1;
1597 }
1598
1599 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, data_retry, rts_retry,
1600 error, 1);
1601
1602 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
1603 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n",
1604 ifp->if_xname, ts, ts->ts_first, ts->ts_last,
1605 condstring, rts_retry, data_retry));
1606}
1607
1608static void
1609rtw_reset_oactive(struct rtw_softc *sc)
1610{
1611 int pri;
1612#ifdef RTW_DEBUG
1613 short oflags = sc->sc_if.if_flags;
1614#endif
1615
1616 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1617 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
1618 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1619
1620 if (!STAILQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0)
1621 sc->sc_if.if_flags &= ~IFF_OACTIVE;
1622 }
1623
1624#ifdef RTW_DEBUG
1625 if (oflags != sc->sc_if.if_flags) {
1626 DPRINTF(sc, RTW_DEBUG_OACTIVE,
1627 ("%s: reset OACTIVE\n", sc->sc_ic.ic_if.if_xname));
1628 }
1629#endif
1630}
1631
1632/* Collect transmitted packets. */
1633static __inline void
1634rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb,
1635 struct rtw_txdesc_blk *tdb, int force)
1636{
1637 struct rtw_txsoft *ts;
1638 int ndesc;
1639
1640 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1641 ndesc = 1 + ts->ts_last - ts->ts_first;
1642 if (ts->ts_last < ts->ts_first)
1643 ndesc += tdb->tdb_ndesc;
1644
1645 KKASSERT(ndesc > 0);
1646
1647 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1648 BUS_DMASYNC_POSTREAD);
1649
1650 if (force) {
1651 int i;
1652
1653 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) {
1654 tdb->tdb_desc[i].td_stat &=
1655 ~htole32(RTW_TXSTAT_OWN);
1656 if (i == ts->ts_last)
1657 break;
1658 }
1659 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1660 BUS_DMASYNC_PREWRITE);
1661 } else if ((tdb->tdb_desc[ts->ts_last].td_stat &
1662 htole32(RTW_TXSTAT_OWN)) != 0) {
1663 break;
1664 }
1665
1666 rtw_collect_txpkt(sc, tdb, ts, ndesc);
1667 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1668 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1669 }
1670 /* no more pending transmissions, cancel watchdog */
1671 if (ts == NULL)
1672 tsb->tsb_tx_timer = 0;
1673 rtw_reset_oactive(sc);
1674}
1675
1676static void
1677rtw_intr_tx(struct rtw_softc *sc, uint16_t isr)
1678{
1679 int pri;
1680
1681 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1682 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1683 &sc->sc_txdesc_blk[pri], 0);
1684 }
1685 if (isr)
1686 rtw_start(&sc->sc_ic.ic_if);
1687}
1688
1689static __inline struct mbuf *
1690rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni)
1691{
1692 struct ieee80211com *ic = &sc->sc_ic;
1693 struct ieee80211_beacon_offsets boff;
1694 struct mbuf *m;
1695
1696 m = ieee80211_beacon_alloc(ic, ni, &boff);
1697 if (m != NULL) {
1698 RTW_DPRINTF(RTW_DEBUG_BEACON,
1699 ("%s: m %p len %u\n", ic->ic_if.if_xname, m,
1700 m->m_len));
1701 }
1702 return m;
1703}
1704
1705static void
1706rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr)
1707{
1708 struct ieee80211com *ic = &sc->sc_ic;
1709 struct rtw_regs *regs = &sc->sc_regs;
1710 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN];
1711 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN];
1712
1713#ifdef RTW_DEBUG
1714 uint32_t tsfth, tsftl;
1715
1716 tsfth = RTW_READ(regs, RTW_TSFTRH);
1717 tsftl = RTW_READ(regs, RTW_TSFTRL);
1718#endif
1719
1720 if (isr & (RTW_INTR_TBDOK | RTW_INTR_TBDER)) {
1721#ifdef RTW_DEBUG
1722 int next = rtw_txring_next(regs, tdb);
1723#endif
1724
1725 RTW_DPRINTF(RTW_DEBUG_BEACON,
1726 ("%s: beacon ring %sprocessed, "
1727 "isr = %#04x, next %d expected %d, %llu\n",
1728 ic->ic_if.if_xname,
1729 (next == tdb->tdb_next) ? "" : "un",
1730 isr, next, tdb->tdb_next,
1731 (uint64_t)tsfth << 32 | tsftl));
1732
1733 if ((RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){
1734 rtw_collect_txring(sc, tsb, tdb, 1);
1735 tdb->tdb_next = 0;
1736 }
1737 }
1738 /* Start beacon transmission. */
1739
1740 if ((isr & RTW_INTR_BCNINT) && ic->ic_state == IEEE80211_S_RUN &&
1741 STAILQ_EMPTY(&tsb->tsb_dirtyq)) {
1742 struct mbuf *m;
1743
1744 RTW_DPRINTF(RTW_DEBUG_BEACON,
1745 ("%s: beacon prep. time, isr = %#04x, %llu\n",
1746 ic->ic_if.if_xname, isr,
1747 (uint64_t)tsfth << 32 | tsftl));
1748
1749 m = rtw_beacon_alloc(sc, ic->ic_bss);
1750 if (m == NULL) {
1751 if_printf(&ic->ic_if, "could not allocate beacon\n");
1752 return;
1753 }
1754
1755 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss);
1756
1757 IF_ENQUEUE(&sc->sc_beaconq, m);
1758
1759 rtw_start(&ic->ic_if);
1760 }
1761}
1762
1763static void
1764rtw_intr_atim(struct rtw_softc *sc)
1765{
1766 /* TBD */
1767 return;
1768}
1769
1770#ifdef RTW_DEBUG
1771static void
1772rtw_dump_rings(struct rtw_softc *sc)
1773{
1774 struct rtw_rxdesc_blk *rdb;
1775 int desc, pri;
1776
1777 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0)
1778 return;
1779
1780 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1781 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1782
1783 if_printf(&sc->sc_ic.ic_if, "txpri %d ndesc %d nfree %d\n",
1784 pri, tdb->tdb_ndesc, tdb->tdb_nfree);
1785 for (desc = 0; desc < tdb->tdb_ndesc; desc++)
1786 rtw_print_txdesc(sc, ".", NULL, tdb, desc);
1787 }
1788
1789 rdb = &sc->sc_rxdesc_blk;
1790
1791 for (desc = 0; desc < RTW_RXQLEN; desc++) {
1792 struct rtw_rxdesc *rd = &rdb->rdb_desc[desc];
1793
1794 if_printf(&sc->sc_ic.ic_if,
1795 "%sctl %08x rsvd0/rssi %08x buf/tsftl %08x "
1796 "rsvd1/tsfth %08x\n",
1797 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "",
1798 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi),
1799 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth));
1800 }
1801}
1802#endif /* RTW_DEBUG */
1803
1804static void
1805rtw_hwring_setup(struct rtw_softc *sc)
1806{
1807 struct rtw_regs *regs = &sc->sc_regs;
1808 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1809 int pri;
1810
1811 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1812 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1813
1814 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
1815 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC,
1816 ("%s: reg[tdb->tdb_basereg] <- %u\n",
1817 sc->sc_ic.ic_if.if_xname, tdb->tdb_base));
1818 }
1819
1820 RTW_WRITE(regs, RTW_RDSAR, rdb->rdb_base);
1821 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1822 ("%s: reg[RDSAR] <- %u\n", sc->sc_ic.ic_if.if_xname,
1823 rdb->rdb_base));
1824
1825 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
1826}
1827
1828static int
1829rtw_swring_setup(struct rtw_softc *sc)
1830{
1831 int rc;
1832
1833 rtw_txdesc_blk_init_all(sc);
1834 rtw_txsoft_blk_init_all(sc);
1835
1836 rc = rtw_rxsoft_blk_init_all(sc);
1837 if (rc) {
1838 if_printf(&sc->sc_ic.ic_if, "could not allocate rx buffers\n");
1839 return rc;
1840 }
1841
1842 rtw_rxdesc_blk_init_all(sc);
1843 sc->sc_rxdesc_blk.rdb_next = 0;
1844 return 0;
1845}
1846
1847static int
1848rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
1849{
1850 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
1851 sizeof(struct rtw_txdesc);
1852}
1853
1854static void
1855rtw_txring_fixup(struct rtw_softc *sc)
1856{
1857 struct rtw_regs *regs = &sc->sc_regs;
1858 int pri;
1859
1860 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1861 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1862 int next;
1863
1864 next = rtw_txring_next(regs, tdb);
1865 if (tdb->tdb_next == next)
1866 continue;
1867 if_printf(&sc->sc_ic.ic_if,
1868 "tx-ring %d expected next %d, read %d\n",
1869 pri, tdb->tdb_next, next);
1870 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1);
1871 }
1872}
1873
1874static void
1875rtw_rxring_fixup(struct rtw_softc *sc)
1876{
1877 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1878 uint32_t rdsar;
1879 int next;
1880
1881 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR));
1882 next = (rdsar - rdb->rdb_base) / sizeof(struct rtw_rxdesc);
1883
1884 if (rdb->rdb_next != next) {
1885 if_printf(&sc->sc_ic.ic_if,
1886 "rx-ring expected next %d, read %d\n",
1887 rdb->rdb_next, next);
1888 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1);
1889 }
1890}
1891
1892static void
1893rtw_txdesc_blk_reset_all(struct rtw_softc *sc)
1894{
1895 int pri;
1896
1897 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1898 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1899 &sc->sc_txdesc_blk[pri], 1);
1900 }
1901}
1902
1903static void
1904rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr)
1905{
1906 struct rtw_regs *regs = &sc->sc_regs;
1907 int xmtr = 0, rcvr = 0;
1908 uint8_t cr = 0;
1909
1910 if (isr & RTW_INTR_TXFOVW) {
1911 if_printf(&sc->sc_ic.ic_if, "tx fifo underflow\n");
1912 rcvr = xmtr = 1;
1913 cr |= RTW_CR_TE | RTW_CR_RE;
1914 }
1915
1916 if (isr & (RTW_INTR_RDU | RTW_INTR_RXFOVW)) {
1917 cr |= RTW_CR_RE;
1918 rcvr = 1;
1919 }
1920
1921 RTW_DPRINTF(RTW_DEBUG_BUGS,
1922 ("%s: restarting xmit/recv, isr %04x\n",
1923 sc->sc_ic.ic_if.if_xname, isr));
1924
1925#ifdef RTW_DEBUG
1926 rtw_dump_rings(sc);
1927#endif /* RTW_DEBUG */
1928
1929 rtw_io_enable(sc, cr, 0);
1930
1931 /* Collect rx'd packets. Refresh rx buffers. */
1932 if (rcvr)
1933 rtw_intr_rx(sc, 0);
1934
1935 /*
1936 * Collect tx'd packets.
1937 * XXX let's hope this stops the transmit timeouts.
1938 */
1939 if (xmtr)
1940 rtw_txdesc_blk_reset_all(sc);
1941
1942 RTW_WRITE16(regs, RTW_IMR, 0);
1943 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1944
1945 if (rtw_do_chip_reset) {
1946 rtw_chip_reset1(sc);
1947 rtw_wep_setkeys(sc);
1948 }
1949
1950 rtw_rxdesc_blk_init_all(sc);
1951
1952#ifdef RTW_DEBUG
1953 rtw_dump_rings(sc);
1954#endif /* RTW_DEBUG */
1955
1956 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
1957 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1958
1959 if (rcvr)
1960 rtw_rxring_fixup(sc);
1961
1962 rtw_io_enable(sc, cr, 1);
1963
1964 if (xmtr)
1965 rtw_txring_fixup(sc);
1966}
1967
1968static __inline void
1969rtw_suspend_ticks(struct rtw_softc *sc)
1970{
1971 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1972 ("%s: suspending ticks\n", sc->sc_ic.ic_if.if_xname));
1973 sc->sc_do_tick = 0;
1974}
1975
1976static void
1977rtw_resume_ticks(struct rtw_softc *sc)
1978{
1979 uint32_t tsftrl0, tsftrl1, next_tick;
1980 struct rtw_regs *regs = &sc->sc_regs;
1981
1982 tsftrl0 = RTW_READ(regs, RTW_TSFTRL);
1983
1984 tsftrl1 = RTW_READ(regs, RTW_TSFTRL);
1985 next_tick = tsftrl1 + 1000000;
1986 RTW_WRITE(regs, RTW_TINT, next_tick);
1987
1988 sc->sc_do_tick = 1;
1989
1990 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1991 ("%s: resume ticks delta %#08x now %#08x next %#08x\n",
1992 sc->sc_ic.ic_if.if_xname, tsftrl1 - tsftrl0, tsftrl1,
1993 next_tick));
1994}
1995
1996static void
1997rtw_intr_timeout(struct rtw_softc *sc)
1998{
1999 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
2000 ("%s: timeout\n", sc->sc_ic.ic_if.if_xname));
2001 if (sc->sc_do_tick)
2002 rtw_resume_ticks(sc);
2003}
2004
2005static void
2006rtw_intr(void *arg)
2007{
2008 struct rtw_softc *sc = arg;
2009 struct rtw_regs *regs = &sc->sc_regs;
2010 struct ifnet *ifp = &sc->sc_if;
2011 int i;
2012
2013 /*
2014 * If the interface isn't running, the interrupt couldn't
2015 * possibly have come from us.
2016 */
2017 if ((sc->sc_flags & RTW_F_ENABLED) == 0 ||
2018 (ifp->if_flags & IFF_RUNNING) == 0) {
2019 RTW_DPRINTF(RTW_DEBUG_INTR,
2020 ("%s: stray interrupt\n", ifp->if_xname));
2021 return;
2022 }
2023
2024 for (i = 0; i < 10; i++) {
2025 uint16_t isr;
2026
2027 isr = RTW_READ16(regs, RTW_ISR);
2028
2029 RTW_WRITE16(regs, RTW_ISR, isr);
2030 RTW_WBR(regs, RTW_ISR, RTW_ISR);
2031
2032 if (sc->sc_intr_ack != NULL)
2033 sc->sc_intr_ack(regs);
2034
2035 if (isr == 0)
2036 break;
2037
2038#ifdef RTW_DEBUG
2039#define PRINTINTR(flag) do { \
2040 if ((isr & flag) != 0) { \
e3869ec7 2041 kprintf("%s" #flag, delim); \
44db266b
SZ
2042 delim = ","; \
2043 } \
2044} while (0)
2045
2046 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) {
2047 const char *delim = "<";
2048
2049 if_printf(ifp, "reg[ISR] = %x", isr);
2050
2051 PRINTINTR(RTW_INTR_TXFOVW);
2052 PRINTINTR(RTW_INTR_TIMEOUT);
2053 PRINTINTR(RTW_INTR_BCNINT);
2054 PRINTINTR(RTW_INTR_ATIMINT);
2055 PRINTINTR(RTW_INTR_TBDER);
2056 PRINTINTR(RTW_INTR_TBDOK);
2057 PRINTINTR(RTW_INTR_THPDER);
2058 PRINTINTR(RTW_INTR_THPDOK);
2059 PRINTINTR(RTW_INTR_TNPDER);
2060 PRINTINTR(RTW_INTR_TNPDOK);
2061 PRINTINTR(RTW_INTR_RXFOVW);
2062 PRINTINTR(RTW_INTR_RDU);
2063 PRINTINTR(RTW_INTR_TLPDER);
2064 PRINTINTR(RTW_INTR_TLPDOK);
2065 PRINTINTR(RTW_INTR_RER);
2066 PRINTINTR(RTW_INTR_ROK);
2067
e3869ec7 2068 kprintf(">\n");
44db266b
SZ
2069 }
2070#undef PRINTINTR
2071#endif /* RTW_DEBUG */
2072
2073 if (isr & RTW_INTR_RX)
2074 rtw_intr_rx(sc, isr & RTW_INTR_RX);
2075 if (isr & RTW_INTR_TX)
2076 rtw_intr_tx(sc, isr & RTW_INTR_TX);
2077 if (isr & RTW_INTR_BEACON)
2078 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON);
2079 if (isr & RTW_INTR_ATIMINT)
2080 rtw_intr_atim(sc);
2081 if (isr & RTW_INTR_IOERROR)
2082 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR);
2083 if (isr & RTW_INTR_TIMEOUT)
2084 rtw_intr_timeout(sc);
2085 }
2086}
2087
2088/* Must be called at splnet. */
2089void
2090rtw_stop(struct rtw_softc *sc, int disable)
2091{
2092 struct ieee80211com *ic = &sc->sc_ic;
2093 struct ifnet *ifp = &ic->ic_if;
2094 struct rtw_regs *regs = &sc->sc_regs;
2095 int i;
2096
2097 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2098 return;
2099
2100 rtw_suspend_ticks(sc);
2101
2102 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2103
2104 if ((sc->sc_flags & RTW_F_INVALID) == 0) {
2105 /* Disable interrupts. */
2106 RTW_WRITE16(regs, RTW_IMR, 0);
2107
2108 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
2109
2110 /*
2111 * Stop the transmit and receive processes. First stop DMA,
2112 * then disable receiver and transmitter.
2113 */
2114 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2115
2116 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
2117
2118 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2119 }
2120
2121 /* Free pending TX mbufs */
2122 for (i = 0; i < RTW_NTXPRI; ++i) {
2123 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[i];
2124 struct rtw_txsoft *ts;
2125
2126 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
2127 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, 0, 0, 0, 0);
2128 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
2129 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
2130 }
2131 tsb->tsb_tx_timer = 0;
2132 }
2133
2134 /* Free pending RX mbufs */
2135 for (i = 0; i < RTW_RXQLEN; i++) {
2136 struct rtw_rxsoft *rs = &sc->sc_rxsoft[i];
2137
2138 if (rs->rs_mbuf != NULL) {
2139 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
2140 BUS_DMASYNC_POSTREAD);
2141 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
2142 m_freem(rs->rs_mbuf);
2143 rs->rs_mbuf = NULL;
2144 }
2145 }
2146
2147 if (disable)
2148 rtw_disable(sc);
2149
2150 /* Mark the interface as not running. Cancel the watchdog timer. */
2151 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2152 ifp->if_timer = 0;
2153}
2154
2155#ifdef RTW_DEBUG
2156const char *
2157rtw_pwrstate_string(enum rtw_pwrstate power)
2158{
2159 switch (power) {
2160 case RTW_ON:
2161 return "on";
2162 case RTW_SLEEP:
2163 return "sleep";
2164 case RTW_OFF:
2165 return "off";
2166 default:
2167 return "unknown";
2168 }
2169}
2170#endif /* RTW_DEBUG */
2171
2172/*
2173 * XXX For Maxim, I am using the RFMD settings gleaned from the
2174 * reference driver, plus a magic Maxim "ON" value that comes from
2175 * the Realtek document "Windows PG for Rtl8180."
2176 */
2177static void
2178rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2179 int before_rf, int digphy)
2180{
2181 uint32_t anaparm;
2182
2183 anaparm = RTW_READ(regs, RTW_ANAPARM);
2184 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2185
2186 switch (power) {
2187 case RTW_OFF:
2188 if (before_rf)
2189 return;
2190 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF;
2191 anaparm |= RTW_ANAPARM_TXDACOFF;
2192 break;
2193 case RTW_SLEEP:
2194 if (!before_rf)
2195 return;
2196 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP;
2197 anaparm |= RTW_ANAPARM_TXDACOFF;
2198 break;
2199 case RTW_ON:
2200 if (!before_rf)
2201 return;
2202 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON;
2203 break;
2204 }
2205 RTW_DPRINTF(RTW_DEBUG_PWR,
2206 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2207 __func__, rtw_pwrstate_string(power),
2208 (before_rf) ? "before" : "after", anaparm));
2209
2210 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2211 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2212}
2213
2214/* XXX I am using the RFMD settings gleaned from the reference
2215 * driver. They agree
2216 */
2217static void
2218rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2219 int before_rf, int digphy)
2220{
2221 uint32_t anaparm;
2222
2223 anaparm = RTW_READ(regs, RTW_ANAPARM);
2224 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2225
2226 switch (power) {
2227 case RTW_OFF:
2228 if (before_rf)
2229 return;
2230 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF;
2231 anaparm |= RTW_ANAPARM_TXDACOFF;
2232 break;
2233 case RTW_SLEEP:
2234 if (!before_rf)
2235 return;
2236 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP;
2237 anaparm |= RTW_ANAPARM_TXDACOFF;
2238 break;
2239 case RTW_ON:
2240 if (!before_rf)
2241 return;
2242 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON;
2243 break;
2244 }
2245 RTW_DPRINTF(RTW_DEBUG_PWR,
2246 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2247 __func__, rtw_pwrstate_string(power),
2248 (before_rf) ? "before" : "after", anaparm));
2249
2250 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2251 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2252}
2253
2254static void
2255rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2256 int before_rf, int digphy)
2257{
2258 uint32_t anaparm;
2259
2260 anaparm = RTW_READ(regs, RTW_ANAPARM);
2261 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2262
2263 switch (power) {
2264 case RTW_OFF:
2265 if (before_rf)
2266 return;
2267 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF;
2268 anaparm |= RTW_ANAPARM_TXDACOFF;
2269 break;
2270 case RTW_SLEEP:
2271 if (!before_rf)
2272 return;
2273 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP;
2274 anaparm |= RTW_ANAPARM_TXDACOFF;
2275 break;
2276 case RTW_ON:
2277 if (!before_rf)
2278 return;
2279 if (digphy) {
2280 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON;
2281 /* XXX guess */
2282 anaparm |= RTW_ANAPARM_TXDACOFF;
2283 } else
2284 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON;
2285 break;
2286 }
2287 RTW_DPRINTF(RTW_DEBUG_PWR,
2288 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2289 __func__, rtw_pwrstate_string(power),
2290 (before_rf) ? "before" : "after", anaparm));
2291
2292 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2293 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2294}
2295
2296static __inline void
2297rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf,
2298 int digphy)
2299{
2300 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2301 sc->sc_pwrstate_cb(&sc->sc_regs, power, before_rf, digphy);
2302 rtw_set_access(sc, RTW_ACCESS_NONE);
2303}
2304
2305static int
2306rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power)
2307{
2308 int rc;
2309
2310 RTW_DPRINTF(RTW_DEBUG_PWR,
2311 ("%s: %s->%s\n", sc->sc_ic.ic_if.if_xname,
2312 rtw_pwrstate_string(sc->sc_pwrstate),
2313 rtw_pwrstate_string(power)));
2314
2315 if (sc->sc_pwrstate == power)
2316 return 0;
2317
2318 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY);
2319 rc = rtw_rf_pwrstate(sc->sc_rf, power);
2320 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY);
2321
2322 switch (power) {
2323 case RTW_ON:
2324 /* TBD set LEDs */
2325 break;
2326 case RTW_SLEEP:
2327 /* TBD */
2328 break;
2329 case RTW_OFF:
2330 /* TBD */
2331 break;
2332 }
2333 if (rc == 0)
2334 sc->sc_pwrstate = power;
2335 else
2336 sc->sc_pwrstate = RTW_OFF;
2337 return rc;
2338}
2339
2340static int
2341rtw_tune(struct rtw_softc *sc)
2342{
2343 struct ieee80211com *ic = &sc->sc_ic;
2344 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
2345 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
2346 u_int chan;
2347 int rc, antdiv, dflantb;
2348
2349 antdiv = sc->sc_flags & RTW_F_ANTDIV;
2350 dflantb = sc->sc_flags & RTW_F_DFLANTB;
2351
2352 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2353 if (chan == IEEE80211_CHAN_ANY)
2354 panic("%s: chan == IEEE80211_CHAN_ANY\n", ic->ic_if.if_xname);
2355
2356 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2357 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2358
2359 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2360 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2361
2362 if (chan == sc->sc_cur_chan) {
2363 RTW_DPRINTF(RTW_DEBUG_TUNE,
2364 ("%s: already tuned chan #%d\n",
2365 ic->ic_if.if_xname, chan));
2366 return 0;
2367 }
2368
2369 rtw_suspend_ticks(sc);
2370
2371 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2372
2373 /* TBD wait for Tx to complete */
2374
2375 KKASSERT((sc->sc_flags & RTW_F_ENABLED) != 0);
2376
2377 rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf,
2378 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan),
2379 sc->sc_csthr, ic->ic_curchan->ic_freq, antdiv,
2380 dflantb, RTW_ON);
2381 if (rc != 0) {
2382 /* XXX condition on powersaving */
e3869ec7 2383 kprintf("%s: phy init failed\n", ic->ic_if.if_xname);
44db266b
SZ
2384 }
2385
2386 sc->sc_cur_chan = chan;
2387
2388 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2389
2390 rtw_resume_ticks(sc);
2391
2392 return rc;
2393}
2394
2395static void
2396rtw_disable(struct rtw_softc *sc)
2397{
2398 int rc;
2399
2400 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2401 return;
2402
2403 /* turn off PHY */
2404 if ((sc->sc_flags & RTW_F_INVALID) == 0 &&
2405 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0)
2406 if_printf(&sc->sc_ic.ic_if, "failed to turn off PHY\n");
2407
2408 sc->sc_flags &= ~RTW_F_ENABLED;
2409}
2410
2411static int
2412rtw_enable(struct rtw_softc *sc)
2413{
2414 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
2415 sc->sc_flags |= RTW_F_ENABLED;
2416 /*
2417 * Power may have been removed, and WEP keys thus reset.
2418 */
2419 sc->sc_flags &= ~RTW_F_DK_VALID;
2420 }
2421 return (0);
2422}
2423
2424static void
2425rtw_transmit_config(struct rtw_regs *regs)
2426{
2427 uint32_t tcr;
2428
2429 tcr = RTW_READ(regs, RTW_TCR);
2430
2431 tcr |= RTW_TCR_CWMIN;
2432 tcr &= ~RTW_TCR_MXDMA_MASK;
2433 tcr |= RTW_TCR_MXDMA_256;
2434 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */
2435 tcr &= ~RTW_TCR_LBK_MASK;
2436 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */
2437
2438 /* set short/long retry limits */
2439 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK);
2440 tcr |= SHIFTIN(4, RTW_TCR_SRL_MASK) | SHIFTIN(4, RTW_TCR_LRL_MASK);
2441
2442 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */
2443
2444 RTW_WRITE(regs, RTW_TCR, tcr);
2445 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
2446}
2447
2448static void
2449rtw_enable_interrupts(struct rtw_softc *sc)
2450{
2451 struct rtw_regs *regs = &sc->sc_regs;
2452
2453 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT;
2454 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT;
2455
2456 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
2457 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2458 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2459 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2460
2461 /* XXX necessary? */
2462 if (sc->sc_intr_ack != NULL)
2463 sc->sc_intr_ack(regs);
2464}
2465
2466static void
2467rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode)
2468{
2469 struct rtw_regs *regs = &sc->sc_regs;
2470 uint8_t msr;
2471
2472 /* I'm guessing that MSR is protected as CONFIG[0123] are. */
2473 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2474
2475 msr = RTW_READ8(regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK;
2476
2477 switch (opmode) {
2478 case IEEE80211_M_AHDEMO:
2479 case IEEE80211_M_IBSS:
2480 msr |= RTW_MSR_NETYPE_ADHOC_OK;
2481 break;
2482 case IEEE80211_M_HOSTAP:
2483 msr |= RTW_MSR_NETYPE_AP_OK;
2484 break;
2485 case IEEE80211_M_MONITOR:
2486 /* XXX */
2487 msr |= RTW_MSR_NETYPE_NOLINK;
2488 break;
2489 case IEEE80211_M_STA:
2490 msr |= RTW_MSR_NETYPE_INFRA_OK;
2491 break;
2492 }
2493 RTW_WRITE8(regs, RTW_MSR, msr);
2494
2495 rtw_set_access(sc, RTW_ACCESS_NONE);
2496}
2497
2498#define rtw_calchash(addr) \
2499 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26)
2500
2501static void
2502rtw_pktfilt_load(struct rtw_softc *sc)
2503{
2504 struct rtw_regs *regs = &sc->sc_regs;
2505 struct ieee80211com *ic = &sc->sc_ic;
2506 struct ifnet *ifp = &ic->ic_if;
2507 struct ifmultiaddr *ifma;
2508 uint32_t hashes[2] = { 0, 0 };
2509 int hash;
2510
2511 /* XXX might be necessary to stop Rx/Tx engines while setting filters */
2512
2513 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK;
2514 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK);
2515
2516 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT;
2517 /* MAC auto-reset PHY (huh?) */
2518 sc->sc_rcr |= RTW_RCR_ENMARP;
2519 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */
2520 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE;
2521
2522 switch (ic->ic_opmode) {
2523 case IEEE80211_M_MONITOR:
2524 sc->sc_rcr |= RTW_RCR_MONITOR;
2525 break;
2526 case IEEE80211_M_AHDEMO:
2527 case IEEE80211_M_IBSS:
2528 /* receive broadcasts in our BSS */
2529 sc->sc_rcr |= RTW_RCR_ADD3;
2530 break;
2531 default:
2532 break;
2533 }
2534
2535 ifp->if_flags &= ~IFF_ALLMULTI;
2536
2537 /* XXX accept all broadcast if scanning */
2538 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2539 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2540
2541 if (ifp->if_flags & IFF_PROMISC) {
2542 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2543allmulti:
2544 ifp->if_flags |= IFF_ALLMULTI;
2545 goto setit;
2546 }
2547
2548 /*
2549 * Program the 64-bit multicast hash filter.
2550 */
2551 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2552 if (ifma->ifma_addr->sa_family != AF_LINK)
2553 continue;
2554
2555 hash = rtw_calchash(
2556 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
2557 hashes[hash >> 5] |= (1 << (hash & 0x1f));
2558 sc->sc_rcr |= RTW_RCR_AM;
2559 }
2560
2561 /* all bits set => hash is useless */
2562 if (~(hashes[0] & hashes[1]) == 0)
2563 goto allmulti;
2564
2565setit:
2566 if (ifp->if_flags & IFF_ALLMULTI) {
2567 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */
2568 hashes[0] = hashes[1] = 0xffffffff;
2569 }
2570
2571 RTW_WRITE(regs, RTW_MAR0, hashes[0]);
2572 RTW_WRITE(regs, RTW_MAR1, hashes[1]);
2573 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
2574 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
2575
2576 DPRINTF(sc, RTW_DEBUG_PKTFILT,
2577 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n",
2578 ifp->if_xname, RTW_READ(regs, RTW_MAR0),
2579 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
2580}
2581
2582/* Must be called at splnet. */
2583static void
2584rtw_init(void *xsc)
2585{
2586 struct rtw_softc *sc = xsc;
2587 struct ieee80211com *ic = &sc->sc_ic;
2588 struct ifnet *ifp = &ic->ic_if;
2589 struct rtw_regs *regs = &sc->sc_regs;
2590 int rc = 0;
2591
2592 rc = rtw_enable(sc);
2593 if (rc)
2594 goto out;
2595
2596 /* Cancel pending I/O and reset. */
2597 rtw_stop(sc, 0);
2598
2599 DPRINTF(sc, RTW_DEBUG_TUNE,
2600 ("%s: channel %d freq %d flags 0x%04x\n", ifp->if_xname,
2601 ieee80211_chan2ieee(ic, ic->ic_curchan),
2602 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
2603
2604 rc = rtw_pwrstate(sc, RTW_OFF);
2605 if (rc)
2606 goto out;
2607
2608 rc = rtw_swring_setup(sc);
2609 if (rc)
2610 goto out;
2611
2612 rtw_transmit_config(regs);
2613
2614 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2615
2616 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
2617 RTW_WBW(regs, RTW_MSR, RTW_BRSR);
2618
2619 /* long PLCP header, 1Mb/2Mb basic rate */
2620 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS);
2621 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
2622
2623 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2624 rtw_set_access(sc, RTW_ACCESS_NONE);
2625
2626 /* XXX from reference sources */
2627 RTW_WRITE(regs, RTW_FEMR, 0xffff);
2628 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
2629
2630 rtw_set_rfprog(sc);
2631
2632 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
2633 /* from Linux driver */
2634 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
2635
2636 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
2637
2638 rtw_enable_interrupts(sc);
2639
2640 rtw_pktfilt_load(sc);
2641
2642 rtw_hwring_setup(sc);
2643
2644 rtw_wep_setkeys(sc);
2645
2646 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2647
2648 ifp->if_flags |= IFF_RUNNING;
2649 ic->ic_state = IEEE80211_S_INIT;
2650
2651 RTW_WRITE16(regs, RTW_BSSID16, 0x0);
2652 RTW_WRITE(regs, RTW_BSSID32, 0x0);
2653
2654 rtw_resume_ticks(sc);
2655
2656 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
2657
2658 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2659 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2660 else
2661 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2662
2663out:
2664 if (rc)
2665 if_printf(ifp, "interface not running\n");
2666}
2667
2668static void
2669rtw_led_init(struct rtw_softc *sc)
2670{
2671 struct rtw_regs *regs = &sc->sc_regs;
2672 uint8_t cfg0, cfg1;
2673
2674 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2675
2676 cfg0 = RTW_READ8(regs, RTW_CONFIG0);
2677 cfg0 |= RTW_CONFIG0_LEDGPOEN;
2678 RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
2679
2680 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2681 RTW_DPRINTF(RTW_DEBUG_LED,
2682 ("%s: read %02x from reg[CONFIG1]\n",
2683 sc->sc_ic.ic_if.if_xname, cfg1));
2684
2685 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2686 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2687 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
2688
2689 rtw_set_access(sc, RTW_ACCESS_NONE);
2690}
2691
2692/*
2693 * IEEE80211_S_INIT: LED1 off
2694 *
2695 * IEEE80211_S_AUTH,
2696 * IEEE80211_S_ASSOC,
2697 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx
2698 *
2699 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx
2700 */
2701static void
2702rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate)
2703{
2704 struct rtw_led_state *ls = &sc->sc_led_state;
2705
2706 switch (nstate) {
2707 case IEEE80211_S_INIT:
2708 rtw_led_init(sc);
2709 callout_stop(&ls->ls_slow_ch);
2710 callout_stop(&ls->ls_fast_ch);
2711 ls->ls_slowblink = 0;
2712 ls->ls_actblink = 0;
2713 ls->ls_default = 0;
2714 break;
2715 case IEEE80211_S_SCAN:
2716 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2717 rtw_led_slowblink, sc);
2718 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2719 rtw_led_fastblink, sc);
2720 /*FALLTHROUGH*/
2721 case IEEE80211_S_AUTH:
2722 case IEEE80211_S_ASSOC:
2723 ls->ls_default = RTW_LED1;
2724 ls->ls_actblink = RTW_LED1;
2725 ls->ls_slowblink = RTW_LED1;
2726 break;
2727 case IEEE80211_S_RUN:
2728 ls->ls_slowblink = 0;
2729 break;
2730 }
2731 rtw_led_set(sc);
2732}
2733
2734static void
2735rtw_led_set(struct rtw_softc *sc)
2736{
2737 struct rtw_led_state *ls = &sc->sc_led_state;
2738 struct rtw_regs *regs = &sc->sc_regs;
2739 uint8_t led_condition, mask, newval, val;
2740 bus_size_t ofs;
2741
2742 led_condition = ls->ls_default;
2743
2744 if (ls->ls_state & RTW_LED_S_SLOW)
2745 led_condition ^= ls->ls_slowblink;
2746 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX))
2747 led_condition ^= ls->ls_actblink;
2748
2749 RTW_DPRINTF(RTW_DEBUG_LED,
2750 ("%s: LED condition %02x\n", sc->sc_ic.ic_if.if_xname,
2751 led_condition));
2752
2753 switch (sc->sc_hwverid) {
2754 default:
2755 case 'F':
2756 ofs = RTW_PSR;
2757 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;
2758 if (led_condition & RTW_LED0)
2759 newval &= ~RTW_PSR_LEDGPO0;
2760 if (led_condition & RTW_LED1)
2761 newval &= ~RTW_PSR_LEDGPO1;
2762 break;
2763 case 'D':
2764 ofs = RTW_9346CR;
2765 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;
2766 newval = RTW_9346CR_EEM_PROGRAM;
2767 if (led_condition & RTW_LED0)
2768 newval |= RTW_9346CR_EEDI;
2769 if (led_condition & RTW_LED1)
2770 newval |= RTW_9346CR_EECS;
2771 break;
2772 }
2773 val = RTW_READ8(regs, ofs);
2774 RTW_DPRINTF(RTW_DEBUG_LED,
2775 ("%s: read %02x from reg[%02x]\n",
2776 sc->sc_ic.ic_if.if_xname, val, ofs));
2777 val &= ~mask;
2778 val |= newval;
2779 RTW_WRITE8(regs, ofs, val);
2780 RTW_DPRINTF(RTW_DEBUG_LED,
2781 ("%s: wrote %02x to reg[%02x]\n",
2782 sc->sc_ic.ic_if.if_xname, val, ofs));
2783 RTW_SYNC(regs, ofs, ofs);
2784}
2785
2786static void
2787rtw_led_fastblink(void *arg)
2788{
2789 struct rtw_softc *sc = arg;
2790 struct ifnet *ifp = &sc->sc_ic.ic_if;
2791 struct rtw_led_state *ls = &sc->sc_led_state;
2792 int ostate;
2793
2794 lwkt_serialize_enter(ifp->if_serializer);
2795
2796 ostate = ls->ls_state;
2797 ls->ls_state ^= ls->ls_event;
2798
2799 if ((ls->ls_event & RTW_LED_S_TX) == 0)
2800 ls->ls_state &= ~RTW_LED_S_TX;
2801
2802 if ((ls->ls_event & RTW_LED_S_RX) == 0)
2803 ls->ls_state &= ~RTW_LED_S_RX;
2804
2805 ls->ls_event = 0;
2806
2807 if (ostate != ls->ls_state)
2808 rtw_led_set(sc);
2809
2810 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2811 rtw_led_fastblink, sc);
2812
2813 lwkt_serialize_exit(ifp->if_serializer);
2814}
2815
2816static void
2817rtw_led_slowblink(void *arg)
2818{
2819 struct rtw_softc *sc = arg;
2820 struct ifnet *ifp = &sc->sc_ic.ic_if;
2821 struct rtw_led_state *ls = &sc->sc_led_state;
2822
2823 lwkt_serialize_enter(ifp->if_serializer);
2824
2825 ls->ls_state ^= RTW_LED_S_SLOW;
2826 rtw_led_set(sc);
2827 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2828 rtw_led_slowblink, sc);
2829
2830 lwkt_serialize_exit(ifp->if_serializer);
2831}
2832
2833static int
2834rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2835{
2836 struct rtw_softc *sc = ifp->if_softc;
2837 int rc = 0;
2838
2839 switch (cmd) {
2840 case SIOCSIFFLAGS:
2841 if (ifp->if_flags & IFF_UP) {
2842 if ((ifp->if_flags & IFF_RUNNING) == 0)
2843 rtw_init(sc);
2844 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2845 } else if (sc->sc_flags & RTW_F_ENABLED) {
2846 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2847 rtw_stop(sc, 1);
2848 }
2849 break;
2850 case SIOCADDMULTI:
2851 case SIOCDELMULTI:
2852 if (ifp->if_flags & IFF_RUNNING)
2853 rtw_pktfilt_load(sc);
2854 break;
2855 default:
2856 rc = ieee80211_ioctl(&sc->sc_ic, cmd, data, cr);
2857 if (rc == ENETRESET) {
2858 if (sc->sc_flags & RTW_F_ENABLED)
2859 rtw_init(sc);
2860 rc = 0;
2861 }
2862 break;
2863 }
2864 return rc;
2865}
2866
2867/*
2868 * Select a transmit ring with at least one h/w and s/w descriptor free.
2869 * Return 0 on success, -1 on failure.
2870 */
2871static __inline int
2872rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp,
2873 struct rtw_txdesc_blk **tdbp, int pri)
2874{
2875 struct rtw_txsoft_blk *tsb;
2876 struct rtw_txdesc_blk *tdb;
2877
2878 KKASSERT(pri >= 0 && pri < RTW_NTXPRI);
2879
2880 tsb = &sc->sc_txsoft_blk[pri];
2881 tdb = &sc->sc_txdesc_blk[pri];
2882
2883 if (STAILQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) {
2884 if (tsb->tsb_tx_timer == 0)
2885 tsb->tsb_tx_timer = 5;
2886 *tsbp = NULL;
2887 *tdbp = NULL;
2888 return -1;
2889 }
2890 *tsbp = tsb;
2891 *tdbp = tdb;
2892 return 0;
2893}
2894
2895static __inline struct mbuf *
2896rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri,
2897 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp,
2898 struct ieee80211_node **nip, int *if_flagsp)
2899{
2900 struct mbuf *m;
2901 struct ifnet *ifp = &sc->sc_if;
2902
2903 if (IF_QEMPTY(ifq))
2904 return NULL;
2905 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2906 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2907 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2908 *if_flagsp |= IFF_OACTIVE;
2909 ifp->if_timer = 1;
2910 return NULL;
2911 }
2912 IF_DEQUEUE(ifq, m);
2913 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2914 m->m_pkthdr.rcvif = NULL;
2915 KKASSERT(*nip != NULL);
2916 return m;
2917}
2918
2919/*
2920 * Point *mp at the next 802.11 frame to transmit. Point *tsbp
2921 * at the driver's selection of transmit control block for the packet.
2922 */
2923static int
2924rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp,
2925 struct rtw_txdesc_blk **tdbp, struct mbuf **mp,
2926 struct ieee80211_node **nip)
2927{
2928 struct rtw_softc *sc = ifp->if_softc;
2929 int *if_flagsp = &ifp->if_flags;
2930 struct ether_header *eh;
2931 struct mbuf *m0;
2932 int pri;
2933
2934 DPRINTF(sc, RTW_DEBUG_XMIT,
2935 ("%s: enter %s\n", ifp->if_xname, __func__));
2936
2937 if (sc->sc_ic.ic_state == IEEE80211_S_RUN &&
2938 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp,
2939 tdbp, nip, if_flagsp)) != NULL) {
2940 DPRINTF(sc, RTW_DEBUG_XMIT,
2941 ("%s: dequeue beacon frame\n", ifp->if_xname));
2942 return 0;
2943 }
2944
2945 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp,
2946 tdbp, nip, if_flagsp)) != NULL) {
2947 DPRINTF(sc, RTW_DEBUG_XMIT,
2948 ("%s: dequeue mgt frame\n", ifp->if_xname));
2949 return 0;
2950 }
2951
2952 *mp = NULL;
2953
2954 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) {
2955 DPRINTF(sc, RTW_DEBUG_XMIT,
2956 ("%s: not running\n", ifp->if_xname));
2957 return 0;
2958 }
2959
2960 m0 = ifq_poll(&ifp->if_snd);
2961 if (m0 == NULL) {
2962 DPRINTF(sc, RTW_DEBUG_XMIT,
2963 ("%s: no frame ready\n", ifp->if_xname));
2964 return 0;
2965 }
2966
2967 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD;
2968
2969 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2970 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2971 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2972 *if_flagsp |= IFF_OACTIVE;
2973 sc->sc_if.if_timer = 1;
2974 return 0;
2975 }
2976
2977 ifq_dequeue(&ifp->if_snd, m0);
2978 DPRINTF(sc, RTW_DEBUG_XMIT,
2979 ("%s: dequeue data frame\n", ifp->if_xname));
2980
2981 BPF_MTAP(ifp, m0);
2982
2983 eh = mtod(m0, struct ether_header *);
2984 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost);
2985 if (*nip == NULL) {
2986 /* NB: ieee80211_find_txnode does stat+msg */
2987 m_freem(m0);
2988 return -1;
2989 }
2990
2991 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) {
2992 DPRINTF(sc, RTW_DEBUG_XMIT,
2993 ("%s: encap error\n", ifp->if_xname));
2994 ieee80211_free_node(*nip);
2995 ifp->if_oerrors++;
2996 return -1;
2997 }
2998
2999 ifp->if_opackets++;
3000 DPRINTF(sc, RTW_DEBUG_XMIT,
3001 ("%s: leave %s\n", ifp->if_xname, __func__));
3002 *mp = m0;
3003 return 0;
3004}
3005
3006static __inline int
3007rtw_txsegs_too_short(struct rtw_txsegs *segs)
3008{
3009 int i;
3010
3011 for (i = 0; i < segs->nseg; i++) {
3012 if (segs->segs[i].ds_len < 4)
3013 return 1;
3014 }
3015 return 0;
3016}
3017
3018static __inline int
3019rtw_txsegs_too_long(struct rtw_txsegs *segs)
3020{
3021 int i;
3022
3023 for (i = 0; i < segs->nseg; i++) {
3024 if (segs->segs[i].ds_len > RTW_TXLEN_LENGTH_MASK)
3025 return 1;
3026 }
3027 return 0;
3028}
3029
3030static void
3031rtw_txbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
3032 bus_size_t mapsize, int error)
3033{
3034 struct rtw_txsegs *s = arg;
3035
3036 if (error)
3037 return;
3038
3039 KASSERT(nseg <= RTW_MAXPKTSEGS, ("too many tx mbuf seg\n"));
3040
3041 s->nseg = nseg;
3042 bcopy(seg, s->segs, sizeof(*seg) * nseg);
3043}
3044
3045static struct mbuf *
3046rtw_load_txbuf(struct rtw_softc *sc, struct rtw_txsoft *ts,
3047 struct rtw_txsegs *segs, int ndesc_free, struct mbuf *m)
3048{
3049 int unload = 0, error;
3050
3051 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap, m,
3052 rtw_txbuf_dma_map, segs, BUS_DMA_NOWAIT);
3053 if (error && error != E2BIG) {
3054 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf1\n");
3055 goto back;
3056 }
3057
3058 if (error || segs->nseg > ndesc_free || rtw_txsegs_too_short(segs)) {
3059 struct mbuf *m_new;
3060
3061 if (error == 0)
3062 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3063
3064 m_new = m_defrag(m, MB_DONTWAIT);
3065 if (m_new == NULL) {
3066 if_printf(&sc->sc_ic.ic_if, "can't defrag tx mbuf\n");
3067 error = ENOBUFS;
3068 goto back;
3069 }
3070 m = m_new;
3071
3072 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap,
3073 m, rtw_txbuf_dma_map, segs,
3074 BUS_DMA_NOWAIT);
3075 if (error) {
3076 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf2\n");
3077 goto back;
3078 }
3079 unload = 1;
3080
3081 error = E2BIG;
3082 if (segs->nseg > ndesc_free) {
3083 if_printf(&sc->sc_ic.ic_if, "not enough free txdesc\n");
3084 goto back;
3085 }
3086 if (rtw_txsegs_too_short(segs)) {
3087 if_printf(&sc->sc_ic.ic_if, "segment too short\n");
3088 goto back;
3089 }
3090 error = 0;
3091 }
3092
3093 if (rtw_txsegs_too_long(segs)) {
3094 if_printf(&sc->sc_ic.ic_if, "segment too long\n");
3095 unload = 1;
3096 error = E2BIG;
3097 }
3098
3099back:
3100 if (error) {
3101 if (unload)
3102 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3103 m_freem(m);
3104 m = NULL;
3105 } else {
3106 bus_dmamap_sync(sc->sc_txsoft_dmat, ts->ts_dmamap,
3107 BUS_DMASYNC_PREWRITE);
3108 }
3109 return m;
3110}
3111
3112#ifdef RTW_DEBUG
3113static void
3114rtw_print_txdesc(struct rtw_softc *sc, const char *action,
3115 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc)
3116{
3117 struct rtw_txdesc *td = &tdb->tdb_desc[desc];
3118
3119 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
3120 ("%s: %p %s txdesc[%d] "
3121 "next %#08x buf %#08x "
3122 "ctl0 %#08x ctl1 %#08x len %#08x\n",
3123 sc->sc_ic.ic_if.if_xname, ts, action,
3124 desc, le32toh(td->td_buf), le32toh(td->td_next),
3125 le32toh(td->td_ctl0), le32toh(td->td_ctl1),
3126 le32toh(td->td_len)));
3127}
3128#endif /* RTW_DEBUG */
3129
3130static void
3131rtw_start(struct ifnet *ifp)
3132{
3133 struct rtw_softc *sc = ifp->if_softc;
3134 struct ieee80211com *ic = &sc->sc_ic;
3135 struct ieee80211_node *ni;
3136 struct rtw_txsoft *ts;
3137 struct mbuf *m0;
3138 uint32_t proto_ctl0;
3139
3140 DPRINTF(sc, RTW_DEBUG_XMIT,
3141 ("%s: enter %s\n", ifp->if_xname, __func__));
3142
3143 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3144 goto out;
3145
3146 /* XXX do real rate control */
3147 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS;
3148
3149 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3150 proto_ctl0 |= RTW_TXCTL0_SPLCP;
3151
3152 for (;;) {
3153 struct rtw_txsegs segs;
3154 struct rtw_duration *d0;
3155 struct ieee80211_frame_min *wh;
3156 struct rtw_txsoft_blk *tsb;
3157 struct rtw_txdesc_blk *tdb;
3158 struct rtw_txdesc *td;
3159 struct ieee80211_key *k;
3160 uint32_t ctl0, ctl1;
3161 uint8_t tppoll;
3162 int desc, i, lastdesc, npkt, rate, rateidx, ratectl;
3163
3164 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1)
3165 continue;
3166 if (m0 == NULL)
3167 break;
3168
3169 wh = mtod(m0, struct ieee80211_frame_min *);
3170
3171 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 &&
3172 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3173 ieee80211_free_node(ni);
3174 m_freem(m0);
3175 break;
3176 } else {
3177 k = NULL;
3178 }
3179
3180 ts = STAILQ_FIRST(&tsb->tsb_freeq);
3181
3182 m0 = rtw_load_txbuf(sc, ts, &segs, tdb->tdb_nfree, m0);
3183 if (m0 == NULL || segs.nseg == 0) {
3184 DPRINTF(sc, RTW_DEBUG_XMIT,
3185 ("%s: %s failed\n", ifp->if_xname, __func__));
3186 goto post_dequeue_err;
3187 }
3188
3189 /*
3190 * Note well: rtw_load_txbuf may have created a new chain,
3191 * so we must find the header once more.
3192 */
3193 wh = mtod(m0, struct ieee80211_frame_min *);
3194
3195 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3196 IEEE80211_FC0_TYPE_MGT) {
3197 rateidx = 0;
3198 rate = 2; /* 1Mbit/s */
3199 ratectl = 0;
3200 } else {
3201 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len,
3202 &rateidx, 1);
3203 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx);
3204 ratectl =1;
3205
3206 if (rate == 0) {
3207 if_printf(ifp, "incorrect rate\n");
3208 rateidx = 0;
3209 rate = 2; /* 1Mbit/s */
3210 ratectl = 0;
3211 }
3212 }
3213
3214#ifdef RTW_DEBUG
3215 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
3216 (IFF_DEBUG | IFF_LINK2)) {
3217 ieee80211_dump_pkt(mtod(m0, uint8_t *),
3218 (segs.nseg == 1) ? m0->m_pkthdr.len
3219 : sizeof(wh),
3220 rate, 0);
3221 }
3222#endif /* RTW_DEBUG */
3223 ctl0 = proto_ctl0 |
3224 SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
3225
3226 switch (rate) {
3227 default:
3228 case 2:
3229 ctl0 |= RTW_TXCTL0_RATE_1MBPS;
3230 break;
3231 case 4:
3232 ctl0 |= RTW_TXCTL0_RATE_2MBPS;
3233 break;
3234 case 11:
3235 ctl0 |= RTW_TXCTL0_RATE_5MBPS;
3236 break;
3237 case 22:
3238 ctl0 |= RTW_TXCTL0_RATE_11MBPS;
3239 break;
3240 }
3241 /* XXX >= ? Compare after fragmentation? */
3242 if (m0->m_pkthdr.len > ic->ic_rtsthreshold)
3243 ctl0 |= RTW_TXCTL0_RTSEN;
3244
3245 /*
3246 * XXX Sometimes writes a bogus keyid; h/w doesn't
3247 * seem to care, since we don't activate h/w Tx
3248 * encryption.
3249 */
3250 if (k != NULL) {
3251 ctl0 |= SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &
3252 RTW_TXCTL0_KEYID_MASK;
3253 }
3254
3255 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3256 IEEE80211_FC0_TYPE_MGT) {
3257 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
3258 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3259 IEEE80211_FC0_SUBTYPE_BEACON)
3260 ctl0 |= RTW_TXCTL0_BEACON;
3261 }
3262
3263 if (rtw_compute_duration(wh, k, m0->m_pkthdr.len,
3264 ic->ic_flags, ic->ic_fragthreshold,
3265 rate, &ts->ts_d0, &ts->ts_dn, &npkt,
3266 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3267 (IFF_DEBUG|IFF_LINK2)) == -1) {
3268 DPRINTF(sc, RTW_DEBUG_XMIT,
3269 ("%s: fail compute duration\n", __func__));
3270 goto post_load_err;
3271 }
3272
3273 d0 = &ts->ts_d0;
3274
3275 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur);
3276
3277 ctl1 = SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
3278 SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
3279
3280 if (d0->d_residue)
3281 ctl1 |= RTW_TXCTL1_LENGEXT;
3282
3283 /* TBD fragmentation */
3284
3285 ts->ts_first = tdb->tdb_next;
3286 KKASSERT(ts->ts_first < tdb->tdb_ndesc);
3287
3288 if (ic->ic_rawbpf != NULL)
3289 bpf_mtap(ic->ic_rawbpf, m0);
3290
3291 if (sc->sc_radiobpf != NULL) {
3292 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
3293
3294 rt->rt_flags = 0;
3295 rt->rt_rate = rate;
3296
3297 bpf_ptap(sc->sc_radiobpf, m0, rt,
3298 sizeof(sc->sc_txtapu));
3299 }
3300
3301 for (i = 0, lastdesc = desc = ts->ts_first; i < segs.nseg;
3302 i++, desc = RTW_NEXT_IDX(tdb, desc)) {
3303 td = &tdb->tdb_desc[desc];
3304 td->td_ctl0 = htole32(ctl0);
3305 if (i != 0)
3306 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3307 td->td_ctl1 = htole32(ctl1);
3308 td->td_buf = htole32(segs.segs[i].ds_addr);
3309 td->td_len = htole32(segs.segs[i].ds_len);
3310 lastdesc = desc;
3311#ifdef RTW_DEBUG
3312 rtw_print_txdesc(sc, "load", ts, tdb, desc);
3313#endif /* RTW_DEBUG */
3314 }
3315
3316 KKASSERT(desc < tdb->tdb_ndesc);
3317
3318 ts->ts_ni = ni;
3319 KKASSERT(ni != NULL);
3320 ts->ts_mbuf = m0;
3321 ts->ts_rateidx = rateidx;
3322 ts->ts_ratectl = ratectl;
3323 ts->ts_last = lastdesc;
3324 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS);
3325 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_FS);
3326
3327#ifdef RTW_DEBUG
3328 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first);
3329 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last);
3330#endif /* RTW_DEBUG */
3331
3332 tdb->tdb_nfree -= segs.nseg;
3333 tdb->tdb_next = desc;
3334
3335 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3336
3337#ifdef RTW_DEBUG
3338 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first);
3339#endif /* RTW_DEBUG */
3340
3341 STAILQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q);
3342 STAILQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q);
3343
3344 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN])
3345 sc->sc_led_state.ls_event |= RTW_LED_S_TX;
3346 tsb->tsb_tx_timer = 5;
3347 ifp->if_timer = 1;
3348 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL);
3349 tppoll &= ~RTW_TPPOLL_SALL;
3350 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL;
3351 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll);
3352 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL);
3353
3354 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
3355 BUS_DMASYNC_PREWRITE);
3356 }
3357out:
3358 DPRINTF(sc, RTW_DEBUG_XMIT,
3359 ("%s: leave %s\n", ifp->if_xname, __func__));
3360 return;
3361
3362post_load_err:
3363 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3364 m_freem(m0);
3365post_dequeue_err:
3366 ieee80211_free_node(ni);
3367
3368 DPRINTF(sc, RTW_DEBUG_XMIT,
3369 ("%s: leave %s\n", ifp->if_xname, __func__));
3370}
3371
3372static void
3373rtw_idle(struct rtw_softc *sc)
3374{
3375 struct rtw_regs *regs = &sc->sc_regs;
3376 int active;
3377
3378 /* request stop DMA; wait for packets to stop transmitting. */
3379
3380 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
3381 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
3382
3383 for (active = 0;
3384 active < 300 &&
3385 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0;
3386 active++)
3387 DELAY(10);
3388 if_printf(&sc->sc_ic.ic_if, "transmit DMA idle in %dus\n", active * 10);
3389}
3390
3391static void
3392rtw_watchdog(struct ifnet *ifp)
3393{
3394 int pri, tx_timeouts = 0;
3395 struct rtw_softc *sc = ifp->if_softc;
3396
3397 ifp->if_timer = 0;
3398
3399 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
3400 return;
3401
3402 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3403 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
3404
3405 if (tsb->tsb_tx_timer == 0)
3406 continue;
3407 else if (--tsb->tsb_tx_timer == 0) {
3408 if (STAILQ_EMPTY(&tsb->tsb_dirtyq))
3409 continue;
3410 if_printf(ifp, "transmit timeout, priority %d\n", pri);
3411 ifp->if_oerrors++;
3412 tx_timeouts++;
3413 } else {
3414 ifp->if_timer = 1;
3415 }
3416 }
3417
3418 if (tx_timeouts > 0) {
3419 /*
3420 * Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr,
3421 * reset s/w tx-ring pointers, and start transmission.
3422 *
3423 * TBD Stop/restart just the broken rings?
3424 */
3425 rtw_idle(sc);
3426 rtw_io_enable(sc, RTW_CR_TE, 0);
3427 rtw_txdesc_blk_reset_all(sc);
3428 rtw_io_enable(sc, RTW_CR_TE, 1);
3429 rtw_txring_fixup(sc);
3430 rtw_start(ifp);
3431 }
3432 ieee80211_watchdog(&sc->sc_ic);
3433}
3434
3435static void
3436rtw_next_scan(void *arg)
3437{
3438 struct ieee80211com *ic = arg;
3439 struct ifnet *ifp = &ic->ic_if;
3440
3441 lwkt_serialize_enter(ifp->if_serializer);
3442
3443 /* don't call rtw_start w/o network interrupts blocked */
3444 if (ic->ic_state == IEEE80211_S_SCAN)
3445 ieee80211_next_scan(ic);
3446
3447 lwkt_serialize_exit(ifp->if_serializer);
3448}
3449
3450static void
3451rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0)
3452{
3453 uint16_t bcnitv, bintritv, intval;
3454 int i;
3455 struct rtw_regs *regs = &sc->sc_regs;
3456
3457 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3458 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
3459
3460 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
3461
3462 rtw_set_access(sc, RTW_ACCESS_CONFIG);
3463
3464 intval = MIN(intval0, SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK));
3465
3466 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
3467 bcnitv |= SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);
3468 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
3469 /* interrupt host 1ms before the TBTT */
3470 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
3471 bintritv |= SHIFTIN(1000, RTW_BINTRITV_BINTRITV);
3472 RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
3473 /* magic from Linux */
3474 RTW_WRITE16(regs, RTW_ATIMWND, SHIFTIN(1, RTW_ATIMWND_ATIMWND));
3475 RTW_WRITE16(regs, RTW_ATIMTRITV, SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));
3476 rtw_set_access(sc, RTW_ACCESS_NONE);
3477
3478 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3479}
3480
3481/* Synchronize the hardware state with the software state. */
3482static int
3483rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3484{
3485 struct ifnet *ifp = ic->ic_ifp;
3486 struct rtw_softc *sc = ifp->if_softc;
3487 enum ieee80211_state ostate;
3488 int error;
3489
3490 ostate = ic->ic_state;
3491
3492 ieee80211_ratectl_newstate(ic, nstate);
3493 rtw_led_newstate(sc, nstate);
3494
3495 if (nstate == IEEE80211_S_INIT) {
3496 callout_stop(&sc->sc_scan_ch);
3497 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
3498 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3499 }
3500
3501 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT)
3502 rtw_pwrstate(sc, RTW_ON);
3503
3504 error = rtw_tune(sc);
3505 if (error != 0)
3506 return error;
3507
3508 switch (nstate) {
3509 case IEEE80211_S_INIT:
3510 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__);
3511 break;
3512 case IEEE80211_S_SCAN:
3513 if (ostate != IEEE80211_S_SCAN) {
3514 memset(ic->ic_bss->ni_bssid, 0, IEEE80211_ADDR_LEN);
3515 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3516 }
3517
3518 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000,
3519 rtw_next_scan, ic);
3520
3521 break;
3522 case IEEE80211_S_RUN:
3523 switch (ic->ic_opmode) {
3524 case IEEE80211_M_HOSTAP:
3525 case IEEE80211_M_IBSS:
3526 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3527 /*FALLTHROUGH*/
3528 case IEEE80211_M_AHDEMO:
3529 case IEEE80211_M_STA:
3530 rtw_join_bss(sc, ic->ic_bss->ni_bssid,
3531 ic->ic_bss->ni_intval);
3532 break;
3533 case IEEE80211_M_MONITOR:
3534 break;
3535 }
3536 rtw_set_nettype(sc, ic->ic_opmode);
3537 break;
3538 case IEEE80211_S_ASSOC:
3539 case IEEE80211_S_AUTH:
3540 break;
3541 }
3542
3543 if (nstate != IEEE80211_S_SCAN)
3544 callout_stop(&sc->sc_scan_ch);
3545
3546 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3547}
3548
3549/* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */
3550static uint64_t
3551rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp)
3552{
3553 uint32_t tsftl, tsfth;
3554
3555 tsfth = RTW_READ(regs, RTW_TSFTRH);
3556 tsftl = RTW_READ(regs, RTW_TSFTRL);
3557 if (tsftl < rstamp) /* Compensate for rollover. */
3558 tsfth--;
3559 return ((uint64_t)tsfth << 32) | rstamp;
3560}
3561
3562static void
3563rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
3564 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
3565{
3566 struct ifnet *ifp = &ic->ic_if;
3567 struct rtw_softc *sc = ifp->if_softc;
3568
3569 sc->sc_mtbl.mt_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
3570
3571 switch (subtype) {
3572 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3573 case IEEE80211_FC0_SUBTYPE_BEACON:
3574 if (ic->ic_opmode == IEEE80211_M_IBSS &&
3575 ic->ic_state == IEEE80211_S_RUN) {
3576 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp);
3577
3578 if (le64toh(ni->ni_tstamp.tsf) >= tsf)
3579 ieee80211_ibss_merge(ni);
3580 }
3581 break;
3582 default:
3583 break;
3584 }
3585}
3586
3587#ifdef foo
3588static struct ieee80211_node *
3589rtw_node_alloc(struct ieee80211_node_table *nt)
3590{
3591 struct ifnet *ifp = nt->nt_ic->ic_ifp;
3592 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3593 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt);
3594
3595 DPRINTF(sc, RTW_DEBUG_NODE,
3596 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
3597 return ni;
3598}
3599
3600static void
3601rtw_node_free(struct ieee80211_node *ni)
3602{
3603 struct ieee80211com *ic = ni->ni_ic;
3604 struct ifnet *ifp = ic->ic_ifp;
3605 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3606
3607 DPRINTF(sc, RTW_DEBUG_NODE,
3608 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
3609 ether_sprintf(ni->ni_bssid)));
3610 sc->sc_mtbl.mt_node_free(ni);
3611}
3612#endif
3613
3614static int
3615rtw_media_change(struct ifnet *ifp)
3616{
3617 int error;
3618
3619 error = ieee80211_media_change(ifp);
3620 if (error == ENETRESET) {
3621 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
3622 (IFF_RUNNING|IFF_UP))
3623 rtw_init(ifp); /* XXX lose error */
3624 error = 0;
3625 }
3626 return error;
3627}
3628
3629static void
3630rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
3631{
3632 struct rtw_softc *sc = ifp->if_softc;
3633
3634 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
3635 imr->ifm_active = IFM_IEEE80211 | IFM_NONE;
3636 imr->ifm_status = 0;
3637 return;
3638 }
3639 ieee80211_media_status(ifp, imr);
3640}
3641
3642static __inline void
3643rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic)
3644{
3645 mtbl->mt_newstate = ic->ic_newstate;
3646 ic->ic_newstate = rtw_newstate;
3647
3648 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt;
3649 ic->ic_recv_mgmt = rtw_recv_mgmt;
3650
3651#ifdef foo
3652 mtbl->mt_node_free = ic->ic_node_free;
3653 ic->ic_node_free = rtw_node_free;
3654
3655 mtbl->mt_node_alloc = ic->ic_node_alloc;
3656 ic->ic_node_alloc = rtw_node_alloc;
3657#endif
3658
3659 ic->ic_crypto.cs_key_delete = rtw_key_delete;
3660 ic->ic_crypto.cs_key_set = rtw_key_set;
3661 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin;
3662 ic->ic_crypto.cs_key_update_end = rtw_key_update_end;
3663}
3664
3665static __inline void
3666rtw_init_radiotap(struct rtw_softc *sc)
3667{
3668 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
3669 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT);
3670
3671 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
3672 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT);
3673}
3674
3675static struct rtw_rf *
3676rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy)
3677{
3678 rtw_rf_write_t rf_write;
3679 struct rtw_rf *rf;
3680
3681 switch (rfchipid) {
3682 default:
3683 rf_write = rtw_rf_hostwrite;
3684 break;
3685 case RTW_RFCHIPID_INTERSIL:
3686 case RTW_RFCHIPID_PHILIPS:
3687 case RTW_RFCHIPID_GCT: /* XXX a guess */
3688 case RTW_RFCHIPID_RFMD:
3689 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite;
3690 break;
3691 }
3692
3693 switch (rfchipid) {
3694 case RTW_RFCHIPID_GCT:
3695 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0);
3696 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3697 break;
3698 case RTW_RFCHIPID_MAXIM:
3699 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0);
3700 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3701 break;
3702 case RTW_RFCHIPID_PHILIPS:
3703 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy);
3704 sc->sc_pwrstate_cb = rtw_philips_pwrstate;
3705 break;
3706 case RTW_RFCHIPID_RFMD:
3707 /* XXX RFMD has no RF constructor */
3708 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate;
3709 /*FALLTHROUGH*/
3710 default:
3711 return NULL;
3712 }
3713 rf->rf_continuous_tx_cb =
3714 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable;
3715 rf->rf_continuous_tx_arg = sc;
3716 return rf;
3717}
3718
3719/* Revision C and later use a different PHY delay setting than
3720 * revisions A and B.
3721 */
3722static uint8_t
3723rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr)
3724{
3725#define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV)
3726#define REVC (REVAB | RTW_RCR_RXFTH_WHOLE)
3727
3728 uint8_t phydelay = SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);
3729
3730 RTW_WRITE(regs, RTW_RCR, REVAB);
3731 RTW_WBW(regs, RTW_RCR, RTW_RCR);
3732 RTW_WRITE(regs, RTW_RCR, REVC);
3733
3734 RTW_WBR(regs, RTW_RCR, RTW_RCR);
3735 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
3736 phydelay |= RTW_PHYDELAY_REVC_MAGIC;
3737
3738 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
3739 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
3740
3741 return phydelay;
3742#undef REVC
3743#undef REVAB
3744}
3745
3746int
3747rtw_attach(device_t dev)
3748{
3749 struct rtw_softc *sc = device_get_softc(dev);
3750 struct ieee80211com *ic = &sc->sc_ic;
3751 const struct ieee80211_cipher *wep_cipher;
3752 struct ifnet *ifp = &ic->ic_if;
3753 int rc;
3754
3755 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
3756 KKASSERT(wep_cipher != NULL);
3757
3758 memcpy(&rtw_cipher_wep, wep_cipher, sizeof(rtw_cipher_wep));
3759 rtw_cipher_wep.ic_decap = rtw_wep_decap;
3760
3761 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3762
3763 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
3764 case RTW_TCR_HWVERID_F:
3765 sc->sc_hwverid = 'F';
3766 break;
3767 case RTW_TCR_HWVERID_D:
3768 sc->sc_hwverid = 'D';
3769 break;
3770 default:
3771 sc->sc_hwverid = '?';
3772 break;
3773 }
3774
3775 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3776 &sc->sc_irq_rid,
3777 RF_ACTIVE | RF_SHAREABLE);
3778 if (sc->sc_irq_res == NULL) {
3779 device_printf(dev, "could not alloc irq res\n");
3780 return ENXIO;
3781 }
3782
3783 /* Allocate h/w desc blocks */
3784 rc = rtw_desc_blk_alloc(sc);
3785 if (rc)
3786 goto err;
3787
3788 /* Allocate s/w desc blocks */
3789 rc = rtw_soft_blk_alloc(sc);
3790 if (rc)
3791 goto err;
3792
3793 /* Reset the chip to a known state. */
3794 rc = rtw_reset(sc);
3795 if (rc) {
3796 device_printf(dev, "could not reset\n");
3797 goto err;
3798 }
3799
3800 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
3801
3802 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0)
3803 sc->sc_flags |= RTW_F_9356SROM;
3804
3805 rc = rtw_srom_read(sc);
3806 if (rc)
3807 goto err;
3808
3809 rc = rtw_srom_parse(sc);
3810 if (rc) {
3811 device_printf(dev, "malformed serial ROM\n");
3812 goto err;
3813 }
3814
3815 device_printf(dev, "%s PHY\n",
3816 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital"
3817 : "analog");
3818
3819 device_printf(dev, "CS threshold %u\n", sc->sc_csthr);
3820
3821 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid,
3822 sc->sc_flags & RTW_F_DIGPHY);
3823 if (sc->sc_rf == NULL) {
3824 device_printf(dev, "could not attach RF\n");
3825 rc = ENXIO;
3826 goto err;
3827 }
3828
3829 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr);
3830
3831 RTW_DPRINTF(RTW_DEBUG_ATTACH,
3832 ("%s: PHY delay %d\n", ifp->if_xname, sc->sc_phydelay));
3833
3834 if (sc->sc_locale == RTW_LOCALE_UNKNOWN)
3835 rtw_identify_country(sc);
3836
3837 rtw_init_channels(sc);
3838
3839 rc = rtw_identify_sta(sc);
3840 if (rc)
3841 goto err;
3842
3843 ifp->if_softc = sc;
3844 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
3845 ifp->if_init = rtw_init;
3846 ifp->if_ioctl = rtw_ioctl;
3847 ifp->if_start = rtw_start;
3848 ifp->if_watchdog = rtw_watchdog;
3849 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
3850 ifq_set_ready(&ifp->if_snd);
3851
3852 ic->ic_phytype = IEEE80211_T_DS;
3853 ic->ic_opmode = IEEE80211_M_STA;
3854 ic->ic_caps = IEEE80211_C_PMGT |
3855 IEEE80211_C_IBSS |
3856 IEEE80211_C_HOSTAP |
3857 IEEE80211_C_MONITOR;
3858 ic->ic_sup_rates[IEEE80211_MODE_11B] = rtw_rates_11b;
3859
3860 /* initialize led callout */
3861 callout_init(&sc->sc_led_state.ls_fast_ch);
3862 callout_init(&sc->sc_led_state.ls_slow_ch);
3863
3864 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
3865 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
3866
3867 /*
3868 * Call MI attach routines.
3869 */
3870 ieee80211_ifattach(&sc->sc_ic);
3871
3872 /* Override some ieee80211 methods */
3873 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic);
3874
3875 /*
3876 * possibly we should fill in our own sc_send_prresp, since
3877 * the RTL8180 is probably sending probe responses in ad hoc
3878 * mode.
3879 */
3880
3881 /* complete initialization */
3882 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status);
3883 callout_init(&sc->sc_scan_ch);
3884
3885 rtw_init_radiotap(sc);
3886
3887 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
3888 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
3889
3890 rc = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, rtw_intr, sc,
3891 &sc->sc_irq_handle, ifp->if_serializer);
3892 if (rc) {
3893 device_printf(dev, "can't set up interrupt\n");
3894 bpfdetach(ifp);
3895 ieee80211_ifdetach(ic);
3896 goto err;
3897 }
3898
3899 device_printf(dev, "hardware version %c\n", sc->sc_hwverid);
3900 if (bootverbose)
3901 ieee80211_announce(ic);
3902 return 0;
3903err:
3904 rtw_detach(dev);
3905 return rc;
3906}
3907
3908int
3909rtw_detach(device_t dev)
3910{
3911 struct rtw_softc *sc = device_get_softc(dev);
3912 struct ifnet *ifp = &sc->sc_ic.ic_if;
3913
3914 if (device_is_attached(dev)) {
3915 lwkt_serialize_enter(ifp->if_serializer);
3916
3917 rtw_stop(sc, 1);
3918 sc->sc_flags |= RTW_F_INVALID;
3919
3920 callout_stop(&sc->sc_scan_ch);
3921 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
3922
3923 lwkt_serialize_exit(ifp->if_serializer);
3924
3925 ieee80211_ifdetach(&sc->sc_ic);
3926 }
3927
3928 if (sc->sc_rf != NULL)
3929 rtw_rf_destroy(sc->sc_rf);
3930
3931 if (sc->sc_srom.sr_content != NULL)
efda3bd0 3932 kfree(sc->sc_srom.sr_content, M_DEVBUF);
44db266b
SZ
3933
3934 if (sc->sc_irq_res != NULL) {
3935 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
3936 sc->sc_irq_res);
3937 }
3938
3939 rtw_soft_blk_free(sc);
3940 rtw_desc_blk_free(sc);
3941 return 0;
3942}
3943
3944static void
3945rtw_desc_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3946{
3947 if (error)
3948 return;
3949
3950 KASSERT(nseg == 1, ("too many desc segments\n"));
3951 *((uint32_t *)arg) = seg->ds_addr; /* XXX bus_addr_t */
3952}
3953
3954static int
3955rtw_dma_alloc(struct rtw_softc *sc, bus_dma_tag_t *dmat, int len,
3956 void **desc, uint32_t *phyaddr, bus_dmamap_t *dmamap)
3957{
3958 int error;
3959
3960 error = bus_dma_tag_create(NULL, RTW_DESC_ALIGNMENT, 0,
3961 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3962 NULL, NULL, len, 1, len, 0, dmat);
3963 if (error) {
3964 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA tag");
3965 return error;
3966 }
3967
3968 error = bus_dmamem_alloc(*dmat, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3969 dmamap);
3970 if (error) {
3971 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA mem");
3972 return error;
3973 }
3974
3975 error = bus_dmamap_load(*dmat, *dmamap, *desc, len,
3976 rtw_desc_dma_addr, phyaddr, BUS_DMA_WAITOK);
3977 if (error) {
3978 if_printf(&sc->sc_ic.ic_if, "could not load desc DMA mem");
3979 bus_dmamem_free(*dmat, *desc, *dmamap);
3980 *desc = NULL;
3981 return error;
3982 }
3983 return 0;
3984}
3985
3986static void
3987rtw_dma_free(struct rtw_softc *sc __unused, bus_dma_tag_t *dmat, void **desc,
3988 bus_dmamap_t *dmamap)
3989{
3990 if (*desc != NULL) {
3991 bus_dmamap_unload(*dmat, *dmamap);
3992 bus_dmamem_free(*dmat, *desc, *dmamap);
3993 *desc = NULL;
3994 }
3995
3996 if (*dmat != NULL) {
3997 bus_dma_tag_destroy(*dmat);
3998 *dmat = NULL;
3999 }
4000}
4001
4002static void
4003rtw_txdesc_blk_free(struct rtw_softc *sc, int q_no)
4004{
4005 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4006
4007 rtw_dma_free(sc, &tdb->tdb_dmat, (void **)&tdb->tdb_desc,
4008 &tdb->tdb_dmamap);
4009}
4010
4011static int
4012rtw_txdesc_blk_alloc(struct rtw_softc *sc, int q_len, int q_no,
4013 bus_size_t q_basereg)
4014{
4015 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4016 int i, error;
4017
4018 /*
4019 * Setup TX h/w desc
4020 */
4021 error = rtw_dma_alloc(sc, &tdb->tdb_dmat,
4022 q_len * sizeof(*tdb->tdb_desc),
4023 (void **)&tdb->tdb_desc, &tdb->tdb_base,
4024 &tdb->tdb_dmamap);
4025 if (error) {
e3869ec7 4026 kprintf("%dth tx\n", q_no);
44db266b
SZ
4027 return error;
4028 }
4029 tdb->tdb_basereg = q_basereg;
4030
4031 tdb->tdb_ndesc = q_len;
4032 for (i = 0; i < tdb->tdb_ndesc; ++i)
4033 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i));
4034
4035 return 0;
4036}
4037
4038static void
4039rtw_rxdesc_blk_free(struct rtw_softc *sc)
4040{
4041 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4042
4043 rtw_dma_free(sc, &rdb->rdb_dmat, (void **)&rdb->rdb_desc,
4044 &rdb->rdb_dmamap);
4045}
4046
4047static int
4048rtw_rxdesc_blk_alloc(struct rtw_softc *sc, int q_len)
4049{
4050 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4051 int error;
4052
4053 /*
4054 * Setup RX h/w desc
4055 */
4056 error = rtw_dma_alloc(sc, &rdb->rdb_dmat,
4057 q_len * sizeof(*rdb->rdb_desc),
4058 (void **)&rdb->rdb_desc, &rdb->rdb_base,
4059 &rdb->rdb_dmamap);
4060 if (error) {
e3869ec7 4061 kprintf("rx\n");
44db266b
SZ
4062 } else {
4063 rdb->rdb_ndesc = q_len;
4064 }
4065
4066 return error;
4067}
4068
4069static void
4070rtw_txsoft_blk_free(struct rtw_softc *sc, int n_sd, int q_no)
4071{
4072 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4073
4074 if (tsb->tsb_desc != NULL) {
4075 int i;
4076
4077 for (i = 0; i < n_sd; ++i) {
4078 bus_dmamap_destroy(sc->sc_txsoft_dmat,
4079 tsb->tsb_desc[i].ts_dmamap);
4080 }
efda3bd0 4081 kfree(tsb->tsb_desc, M_DEVBUF);
44db266b
SZ
4082 tsb->tsb_desc = NULL;
4083 }
4084}
4085
4086static int
4087rtw_txsoft_blk_alloc(struct rtw_softc *sc, int q_len, int q_no, uint8_t q_poll)
4088{
4089 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4090 int i, error;
4091
4092 STAILQ_INIT(&tsb->tsb_dirtyq);
4093 STAILQ_INIT(&tsb->tsb_freeq);
4094 tsb->tsb_ndesc = q_len;
efda3bd0 4095 tsb->tsb_desc = kmalloc(q_len * sizeof(*tsb->tsb_desc), M_DEVBUF,
44db266b
SZ
4096 M_WAITOK | M_ZERO);
4097 tsb->tsb_poll = q_poll;
4098
4099 for (i = 0; i < tsb->tsb_ndesc; ++i) {
4100 error = bus_dmamap_create(sc->sc_txsoft_dmat, 0,
4101 &tsb->tsb_desc[i].ts_dmamap);
4102 if (error) {
4103 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4104 "for soft tx desc\n");
4105 rtw_txsoft_blk_free(sc, i, q_no);
4106 return error;
4107 }
4108 }
4109 return 0;
4110}
4111
4112static void
4113rtw_rxsoft_blk_free(struct rtw_softc *sc, int n_sd)
4114{
4115 if (sc->sc_rxsoft_free) {
4116 int i;
4117
4118 for (i = 0; i < n_sd; ++i) {
4119 bus_dmamap_destroy(sc->sc_rxsoft_dmat,
4120 sc->sc_rxsoft[i].rs_dmamap);
4121 }
4122 sc->sc_rxsoft_free = 0;
4123 }
4124}
4125
4126static int
4127rtw_rxsoft_blk_alloc(struct rtw_softc *sc, int q_len)
4128{
4129 int i, error;
4130
4131 sc->sc_rxsoft_free = 1;
4132
4133 /*
4134 * Setup RX s/w desc
4135 */
4136 for (i = 0; i < q_len; ++i) {
4137 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0,
4138 &sc->sc_rxsoft[i].rs_dmamap);
4139 if (error) {
4140 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4141 "for soft rx desc\n");
4142 rtw_rxsoft_blk_free(sc, i);
4143 return error;
4144 }
4145 }
4146 return 0;
4147}
4148
4149#define TXQ_PARAM(q, poll, breg) \
4150 [RTW_TXPRI ## q] = { \
4151 .txq_len = RTW_TXQLEN ## q, \
4152 .txq_poll = poll, \
4153 .txq_basereg = breg \
4154 }
4155static const struct {
4156 int txq_len;
4157 uint8_t txq_poll;
4158 bus_size_t txq_basereg;
4159} txq_params[RTW_NTXPRI] = {
4160 TXQ_PARAM(LO, RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ, RTW_TLPDA),
4161 TXQ_PARAM(MD, RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ, RTW_TNPDA),
4162 TXQ_PARAM(HI, RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ, RTW_THPDA),
4163 TXQ_PARAM(BCN, RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ, RTW_TBDA)
4164};
4165#undef TXQ_PARAM
4166
4167static int
4168rtw_desc_blk_alloc(struct rtw_softc *sc)
4169{
4170 int i, error;
4171
4172 /* Create h/w TX desc */
4173 for (i = 0; i < RTW_NTXPRI; ++i) {
4174 error = rtw_txdesc_blk_alloc(sc, txq_params[i].txq_len, i,
4175 txq_params[i].txq_basereg);
4176 if (error)
4177 return error;
4178 }
4179
4180 /* Create h/w RX desc */
4181 return rtw_rxdesc_blk_alloc(sc, RTW_RXQLEN);
4182}
4183
4184static void
4185rtw_desc_blk_free(struct rtw_softc *sc)
4186{
4187 int i;
4188
4189 for (i = 0; i < RTW_NTXPRI; ++i)
4190 rtw_txdesc_blk_free(sc, i);
4191 rtw_rxdesc_blk_free(sc);
4192}
4193
4194static int
4195rtw_soft_blk_alloc(struct rtw_softc *sc)
4196{
4197 int i, error;
4198
4199 /* Create DMA tag for TX mbuf */
4200 error = bus_dma_tag_create(NULL, 1, 0,
4201 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4202 NULL, NULL,
4203 MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES,
4204 0, &sc->sc_txsoft_dmat);
4205 if (error) {
4206 if_printf(&sc->sc_ic.ic_if, "could not alloc txsoft DMA tag\n");
4207 return error;
4208 }
4209
4210 /* Create DMA tag for RX mbuf */
4211 error = bus_dma_tag_create(NULL, 1, 0,
4212 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4213 NULL, NULL,
4214 MCLBYTES, 1, MCLBYTES,
4215 0, &sc->sc_rxsoft_dmat);
4216 if (error) {
4217 if_printf(&sc->sc_ic.ic_if, "could not alloc rxsoft DMA tag\n");
4218 return error;
4219 }
4220
4221 /* Create a spare DMA map for RX mbuf */
4222 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0, &sc->sc_rxsoft_dmamap);
4223 if (error) {
4224 if_printf(&sc->sc_ic.ic_if, "could not alloc spare rxsoft "
4225 "DMA map\n");
4226 bus_dma_tag_destroy(sc->sc_rxsoft_dmat);
4227 sc->sc_rxsoft_dmat = NULL;
4228 return error;
4229 }
4230
4231 /* Create s/w TX desc */
4232 for (i = 0; i < RTW_NTXPRI; ++i) {
4233 error = rtw_txsoft_blk_alloc(sc, txq_params[i].txq_len, i,