Device layer rollup commit.
[dragonfly.git] / sys / dev / serial / rp / rpreg.h
CommitLineData
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1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted prodived that the follwoing conditions
7 * are met.
8 * 1. Redistributions of source code must retain the above copyright
9 * notive, this list of conditions and the following disclainer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials prodided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Comtrol Corporation.
16 * 4. The name of Comtrol Corporation may not be used to endorse or
17 * promote products derived from this software without specific
18 * prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/dev/rp/rpreg.h,v 1.4.2.1 2002/06/18 03:11:46 obrien Exp $
e4c9c0c8 33 * $DragonFly: src/sys/dev/serial/rp/rpreg.h,v 1.3 2004/05/19 22:52:49 dillon Exp $
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34 */
35
36/*
37 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
38 */
39
40typedef unsigned char Byte_t;
41typedef unsigned int ByteIO_t;
42
43typedef unsigned int Word_t;
44typedef unsigned int WordIO_t;
45
46typedef unsigned long DWord_t;
47typedef unsigned int DWordIO_t;
48
49#define rp_readio(size, ctlp, rid, offset) \
50 (bus_space_read_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset))
51#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
52 (bus_space_read_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
53#define rp_writeio(size, ctlp, rid, offset, data) \
54 (bus_space_write_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, data))
55#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
56 (bus_space_write_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
57
58#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset)
59#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset)
60#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset)
61#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data)
62#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data)
63#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data)
64#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count)
65#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count)
66#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count)
67#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count)
68#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count)
69#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count)
70
71#define rp_readaiop1(ctlp, aiop, offset) \
72 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
73#define rp_readaiop2(ctlp, aiop, offset) \
74 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
75#define rp_readaiop4(ctlp, aiop, offset) \
76 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
77#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
78 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
79#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
80 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
81#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
82 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
83#define rp_writeaiop1(ctlp, aiop, offset, data) \
84 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
85#define rp_writeaiop2(ctlp, aiop, offset, data) \
86 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
87#define rp_writeaiop4(ctlp, aiop, offset, data) \
88 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
89#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
90 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
91#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
92 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
93#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
94 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
95
96#define rp_readch1(chp, offset) \
97 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
98#define rp_readch2(chp, offset) \
99 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
100#define rp_readch4(chp, offset) \
101 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
102#define rp_readmultich1(chp, offset, addr, count) \
103 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
104#define rp_readmultich2(chp, offset, addr, count) \
105 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
106#define rp_readmultich4(chp, offset, addr, count) \
107 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
108#define rp_writech1(chp, offset, data) \
109 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
110#define rp_writech2(chp, offset, data) \
111 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
112#define rp_writech4(chp, offset, data) \
113 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
114#define rp_writemultich1(chp, offset, addr, count) \
115 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
116#define rp_writemultich2(chp, offset, addr, count) \
117 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
118#define rp_writemultich4(chp, offset, addr, count) \
119 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
120
121/*
122 * End of OS-specific defines
123 */
124
125#define ROCKET_H
126
127#define CTL_SIZE 4
128#define AIOP_CTL_SIZE 4
129#define CHAN_AIOP_SIZE 8
130#define MAX_PORTS_PER_AIOP 8
131#define MAX_AIOPS_PER_BOARD 4
132#define MAX_PORTS_PER_BOARD 32
133
134/* Controller ID numbers */
135#define CTLID_NULL -1 /* no controller exists */
136#define CTLID_0001 0x0001 /* controller release 1 */
137
138/* AIOP ID numbers, identifies AIOP type implementing channel */
139#define AIOPID_NULL -1 /* no AIOP or channel exists */
140#define AIOPID_0001 0x0001 /* AIOP release 1 */
141
142#define NULLDEV -1 /* identifies non-existant device */
143#define NULLCTL -1 /* identifies non-existant controller */
144#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
145#define NULLAIOP -1 /* identifies non-existant AIOP */
146#define NULLCHAN -1 /* identifies non-existant channel */
147
148/************************************************************************
149 Global Register Offsets - Direct Access - Fixed values
150************************************************************************/
151
152#define _CMD_REG 0x38 /* Command Register 8 Write */
153#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
154#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
155#define _UNUSED 0x3B /* Unused 8 */
156#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
157#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
158
159/************************************************************************
160 Channel Register Offsets for 1st channel in AIOP - Direct Access
161************************************************************************/
162#define _TD0 0x00 /* Transmit Data 16 Write */
163#define _RD0 0x00 /* Receive Data 16 Read */
164#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
165#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
166#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
167
168/************************************************************************
169 Tx Control Register Offsets - Indexed - External - Fixed
170************************************************************************/
171#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
172#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
173#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
174#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
175#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
176#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
177
178/************************************************************************
179 Receive FIFO
180************************************************************************/
181#define RXFIFO_DATA 0x5f
182#define RXFIFO_OUT 0x5c
183#define RXFIFO_EN 0x08
184#define RXFIFO_DIS 0xa7
185
186/************************************************************************
187Memory Controller Register Offsets - Indexed - External - Fixed
188************************************************************************/
189#define _RX_FIFO 0x000 /* Rx FIFO */
190#define _TX_FIFO 0x800 /* Tx FIFO */
191#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
192#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
193#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
194#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
195#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
196#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
197
198#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
199#define TXFIFO_SIZE 255 /* size of Tx FIFO */
200#define RXFIFO_SIZE 1023 /* size of Rx FIFO */
201
202/************************************************************************
203Tx Priority Buffer - Indexed - External - Fixed
204************************************************************************/
205#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
206#define TXP_SIZE 0x20 /* 32 bytes */
207
208/************************************************************************
209Channel Register Offsets - Indexed - Internal - Fixed
210************************************************************************/
211
212#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
213#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
214#define _BAUD 0xFF4 /* Baud Rate 16 Write */
215#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
216
217#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
218
219#define BRD50 4607
220#define BRD75 3071
221#define BRD110 2094
222#define BRD134 1712
223#define BRD150 1535
224#define BRD200 1151
225#define BRD300 767
226#define BRD600 383
227#define BRD1200 191
228#define BRD1800 127
229#define BRD2000 114
230#define BRD2400 95
231#define BRD3600 64
232#define BRD4800 47
233#define BRD7200 31
234#define BRD9600 23
235#define BRD14400 15
236#define BRD19200 11
237#define BRD38400 5
238#define BRD57600 3
239#define BRD76800 2
240#define BRD115200 1
241#define BRD230400 0
242
243#define STMBREAK 0x08 /* BREAK */
244#define STMFRAME 0x04 /* framing error */
245#define STMRCVROVR 0x02 /* receiver over run error */
246#define STMPARITY 0x01 /* parity error */
247#define STMERROR (STMBREAK | STMFRAME | STMPARITY)
248#define STMBREAKH 0x800 /* BREAK */
249#define STMFRAMEH 0x400 /* framing error */
250#define STMRCVROVRH 0x200 /* receiver over run error */
251#define STMPARITYH 0x100 /* parity error */
252#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
253
254#define CTS_ACT 0x20 /* CTS input asserted */
255#define DSR_ACT 0x10 /* DSR input asserted */
256#define CD_ACT 0x08 /* CD input asserted */
257#define TXFIFOMT 0x04 /* Tx FIFO is empty */
258#define TXSHRMT 0x02 /* Tx shift register is empty */
259#define RDA 0x01 /* Rx data available */
260#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
261
262#define STATMODE 0x8000 /* status mode enable bit */
263#define RXFOVERFL 0x2000 /* receive FIFO overflow */
264#define RX2MATCH 0x1000 /* receive compare byte 2 match */
265#define RX1MATCH 0x0800 /* receive compare byte 1 match */
266#define RXBREAK 0x0400 /* received BREAK */
267#define RXFRAME 0x0200 /* received framing error */
268#define RXPARITY 0x0100 /* received parity error */
269#define STATERROR (RXBREAK | RXFRAME | RXPARITY)
270
271#define CTSFC_EN 0x80 /* CTS flow control enable bit */
272#define RTSTOG_EN 0x40 /* RTS toggle enable bit */
273#define TXINT_EN 0x10 /* transmit interrupt enable */
274#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
275#define PARITY_EN 0x04 /* enable parity (0 = no parity) */
276#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
277#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
278
279#define SETBREAK 0x10 /* send break condition (must clear) */
280#define LOCALLOOP 0x08 /* local loopback set for test */
281#define SET_DTR 0x04 /* assert DTR */
282#define SET_RTS 0x02 /* assert RTS */
283#define TX_ENABLE 0x01 /* enable transmitter */
284
285#define RTSFC_EN 0x40 /* RTS flow control enable */
286#define RXPROC_EN 0x20 /* receive processor enable */
287#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
288#define TRIG_1 0x08 /* trigger level 1 char */
289#define TRIG_1_2 0x10 /* trigger level 1/2 */
290#define TRIG_7_8 0x18 /* trigger level 7/8 */
291#define TRIG_MASK 0x18 /* trigger level mask */
292#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
293#define RXINT_EN 0x02 /* Rx interrupt enable */
294#define MCINT_EN 0x01 /* modem change interrupt enable */
295
296#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
297#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
298#define SRC_INT 0x08 /* special receive condition interrupt */
299#define DELTA_CD 0x04 /* CD change interrupt */
300#define DELTA_CTS 0x02 /* CTS change interrupt */
301#define DELTA_DSR 0x01 /* DSR change interrupt */
302
303#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
304#define IGN2_EN 0x08 /* ignore byte 2 enable */
305#define IGN1_EN 0x04 /* ignore byte 1 enable */
306#define COMP2_EN 0x02 /* compare byte 2 enable */
307#define COMP1_EN 0x01 /* compare byte 1 enable */
308
309#define RESET_ALL 0x80 /* reset AIOP (all channels) */
310#define TXOVERIDE 0x40 /* Transmit software off override */
311#define RESETUART 0x20 /* reset channel's UART */
312#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
313#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
314
315#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
316#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
317#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
318#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
319
320#define INTR_EN 0x08 /* allow interrupts to host */
321#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
322
323#define CHAN3_EN 0x08 /* enable AIOP 3 */
324#define CHAN2_EN 0x04 /* enable AIOP 2 */
325#define CHAN1_EN 0x02 /* enable AIOP 1 */
326#define CHAN0_EN 0x01 /* enable AIOP 0 */
327#define FREQ_DIS 0x00
328#define FREQ_274HZ 0x60
329#define FREQ_137HZ 0x50
330#define FREQ_69HZ 0x40
331#define FREQ_34HZ 0x30
332#define FREQ_17HZ 0x20
333#define FREQ_9HZ 0x10
334#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
335
336#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
337
338#define RDATASIZE 72
339#define RREGDATASIZE 52
340
341#ifndef TRUE
342#define TRUE 1
343#endif
344
345#ifndef FALSE
346#define FALSE 0
347#endif
348
349struct CONTROLLER_str;
350struct CHANNEL_str;
351
352/* The types of bus-specific methods */
353typedef int rp_aiop2rid_t(int, int);
354typedef int rp_aiop2off_t(int, int);
355typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
356
357/* Controller level information structure */
358struct CONTROLLER_str
359{
360 int CtlID;
361 int NumAiop;
362 int AiopID[AIOP_CTL_SIZE];
363 int AiopNumChan[AIOP_CTL_SIZE];
364
365 /* Device and resource management */
366 device_t dev; /* device */
367 int io_num; /* Number of IO resources */
368 int *io_rid; /* IO resource IDs */
369 struct resource **io; /* IO resources */
370
371 struct rp_port *rp; /* port */
372 struct tty *tty; /* tty */
373
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374 /* Bus-specific properties */
375 void *bus_ctlp;
376
377 /* Bus-specific methods */
378 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */
379 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */
380 rp_ctlmask_t *ctlmask; /* Int status */
381};
382typedef struct CONTROLLER_str CONTROLLER_T;
383typedef CONTROLLER_T CONTROLLER_t;
384
385/* Channel level information structure */
386struct CHANNEL_str
387{
388 CONTROLLER_t *CtlP;
389 int AiopNum;
390 int ChanID;
391 int ChanNum;
392
393 Word_t TxFIFO;
394 Word_t TxFIFOPtrs;
395 Word_t RxFIFO;
396 Word_t RxFIFOPtrs;
397 Word_t TxPrioCnt;
398 Word_t TxPrioPtr;
399 Word_t TxPrioBuf;
400
401 Byte_t R[RREGDATASIZE];
402
403 Byte_t BaudDiv[4];
404 Byte_t TxControl[4];
405 Byte_t RxControl[4];
406 Byte_t TxEnables[4];
407 Byte_t TxCompare[4];
408 Byte_t TxReplace1[4];
409 Byte_t TxReplace2[4];
410};
411
412typedef struct CHANNEL_str CHANNEL_T;
413typedef CHANNEL_T CHANNEL_t;
414typedef CHANNEL_T * CHANPTR_T;
415
416#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0)
417#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0)
418#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0)
419#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0)
420
421/***************************************************************************
422Function: sClrBreak
423Purpose: Stop sending a transmit BREAK signal
424Call: sClrBreak(ChP)
425 CHANNEL_T *ChP; Ptr to channel structure
426*/
427#define sClrBreak(ChP) \
428{ \
429 (ChP)->TxControl[3] &= ~SETBREAK; \
430 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
431}
432
433/***************************************************************************
434Function: sClrDTR
435Purpose: Clr the DTR output
436Call: sClrDTR(ChP)
437 CHANNEL_T *ChP; Ptr to channel structure
438*/
439#define sClrDTR(ChP) \
440{ \
441 (ChP)->TxControl[3] &= ~SET_DTR; \
442 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
443}
444
445/***************************************************************************
446Function: sClrRTS
447Purpose: Clr the RTS output
448Call: sClrRTS(ChP)
449 CHANNEL_T *ChP; Ptr to channel structure
450*/
451#define sClrRTS(ChP) \
452{ \
453 (ChP)->TxControl[3] &= ~SET_RTS; \
454 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
455}
456
457/***************************************************************************
458Function: sClrTxXOFF
459Purpose: Clear any existing transmit software flow control off condition
460Call: sClrTxXOFF(ChP)
461 CHANNEL_T *ChP; Ptr to channel structure
462*/
463#define sClrTxXOFF(ChP) \
464{ \
465 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
466 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
467}
468
469/***************************************************************************
470Function: sDisCTSFlowCtl
471Purpose: Disable output flow control using CTS
472Call: sDisCTSFlowCtl(ChP)
473 CHANNEL_T *ChP; Ptr to channel structure
474*/
475#define sDisCTSFlowCtl(ChP) \
476{ \
477 (ChP)->TxControl[2] &= ~CTSFC_EN; \
478 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
479}
480
481/***************************************************************************
482Function: DisParity
483Purpose: Disable parity
484Call: sDisParity(ChP)
485 CHANNEL_T *ChP; Ptr to channel structure
486Comments: Function sSetParity() can be used in place of functions sEnParity(),
487 sDisParity(), sSetOddParity(), and sSetEvenParity().
488*/
489#define sDisParity(ChP) \
490{ \
491 (ChP)->TxControl[2] &= ~PARITY_EN; \
492 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
493}
494
495/***************************************************************************
496Function: sDisRxFIFO
497Purpose: Disable Rx FIFO
498Call: sDisRxFIFO(ChP)
499 CHANNEL_T *ChP; Ptr to channel structure
500*/
501#define sDisRxFIFO(ChP) \
502{ \
503 (ChP)->R[0x32] = 0x0a; \
504 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
505}
506
507/***************************************************************************
508Function: sDisRxStatusMode
509Purpose: Disable the Rx status mode
510Call: sDisRxStatusMode(ChP)
511 CHANNEL_T *ChP; Ptr to channel structure
512Comments: This takes the channel out of the receive status mode. All
513 subsequent reads of receive data using sReadRxWord() will return
514 two data bytes.
515*/
516#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
517
518/***************************************************************************
519Function: sDisTransmit
520Purpose: Disable transmit
521Call: sDisTransmit(ChP)
522 CHANNEL_T *ChP; Ptr to channel structure
523 This disables movement of Tx data from the Tx FIFO into the 1 byte
524 Tx buffer. Therefore there could be up to a 2 byte latency
525 between the time sDisTransmit() is called and the transmit buffer
526 and transmit shift register going completely empty.
527*/
528#define sDisTransmit(ChP) \
529{ \
530 (ChP)->TxControl[3] &= ~TX_ENABLE; \
531 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
532}
533
534/***************************************************************************
535Function: sDisTxSoftFlowCtl
536Purpose: Disable Tx Software Flow Control
537Call: sDisTxSoftFlowCtl(ChP)
538 CHANNEL_T *ChP; Ptr to channel structure
539*/
540#define sDisTxSoftFlowCtl(ChP) \
541{ \
542 (ChP)->R[0x06] = 0x8a; \
543 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x04]); \
544}
545
546/***************************************************************************
547Function: sEnCTSFlowCtl
548Purpose: Enable output flow control using CTS
549Call: sEnCTSFlowCtl(ChP)
550 CHANNEL_T *ChP; Ptr to channel structure
551*/
552#define sEnCTSFlowCtl(ChP) \
553{ \
554 (ChP)->TxControl[2] |= CTSFC_EN; \
555 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
556}
557
558/***************************************************************************
559Function: EnParity
560Purpose: Enable parity
561Call: sEnParity(ChP)
562 CHANNEL_T *ChP; Ptr to channel structure
563Comments: Function sSetParity() can be used in place of functions sEnParity(),
564 sDisParity(), sSetOddParity(), and sSetEvenParity().
565
566Warnings: Before enabling parity odd or even parity should be chosen using
567 functions sSetOddParity() or sSetEvenParity().
568*/
569#define sEnParity(ChP) \
570{ \
571 (ChP)->TxControl[2] |= PARITY_EN; \
572 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
573}
574
575/***************************************************************************
576Function: sEnRTSFlowCtl
577Return: void
578*/
579#define sEnRTSFlowCtl(ChP) \
580{ \
581 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
582 (ChP)->TxControl[3] &= ~SET_RTS; \
583 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
584 (ChP)->RxControl[2] |= RTSFC_EN; \
585 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
586}
587
588/***************************************************************************
589Function: sDisRTSFlowCtl
590Return: void
591*/
592#define sDisRTSFlowCtl(ChP) \
593{ \
594 (ChP)->RxControl[2] &= ~RTSFC_EN; \
595 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
596}
597
598/***************************************************************************
599Function: sEnRxFIFO
600Purpose: Enable Rx FIFO
601Call: sEnRxFIFO(ChP)
602 CHANNEL_T *ChP; Ptr to channel structure
603*/
604#define sEnRxFIFO(ChP) \
605{ \
606 (ChP)->R[0x32] = 0x08; \
607 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
608}
609
610/***************************************************************************
611Function: sEnRxProcessor
612Purpose: Enable the receive processor
613Call: sEnRxProcessor(ChP)
614 CHANNEL_T *ChP; Ptr to channel structure
615Comments: This function is used to start the receive processor. When
616 the channel is in the reset state the receive processor is not
617 running. This is done to prevent the receive processor from
618 executing invalid microcode instructions prior to the
619 downloading of the microcode.
620
621Warnings: This function must be called after valid microcode has been
622 downloaded to the AIOP, and it must not be called before the
623 microcode has been downloaded.
624*/
625#define sEnRxProcessor(ChP) \
626{ \
627 (ChP)->RxControl[2] |= RXPROC_EN; \
628 rp_writech2(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
629}
630
631/***************************************************************************
632Function: sEnRxStatusMode
633Purpose: Enable the Rx status mode
634Call: sEnRxStatusMode(ChP)
635 CHANNEL_T *ChP; Ptr to channel structure
636Comments: This places the channel in the receive status mode. All subsequent
637 reads of receive data using sReadRxWord() will return a data byte
638 in the low word and a status byte in the high word.
639
640*/
641#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
642
643/***************************************************************************
644Function: sEnTransmit
645Purpose: Enable transmit
646Call: sEnTransmit(ChP)
647 CHANNEL_T *ChP; Ptr to channel structure
648*/
649#define sEnTransmit(ChP) \
650{ \
651 (ChP)->TxControl[3] |= TX_ENABLE; \
652 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
653}
654
655/***************************************************************************
656Function: sGetAiopIntStatus
657Purpose: Get the AIOP interrupt status
658Call: sGetAiopIntStatus(CtlP,AiopNum)
659 CONTROLLER_T *CtlP; Ptr to controller structure
660 int AiopNum; AIOP number
661Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
662 represent channels 0 through 7 respectively. If a
663 bit is set that channel is interrupting.
664*/
665#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
666
667/***************************************************************************
668Function: sGetAiopNumChan
669Purpose: Get the number of channels supported by an AIOP
670Call: sGetAiopNumChan(CtlP,AiopNum)
671 CONTROLLER_T *CtlP; Ptr to controller structure
672 int AiopNum; AIOP number
673Return: int: The number of channels supported by the AIOP
674*/
675#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
676
677/***************************************************************************
678Function: sGetChanIntID
679Purpose: Get a channel's interrupt identification byte
680Call: sGetChanIntID(ChP)
681 CHANNEL_T *ChP; Ptr to channel structure
682Return: Byte_t: The channel interrupt ID. Can be any
683 combination of the following flags:
684 RXF_TRIG: Rx FIFO trigger level interrupt
685 TXFIFO_MT: Tx FIFO empty interrupt
686 SRC_INT: Special receive condition interrupt
687 DELTA_CD: CD change interrupt
688 DELTA_CTS: CTS change interrupt
689 DELTA_DSR: DSR change interrupt
690*/
691#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
692
693/***************************************************************************
694Function: sGetChanNum
695Purpose: Get the number of a channel within an AIOP
696Call: sGetChanNum(ChP)
697 CHANNEL_T *ChP; Ptr to channel structure
698Return: int: Channel number within AIOP, or NULLCHAN if channel does
699 not exist.
700*/
701#define sGetChanNum(ChP) (ChP)->ChanNum
702
703/***************************************************************************
704Function: sGetChanStatus
705Purpose: Get the channel status
706Call: sGetChanStatus(ChP)
707 CHANNEL_T *ChP; Ptr to channel structure
708Return: Word_t: The channel status. Can be any combination of
709 the following flags:
710 LOW BYTE FLAGS
711 CTS_ACT: CTS input asserted
712 DSR_ACT: DSR input asserted
713 CD_ACT: CD input asserted
714 TXFIFOMT: Tx FIFO is empty
715 TXSHRMT: Tx shift register is empty
716 RDA: Rx data available
717
718 HIGH BYTE FLAGS
719 STATMODE: status mode enable bit
720 RXFOVERFL: receive FIFO overflow
721 RX2MATCH: receive compare byte 2 match
722 RX1MATCH: receive compare byte 1 match
723 RXBREAK: received BREAK
724 RXFRAME: received framing error
725 RXPARITY: received parity error
726Warnings: This function will clear the high byte flags in the Channel
727 Status Register.
728*/
729#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
730
731/***************************************************************************
732Function: sGetChanStatusLo
733Purpose: Get the low byte only of the channel status
734Call: sGetChanStatusLo(ChP)
735 CHANNEL_T *ChP; Ptr to channel structure
736Return: Byte_t: The channel status low byte. Can be any combination
737 of the following flags:
738 CTS_ACT: CTS input asserted
739 DSR_ACT: DSR input asserted
740 CD_ACT: CD input asserted
741 TXFIFOMT: Tx FIFO is empty
742 TXSHRMT: Tx shift register is empty
743 RDA: Rx data available
744*/
745#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
746
747/***************************************************************************
748Function: sGetRxCnt
749Purpose: Get the number of data bytes in the Rx FIFO
750Call: sGetRxCnt(ChP)
751 CHANNEL_T *ChP; Ptr to channel structure
752Return: int: The number of data bytes in the Rx FIFO.
753Comments: Byte read of count register is required to obtain Rx count.
754
755*/
756#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
757
758/***************************************************************************
759Function: sGetTxCnt
760Purpose: Get the number of data bytes in the Tx FIFO
761Call: sGetTxCnt(ChP)
762 CHANNEL_T *ChP; Ptr to channel structure
763Return: Byte_t: The number of data bytes in the Tx FIFO.
764Comments: Byte read of count register is required to obtain Tx count.
765
766*/
767#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
768
769/*****************************************************************************
770Function: sGetTxRxDataIO
771Purpose: Get the offset of a channel's TxRx Data register
772Call: sGetTxRxDataIO(ChP)
773 CHANNEL_T *ChP; Ptr to channel structure
774Return: WordIO_t: offset of a channel's TxRx Data register
775*/
776#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
777
778/***************************************************************************
779Function: sInitChanDefaults
780Purpose: Initialize a channel structure to its default state.
781Call: sInitChanDefaults(ChP)
782 CHANNEL_T *ChP; Ptr to the channel structure
783Comments: This function must be called once for every channel structure
784 that exists before any other SSCI calls can be made.
785
786*/
787#define sInitChanDefaults(ChP) \
788{ \
789 (ChP)->CtlP = NULLCTLPTR; \
790 (ChP)->AiopNum = NULLAIOP; \
791 (ChP)->ChanID = AIOPID_NULL; \
792 (ChP)->ChanNum = NULLCHAN; \
793}
794
795/***************************************************************************
796Function: sResetAiopByNum
797Purpose: Reset the AIOP by number
798Call: sResetAiopByNum(CTLP,AIOPNUM)
799 CONTROLLER_T CTLP; Ptr to controller structure
800 AIOPNUM; AIOP index
801*/
802#define sResetAiopByNum(CTLP,AIOPNUM) \
803{ \
804 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
805 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
806}
807
808/***************************************************************************
809Function: sSendBreak
810Purpose: Send a transmit BREAK signal
811Call: sSendBreak(ChP)
812 CHANNEL_T *ChP; Ptr to channel structure
813*/
814#define sSendBreak(ChP) \
815{ \
816 (ChP)->TxControl[3] |= SETBREAK; \
817 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
818}
819
820/***************************************************************************
821Function: sSetBaud
822Purpose: Set baud rate
823Call: sSetBaud(ChP,Divisor)
824 CHANNEL_T *ChP; Ptr to channel structure
825 Word_t Divisor; 16 bit baud rate divisor for channel
826*/
827#define sSetBaud(ChP,DIVISOR) \
828{ \
829 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
830 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
831 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->BaudDiv[0]); \
832}
833
834/***************************************************************************
835Function: sSetData7
836Purpose: Set data bits to 7
837Call: sSetData7(ChP)
838 CHANNEL_T *ChP; Ptr to channel structure
839*/
840#define sSetData7(ChP) \
841{ \
842 (ChP)->TxControl[2] &= ~DATA8BIT; \
843 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
844}
845
846/***************************************************************************
847Function: sSetData8
848Purpose: Set data bits to 8
849Call: sSetData8(ChP)
850 CHANNEL_T *ChP; Ptr to channel structure
851*/
852#define sSetData8(ChP) \
853{ \
854 (ChP)->TxControl[2] |= DATA8BIT; \
855 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
856}
857
858/***************************************************************************
859Function: sSetDTR
860Purpose: Set the DTR output
861Call: sSetDTR(ChP)
862 CHANNEL_T *ChP; Ptr to channel structure
863*/
864#define sSetDTR(ChP) \
865{ \
866 (ChP)->TxControl[3] |= SET_DTR; \
867 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
868}
869
870/***************************************************************************
871Function: sSetEvenParity
872Purpose: Set even parity
873Call: sSetEvenParity(ChP)
874 CHANNEL_T *ChP; Ptr to channel structure
875Comments: Function sSetParity() can be used in place of functions sEnParity(),
876 sDisParity(), sSetOddParity(), and sSetEvenParity().
877
878Warnings: This function has no effect unless parity is enabled with function
879 sEnParity().
880*/
881#define sSetEvenParity(ChP) \
882{ \
883 (ChP)->TxControl[2] |= EVEN_PAR; \
884 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
885}
886
887/***************************************************************************
888Function: sSetOddParity
889Purpose: Set odd parity
890Call: sSetOddParity(ChP)
891 CHANNEL_T *ChP; Ptr to channel structure
892Comments: Function sSetParity() can be used in place of functions sEnParity(),
893 sDisParity(), sSetOddParity(), and sSetEvenParity().
894
895Warnings: This function has no effect unless parity is enabled with function
896 sEnParity().
897*/
898#define sSetOddParity(ChP) \
899{ \
900 (ChP)->TxControl[2] &= ~EVEN_PAR; \
901 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
902}
903
904/***************************************************************************
905Function: sSetRTS
906Purpose: Set the RTS output
907Call: sSetRTS(ChP)
908 CHANNEL_T *ChP; Ptr to channel structure
909*/
910#define sSetRTS(ChP) \
911{ \
912 (ChP)->TxControl[3] |= SET_RTS; \
913 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
914}
915
916/***************************************************************************
917Function: sSetRxTrigger
918Purpose: Set the Rx FIFO trigger level
919Call: sSetRxProcessor(ChP,Level)
920 CHANNEL_T *ChP; Ptr to channel structure
921 Byte_t Level; Number of characters in Rx FIFO at which the
922 interrupt will be generated. Can be any of the following flags:
923
924 TRIG_NO: no trigger
925 TRIG_1: 1 character in FIFO
926 TRIG_1_2: FIFO 1/2 full
927 TRIG_7_8: FIFO 7/8 full
928Comments: An interrupt will be generated when the trigger level is reached
929 only if function sEnInterrupt() has been called with flag
930 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
931 register will be set whenever the trigger level is reached
932 regardless of the setting of RXINT_EN.
933
934*/
935#define sSetRxTrigger(ChP,LEVEL) \
936{ \
937 (ChP)->RxControl[2] &= ~TRIG_MASK; \
938 (ChP)->RxControl[2] |= LEVEL; \
939 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
940}
941
942/***************************************************************************
943Function: sSetStop1
944Purpose: Set stop bits to 1
945Call: sSetStop1(ChP)
946 CHANNEL_T *ChP; Ptr to channel structure
947*/
948#define sSetStop1(ChP) \
949{ \
950 (ChP)->TxControl[2] &= ~STOP2; \
951 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
952}
953
954/***************************************************************************
955Function: sSetStop2
956Purpose: Set stop bits to 2
957Call: sSetStop2(ChP)
958 CHANNEL_T *ChP; Ptr to channel structure
959*/
960#define sSetStop2(ChP) \
961{ \
962 (ChP)->TxControl[2] |= STOP2; \
963 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
964}
965
966/***************************************************************************
967Function: sStartRxProcessor
968Purpose: Start a channel's receive processor
969Call: sStartRxProcessor(ChP)
970 CHANNEL_T *ChP; Ptr to channel structure
971Comments: This function is used to start a Rx processor after it was
972 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
973 will restart both the Rx processor and software input flow control.
974
975*/
976#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0])
977
978/***************************************************************************
979Function: sWriteTxByte
980Purpose: Write a transmit data byte to a channel.
981 CHANNEL_T *ChP; Ptr to channel structure
982 ByteIO_t io: Channel transmit register I/O address. This can
983 be obtained with sGetTxRxDataIO().
984 Byte_t Data; The transmit data byte.
985Warnings: This function writes the data byte without checking to see if
986 sMaxTxSize is exceeded in the Tx FIFO.
987*/
988#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
989
990int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
991int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
992int sInitChan( CONTROLLER_T *CtlP,
993 CHANNEL_T *ChP,
994 int AiopNum,
995 int ChanNum);
996Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
997void sStopRxProcessor(CHANNEL_T *ChP);
998void sStopSWInFlowCtl(CHANNEL_T *ChP);
999void sFlushRxFIFO(CHANNEL_T *ChP);
1000void sFlushTxFIFO(CHANNEL_T *ChP);
1001int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1002void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1003void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1004int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
1005void rp_releaseresource(CONTROLLER_t *ctlp);
1006
1007#ifndef ROCKET_C
1008extern Byte_t R[RDATASIZE];
1009extern CONTROLLER_T sController[CTL_SIZE];
1010extern Byte_t sIRQMap[16];
1011#endif
1012extern Byte_t rp_sBitMapClrTbl[8];
1013extern Byte_t rp_sBitMapSetTbl[8];