bge: Add comment about coalesce parameters during interrupt
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
011c0f93 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
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34 */
35
36/*
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
41 */
42
43/*
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
54 * into the driver.
55 *
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58 *
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
62 *
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
65 *
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
70 * ring.
71 */
72
315fe0ee 73#include "opt_polling.h"
a7db2caa 74
984263bc 75#include <sys/param.h>
62be1357 76#include <sys/bus.h>
20c9a969 77#include <sys/endian.h>
62be1357 78#include <sys/kernel.h>
6b880771 79#include <sys/ktr.h>
9db4b353 80#include <sys/interrupt.h>
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81#include <sys/mbuf.h>
82#include <sys/malloc.h>
984263bc 83#include <sys/queue.h>
62be1357 84#include <sys/rman.h>
16dca0df 85#include <sys/serialize.h>
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86#include <sys/socket.h>
87#include <sys/sockio.h>
055d06f0 88#include <sys/sysctl.h>
984263bc 89
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90#include <net/bpf.h>
91#include <net/ethernet.h>
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92#include <net/if.h>
93#include <net/if_arp.h>
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94#include <net/if_dl.h>
95#include <net/if_media.h>
984263bc 96#include <net/if_types.h>
62be1357 97#include <net/ifq_var.h>
1f2de5d4 98#include <net/vlan/if_vlan_var.h>
b637f170 99#include <net/vlan/if_vlan_ether.h>
984263bc 100
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101#include <dev/netif/mii_layer/mii.h>
102#include <dev/netif/mii_layer/miivar.h>
1f2de5d4 103#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 104
f952ab63 105#include <bus/pci/pcidevs.h>
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106#include <bus/pci/pcireg.h>
107#include <bus/pci/pcivar.h>
984263bc 108
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109#include <dev/netif/bge/if_bgereg.h>
110
111/* "device miibus" required. See GENERIC if you get errors here. */
112#include "miibus_if.h"
984263bc 113
3daed3db 114#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
cb623c48 115#define BGE_MIN_FRAME 60
984263bc 116
d265721a 117static const struct bge_type bge_devs[] = {
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118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119 "3COM 3C996 Gigabit Ethernet" },
120
f952ab63 121 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
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122 "Alteon BCM5700 Gigabit Ethernet" },
123 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124 "Alteon BCM5701 Gigabit Ethernet" },
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125
126 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127 "Altima AC1000 Gigabit Ethernet" },
128 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129 "Altima AC1002 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131 "Altima AC9100 Gigabit Ethernet" },
132
133 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134 "Apple BCM5701 Gigabit Ethernet" },
135
f952ab63 136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
984263bc 137 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
984263bc 139 "Broadcom BCM5701 Gigabit Ethernet" },
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140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141 "Broadcom BCM5702 Gigabit Ethernet" },
f952ab63 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
984263bc 143 "Broadcom BCM5702X Gigabit Ethernet" },
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144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145 "Broadcom BCM5702 Gigabit Ethernet" },
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146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147 "Broadcom BCM5703 Gigabit Ethernet" },
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148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149 "Broadcom BCM5703X Gigabit Ethernet" },
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150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151 "Broadcom BCM5703 Gigabit Ethernet" },
f952ab63 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
984263bc 153 "Broadcom BCM5704C Dual Gigabit Ethernet" },
f952ab63 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
984263bc 155 "Broadcom BCM5704S Dual Gigabit Ethernet" },
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156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157 "Broadcom BCM5704S Dual Gigabit Ethernet" },
f952ab63 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
7e40b8c5 159 "Broadcom BCM5705 Gigabit Ethernet" },
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160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161 "Broadcom BCM5705F Gigabit Ethernet" },
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162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163 "Broadcom BCM5705K Gigabit Ethernet" },
f952ab63 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
7e40b8c5 165 "Broadcom BCM5705M Gigabit Ethernet" },
9a6ee7e2 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
7e40b8c5 167 "Broadcom BCM5705M Gigabit Ethernet" },
92decf65 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
9a6ee7e2 169 "Broadcom BCM5714C Gigabit Ethernet" },
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170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171 "Broadcom BCM5714S Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173 "Broadcom BCM5715 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175 "Broadcom BCM5715S Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177 "Broadcom BCM5720 Gigabit Ethernet" },
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178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179 "Broadcom BCM5721 Gigabit Ethernet" },
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180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181 "Broadcom BCM5722 Gigabit Ethernet" },
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182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183 "Broadcom BCM5723 Gigabit Ethernet" },
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184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185 "Broadcom BCM5750 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187 "Broadcom BCM5750M Gigabit Ethernet" },
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188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189 "Broadcom BCM5751 Gigabit Ethernet" },
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190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191 "Broadcom BCM5751F Gigabit Ethernet" },
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192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193 "Broadcom BCM5751M Gigabit Ethernet" },
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194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195 "Broadcom BCM5752 Gigabit Ethernet" },
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196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197 "Broadcom BCM5752M Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199 "Broadcom BCM5753 Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201 "Broadcom BCM5753F Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203 "Broadcom BCM5753M Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205 "Broadcom BCM5754 Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207 "Broadcom BCM5754M Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209 "Broadcom BCM5755 Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211 "Broadcom BCM5755M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213 "Broadcom BCM5756 Gigabit Ethernet" },
f47afe1a
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214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215 "Broadcom BCM5761 Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217 "Broadcom BCM5761E Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219 "Broadcom BCM5761S Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221 "Broadcom BCM5761SE Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223 "Broadcom BCM5764 Gigabit Ethernet" },
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224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225 "Broadcom BCM5780 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227 "Broadcom BCM5780S Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229 "Broadcom BCM5781 Gigabit Ethernet" },
f952ab63 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
7e40b8c5 231 "Broadcom BCM5782 Gigabit Ethernet" },
f47afe1a
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232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233 "Broadcom BCM5784 Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235 "Broadcom BCM5785F Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237 "Broadcom BCM5785G Gigabit Ethernet" },
0ecb11d7
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238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239 "Broadcom BCM5786 Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241 "Broadcom BCM5787 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243 "Broadcom BCM5787F Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245 "Broadcom BCM5787M Gigabit Ethernet" },
9a6ee7e2 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
f952ab63 247 "Broadcom BCM5788 Gigabit Ethernet" },
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248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249 "Broadcom BCM5789 Gigabit Ethernet" },
f952ab63
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250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251 "Broadcom BCM5901 Fast Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253 "Broadcom BCM5901A2 Fast Ethernet" },
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254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255 "Broadcom BCM5903M Fast Ethernet" },
591dfc77
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256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257 "Broadcom BCM5906 Fast Ethernet"},
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259 "Broadcom BCM5906M Fast Ethernet"},
f47afe1a
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260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261 "Broadcom BCM57760 Gigabit Ethernet"},
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263 "Broadcom BCM57780 Gigabit Ethernet"},
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265 "Broadcom BCM57788 Gigabit Ethernet"},
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267 "Broadcom BCM57790 Gigabit Ethernet"},
f952ab63 268 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
984263bc 269 "SysKonnect Gigabit Ethernet" },
0ecb11d7 270
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271 { 0, 0, NULL }
272};
273
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274#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
275#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
f47afe1a 279#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
5225ba10 280#define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788)
0ecb11d7 281
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282typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
283
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284static int bge_probe(device_t);
285static int bge_attach(device_t);
286static int bge_detach(device_t);
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287static void bge_txeof(struct bge_softc *, uint16_t);
288static void bge_rxeof(struct bge_softc *, uint16_t);
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289
290static void bge_tick(void *);
291static void bge_stats_update(struct bge_softc *);
292static void bge_stats_update_regs(struct bge_softc *);
e0b35c1f
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293static struct mbuf *
294 bge_defrag_shortdma(struct mbuf *);
4a607ed6 295static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
33c39a69 296
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297#ifdef DEVICE_POLLING
298static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
299#endif
33c39a69 300static void bge_intr(void *);
90ad1c96 301static void bge_intr_status_tag(void *);
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302static void bge_enable_intr(struct bge_softc *);
303static void bge_disable_intr(struct bge_softc *);
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304static void bge_start(struct ifnet *);
305static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
306static void bge_init(void *);
307static void bge_stop(struct bge_softc *);
308static void bge_watchdog(struct ifnet *);
309static void bge_shutdown(device_t);
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310static int bge_suspend(device_t);
311static int bge_resume(device_t);
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312static int bge_ifmedia_upd(struct ifnet *);
313static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
314
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315static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
316static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
317
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318static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
319static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
320
33c39a69 321static void bge_setmulti(struct bge_softc *);
6439b28a 322static void bge_setpromisc(struct bge_softc *);
33c39a69 323
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324static int bge_alloc_jumbo_mem(struct bge_softc *);
325static void bge_free_jumbo_mem(struct bge_softc *);
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326static struct bge_jslot
327 *bge_jalloc(struct bge_softc *);
328static void bge_jfree(void *);
329static void bge_jref(void *);
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330static int bge_newbuf_std(struct bge_softc *, int, int);
331static int bge_newbuf_jumbo(struct bge_softc *, int, int);
332static void bge_setup_rxdesc_std(struct bge_softc *, int);
333static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
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334static int bge_init_rx_ring_std(struct bge_softc *);
335static void bge_free_rx_ring_std(struct bge_softc *);
336static int bge_init_rx_ring_jumbo(struct bge_softc *);
337static void bge_free_rx_ring_jumbo(struct bge_softc *);
338static void bge_free_tx_ring(struct bge_softc *);
339static int bge_init_tx_ring(struct bge_softc *);
340
341static int bge_chipinit(struct bge_softc *);
342static int bge_blockinit(struct bge_softc *);
6ac6e1b9 343static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
984263bc 344
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345static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
346static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
984263bc 347#ifdef notdef
33c39a69 348static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
984263bc 349#endif
33c39a69 350static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
0ecb11d7 351static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
591dfc77 352static void bge_writembx(struct bge_softc *, int, int);
984263bc 353
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354static int bge_miibus_readreg(device_t, int, int);
355static int bge_miibus_writereg(device_t, int, int, int);
356static void bge_miibus_statchg(device_t);
db861466
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357static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
358static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
359static void bge_copper_link_upd(struct bge_softc *, uint32_t);
2dd0af35 360static void bge_autopoll_link_upd(struct bge_softc *, uint32_t);
984263bc 361
33c39a69 362static void bge_reset(struct bge_softc *);
984263bc 363
20c9a969
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364static int bge_dma_alloc(struct bge_softc *);
365static void bge_dma_free(struct bge_softc *);
366static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
367 bus_dma_tag_t *, bus_dmamap_t *,
368 void **, bus_addr_t *);
369static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
370
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371static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
372static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
373static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
374static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
375
055d06f0
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376static void bge_coal_change(struct bge_softc *);
377static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
378static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
90ad1c96
SZ
379static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
380static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
381static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
382static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
383static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
384static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
055d06f0
SZ
385static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
386
5c56d5d8
SZ
387/*
388 * Set following tunable to 1 for some IBM blade servers with the DNLK
389 * switch module. Auto negotiation is broken for those configurations.
390 */
391static int bge_fake_autoneg = 0;
392TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
393
6b880771
SZ
394#if !defined(KTR_IF_BGE)
395#define KTR_IF_BGE KTR_ALL
396#endif
397KTR_INFO_MASTER(if_bge);
5bf48697
AE
398KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
399KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
400KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
6b880771
SZ
401#define logif(name) KTR_LOG(if_bge_ ## name)
402
984263bc
MD
403static device_method_t bge_methods[] = {
404 /* Device interface */
405 DEVMETHOD(device_probe, bge_probe),
406 DEVMETHOD(device_attach, bge_attach),
407 DEVMETHOD(device_detach, bge_detach),
408 DEVMETHOD(device_shutdown, bge_shutdown),
aa65409c
SZ
409 DEVMETHOD(device_suspend, bge_suspend),
410 DEVMETHOD(device_resume, bge_resume),
984263bc
MD
411
412 /* bus interface */
413 DEVMETHOD(bus_print_child, bus_generic_print_child),
414 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
415
416 /* MII interface */
417 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
418 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
419 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
420
421 { 0, 0 }
422};
423
33c39a69 424static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
984263bc
MD
425static devclass_t bge_devclass;
426
32832096 427DECLARE_DUMMY_MODULE(if_bge);
aa2b9d05
SW
428DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
429DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
984263bc 430
33c39a69
JS
431static uint32_t
432bge_readmem_ind(struct bge_softc *sc, uint32_t off)
984263bc 433{
33c39a69 434 device_t dev = sc->bge_dev;
0ecb11d7 435 uint32_t val;
984263bc 436
81418829
SZ
437 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
438 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
439 return 0;
440
984263bc 441 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
0ecb11d7
SZ
442 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
443 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
444 return (val);
984263bc
MD
445}
446
447static void
33c39a69 448bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 449{
33c39a69 450 device_t dev = sc->bge_dev;
984263bc 451
81418829
SZ
452 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
453 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
454 return;
455
984263bc
MD
456 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
457 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
0ecb11d7 458 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
984263bc
MD
459}
460
461#ifdef notdef
33c39a69
JS
462static uint32_t
463bge_readreg_ind(struct bge_softc *sc, uin32_t off)
984263bc 464{
33c39a69 465 device_t dev = sc->bge_dev;
984263bc
MD
466
467 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
468 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
469}
470#endif
471
472static void
33c39a69 473bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 474{
33c39a69 475 device_t dev = sc->bge_dev;
984263bc
MD
476
477 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
478 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
984263bc
MD
479}
480
0ecb11d7
SZ
481static void
482bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
483{
484 CSR_WRITE_4(sc, off, val);
485}
486
591dfc77
SZ
487static void
488bge_writembx(struct bge_softc *sc, int off, int val)
489{
490 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
491 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
492
493 CSR_WRITE_4(sc, off, val);
e8b8fe83
SZ
494 if (sc->bge_mbox_reorder)
495 CSR_READ_4(sc, off);
591dfc77
SZ
496}
497
498static uint8_t
499bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
500{
501 uint32_t access, byte = 0;
502 int i;
503
504 /* Lock. */
505 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
506 for (i = 0; i < 8000; i++) {
507 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
508 break;
509 DELAY(20);
510 }
511 if (i == 8000)
512 return (1);
513
514 /* Enable access. */
515 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
516 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
517
518 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
519 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
520 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
521 DELAY(10);
522 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
523 DELAY(10);
524 break;
525 }
526 }
527
528 if (i == BGE_TIMEOUT * 10) {
529 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
530 return (1);
531 }
532
533 /* Get result. */
534 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
535
536 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
537
538 /* Disable access. */
539 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
540
541 /* Unlock. */
542 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
543 CSR_READ_4(sc, BGE_NVRAM_SWARB);
544
545 return (0);
546}
547
548/*
549 * Read a sequence of bytes from NVRAM.
550 */
551static int
552bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
553{
554 int err = 0, i;
555 uint8_t byte = 0;
556
557 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
558 return (1);
559
560 for (i = 0; i < cnt; i++) {
561 err = bge_nvram_getbyte(sc, off + i, &byte);
562 if (err)
563 break;
564 *(dest + i) = byte;
565 }
566
567 return (err ? 1 : 0);
568}
569
984263bc
MD
570/*
571 * Read a byte of data stored in the EEPROM at address 'addr.' The
572 * BCM570x supports both the traditional bitbang interface and an
573 * auto access interface for reading the EEPROM. We use the auto
574 * access method.
575 */
33c39a69
JS
576static uint8_t
577bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
984263bc
MD
578{
579 int i;
33c39a69 580 uint32_t byte = 0;
984263bc
MD
581
582 /*
583 * Enable use of auto EEPROM access so we can avoid
584 * having to use the bitbang method.
585 */
586 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
587
588 /* Reset the EEPROM, load the clock period. */
589 CSR_WRITE_4(sc, BGE_EE_ADDR,
590 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
591 DELAY(20);
592
593 /* Issue the read EEPROM command. */
594 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
595
596 /* Wait for completion */
597 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
598 DELAY(10);
599 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
600 break;
601 }
602
603 if (i == BGE_TIMEOUT) {
c6fd6f3b 604 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
7b47d9c2 605 return(1);
984263bc
MD
606 }
607
608 /* Get result. */
609 byte = CSR_READ_4(sc, BGE_EE_DATA);
610
611 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
612
613 return(0);
614}
615
616/*
617 * Read a sequence of bytes from the EEPROM.
618 */
619static int
33c39a69 620bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
984263bc 621{
33c39a69
JS
622 size_t i;
623 int err;
624 uint8_t byte;
984263bc 625
33c39a69 626 for (byte = 0, err = 0, i = 0; i < len; i++) {
984263bc
MD
627 err = bge_eeprom_getbyte(sc, off + i, &byte);
628 if (err)
629 break;
630 *(dest + i) = byte;
631 }
632
633 return(err ? 1 : 0);
634}
635
636static int
33c39a69 637bge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 638{
f7a1f3ba 639 struct bge_softc *sc = device_get_softc(dev);
2dd0af35 640 uint32_t val;
984263bc
MD
641 int i;
642
fd894027
SZ
643 KASSERT(phy == sc->bge_phyno,
644 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
984263bc 645
2dd0af35
SZ
646 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
647 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
648 CSR_WRITE_4(sc, BGE_MI_MODE,
649 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
650 DELAY(80);
984263bc
MD
651 }
652
2dd0af35
SZ
653 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
654 BGE_MIPHY(phy) | BGE_MIREG(reg));
984263bc 655
2dd0af35 656 /* Poll for the PHY register access to complete. */
984263bc 657 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba 658 DELAY(10);
984263bc 659 val = CSR_READ_4(sc, BGE_MI_COMM);
2dd0af35
SZ
660 if ((val & BGE_MICOMM_BUSY) == 0) {
661 DELAY(5);
662 val = CSR_READ_4(sc, BGE_MI_COMM);
984263bc 663 break;
2dd0af35 664 }
984263bc 665 }
984263bc 666 if (i == BGE_TIMEOUT) {
2dd0af35
SZ
667 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
668 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
984263bc 669 val = 0;
984263bc
MD
670 }
671
2dd0af35
SZ
672 /* Restore the autopoll bit if necessary. */
673 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
674 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
675 DELAY(80);
984263bc
MD
676 }
677
678 if (val & BGE_MICOMM_READFAIL)
2dd0af35 679 return 0;
984263bc 680
2dd0af35 681 return (val & 0xFFFF);
984263bc
MD
682}
683
684static int
33c39a69 685bge_miibus_writereg(device_t dev, int phy, int reg, int val)
984263bc 686{
f7a1f3ba 687 struct bge_softc *sc = device_get_softc(dev);
984263bc
MD
688 int i;
689
fd894027
SZ
690 KASSERT(phy == sc->bge_phyno,
691 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
984263bc 692
591dfc77
SZ
693 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
694 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
2dd0af35 695 return 0;
591dfc77 696
2dd0af35
SZ
697 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
698 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
699 CSR_WRITE_4(sc, BGE_MI_MODE,
700 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
701 DELAY(80);
984263bc
MD
702 }
703
2dd0af35
SZ
704 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
705 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
984263bc
MD
706
707 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba
SZ
708 DELAY(10);
709 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
710 DELAY(5);
711 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
984263bc 712 break;
f7a1f3ba 713 }
984263bc 714 }
984263bc 715 if (i == BGE_TIMEOUT) {
f7a1f3ba 716 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
2dd0af35 717 "(phy %d, reg %d, val %d)\n", phy, reg, val);
984263bc
MD
718 }
719
2dd0af35
SZ
720 /* Restore the autopoll bit if necessary. */
721 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
722 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
723 DELAY(80);
724 }
725
726 return 0;
984263bc
MD
727}
728
729static void
33c39a69 730bge_miibus_statchg(device_t dev)
984263bc
MD
731{
732 struct bge_softc *sc;
733 struct mii_data *mii;
734
735 sc = device_get_softc(dev);
736 mii = device_get_softc(sc->bge_miibus);
737
2dd0af35
SZ
738 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
739 (IFM_ACTIVE | IFM_AVALID)) {
740 switch (IFM_SUBTYPE(mii->mii_media_active)) {
741 case IFM_10_T:
742 case IFM_100_TX:
743 sc->bge_link = 1;
744 break;
745 case IFM_1000_T:
746 case IFM_1000_SX:
747 case IFM_2500_SX:
748 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
749 sc->bge_link = 1;
750 else
751 sc->bge_link = 0;
752 break;
753 default:
754 sc->bge_link = 0;
755 break;
756 }
757 } else {
758 sc->bge_link = 0;
759 }
760 if (sc->bge_link == 0)
761 return;
762
984263bc 763 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
4d38e186
SZ
764 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
765 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
984263bc
MD
766 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
767 } else {
768 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
769 }
770
771 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
772 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
773 } else {
774 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
775 }
984263bc
MD
776}
777
984263bc
MD
778/*
779 * Memory management for jumbo frames.
780 */
984263bc 781static int
33c39a69 782bge_alloc_jumbo_mem(struct bge_softc *sc)
984263bc 783{
20c9a969 784 struct ifnet *ifp = &sc->arpcom.ac_if;
2aa9b12f 785 struct bge_jslot *entry;
20c9a969
SZ
786 uint8_t *ptr;
787 bus_addr_t paddr;
788 int i, error;
984263bc 789
20c9a969
SZ
790 /*
791 * Create tag for jumbo mbufs.
792 * This is really a bit of a kludge. We allocate a special
793 * jumbo buffer pool which (thanks to the way our DMA
794 * memory allocation works) will consist of contiguous
795 * pages. This means that even though a jumbo buffer might
796 * be larger than a page size, we don't really need to
797 * map it into more than one DMA segment. However, the
798 * default mbuf tag will result in multi-segment mappings,
799 * so we have to create a special jumbo mbuf tag that
800 * lets us get away with mapping the jumbo buffers as
801 * a single segment. I think eventually the driver should
802 * be changed so that it uses ordinary mbufs and cluster
803 * buffers, i.e. jumbo frames can span multiple DMA
804 * descriptors. But that's a project for another day.
805 */
984263bc 806
20c9a969
SZ
807 /*
808 * Create DMA stuffs for jumbo RX ring.
809 */
810 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
811 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
812 &sc->bge_cdata.bge_rx_jumbo_ring_map,
da44240f 813 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
20c9a969
SZ
814 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
815 if (error) {
816 if_printf(ifp, "could not create jumbo RX ring\n");
817 return error;
818 }
819
820 /*
821 * Create DMA stuffs for jumbo buffer block.
822 */
823 error = bge_dma_block_alloc(sc, BGE_JMEM,
824 &sc->bge_cdata.bge_jumbo_tag,
825 &sc->bge_cdata.bge_jumbo_map,
826 (void **)&sc->bge_ldata.bge_jumbo_buf,
827 &paddr);
828 if (error) {
829 if_printf(ifp, "could not create jumbo buffer\n");
830 return error;
984263bc
MD
831 }
832
833 SLIST_INIT(&sc->bge_jfree_listhead);
984263bc
MD
834
835 /*
836 * Now divide it up into 9K pieces and save the addresses
837 * in an array. Note that we play an evil trick here by using
838 * the first few bytes in the buffer to hold the the address
839 * of the softc structure for this interface. This is because
840 * bge_jfree() needs it, but it is called by the mbuf management
841 * code which will not pass it to us explicitly.
842 */
20c9a969 843 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
2aa9b12f
JS
844 entry = &sc->bge_cdata.bge_jslots[i];
845 entry->bge_sc = sc;
846 entry->bge_buf = ptr;
20c9a969 847 entry->bge_paddr = paddr;
2aa9b12f
JS
848 entry->bge_inuse = 0;
849 entry->bge_slot = i;
850 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
20c9a969 851
2aa9b12f 852 ptr += BGE_JLEN;
20c9a969 853 paddr += BGE_JLEN;
984263bc 854 }
20c9a969 855 return 0;
984263bc
MD
856}
857
858static void
33c39a69 859bge_free_jumbo_mem(struct bge_softc *sc)
984263bc 860{
20c9a969
SZ
861 /* Destroy jumbo RX ring. */
862 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
863 sc->bge_cdata.bge_rx_jumbo_ring_map,
864 sc->bge_ldata.bge_rx_jumbo_ring);
865
866 /* Destroy jumbo buffer block. */
867 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
868 sc->bge_cdata.bge_jumbo_map,
869 sc->bge_ldata.bge_jumbo_buf);
984263bc
MD
870}
871
872/*
873 * Allocate a jumbo buffer.
874 */
2aa9b12f 875static struct bge_jslot *
33c39a69 876bge_jalloc(struct bge_softc *sc)
984263bc 877{
2aa9b12f 878 struct bge_jslot *entry;
33c39a69 879
16dca0df 880 lwkt_serialize_enter(&sc->bge_jslot_serializer);
984263bc 881 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
16dca0df
MD
882 if (entry) {
883 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
884 entry->bge_inuse = 1;
885 } else {
c6fd6f3b 886 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
984263bc 887 }
16dca0df 888 lwkt_serialize_exit(&sc->bge_jslot_serializer);
2aa9b12f 889 return(entry);
984263bc
MD
890}
891
892/*
893 * Adjust usage count on a jumbo buffer.
894 */
895static void
2aa9b12f 896bge_jref(void *arg)
984263bc 897{
2aa9b12f
JS
898 struct bge_jslot *entry = (struct bge_jslot *)arg;
899 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
900
901 if (sc == NULL)
902 panic("bge_jref: can't find softc pointer!");
903
16dca0df 904 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc
MD
905 panic("bge_jref: asked to reference buffer "
906 "that we don't manage!");
16dca0df 907 } else if (entry->bge_inuse == 0) {
984263bc 908 panic("bge_jref: buffer already free!");
16dca0df
MD
909 } else {
910 atomic_add_int(&entry->bge_inuse, 1);
911 }
984263bc
MD
912}
913
914/*
915 * Release a jumbo buffer.
916 */
917static void
2aa9b12f 918bge_jfree(void *arg)
984263bc 919{
2aa9b12f
JS
920 struct bge_jslot *entry = (struct bge_jslot *)arg;
921 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
922
923 if (sc == NULL)
924 panic("bge_jfree: can't find softc pointer!");
925
16dca0df 926 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc 927 panic("bge_jfree: asked to free buffer that we don't manage!");
16dca0df 928 } else if (entry->bge_inuse == 0) {
984263bc 929 panic("bge_jfree: buffer already free!");
16dca0df
MD
930 } else {
931 /*
932 * Possible MP race to 0, use the serializer. The atomic insn
933 * is still needed for races against bge_jref().
934 */
935 lwkt_serialize_enter(&sc->bge_jslot_serializer);
936 atomic_subtract_int(&entry->bge_inuse, 1);
937 if (entry->bge_inuse == 0) {
938 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
939 entry, jslot_link);
940 }
941 lwkt_serialize_exit(&sc->bge_jslot_serializer);
942 }
984263bc
MD
943}
944
945
946/*
947 * Intialize a standard receive ring descriptor.
948 */
949static int
1436f9a0 950bge_newbuf_std(struct bge_softc *sc, int i, int init)
984263bc 951{
33c39a69 952 struct mbuf *m_new = NULL;
20c9a969 953 bus_dma_segment_t seg;
1436f9a0 954 bus_dmamap_t map;
2de621e9 955 int error, nsegs;
984263bc 956
1436f9a0
SZ
957 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
958 if (m_new == NULL)
959 return ENOBUFS;
20c9a969 960 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
984263bc 961
0ecb11d7 962 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
984263bc 963 m_adj(m_new, ETHER_ALIGN);
20c9a969 964
2de621e9
SZ
965 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
966 sc->bge_cdata.bge_rx_tmpmap, m_new,
967 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
968 if (error) {
1436f9a0 969 m_freem(m_new);
2de621e9 970 return error;
20c9a969
SZ
971 }
972
1436f9a0
SZ
973 if (!init) {
974 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
975 sc->bge_cdata.bge_rx_std_dmamap[i],
976 BUS_DMASYNC_POSTREAD);
977 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
978 sc->bge_cdata.bge_rx_std_dmamap[i]);
979 }
20c9a969 980
1436f9a0
SZ
981 map = sc->bge_cdata.bge_rx_tmpmap;
982 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
983 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
984
985 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
2de621e9 986 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1436f9a0
SZ
987
988 bge_setup_rxdesc_std(sc, i);
20c9a969 989 return 0;
984263bc
MD
990}
991
1436f9a0
SZ
992static void
993bge_setup_rxdesc_std(struct bge_softc *sc, int i)
994{
995 struct bge_rxchain *rc;
996 struct bge_rx_bd *r;
997
998 rc = &sc->bge_cdata.bge_rx_std_chain[i];
999 r = &sc->bge_ldata.bge_rx_std_ring[i];
1000
1001 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1002 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1003 r->bge_len = rc->bge_mbuf->m_len;
1004 r->bge_idx = i;
1005 r->bge_flags = BGE_RXBDFLAG_END;
1006}
1007
984263bc
MD
1008/*
1009 * Initialize a jumbo receive ring descriptor. This allocates
1010 * a jumbo buffer from the pool managed internally by the driver.
1011 */
1012static int
1436f9a0 1013bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
984263bc
MD
1014{
1015 struct mbuf *m_new = NULL;
20c9a969 1016 struct bge_jslot *buf;
20c9a969 1017 bus_addr_t paddr;
984263bc 1018
1436f9a0
SZ
1019 /* Allocate the mbuf. */
1020 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1021 if (m_new == NULL)
1022 return ENOBUFS;
2aa9b12f 1023
1436f9a0
SZ
1024 /* Allocate the jumbo buffer */
1025 buf = bge_jalloc(sc);
1026 if (buf == NULL) {
1027 m_freem(m_new);
1028 return ENOBUFS;
984263bc 1029 }
1436f9a0
SZ
1030
1031 /* Attach the buffer to the mbuf. */
1032 m_new->m_ext.ext_arg = buf;
1033 m_new->m_ext.ext_buf = buf->bge_buf;
1034 m_new->m_ext.ext_free = bge_jfree;
1035 m_new->m_ext.ext_ref = bge_jref;
1036 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1037
1038 m_new->m_flags |= M_EXT;
1039
20c9a969
SZ
1040 m_new->m_data = m_new->m_ext.ext_buf;
1041 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc 1042
20c9a969 1043 paddr = buf->bge_paddr;
0ecb11d7 1044 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
984263bc 1045 m_adj(m_new, ETHER_ALIGN);
20c9a969
SZ
1046 paddr += ETHER_ALIGN;
1047 }
1048
1436f9a0
SZ
1049 /* Save necessary information */
1050 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1051 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1052
984263bc 1053 /* Set up the descriptor. */
1436f9a0
SZ
1054 bge_setup_rxdesc_jumbo(sc, i);
1055 return 0;
1056}
1057
1058static void
1059bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1060{
1061 struct bge_rx_bd *r;
1062 struct bge_rxchain *rc;
20c9a969
SZ
1063
1064 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1436f9a0 1065 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
984263bc 1066
1436f9a0
SZ
1067 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1068 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1069 r->bge_len = rc->bge_mbuf->m_len;
1070 r->bge_idx = i;
1071 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
984263bc
MD
1072}
1073
984263bc 1074static int
33c39a69 1075bge_init_rx_ring_std(struct bge_softc *sc)
984263bc 1076{
1436f9a0 1077 int i, error;
984263bc 1078
1436f9a0
SZ
1079 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1080 error = bge_newbuf_std(sc, i, 1);
1081 if (error)
1082 return error;
984263bc
MD
1083 };
1084
1436f9a0 1085 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
591dfc77 1086 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc
MD
1087
1088 return(0);
1089}
1090
1091static void
33c39a69 1092bge_free_rx_ring_std(struct bge_softc *sc)
984263bc
MD
1093{
1094 int i;
1095
1096 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1436f9a0
SZ
1097 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1098
1099 if (rc->bge_mbuf != NULL) {
ddca511d 1100 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
20c9a969 1101 sc->bge_cdata.bge_rx_std_dmamap[i]);
1436f9a0
SZ
1102 m_freem(rc->bge_mbuf);
1103 rc->bge_mbuf = NULL;
984263bc 1104 }
20c9a969 1105 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
984263bc
MD
1106 sizeof(struct bge_rx_bd));
1107 }
984263bc
MD
1108}
1109
1110static int
33c39a69 1111bge_init_rx_ring_jumbo(struct bge_softc *sc)
984263bc 1112{
984263bc 1113 struct bge_rcb *rcb;
1436f9a0 1114 int i, error;
984263bc
MD
1115
1116 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1117 error = bge_newbuf_jumbo(sc, i, 1);
1118 if (error)
1119 return error;
984263bc
MD
1120 };
1121
1436f9a0 1122 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
984263bc 1123
20c9a969 1124 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
984263bc
MD
1125 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1126 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1127
591dfc77 1128 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
1129
1130 return(0);
1131}
1132
1133static void
33c39a69 1134bge_free_rx_ring_jumbo(struct bge_softc *sc)
984263bc
MD
1135{
1136 int i;
1137
1138 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1139 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1140
1141 if (rc->bge_mbuf != NULL) {
1142 m_freem(rc->bge_mbuf);
1143 rc->bge_mbuf = NULL;
984263bc 1144 }
20c9a969 1145 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
984263bc
MD
1146 sizeof(struct bge_rx_bd));
1147 }
984263bc
MD
1148}
1149
1150static void
33c39a69 1151bge_free_tx_ring(struct bge_softc *sc)
984263bc
MD
1152{
1153 int i;
1154
984263bc
MD
1155 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1156 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
ddca511d 1157 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 1158 sc->bge_cdata.bge_tx_dmamap[i]);
984263bc
MD
1159 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1160 sc->bge_cdata.bge_tx_chain[i] = NULL;
1161 }
20c9a969 1162 bzero(&sc->bge_ldata.bge_tx_ring[i],
984263bc
MD
1163 sizeof(struct bge_tx_bd));
1164 }
984263bc
MD
1165}
1166
1167static int
33c39a69 1168bge_init_tx_ring(struct bge_softc *sc)
984263bc
MD
1169{
1170 sc->bge_txcnt = 0;
1171 sc->bge_tx_saved_considx = 0;
94db8384
SZ
1172 sc->bge_tx_prodidx = 0;
1173
1174 /* Initialize transmit producer index for host-memory send ring. */
591dfc77 1175 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1176
984263bc
MD
1177 /* 5700 b2 errata */
1178 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1179 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1180
591dfc77 1181 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1182 /* 5700 b2 errata */
1183 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1184 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1185
1186 return(0);
1187}
1188
984263bc 1189static void
33c39a69 1190bge_setmulti(struct bge_softc *sc)
984263bc
MD
1191{
1192 struct ifnet *ifp;
1193 struct ifmultiaddr *ifma;
33c39a69 1194 uint32_t hashes[4] = { 0, 0, 0, 0 };
984263bc
MD
1195 int h, i;
1196
1197 ifp = &sc->arpcom.ac_if;
1198
1199 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1200 for (i = 0; i < 4; i++)
1201 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1202 return;
1203 }
1204
1205 /* First, zot all the existing filters. */
1206 for (i = 0; i < 4; i++)
1207 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1208
1209 /* Now program new ones. */
441d34b2 1210 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1211 if (ifma->ifma_addr->sa_family != AF_LINK)
1212 continue;
3b4ec5b8
JS
1213 h = ether_crc32_le(
1214 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1215 ETHER_ADDR_LEN) & 0x7f;
984263bc
MD
1216 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1217 }
1218
1219 for (i = 0; i < 4; i++)
1220 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
984263bc
MD
1221}
1222
1223/*
1224 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1225 * self-test results.
1226 */
1227static int
33c39a69 1228bge_chipinit(struct bge_softc *sc)
984263bc 1229{
33c39a69
JS
1230 int i;
1231 uint32_t dma_rw_ctl;
c5a5f269 1232 uint16_t val;
984263bc 1233
20c9a969 1234 /* Set endian type before we access any non-PCI registers. */
90ad1c96
SZ
1235 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1236 BGE_INIT | sc->bge_pci_miscctl, 4);
984263bc 1237
984263bc
MD
1238 /* Clear the MAC control register */
1239 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1240
1241 /*
1242 * Clear the MAC statistics block in the NIC's
1243 * internal memory.
1244 */
1245 for (i = BGE_STATS_BLOCK;
33c39a69 1246 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1247 BGE_MEMWIN_WRITE(sc, i, 0);
1248
1249 for (i = BGE_STATUS_BLOCK;
33c39a69 1250 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1251 BGE_MEMWIN_WRITE(sc, i, 0);
1252
c5a5f269
SZ
1253 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1254 /*
1255 * Fix data corruption caused by non-qword write with WB.
1256 * Fix master abort in PCI mode.
1257 * Fix PCI latency timer.
1258 */
1259 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1260 val |= (1 << 10) | (1 << 12) | (1 << 13);
1261 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1262 }
1263
984263bc 1264 /* Set up the PCI DMA control register. */
0ecb11d7 1265 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
1266 /* PCI Express */
1267 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1268 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1269 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1270 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
984263bc 1271 /* PCI-X bus */
0ecb11d7
SZ
1272 if (BGE_IS_5714_FAMILY(sc)) {
1273 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1274 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1275 /* XXX magic values, Broadcom-supplied Linux driver */
1276 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1277 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1278 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1279 } else {
1280 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1281 }
33af0f18
SZ
1282 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1283 /*
1284 * In the BCM5703, the DMA read watermark should
1285 * be set to less than or equal to the maximum
1286 * memory read byte count of the PCI-X command
1287 * register.
1288 */
1289 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1290 (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1291 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7
SZ
1292 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293 /*
1294 * The 5704 uses a different encoding of read/write
1295 * watermarks.
1296 */
984263bc
MD
1297 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1298 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1299 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1300 } else {
984263bc
MD
1301 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304 (0x0F);
0ecb11d7 1305 }
984263bc
MD
1306
1307 /*
1308 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1309 * for hardware bugs.
1310 */
1311 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1312 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
33c39a69 1313 uint32_t tmp;
984263bc
MD
1314
1315 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1316 if (tmp == 0x6 || tmp == 0x7)
1317 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1318 }
0ecb11d7
SZ
1319 } else {
1320 /* Conventional PCI bus */
1321 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1322 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1323 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1324 (0x0F);
984263bc
MD
1325 }
1326
1327 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
7e40b8c5 1328 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
0ecb11d7 1329 sc->bge_asicrev == BGE_ASICREV_BCM5705)
984263bc
MD
1330 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1331 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1332
1333 /*
1334 * Set up general mode register.
1335 */
20c9a969 1336 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
984263bc 1337 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
bf29e666 1338 BGE_MODECTL_TX_NO_PHDR_CSUM);
984263bc 1339
33dd4678
SZ
1340 /*
1341 * BCM5701 B5 have a bug causing data corruption when using
1342 * 64-bit DMA reads, which can be terminated early and then
1343 * completed later as 32-bit accesses, in combination with
1344 * certain bridges.
1345 */
1346 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1347 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1348 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1349
984263bc
MD
1350 /*
1351 * Disable memory write invalidate. Apparently it is not supported
1352 * properly by these devices.
1353 */
1354 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1355
984263bc
MD
1356 /* Set the timer prescaler (always 66Mhz) */
1357 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1358
591dfc77
SZ
1359 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1360 DELAY(40); /* XXX */
1361
1362 /* Put PHY into ready state */
1363 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1364 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1365 DELAY(40);
1366 }
1367
984263bc
MD
1368 return(0);
1369}
1370
1371static int
33c39a69 1372bge_blockinit(struct bge_softc *sc)
984263bc
MD
1373{
1374 struct bge_rcb *rcb;
20c9a969
SZ
1375 bus_size_t vrcb;
1376 bge_hostaddr taddr;
0ecb11d7 1377 uint32_t val;
d287a587 1378 int i, limit;
984263bc
MD
1379
1380 /*
1381 * Initialize the memory window pointer register so that
1382 * we can access the first 32K of internal NIC RAM. This will
1383 * allow us to set up the TX send ring RCBs and the RX return
1384 * ring RCBs, plus other things which live in NIC memory.
1385 */
1386 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1387
7e40b8c5
HP
1388 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1389
0ecb11d7 1390 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5 1391 /* Configure mbuf memory pool */
0ecb11d7
SZ
1392 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1393 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1394 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1395 else
1396 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
984263bc 1397
7e40b8c5
HP
1398 /* Configure DMA resource pool */
1399 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1400 BGE_DMA_DESCRIPTORS);
1401 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1402 }
984263bc
MD
1403
1404 /* Configure mbuf pool watermarks */
591dfc77 1405 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1406 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1407 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
591dfc77
SZ
1408 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1409 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1410 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1411 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1412 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1413 } else {
1414 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1415 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1416 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
7e40b8c5 1417 }
984263bc
MD
1418
1419 /* Configure DMA resource watermarks */
1420 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1421 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1422
1423 /* Enable buffer manager */
6ac6e1b9
SZ
1424 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1425 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
984263bc 1426
6ac6e1b9
SZ
1427 /* Poll for buffer manager start indication */
1428 for (i = 0; i < BGE_TIMEOUT; i++) {
1429 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1430 break;
1431 DELAY(10);
1432 }
984263bc 1433
6ac6e1b9
SZ
1434 if (i == BGE_TIMEOUT) {
1435 if_printf(&sc->arpcom.ac_if,
1436 "buffer manager failed to start\n");
1437 return(ENXIO);
984263bc
MD
1438 }
1439
1440 /* Enable flow-through queues */
1441 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1442 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1443
1444 /* Wait until queue initialization is complete */
1445 for (i = 0; i < BGE_TIMEOUT; i++) {
1446 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1447 break;
1448 DELAY(10);
1449 }
1450
1451 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1452 if_printf(&sc->arpcom.ac_if,
1453 "flow-through queue init failed\n");
984263bc
MD
1454 return(ENXIO);
1455 }
1456
d287a587
SZ
1457 /*
1458 * Summary of rings supported by the controller:
1459 *
1460 * Standard Receive Producer Ring
1461 * - This ring is used to feed receive buffers for "standard"
1462 * sized frames (typically 1536 bytes) to the controller.
1463 *
1464 * Jumbo Receive Producer Ring
1465 * - This ring is used to feed receive buffers for jumbo sized
1466 * frames (i.e. anything bigger than the "standard" frames)
1467 * to the controller.
1468 *
1469 * Mini Receive Producer Ring
1470 * - This ring is used to feed receive buffers for "mini"
1471 * sized frames to the controller.
1472 * - This feature required external memory for the controller
1473 * but was never used in a production system. Should always
1474 * be disabled.
1475 *
1476 * Receive Return Ring
1477 * - After the controller has placed an incoming frame into a
1478 * receive buffer that buffer is moved into a receive return
1479 * ring. The driver is then responsible to passing the
1480 * buffer up to the stack. Many versions of the controller
1481 * support multiple RR rings.
1482 *
1483 * Send Ring
1484 * - This ring is used for outgoing frames. Many versions of
1485 * the controller support multiple send rings.
1486 */
1487
1488 /* Initialize the standard receive producer ring control block. */
20c9a969
SZ
1489 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1490 rcb->bge_hostaddr.bge_addr_lo =
1491 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1492 rcb->bge_hostaddr.bge_addr_hi =
1493 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
d287a587
SZ
1494 if (BGE_IS_5705_PLUS(sc)) {
1495 /*
1496 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1497 * Bits 15-2 : Reserved (should be 0)
1498 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1499 * Bit 0 : Reserved
1500 */
7e40b8c5 1501 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
d287a587
SZ
1502 } else {
1503 /*
1504 * Ring size is always XXX entries
1505 * Bits 31-16: Maximum RX frame size
1506 * Bits 15-2 : Reserved (should be 0)
1507 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1508 * Bit 0 : Reserved
1509 */
7e40b8c5
HP
1510 rcb->bge_maxlen_flags =
1511 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
d287a587 1512 }
0ecb11d7 1513 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
d287a587 1514 /* Write the standard receive producer ring control block. */
984263bc
MD
1515 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1516 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1517 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1518 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
d287a587
SZ
1519 /* Reset the standard receive producer ring producer index. */
1520 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
984263bc
MD
1521
1522 /*
d287a587
SZ
1523 * Initialize the jumbo RX producer ring control
1524 * block. We set the 'ring disabled' bit in the
1525 * flags field until we're actually ready to start
984263bc
MD
1526 * using this ring (i.e. once we set the MTU
1527 * high enough to require it).
1528 */
0ecb11d7 1529 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969 1530 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
d287a587 1531 /* Get the jumbo receive producer ring RCB parameters. */
20c9a969
SZ
1532 rcb->bge_hostaddr.bge_addr_lo =
1533 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1534 rcb->bge_hostaddr.bge_addr_hi =
1535 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
7e40b8c5
HP
1536 rcb->bge_maxlen_flags =
1537 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1538 BGE_RCB_FLAG_RING_DISABLED);
0ecb11d7 1539 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
7e40b8c5
HP
1540 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1541 rcb->bge_hostaddr.bge_addr_hi);
1542 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1543 rcb->bge_hostaddr.bge_addr_lo);
d287a587 1544 /* Program the jumbo receive producer ring RCB parameters. */
7e40b8c5
HP
1545 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1546 rcb->bge_maxlen_flags);
1547 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
d287a587
SZ
1548 /* Reset the jumbo receive producer ring producer index. */
1549 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1550 }
7e40b8c5 1551
d287a587
SZ
1552 /* Disable the mini receive producer ring RCB. */
1553 if (BGE_IS_5700_FAMILY(sc)) {
20c9a969 1554 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
7e40b8c5
HP
1555 rcb->bge_maxlen_flags =
1556 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1557 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1558 rcb->bge_maxlen_flags);
d287a587
SZ
1559 /* Reset the mini receive producer ring producer index. */
1560 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
7e40b8c5 1561 }
984263bc 1562
54919593
SZ
1563 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1564 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1565 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1566 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1567 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1568 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1569 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1570 }
1571
984263bc 1572 /*
d287a587
SZ
1573 * The BD ring replenish thresholds control how often the
1574 * hardware fetches new BD's from the producer rings in host
1575 * memory. Setting the value too low on a busy system can
1576 * starve the hardware and recue the throughpout.
1577 *
984263bc
MD
1578 * Set the BD ring replentish thresholds. The recommended
1579 * values are 1/8th the number of descriptors allocated to
1580 * each ring.
1581 */
0ecb11d7
SZ
1582 if (BGE_IS_5705_PLUS(sc))
1583 val = 8;
1584 else
1585 val = BGE_STD_RX_RING_CNT / 8;
1586 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
127003d4
SZ
1587 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1588 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1589 BGE_JUMBO_RX_RING_CNT/8);
1590 }
984263bc
MD
1591
1592 /*
d287a587
SZ
1593 * Disable all send rings by setting the 'ring disabled' bit
1594 * in the flags field of all the TX send ring control blocks,
1595 * located in NIC memory.
984263bc 1596 */
d287a587
SZ
1597 if (!BGE_IS_5705_PLUS(sc)) {
1598 /* 5700 to 5704 had 16 send rings. */
1599 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1600 } else {
1601 limit = 1;
1602 }
20c9a969 1603 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
d287a587 1604 for (i = 0; i < limit; i++) {
20c9a969
SZ
1605 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1606 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1607 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1608 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1609 }
1610
d287a587 1611 /* Configure send ring RCB 0 (we use only the first ring) */
20c9a969
SZ
1612 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1613 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1614 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1615 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1616 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1617 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
d287a587
SZ
1618 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1619 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
984263bc 1620
d287a587
SZ
1621 /*
1622 * Disable all receive return rings by setting the
1623 * 'ring diabled' bit in the flags field of all the receive
1624 * return ring control blocks, located in NIC memory.
1625 */
1626 if (!BGE_IS_5705_PLUS(sc))
1627 limit = BGE_RX_RINGS_MAX;
1628 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1629 limit = 4;
1630 else
1631 limit = 1;
1632 /* Disable all receive return rings. */
20c9a969 1633 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
d287a587 1634 for (i = 0; i < limit; i++) {
20c9a969
SZ
1635 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1636 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1637 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
d287a587 1638 BGE_RCB_FLAG_RING_DISABLED);
20c9a969 1639 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
591dfc77 1640 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
33c39a69 1641 (i * (sizeof(uint64_t))), 0);
20c9a969 1642 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1643 }
1644
984263bc 1645 /*
d287a587
SZ
1646 * Set up receive return ring 0. Note that the NIC address
1647 * for RX return rings is 0x0. The return rings live entirely
1648 * within the host, so the nicaddr field in the RCB isn't used.
984263bc 1649 */
20c9a969
SZ
1650 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1651 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1652 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1653 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
d287a587 1654 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
20c9a969
SZ
1655 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
984263bc
MD
1657
1658 /* Set random backoff seed for TX */
1659 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1660 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1661 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1662 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1663 BGE_TX_BACKOFF_SEED_MASK);
1664
1665 /* Set inter-packet gap */
1666 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1667
1668 /*
1669 * Specify which ring to use for packets that don't match
1670 * any RX rules.
1671 */
1672 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1673
1674 /*
1675 * Configure number of RX lists. One interrupt distribution
1676 * list, sixteen active lists, one bad frames class.
1677 */
1678 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1679
1680 /* Inialize RX list placement stats mask. */
1681 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1682 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1683
1684 /* Disable host coalescing until we get it set up */
1685 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1686
1687 /* Poll to make sure it's shut down. */
1688 for (i = 0; i < BGE_TIMEOUT; i++) {
1689 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1690 break;
1691 DELAY(10);
1692 }
1693
1694 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1695 if_printf(&sc->arpcom.ac_if,
1696 "host coalescing engine failed to idle\n");
984263bc
MD
1697 return(ENXIO);
1698 }
1699
1700 /* Set up host coalescing defaults */
1701 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1702 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
90ad1c96
SZ
1703 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1704 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
0ecb11d7 1705 if (!BGE_IS_5705_PLUS(sc)) {
90ad1c96
SZ
1706 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1707 sc->bge_rx_coal_ticks_int);
1708 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1709 sc->bge_tx_coal_ticks_int);
7e40b8c5 1710 }
e6ad4b47
SZ
1711 /*
1712 * NOTE:
1713 * The datasheet (57XX-PG105-R) says BCM5705+ do not
1714 * have following two registers; obviously it is wrong.
1715 */
90ad1c96
SZ
1716 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1717 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
984263bc
MD
1718
1719 /* Set up address of statistics block */
0ecb11d7 1720 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1721 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1722 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
7e40b8c5 1723 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
20c9a969 1724 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
7e40b8c5
HP
1725
1726 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1727 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1728 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1729 }
984263bc
MD
1730
1731 /* Set up address of status block */
a1620bc8 1732 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
20c9a969
SZ
1733 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1734 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
984263bc 1735 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
20c9a969 1736 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
984263bc 1737
8b1932b2
SZ
1738 /*
1739 * Set up status block partail update size.
1740 *
1741 * Because only single TX ring, RX produce ring and Rx return ring
1742 * are used, ask device to update only minimum part of status block
1743 * except for BCM5700 AX/BX, whose status block partial update size
1744 * can't be configured.
1745 */
1746 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1747 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1748 /* XXX Actually reserved on BCM5700 AX/BX */
1749 val = BGE_STATBLKSZ_FULL;
1750 } else {
1751 val = BGE_STATBLKSZ_32BYTE;
1752 }
90ad1c96
SZ
1753#if 0
1754 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
1755 val |= 0x00000200 | 0x00000400;
1756 if_printf(&sc->arpcom.ac_if, "enable TMR\n");
1757 }
1758#endif
8b1932b2 1759
984263bc 1760 /* Turn on host coalescing state machine */
8b1932b2 1761 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
984263bc
MD
1762
1763 /* Turn on RX BD completion state machine and enable attentions */
1764 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1765 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1766
1767 /* Turn on RX list placement state machine */
1768 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1769
1770 /* Turn on RX list selector state machine. */
0ecb11d7 1771 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1772 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc 1773
4d38e186
SZ
1774 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1775 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1776 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1777 BGE_MACMODE_FRMHDR_DMA_ENB;
1778
1779 if (sc->bge_flags & BGE_FLAG_TBI)
1780 val |= BGE_PORTMODE_TBI;
1781 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1782 val |= BGE_PORTMODE_GMII;
1783 else
1784 val |= BGE_PORTMODE_MII;
1785
984263bc 1786 /* Turn on DMA, clear stats */
4d38e186 1787 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
984263bc
MD
1788
1789 /* Set misc. local control, enable interrupts on attentions */
1790 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1791
1792#ifdef notdef
1793 /* Assert GPIO pins for PHY reset */
1794 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1795 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1796 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1797 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1798#endif
1799
1800 /* Turn on DMA completion state machine */
0ecb11d7 1801 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1802 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
1803
1804 /* Turn on write DMA state machine */
0ecb11d7 1805 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
832863d2
SZ
1806 if (BGE_IS_5755_PLUS(sc)) {
1807 /* Enable host coalescing bug fix. */
1808 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1809 }
ef016c7e
SZ
1810 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1811 /* Request larger DMA burst size to get better performance. */
1812 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1813 }
0ecb11d7 1814 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
671bd7ed
SZ
1815 DELAY(40);
1816
b4ecb050
SZ
1817 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1818 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1819 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1820 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1821 /*
1822 * Enable fix for read DMA FIFO overruns.
1823 * The fix is to limit the number of RX BDs
1824 * the hardware would fetch at a fime.
1825 */
1826 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1827 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1828 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1829 }
1830
984263bc 1831 /* Turn on read DMA state machine */
671bd7ed 1832 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
f47afe1a
MN
1833 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1834 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1835 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1836 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1837 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1838 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
671bd7ed
SZ
1839 if (sc->bge_flags & BGE_FLAG_PCIE)
1840 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1841 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1842 DELAY(40);
984263bc
MD
1843
1844 /* Turn on RX data completion state machine */
1845 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1846
1847 /* Turn on RX BD initiator state machine */
1848 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1849
1850 /* Turn on RX data and RX BD initiator state machine */
1851 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1852
1853 /* Turn on Mbuf cluster free state machine */
0ecb11d7 1854 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1855 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
1856
1857 /* Turn on send BD completion state machine */
1858 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1859
1860 /* Turn on send data completion state machine */
f47afe1a
MN
1861 val = BGE_SDCMODE_ENABLE;
1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1863 val |= BGE_SDCMODE_CDELAY;
1864 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
984263bc
MD
1865
1866 /* Turn on send data initiator state machine */
1867 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1868
1869 /* Turn on send BD initiator state machine */
1870 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1871
1872 /* Turn on send BD selector state machine */
1873 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1874
1875 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1876 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1877 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1878
1879 /* ack/clear link change events */
1880 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
1881 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1882 BGE_MACSTAT_LINK_CHANGED);
20c9a969 1883 CSR_WRITE_4(sc, BGE_MI_STS, 0);
984263bc 1884
2dd0af35
SZ
1885 /*
1886 * Enable attention when the link has changed state for
1887 * devices that use auto polling.
1888 */
0ecb11d7 1889 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
1890 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1891 } else {
2dd0af35
SZ
1892 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1893 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1894 DELAY(80);
1895 }
db861466
SZ
1896 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1897 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
984263bc
MD
1898 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1899 BGE_EVTENB_MI_INTERRUPT);
db861466 1900 }
984263bc
MD
1901 }
1902
db861466
SZ
1903 /*
1904 * Clear any pending link state attention.
1905 * Otherwise some link state change events may be lost until attention
1906 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1907 * It's not necessary on newer BCM chips - perhaps enabling link
1908 * state change attentions implies clearing pending attention.
1909 */
1910 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1911 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1912 BGE_MACSTAT_LINK_CHANGED);
1913
984263bc
MD
1914 /* Enable link state change attentions. */
1915 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1916
1917 return(0);
1918}
1919
1920/*
1921 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1922 * against our list and return its name if we find a match. Note
1923 * that since the Broadcom controller contains VPD support, we
1924 * can get the device name string from the controller itself instead
1925 * of the compiled-in string. This is a little slow, but it guarantees
1926 * we'll always announce the right product name.
1927 */
1928static int
33c39a69 1929bge_probe(device_t dev)
984263bc 1930{
d265721a 1931 const struct bge_type *t;
33c39a69
JS
1932 uint16_t product, vendor;
1933
1934 product = pci_get_device(dev);
1935 vendor = pci_get_vendor(dev);
1936
1937 for (t = bge_devs; t->bge_name != NULL; t++) {
1938 if (vendor == t->bge_vid && product == t->bge_did)
1939 break;
1940 }
33c39a69
JS
1941 if (t->bge_name == NULL)
1942 return(ENXIO);
984263bc 1943
d265721a 1944 device_set_desc(dev, t->bge_name);
33c39a69 1945 return(0);
984263bc
MD
1946}
1947
1948static int
33c39a69 1949bge_attach(device_t dev)
984263bc 1950{
984263bc
MD
1951 struct ifnet *ifp;
1952 struct bge_softc *sc;
6b4f9f65
SZ
1953 uint32_t hwcfg = 0, misccfg;
1954 int error = 0, rid, capmask;
0a8b5977 1955 uint8_t ether_addr[ETHER_ADDR_LEN];
6b4f9f65 1956 uint16_t product, vendor;
90ad1c96 1957 driver_intr_t *intr_func;
984263bc 1958
984263bc 1959 sc = device_get_softc(dev);
984263bc 1960 sc->bge_dev = dev;
263489fb 1961 callout_init(&sc->bge_stat_timer);
16dca0df 1962 lwkt_serialize_init(&sc->bge_jslot_serializer);
984263bc 1963
591dfc77
SZ
1964#ifndef BURN_BRIDGES
1965 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1966 uint32_t irq, mem;
1967
1968 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1969 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1970
1971 device_printf(dev, "chip is in D%d power mode "
1972 "-- setting to D0\n", pci_get_powerstate(dev));
1973
1974 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1975
1976 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1977 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1978 }
1979#endif /* !BURN_BRIDGE */
1980
984263bc
MD
1981 /*
1982 * Map control/status registers.
1983 */
cc8ddf9e 1984 pci_enable_busmaster(dev);
984263bc
MD
1985
1986 rid = BGE_PCI_BAR0;
cc8ddf9e
JS
1987 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1988 RF_ACTIVE);
984263bc
MD
1989
1990 if (sc->bge_res == NULL) {
c6fd6f3b 1991 device_printf(dev, "couldn't map memory\n");
baf731bb 1992 return ENXIO;
984263bc
MD
1993 }
1994
1995 sc->bge_btag = rman_get_bustag(sc->bge_res);
1996 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
984263bc 1997
d265721a 1998 /* Save various chip information */
9a6ee7e2 1999 sc->bge_chipid =
f47afe1a
MN
2000 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2001 BGE_PCIMISCCTL_ASICREV_SHIFT;
2002 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2003 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
9a6ee7e2
JS
2004 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2005 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2006
0ecb11d7
SZ
2007 /* Save chipset family. */
2008 switch (sc->bge_asicrev) {
f47afe1a
MN
2009 case BGE_ASICREV_BCM5755:
2010 case BGE_ASICREV_BCM5761:
2011 case BGE_ASICREV_BCM5784:
2012 case BGE_ASICREV_BCM5785:
2013 case BGE_ASICREV_BCM5787:
2014 case BGE_ASICREV_BCM57780:
2015 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2016 BGE_FLAG_5705_PLUS;
2017 break;
2018
0ecb11d7
SZ
2019 case BGE_ASICREV_BCM5700:
2020 case BGE_ASICREV_BCM5701:
2021 case BGE_ASICREV_BCM5703:
2022 case BGE_ASICREV_BCM5704:
2023 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2024 break;
2025
2026 case BGE_ASICREV_BCM5714_A0:
2027 case BGE_ASICREV_BCM5780:
2028 case BGE_ASICREV_BCM5714:
2029 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2030 /* Fall through */
2031
2032 case BGE_ASICREV_BCM5750:
2033 case BGE_ASICREV_BCM5752:
591dfc77 2034 case BGE_ASICREV_BCM5906:
0ecb11d7
SZ
2035 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2036 /* Fall through */
2037
2038 case BGE_ASICREV_BCM5705:
2039 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2040 break;
2041 }
9a6ee7e2 2042
591dfc77
SZ
2043 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2044 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2045
5225ba10
SZ
2046 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2047 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2048 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2049 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2050 sc->bge_flags |= BGE_FLAG_5788;
2051
e0b35c1f
SZ
2052 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2053 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2054 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2055
3c858e35
SZ
2056 /*
2057 * Check if this is a PCI-X or PCI Express device.
2058 */
2059 if (BGE_IS_5705_PLUS(sc)) {
2060 if (pci_is_pcie(dev)) {
2061 sc->bge_flags |= BGE_FLAG_PCIE;
2062 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2063 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2064 }
2065 } else {
2066 /*
2067 * Check if the device is in PCI-X Mode.
2068 * (This bit is not valid on PCI Express controllers.)
2069 */
2070 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2071 BGE_PCISTATE_PCI_BUSMODE) == 0) {
2072 sc->bge_flags |= BGE_FLAG_PCIX;
2073 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2074 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2075 "mbox_reorder", 0);
2076 }
2077 }
2078 device_printf(dev, "CHIP ID 0x%08x; "
2079 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2080 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2081 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2082 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2083 "PCI-E" : "PCI"));
2084
2085 /*
2086 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2087 * not actually a MAC controller bug but an issue with the embedded
2088 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2089 */
2090 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2091 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2092
2093 /* Identify the chips that use an CPMU. */
2094 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2095 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2096 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2097 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2098 sc->bge_flags |= BGE_FLAG_CPMU;
2099
9a6ee7e2 2100 /*
3c858e35
SZ
2101 * When using the BCM5701 in PCI-X mode, data corruption has
2102 * been observed in the first few bytes of some received packets.
2103 * Aligning the packet buffer in memory eliminates the corruption.
2104 * Unfortunately, this misaligns the packet payloads. On platforms
2105 * which do not support unaligned accesses, we will realign the
2106 * payloads by copying the received packets.
9a6ee7e2 2107 */
3c858e35
SZ
2108 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2109 (sc->bge_flags & BGE_FLAG_PCIX))
2110 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
9a6ee7e2 2111
90ad1c96
SZ
2112 if (!BGE_IS_5788(sc) && sc->bge_asicrev != BGE_ASICREV_BCM5700) {
2113 if (device_getenv_int(dev, "status_tag", 1)) {
2114 sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2115 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2116 if (bootverbose)
2117 device_printf(dev, "enable status tag\n");
2118 }
2119 }
2120
3c858e35
SZ
2121 /*
2122 * Set various PHY quirk flags.
2123 */
6b4f9f65
SZ
2124 product = pci_get_device(dev);
2125 vendor = pci_get_vendor(dev);
2126
6b4f9f65
SZ
2127 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2128 sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2129 pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2130 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2131
2132 capmask = MII_CAPMASK_DEFAULT;
2133 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2134 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2135 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2136 vendor == PCI_VENDOR_BROADCOM &&
2137 (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2138 product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2139 product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2140 (vendor == PCI_VENDOR_BROADCOM &&
2141 (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2142 product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2143 product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2144 product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2145 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2146 /* 10/100 only */
2147 capmask &= ~BMSR_EXTSTAT;
2148 }
2149
1932af46 2150 sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
0ecb11d7
SZ
2151 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2152 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2153 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2154 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2155 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1932af46 2156 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
0ecb11d7
SZ
2157
2158 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2159 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1932af46 2160 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
0ecb11d7
SZ
2161
2162 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2163 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1932af46 2164 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
0ecb11d7
SZ
2165
2166 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1932af46 2167 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
0ecb11d7 2168
6b4f9f65
SZ
2169 if (BGE_IS_5705_PLUS(sc) &&
2170 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2171 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2172 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2173 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2174 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
0ecb11d7 2175 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
f47afe1a
MN
2176 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2177 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
0ecb11d7 2178 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2d79280f
SZ
2179 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2180 product != PCI_PRODUCT_BROADCOM_BCM5756)
1932af46 2181 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2d79280f 2182 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1932af46 2183 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
6b4f9f65 2184 } else {
1932af46 2185 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
9a6ee7e2
JS
2186 }
2187 }
2188
0ecb11d7
SZ
2189 /* Allocate interrupt */
2190 rid = 0;
0ecb11d7
SZ
2191 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2192 RF_SHAREABLE | RF_ACTIVE);
0ecb11d7
SZ
2193 if (sc->bge_irq == NULL) {
2194 device_printf(dev, "couldn't map interrupt\n");
2195 error = ENXIO;
2196 goto fail;
2197 }
2198
3c858e35 2199 /* Initialize if_name earlier, so if_printf could be used */
c6fd6f3b
JS
2200 ifp = &sc->arpcom.ac_if;
2201 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
2202
2203 /* Try to reset the chip. */
2204 bge_reset(sc);
2205
2206 if (bge_chipinit(sc)) {
c6fd6f3b 2207 device_printf(dev, "chip initialization failed\n");
984263bc
MD
2208 error = ENXIO;
2209 goto fail;
2210 }
2211
2212 /*
591dfc77 2213 * Get station address
984263bc 2214 */
591dfc77
SZ
2215 error = bge_get_eaddr(sc, ether_addr);
2216 if (error) {
c6fd6f3b 2217 device_printf(dev, "failed to read station address\n");
984263bc
MD
2218 goto fail;
2219 }
2220
20c9a969 2221 /* 5705/5750 limits RX return ring to 512 entries. */
0ecb11d7 2222 if (BGE_IS_5705_PLUS(sc))
20c9a969
SZ
2223 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2224 else
2225 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
984263bc 2226
20c9a969
SZ
2227 error = bge_dma_alloc(sc);
2228 if (error)
984263bc 2229 goto fail;
984263bc
MD
2230
2231 /* Set default tuneable values. */
2232 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
90ad1c96
SZ
2233 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2234 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2235 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2236 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2237 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2238 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2239 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2240 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2241 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2242 } else {
2243 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2244 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2245 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2246 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2247 }
984263bc
MD
2248
2249 /* Set up ifnet structure */
984263bc 2250 ifp->if_softc = sc;
984263bc
MD
2251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2252 ifp->if_ioctl = bge_ioctl;
984263bc 2253 ifp->if_start = bge_start;
315fe0ee
MD
2254#ifdef DEVICE_POLLING
2255 ifp->if_poll = bge_poll;
2256#endif
984263bc
MD
2257 ifp->if_watchdog = bge_watchdog;
2258 ifp->if_init = bge_init;
2259 ifp->if_mtu = ETHERMTU;
cb623c48 2260 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
936ff230
JS
2261 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2262 ifq_set_ready(&ifp->if_snd);
cb623c48
SZ
2263
2264 /*
2265 * 5700 B0 chips do not support checksumming correctly due
2266 * to hardware bugs.
2267 */
2268 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2269 ifp->if_capabilities |= IFCAP_HWCSUM;
2270 ifp->if_hwassist = BGE_CSUM_FEATURES;
2271 }
984263bc
MD
2272 ifp->if_capenable = ifp->if_capabilities;
2273
984263bc
MD
2274 /*
2275 * Figure out what sort of media we have by checking the
2276 * hardware config word in the first 32k of NIC internal memory,
2277 * or fall back to examining the EEPROM if necessary.
2278 * Note: on some BCM5700 cards, this value appears to be unset.
2279 * If that's the case, we have to rely on identifying the NIC
2280 * by its PCI subsystem ID, as we do below for the SysKonnect
2281 * SK-9D41.
2282 */
3c858e35 2283 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
984263bc 2284 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
3c858e35 2285 } else {
7b47d9c2
SZ
2286 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2287 sizeof(hwcfg))) {
2288 device_printf(dev, "failed to read EEPROM\n");
2289 error = ENXIO;
2290 goto fail;
2291 }
984263bc
MD
2292 hwcfg = ntohl(hwcfg);
2293 }
2294
984263bc 2295 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
4d38e186
SZ
2296 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2297 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2298 if (BGE_IS_5714_FAMILY(sc))
2299 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2300 else
2301 sc->bge_flags |= BGE_FLAG_TBI;
2302 }
984263bc 2303
3c858e35
SZ
2304 /* Setup MI MODE */
2305 if (sc->bge_flags & BGE_FLAG_CPMU)
2306 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2307 else
2308 sc->bge_mi_mode = BGE_MIMODE_BASE;
2309 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2310 /* Enable auto polling for BCM570[0-5]. */
2311 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2312 }
2313
2314 /* Setup link status update stuffs */
2315 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2316 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2317 sc->bge_link_upd = bge_bcm5700_link_upd;
2318 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2319 } else if (sc->bge_flags & BGE_FLAG_TBI) {
2320 sc->bge_link_upd = bge_tbi_link_upd;
2321 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2322 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2323 sc->bge_link_upd = bge_autopoll_link_upd;
2324 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2325 } else {
2326 sc->bge_link_upd = bge_copper_link_upd;
2327 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2328 }
2329
fd894027
SZ
2330 /*
2331 * Broadcom's own driver always assumes the internal
2332 * PHY is at GMII address 1. On some chips, the PHY responds
2333 * to accesses at all addresses, which could cause us to
2334 * bogusly attach the PHY 32 times at probe type. Always
2335 * restricting the lookup to address 1 is simpler than
2336 * trying to figure out which chips revisions should be
2337 * special-cased.
2338 */
2339 sc->bge_phyno = 1;
2340
0ecb11d7 2341 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
2342 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2343 bge_ifmedia_upd, bge_ifmedia_sts);
2344 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2345 ifmedia_add(&sc->bge_ifmedia,
2346 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2347 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2348 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
70059b3c 2349 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
984263bc 2350 } else {
fd894027
SZ
2351 struct mii_probe_args mii_args;
2352
2353 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2354 mii_args.mii_probemask = 1 << sc->bge_phyno;
6b4f9f65 2355 mii_args.mii_capmask = capmask;
fd894027
SZ
2356
2357 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2358 if (error) {
c6fd6f3b 2359 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
2360 goto fail;
2361 }
2362 }
2363
055d06f0
SZ
2364 /*
2365 * Create sysctl nodes.
2366 */
2367 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2368 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2369 SYSCTL_STATIC_CHILDREN(_hw),
2370 OID_AUTO,
2371 device_get_nameunit(dev),
2372 CTLFLAG_RD, 0, "");
2373 if (sc->bge_sysctl_tree == NULL) {
2374 device_printf(dev, "can't add sysctl node\n");
2375 error = ENXIO;
2376 goto fail;
2377 }
2378
2379 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2380 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2381 OID_AUTO, "rx_coal_ticks",
2382 CTLTYPE_INT | CTLFLAG_RW,
2383 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2384 "Receive coalescing ticks (usec).");
2385 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2386 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2387 OID_AUTO, "tx_coal_ticks",
2388 CTLTYPE_INT | CTLFLAG_RW,
2389 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2390 "Transmit coalescing ticks (usec).");
2391 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2392 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
90ad1c96 2393 OID_AUTO, "rx_coal_bds",
055d06f0 2394 CTLTYPE_INT | CTLFLAG_RW,
90ad1c96 2395 sc, 0, bge_sysctl_rx_coal_bds, "I",
055d06f0
SZ
2396 "Receive max coalesced BD count.");
2397 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2398 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
90ad1c96 2399 OID_AUTO, "tx_coal_bds",
055d06f0 2400 CTLTYPE_INT | CTLFLAG_RW,
90ad1c96 2401 sc, 0, bge_sysctl_tx_coal_bds, "I",
055d06f0 2402 "Transmit max coalesced BD count.");
c728ae98
SZ
2403 if (sc->bge_flags & BGE_FLAG_PCIE) {
2404 /*
2405 * A common design characteristic for many Broadcom
2406 * client controllers is that they only support a
2407 * single outstanding DMA read operation on the PCIe
2408 * bus. This means that it will take twice as long to
2409 * fetch a TX frame that is split into header and
2410 * payload buffers as it does to fetch a single,
2411 * contiguous TX frame (2 reads vs. 1 read). For these
2412 * controllers, coalescing buffers to reduce the number
2413 * of memory reads is effective way to get maximum
2414 * performance(about 940Mbps). Without collapsing TX
2415 * buffers the maximum TCP bulk transfer performance
2416 * is about 850Mbps. However forcing coalescing mbufs
2417 * consumes a lot of CPU cycles, so leave it off by
2418 * default.
2419 */
2420 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2421 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2422 OID_AUTO, "force_defrag", CTLFLAG_RW,
2423 &sc->bge_force_defrag, 0,
2424 "Force defragment on TX path");
2425 }
90ad1c96
SZ
2426 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2427 if (!BGE_IS_5705_PLUS(sc)) {
2428 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2429 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2430 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2431 sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2432 "Receive coalescing ticks "
2433 "during interrupt (usec).");
2434 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2435 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2436 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2437 sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2438 "Transmit coalescing ticks "
2439 "during interrupt (usec).");
2440 }
2441 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2442 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2443 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2444 sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2445 "Receive max coalesced BD count during interrupt.");
2446 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2447 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2448 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2449 sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2450 "Transmit max coalesced BD count during interrupt.");
2451 }
c728ae98 2452
984263bc
MD
2453 /*
2454 * Call MI attach routine.
2455 */
78195a76 2456 ether_ifattach(ifp, ether_addr, NULL);
984263bc 2457
90ad1c96
SZ
2458 if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
2459 intr_func = bge_intr_status_tag;
2460 else
2461 intr_func = bge_intr;
2462
2463 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2464 &sc->bge_intrhand, ifp->if_serializer);
9a717c15
JS
2465 if (error) {
2466 ether_ifdetach(ifp);
2467 device_printf(dev, "couldn't set up irq\n");
2468 goto fail;
2469 }
9db4b353 2470
28e81a28 2471 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
9db4b353
SZ
2472 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2473
9a717c15 2474 return(0);
984263bc 2475fail:
9a717c15 2476 bge_detach(dev);
984263bc
MD
2477 return(error);
2478}
2479
2480static int
33c39a69 2481bge_detach(device_t dev)
984263bc 2482{
9a717c15 2483 struct bge_softc *sc = device_get_softc(dev);
984263bc 2484
9a717c15 2485 if (device_is_attached(dev)) {
baf731bb
SZ
2486 struct ifnet *ifp = &sc->arpcom.ac_if;
2487
cdf89432 2488 lwkt_serialize_enter(ifp->if_serializer);
9a717c15
JS
2489 bge_stop(sc);
2490 bge_reset(sc);
cdf89432
SZ
2491 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2492 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2493
cdf89432
SZ
2494 ether_ifdetach(ifp);
2495 }
baf731bb 2496
0ecb11d7 2497 if (sc->bge_flags & BGE_FLAG_TBI)
984263bc 2498 ifmedia_removeall(&sc->bge_ifmedia);
cbf32d7e 2499 if (sc->bge_miibus)
984263bc 2500 device_delete_child(dev, sc->bge_miibus);
9a717c15 2501 bus_generic_detach(dev);
984263bc 2502
984263bc
MD
2503 if (sc->bge_irq != NULL)
2504 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2505
2506 if (sc->bge_res != NULL)
2507 bus_release_resource(dev, SYS_RES_MEMORY,
2508 BGE_PCI_BAR0, sc->bge_res);
baf731bb 2509
055d06f0
SZ
2510 if (sc->bge_sysctl_tree != NULL)
2511 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2512
baf731bb
SZ
2513 bge_dma_free(sc);
2514
2515 return 0;
984263bc
MD
2516}
2517
2518static void
33c39a69 2519bge_reset(struct bge_softc *sc)
984263bc
MD
2520{
2521 device_t dev;
9a6ee7e2 2522 uint32_t cachesize, command, pcistate, reset;
0ecb11d7 2523 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
984263bc
MD
2524 int i, val = 0;
2525
2526 dev = sc->bge_dev;
2527
591dfc77
SZ
2528 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2529 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
0ecb11d7
SZ
2530 if (sc->bge_flags & BGE_FLAG_PCIE)
2531 write_op = bge_writemem_direct;
2532 else
2533 write_op = bge_writemem_ind;
2534 } else {
2535 write_op = bge_writereg_ind;
2536 }
2537
984263bc
MD
2538 /* Save some important PCI state. */
2539 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2540 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2541 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2542
2543 pci_write_config(dev, BGE_PCI_MISC_CTL,
2544 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
90ad1c96
SZ
2545 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2546 sc->bge_pci_miscctl, 4);
984263bc 2547
0ecb11d7
SZ
2548 /* Disable fastboot on controllers that support it. */
2549 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
832863d2 2550 BGE_IS_5755_PLUS(sc)) {
0ecb11d7
SZ
2551 if (bootverbose)
2552 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2553 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2554 }
2555
2556 /*
2557 * Write the magic number to SRAM at offset 0xB50.
2558 * When firmware finishes its initialization it will
2559 * write ~BGE_MAGIC_NUMBER to the same location.
2560 */
2561 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2562
9a6ee7e2
JS
2563 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2564
2565 /* XXX: Broadcom Linux driver. */
0ecb11d7 2566 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2567 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2568 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2569 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2570 /* Prevent PCIE link training during global reset */
2571 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2572 reset |= (1<<29);
2573 }
2574 }
2575
0ecb11d7
SZ
2576 /*
2577 * Set GPHY Power Down Override to leave GPHY
2578 * powered up in D0 uninitialized.
2579 */
579c0975 2580 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2330cf73 2581 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
0ecb11d7 2582
984263bc 2583 /* Issue global reset */
0ecb11d7 2584 write_op(sc, BGE_MISC_CFG, reset);
984263bc 2585
591dfc77
SZ
2586 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2587 uint32_t status, ctrl;
2588
2589 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2590 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2591 status | BGE_VCPU_STATUS_DRV_RESET);
2592 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2593 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2594 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2595 }
2596
984263bc
MD
2597 DELAY(1000);
2598
9a6ee7e2 2599 /* XXX: Broadcom Linux driver. */
0ecb11d7 2600 if (sc->bge_flags & BGE_FLAG_PCIE) {
1b13d01b
SZ
2601 uint16_t devctl;
2602
9a6ee7e2
JS
2603 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2604 uint32_t v;
2605
2606 DELAY(500000); /* wait for link training to complete */
2607 v = pci_read_config(dev, 0xc4, 4);
2608 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2609 }
1b13d01b
SZ
2610
2611 /* Clear enable no snoop and disable relaxed ordering. */
2612 devctl = pci_read_config(dev,
2613 sc->bge_pciecap + PCIER_DEVCTRL, 2);
2614 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2615 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2616 devctl, 2);
2617
2618 /* Clear error status. */
2619 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2620 PCIEM_DEVSTS_CORR_ERR |
2621 PCIEM_DEVSTS_NFATAL_ERR |
2622 PCIEM_DEVSTS_FATAL_ERR |
2623 PCIEM_DEVSTS_UNSUPP_REQ, 2);
9a6ee7e2
JS
2624 }
2625
984263bc
MD
2626 /* Reset some of the PCI state that got zapped by reset */
2627 pci_write_config(dev, BGE_PCI_MISC_CTL,
2628 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
90ad1c96
SZ
2629 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2630 sc->bge_pci_miscctl, 4);
984263bc
MD
2631 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2632 pci_write_config(dev, BGE_PCI_CMD, command, 4);
0ecb11d7 2633 write_op(sc, BGE_MISC_CFG, (65 << 1));
984263bc 2634
ab8c1124
SZ
2635 /*
2636 * Disable PCI-X relaxed ordering to ensure status block update
2637 * comes first then packet buffer DMA. Otherwise driver may
2638 * read stale status block.
2639 */
2640 if (sc->bge_flags & BGE_FLAG_PCIX) {
2641 uint16_t devctl;
2642
2643 devctl = pci_read_config(dev,
2644 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2645 devctl &= ~PCIXM_COMMAND_ERO;
2646 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2647 devctl &= ~PCIXM_COMMAND_MAX_READ;
2648 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2649 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2650 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2651 PCIXM_COMMAND_MAX_READ);
2652 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2653 }
2654 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2655 devctl, 2);
2656 }
2657
a313b56f 2658 /* Enable memory arbiter. */
0ecb11d7
SZ
2659 if (BGE_IS_5714_FAMILY(sc)) {
2660 uint32_t val;
2661
2662 val = CSR_READ_4(sc, BGE_MARB_MODE);
2663 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2664 } else {
a313b56f 2665 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
0ecb11d7 2666 }
a313b56f 2667
591dfc77
SZ
2668 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2669 for (i = 0; i < BGE_TIMEOUT; i++) {
2670 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2671 if (val & BGE_VCPU_STATUS_INIT_DONE)
2672 break;
2673 DELAY(100);
2674 }
2675 if (i == BGE_TIMEOUT) {
2676 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2677 return;
2678 }
2679 } else {
2680 /*
2681 * Poll until we see the 1's complement of the magic number.
2682 * This indicates that the firmware initialization
2683 * is complete.
2684 */
d880f7b3 2685 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
591dfc77
SZ
2686 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2687 if (val == ~BGE_MAGIC_NUMBER)
2688 break;
2689 DELAY(10);
2690 }
d880f7b3 2691 if (i == BGE_FIRMWARE_TIMEOUT) {
591dfc77
SZ
2692 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2693 "timed out, found 0x%08x\n", val);
2694 return;
2695 }
984263bc
MD
2696 }
2697
2698 /*
2699 * XXX Wait for the value of the PCISTATE register to
2700 * return to its original pre-reset state. This is a
2701 * fairly good indicator of reset completion. If we don't
2702 * wait for the reset to fully complete, trying to read
2703 * from the device's non-PCI registers may yield garbage
2704 * results.
2705 */
2706 for (i = 0; i < BGE_TIMEOUT; i++) {
2707 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2708 break;
2709 DELAY(10);
2710 }
2711
984263bc 2712 /* Fix up byte swapping */
20c9a969 2713 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
984263bc
MD
2714 BGE_MODECTL_BYTESWAP_DATA);
2715
2716 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2717
70059b3c
JS
2718 /*
2719 * The 5704 in TBI mode apparently needs some special
2720 * adjustment to insure the SERDES drive level is set
2721 * to 1.2V.
2722 */
0ecb11d7
SZ
2723 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2724 (sc->bge_flags & BGE_FLAG_TBI)) {
70059b3c
JS
2725 uint32_t serdescfg;
2726
2727 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2728 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2729 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2730 }
2731
9a6ee7e2 2732 /* XXX: Broadcom Linux driver. */
0ecb11d7 2733 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
3dfc12af
SZ
2734 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2735 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
9a6ee7e2 2736 uint32_t v;
984263bc 2737
3dfc12af 2738 /* Enable Data FIFO protection. */
9a6ee7e2
JS
2739 v = CSR_READ_4(sc, 0x7c00);
2740 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2741 }
2742
2743 DELAY(10000);
984263bc
MD
2744}
2745
2746/*
2747 * Frame reception handling. This is called if there's a frame
2748 * on the receive return list.
2749 *
2750 * Note: we have to be able to handle two possibilities here:
2751 * 1) the frame is from the jumbo recieve ring
2752 * 2) the frame is from the standard receive ring
2753 */
2754
2755static void
90ad1c96 2756bge_rxeof(struct bge_softc *sc, uint16_t rx_prod)
984263bc
MD
2757{
2758 struct ifnet *ifp;
2759 int stdcnt = 0, jumbocnt = 0;
2760
2761 ifp = &sc->arpcom.ac_if;
2762
90ad1c96 2763 while (sc->bge_rx_saved_considx != rx_prod) {
984263bc 2764 struct bge_rx_bd *cur_rx;
33c39a69 2765 uint32_t rxidx;
984263bc 2766 struct mbuf *m = NULL;
33c39a69 2767 uint16_t vlan_tag = 0;
984263bc
MD
2768 int have_tag = 0;
2769
2770 cur_rx =
20c9a969 2771 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
984263bc
MD
2772
2773 rxidx = cur_rx->bge_idx;
7e40b8c5 2774 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
6b880771 2775 logif(rx_pkt);
984263bc
MD
2776
2777 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2778 have_tag = 1;
2779 vlan_tag = cur_rx->bge_vlan_tag;
2780 }
2781
2782 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2783 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
984263bc 2784 jumbocnt++;
1436f9a0
SZ
2785
2786 if (rxidx != sc->bge_jumbo) {
2787 ifp->if_ierrors++;
2788 if_printf(ifp, "sw jumbo index(%d) "
2789 "and hw jumbo index(%d) mismatch, drop!\n",
2790 sc->bge_jumbo, rxidx);
2791 bge_setup_rxdesc_jumbo(sc, rxidx);
2792 continue;
2793 }
2794
2795 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
984263bc
MD
2796 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2797 ifp->if_ierrors++;
1436f9a0 2798 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2799 continue;
2800 }
1436f9a0 2801 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
984263bc 2802 ifp->if_ierrors++;
1436f9a0 2803 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2804 continue;
2805 }
2806 } else {
2807 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
984263bc 2808 stdcnt++;
1436f9a0
SZ
2809
2810 if (rxidx != sc->bge_std) {
2811 ifp->if_ierrors++;
2812 if_printf(ifp, "sw std index(%d) "
2813 "and hw std index(%d) mismatch, drop!\n",
2814 sc->bge_std, rxidx);
2815 bge_setup_rxdesc_std(sc, rxidx);
2816 continue;
2817 }
2818
2819 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
984263bc
MD
2820 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2821 ifp->if_ierrors++;
1436f9a0 2822 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2823 continue;
2824 }
1436f9a0 2825 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
984263bc 2826 ifp->if_ierrors++;
1436f9a0 2827 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2828 continue;
2829 }
2830 }
2831
2832 ifp->if_ipackets++;
061def6f 2833#if !defined(__i386__) && !defined(__x86_64__)
984263bc 2834 /*
061def6f 2835 * The x86 allows unaligned accesses, but for other
984263bc
MD
2836 * platforms we must make sure the payload is aligned.
2837 */
0ecb11d7 2838 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
984263bc
MD
2839 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2840 cur_rx->bge_len);
2841 m->m_data += ETHER_ALIGN;
2842 }
2843#endif
160185fa 2844 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
984263bc
MD
2845 m->m_pkthdr.rcvif = ifp;
2846
cb623c48
SZ
2847 if (ifp->if_capenable & IFCAP_RXCSUM) {
2848 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2849 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2850 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2851 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2852 }
17240569 2853 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
cb623c48 2854 m->m_pkthdr.len >= BGE_MIN_FRAME) {
984263bc 2855 m->m_pkthdr.csum_data =
17240569 2856 cur_rx->bge_tcp_udp_csum;
bf29e666
SZ
2857 m->m_pkthdr.csum_flags |=
2858 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
984263bc
MD
2859 }
2860 }
984263bc
MD
2861
2862 /*
2863 * If we received a packet with a vlan tag, pass it
2864 * to vlan_input() instead of ether_input().
2865 */
2866 if (have_tag) {
e6b5847c
SZ
2867 m->m_flags |= M_VLANTAG;
2868 m->m_pkthdr.ether_vlantag = vlan_tag;
984263bc 2869 have_tag = vlan_tag = 0;
984263bc 2870 }
eda7db08 2871 ifp->if_input(ifp, m);
984263bc
MD
2872 }
2873
591dfc77 2874 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
984263bc 2875 if (stdcnt)
591dfc77 2876 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc 2877 if (jumbocnt)
591dfc77 2878 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
2879}
2880
2881static void
90ad1c96 2882bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
984263bc
MD
2883{
2884 struct bge_tx_bd *cur_tx = NULL;
2885 struct ifnet *ifp;
2886
2887 ifp = &sc->arpcom.ac_if;
2888
2889 /*
2890 * Go through our tx ring and free mbufs for those
2891 * frames that have been sent.
2892 */
90ad1c96 2893 while (sc->bge_tx_saved_considx != tx_cons) {
20c9a969 2894 uint32_t idx = 0;
984263bc
MD
2895
2896 idx = sc->bge_tx_saved_considx;
20c9a969 2897 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
984263bc
MD
2898 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2899 ifp->if_opackets++;
2900 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
ddca511d 2901 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 2902 sc->bge_cdata.bge_tx_dmamap[idx]);
984263bc
MD
2903 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2904 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2905 }
2906 sc->bge_txcnt--;
2907 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
6b880771 2908 logif(tx_pkt);
984263bc
MD
2909 }
2910
20c9a969
SZ
2911 if (cur_tx != NULL &&
2912 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2913 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
984263bc 2914 ifp->if_flags &= ~IFF_OACTIVE;
20c9a969 2915
142ca760
SZ
2916 if (sc->bge_txcnt == 0)
2917 ifp->if_timer = 0;
2918
20c9a969 2919 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2920 if_devstart(ifp);
984263bc
MD
2921}
2922
315fe0ee
MD
2923#ifdef DEVICE_POLLING
2924
2925static void
2926bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2927{
2928 struct bge_softc *sc = ifp->if_softc;
90ad1c96
SZ
2929 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
2930 uint16_t rx_prod, tx_cons;
315fe0ee
MD
2931 uint32_t status;
2932
2933 switch(cmd) {
2934 case POLL_REGISTER:
ba39cc82 2935 bge_disable_intr(sc);
315fe0ee
MD
2936 break;
2937 case POLL_DEREGISTER:
ba39cc82 2938 bge_enable_intr(sc);
315fe0ee
MD
2939 break;
2940 case POLL_AND_CHECK_STATUS:
315fe0ee
MD
2941 /*
2942 * Process link state changes.
2943 */
2944 status = CSR_READ_4(sc, BGE_MAC_STS);
2945 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2946 sc->bge_link_evt = 0;
2947 sc->bge_link_upd(sc, status);
2948 }
2949 /* fall through */
2950 case POLL_ONLY:
90ad1c96
SZ
2951 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2952 sc->bge_status_tag = sblk->bge_status_tag;
2953 /*
2954 * Use a load fence to ensure that status_tag
2955 * is saved before rx_prod and tx_cons.
2956 */
2957 cpu_lfence();
2958 }
2959 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2960 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
315fe0ee 2961 if (ifp->if_flags & IFF_RUNNING) {
90ad1c96
SZ
2962 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2963 if (sc->bge_rx_saved_considx != rx_prod)
2964 bge_rxeof(sc, rx_prod);
2965
2966 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2967 if (sc->bge_tx_saved_considx != tx_cons)
2968 bge_txeof(sc, tx_cons);
315fe0ee
MD
2969 }
2970 break;
2971 }
2972}
2973
2974#endif
2975
984263bc 2976static void
33c39a69 2977bge_intr(void *xsc)
984263bc 2978{
bf522c7f 2979 struct bge_softc *sc = xsc;
33c39a69 2980 struct ifnet *ifp = &sc->arpcom.ac_if;
6b880771
SZ
2981 uint32_t status;
2982
2983 logif(intr);
0029ccf6 2984
142ca760
SZ
2985 /*
2986 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2987 * disable interrupts by writing nonzero like we used to, since with
2988 * our current organization this just gives complications and
2989 * pessimizations for re-enabling interrupts. We used to have races
2990 * instead of the necessary complications. Disabling interrupts
2991 * would just reduce the chance of a status update while we are
2992 * running (by switching to the interrupt-mode coalescence
2993 * parameters), but this chance is already very low so it is more
2994 * efficient to get another interrupt than prevent it.
2995 *
2996 * We do the ack first to ensure another interrupt if there is a
2997 * status update after the ack. We don't check for the status
2998 * changing later because it is more efficient to get another
2999 * interrupt than prevent it, not quite as above (not checking is
3000 * a smaller optimization than not toggling the interrupt enable,
3001 * since checking doesn't involve PCI accesses and toggling require
3002 * the status check). So toggling would probably be a pessimization
3003 * even with MSI. It would only be needed for using a task queue.
3004 */
591dfc77 3005 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
142ca760 3006
984263bc
MD
3007 /*
3008 * Process link state changes.
984263bc 3009 */
db861466
SZ
3010 status = CSR_READ_4(sc, BGE_MAC_STS);
3011 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
3012 sc->bge_link_evt = 0;
3013 sc->bge_link_upd(sc, status);
984263bc
MD
3014 }
3015
3016 if (ifp->if_flags & IFF_RUNNING) {
90ad1c96
SZ
3017 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3018 uint16_t rx_prod, tx_cons;
3019
3020 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3021 if (sc->bge_rx_saved_considx != rx_prod)
3022 bge_rxeof(sc, rx_prod);
3023
3024 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3025 if (sc->bge_tx_saved_considx != tx_cons)
3026 bge_txeof(sc, tx_cons);
3027 }
3028
3029 if (sc->bge_coal_chg)
3030 bge_coal_change(sc);
3031}
3032
3033static void
3034bge_intr_status_tag(void *xsc)
3035{
3036 struct bge_softc *sc = xsc;
3037 struct ifnet *ifp = &sc->arpcom.ac_if;
3038 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3039 uint16_t rx_prod, tx_cons;
3040 uint32_t val, status;
3041
3042 if (sc->bge_status_tag == sblk->bge_status_tag) {
3043 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3044 if (val & BGE_PCISTAT_INTR_NOTACT)
3045 return;
3046 }
3047
3048 /*
3049 * NOTE:
3050 * Interrupt will have to be disabled if tagged status
3051 * is used, else interrupt will always be asserted on
3052 * certain chips (at least on BCM5750 AX/BX).
3053 */
3054 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3055
3056 sc->bge_status_tag = sblk->bge_status_tag;
3057 /*
3058 * Use a load fence to ensure that status_tag is saved
3059 * before rx_prod and tx_cons.
3060 */
3061 cpu_lfence();
3062
3063 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3064 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3065 status = sblk->bge_status;
3066
3067 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) {
3068 val = CSR_READ_4(sc, BGE_MAC_STS);
3069 if ((val & sc->bge_link_chg) || sc->bge_link_evt) {
3070 sc->bge_link_evt = 0;
3071 sc->bge_link_upd(sc, val);
3072 }
3073 }
3074
3075 if (ifp->if_flags & IFF_RUNNING) {
3076 if (sc->bge_rx_saved_considx != rx_prod)
3077 bge_rxeof(sc, rx_prod);
984263bc 3078
90ad1c96
SZ
3079 if (sc->bge_tx_saved_considx != tx_cons)
3080 bge_txeof(sc, tx_cons);
984263bc 3081 }
055d06f0 3082
90ad1c96
SZ
3083 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3084
055d06f0
SZ
3085 if (sc->bge_coal_chg)
3086 bge_coal_change(sc);
984263bc
MD
3087}
3088
3089static void
33c39a69 3090bge_tick(void *xsc)
78195a76
MD
3091{
3092 struct bge_softc *sc = xsc;
3093 struct ifnet *ifp = &sc->arpcom.ac_if;
3094
3095 lwkt_serialize_enter(ifp->if_serializer);
984263bc 3096
0ecb11d7 3097 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
3098 bge_stats_update_regs(sc);
3099 else
3100 bge_stats_update(sc);
9a717c15 3101
0ecb11d7 3102 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
3103 /*
3104 * Since in TBI mode auto-polling can't be used we should poll
3105 * link status manually. Here we register pending link event
3106 * and trigger interrupt.
3107 */
3108 sc->bge_link_evt++;
5225ba10
SZ
3109 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3110 BGE_IS_5788(sc))
3111 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3112 else
3113 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3f82ed83 3114 } else if (!sc->bge_link) {
db861466 3115 mii_tick(device_get_softc(sc->bge_miibus));
984263bc
MD
3116 }
3117
db861466
SZ
3118 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3119
3120 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
3121}
3122
7e40b8c5 3123static void
33c39a69 3124bge_stats_update_regs(struct bge_softc *sc)
7e40b8c5 3125{
33c39a69 3126 struct ifnet *ifp = &sc->arpcom.ac_if;
7e40b8c5 3127 struct bge_mac_stats_regs stats;
33c39a69 3128 uint32_t *s;
7e40b8c5
HP
3129 int i;
3130
33c39a69 3131 s = (uint32_t *)&stats;
7e40b8c5
HP
3132 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3133 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3134 s++;
3135 }
3136
3137 ifp->if_collisions +=
3138 (stats.dot3StatsSingleCollisionFrames +
3139 stats.dot3StatsMultipleCollisionFrames +
3140 stats.dot3StatsExcessiveCollisions +
3141 stats.dot3StatsLateCollisions) -
3142 ifp->if_collisions;
7e40b8c5
HP
3143}
3144
984263bc 3145static void
33c39a69 3146bge_stats_update(struct bge_softc *sc)
984263bc 3147{
33c39a69 3148 struct ifnet *ifp = &sc->arpcom.ac_if;
20c9a969
SZ
3149 bus_size_t stats;
3150
3151 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
984263bc 3152
20c9a969
SZ
3153#define READ_STAT(sc, stats, stat) \
3154 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
984263bc
MD
3155
3156 ifp->if_collisions +=
20c9a969
SZ
3157 (READ_STAT(sc, stats,
3158 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3159 READ_STAT(sc, stats,
3160 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3161 READ_STAT(sc, stats,
3162 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3163 READ_STAT(sc, stats,
3164 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
984263bc
MD
3165 ifp->if_collisions;
3166
20c9a969
SZ
3167#undef READ_STAT
3168
984263bc
MD
3169#ifdef notdef
3170 ifp->if_collisions +=
3171 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3172 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3173 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3174 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3175 ifp->if_collisions;
3176#endif
984263bc
MD
3177}
3178
3179/*
3180 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3181 * pointers to descriptors.
3182 */
3183static int
4a607ed6 3184bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
984263bc 3185{
20c9a969 3186 struct bge_tx_bd *d = NULL;
33c39a69 3187 uint16_t csum_flags = 0;
20c9a969
SZ
3188 bus_dma_segment_t segs[BGE_NSEG_NEW];
3189 bus_dmamap_t map;
2de621e9 3190 int error, maxsegs, nsegs, idx, i;
e0b35c1f 3191 struct mbuf *m_head = *m_head0, *m_new;
984263bc 3192
984263bc
MD
3193 if (m_head->m_pkthdr.csum_flags) {
3194 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3195 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3196 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3197 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3198 if (m_head->m_flags & M_LASTFRAG)
3199 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3200 else if (m_head->m_flags & M_FRAG)
3201 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3202 }
20c9a969
SZ
3203
3204 idx = *txidx;
3205 map = sc->bge_cdata.bge_tx_dmamap[idx];
3206
3207 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3208 KASSERT(maxsegs >= BGE_NSEG_SPARE,
ed20d0e3 3209 ("not enough segments %d", maxsegs));
20c9a969
SZ
3210
3211 if (maxsegs > BGE_NSEG_NEW)
3212 maxsegs = BGE_NSEG_NEW;
3213
cb623c48
SZ
3214 /*
3215 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3216 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3217 * but when such padded frames employ the bge IP/TCP checksum
3218 * offload, the hardware checksum assist gives incorrect results
3219 * (possibly from incorporating its own padding into the UDP/TCP
3220 * checksum; who knows). If we pad such runts with zeros, the
2679514c 3221 * onboard checksum comes out correct.
cb623c48
SZ
3222 */
3223 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3224 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
cf12ba3c 3225 error = m_devpad(m_head, BGE_MIN_FRAME);
2679514c
SZ
3226 if (error)
3227 goto back;
cb623c48 3228 }
2679514c 3229
e0b35c1f
SZ
3230 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3231 m_new = bge_defrag_shortdma(m_head);
3232 if (m_new == NULL) {
3233 error = ENOBUFS;
3234 goto back;
3235 }
3236 *m_head0 = m_head = m_new;
3237 }
c728ae98
SZ
3238 if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3239 m_head->m_next != NULL) {
c728ae98
SZ
3240 /*
3241 * Forcefully defragment mbuf chain to overcome hardware
3242 * limitation which only support a single outstanding
3243 * DMA read operation. If it fails, keep moving on using
3244 * the original mbuf chain.
3245 */
3246 m_new = m_defrag(m_head, MB_DONTWAIT);
3247 if (m_new != NULL)
3248 *m_head0 = m_head = m_new;
3249 }
3250
2de621e9
SZ
3251 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3252 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3253 if (error)
20c9a969 3254 goto back;
984263bc 3255
2de621e9 3256 m_head = *m_head0;
ddca511d 3257 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
984263bc 3258
20c9a969
SZ
3259 for (i = 0; ; i++) {
3260 d = &sc->bge_ldata.bge_tx_ring[idx];
984263bc 3261
2de621e9
SZ
3262 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3263 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
20c9a969
SZ
3264 d->bge_len = segs[i].ds_len;
3265 d->bge_flags = csum_flags;
984263bc 3266
2de621e9 3267 if (i == nsegs - 1)
20c9a969
SZ
3268 break;
3269 BGE_INC(idx, BGE_TX_RING_CNT);
3270 }
3271 /* Mark the last segment as end of packet... */
3272 d->bge_flags |= BGE_TXBDFLAG_END;
984263bc 3273
20c9a969
SZ
3274 /* Set vlan tag to the first segment of the packet. */
3275 d = &sc->bge_ldata.bge_tx_ring[*txidx];
83790f85 3276 if (m_head->m_flags & M_VLANTAG) {
20c9a969 3277 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
83790f85 3278 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
20c9a969
SZ
3279 } else {
3280 d->bge_vlan_tag = 0;
3281 }
3282
3283 /*
3284 * Insure that the map for this transmission is placed at
3285 * the array index of the last descriptor in this chain.
3286 */
3287 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3288 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3289 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2de621e9 3290 sc->bge_txcnt += nsegs;
20c9a969
SZ
3291
3292 BGE_INC(idx, BGE_TX_RING_CNT);
3293 *txidx = idx;
3294back:
4a607ed6 3295 if (error) {
2de621e9 3296 m_freem(*m_head0);
4a607ed6
SZ
3297 *m_head0 = NULL;
3298 }
20c9a969 3299 return error;
984263bc
MD
3300}
3301
3302/*
3303 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3304 * to the mbuf data regions directly in the transmit descriptors.
3305 */
3306static void
33c39a69 3307bge_start(struct ifnet *ifp)
984263bc 3308{
20c9a969 3309 struct bge_softc *sc = ifp->if_softc;
984263bc 3310 struct mbuf *m_head = NULL;
20c9a969 3311 uint32_t prodidx;
2f54d1d2 3312 int need_trans;
984263bc 3313
d47d96f2 3314 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
984263bc
MD
3315 return;
3316
94db8384 3317 prodidx = sc->bge_tx_prodidx;
984263bc 3318
2f54d1d2 3319 need_trans = 0;
75544bcd 3320 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
9db4b353 3321 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
3322 if (m_head == NULL)
3323 break;
3324
3325 /*
cb623c48
SZ
3326 * XXX
3327 * The code inside the if() block is never reached since we
3328 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3329 * requests to checksum TCP/UDP in a fragmented packet.
3330 *
984263bc
MD
3331 * XXX
3332 * safety overkill. If this is a fragmented packet chain
3333 * with delayed TCP/UDP checksums, then only encapsulate
3334 * it if we have enough descriptors to handle the entire
3335 * chain at once.
3336 * (paranoia -- may not actually be needed)
3337 */
9db4b353
SZ
3338 if ((m_head->m_flags & M_FIRSTFRAG) &&
3339 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
984263bc 3340 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
9db4b353 3341 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
984263bc 3342 ifp->if_flags |= IFF_OACTIVE;
9db4b353 3343 ifq_prepend(&ifp->if_snd, m_head);
984263bc
MD
3344