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ioapic: By default, disable I/O APIC if we are booting on a virtual machine
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
984263bc
MD		 1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD		 41#include "use_npx.h"
42#include "use_isa.h"
984263bc
MD		 43#include "opt_compat.h"
44#include "opt_cpu.h"
45#include "opt_ddb.h"
46#include "opt_directio.h"
47#include "opt_inet.h"
48#include "opt_ipx.h"
49#include "opt_maxmem.h"
50#include "opt_msgbuf.h"
51#include "opt_perfmon.h"
52#include "opt_swap.h"
984263bc
MD		 53#include "opt_userconfig.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sysproto.h>
58#include <sys/signalvar.h>
59#include <sys/kernel.h>
60#include <sys/linker.h>
61#include <sys/malloc.h>
62#include <sys/proc.h>
895c1f85 63#include <sys/priv.h>
984263bc
MD		 64#include <sys/buf.h>
65#include <sys/reboot.h>
984263bc
MD		 66#include <sys/mbuf.h>
67#include <sys/msgbuf.h>
68#include <sys/sysent.h>
69#include <sys/sysctl.h>
70#include <sys/vmmeter.h>
71#include <sys/bus.h>
a722be49 72#include <sys/upcall.h>
cb7f4ab1 73#include <sys/usched.h>
527fddf7 74#include <sys/reg.h>
984263bc
MD		 75
76#include <vm/vm.h>
77#include <vm/vm_param.h>
78#include <sys/lock.h>
79#include <vm/vm_kern.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_map.h>
83#include <vm/vm_pager.h>
84#include <vm/vm_extern.h>
85
4b5f931b 86#include <sys/thread2.h>
684a93c4 87#include <sys/mplock2.h>
320c681e 88#include <sys/mutex2.h>
4b5f931b 89
984263bc
MD		 90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
984263bc 96#include <machine/cpu.h>
984263bc
MD		 97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
984263bc
MD		 100#include <machine/md_var.h>
101#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 102#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 103#include <machine/smp.h>
984263bc
MD		 104#ifdef PERFMON
105#include <machine/perfmon.h>
106#endif
107#include <machine/cputypes.h>
87cf6827 108#include <machine/intr_machdep.h>
984263bc
MD		 109
110#ifdef OLD_BUS_ARCH
21ce0dfa 111#include <bus/isa/isa_device.h>
984263bc 112#endif
87cf6827 113#include <machine_base/isa/isa_intr.h>
1f2de5d4 114#include <bus/isa/rtc.h>
984263bc
MD		 115#include <machine/vm86.h>
116#include <sys/random.h>
117#include <sys/ptrace.h>
118#include <machine/sigframe.h>
119
30c5f287 120#include <sys/machintr.h>
9284cddf 121#include <machine_base/icu/icu_abi.h>
7265a4fe 122#include <machine_base/icu/elcr_var.h>
1d6d7089 123#include <machine_base/apic/lapic.h>
ed4d621d 124#include <machine_base/apic/ioapic.h>
a3dd9120 125#include <machine_base/apic/ioapic_abi.h>
d904d4d9 126#include <machine/mptable.h>
30c5f287 127
ff1a75a1
MD		 128#define PHYSMAP_ENTRIES 10
129
d678dc17
MN		 130extern void init386(int first);
131extern void dblfault_handler(void);
984263bc
MD		 132
133extern void printcpuinfo(void); /* XXX header file */
134extern void finishidentcpu(void);
135extern void panicifcpuunsupported(void);
136extern void initializecpu(void);
137
d678dc17 138static void cpu_startup(void *);
d883128f
SZ		 139static void pic_finish(void *);
140static void cpu_finish(void *);
642a6e88 141#ifndef CPU_DISABLE_SSE
d678dc17
MN		 142static void set_fpregs_xmm(struct save87 *, struct savexmm *);
143static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 144#endif /* CPU_DISABLE_SSE */
984263bc
MD		 145#ifdef DIRECTIO
146extern void ffs_rawread_setup(void);
147#endif /* DIRECTIO */
8a8d5d85 148static void init_locks(void);
984263bc 149
7c006a9e 150SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
d883128f
SZ		 151SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
152SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
984263bc 153
984263bc
MD		 154int _udatasel, _ucodesel;
155u_int atdevbase;
c2751817
MD		 156#ifdef SMP
157int64_t tsc_offsets[MAXCPU];
158#else
159int64_t tsc_offsets[1];
160#endif
984263bc
MD		 161
162#if defined(SWTCH_OPTIM_STATS)
163extern int swtch_optim_stats;
164SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
165 CTLFLAG_RD, &swtch_optim_stats, 0, "");
166SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
167 CTLFLAG_RD, &tlb_flush_count, 0, "");
168#endif
169
39d69dae 170long physmem = 0;
984263bc 171
1876681a
SZ		 172u_long ebda_addr = 0;
173
1d903de5
SZ		 174int imcr_present = 0;
175
2abaa030 176int naps = 0; /* # of Applications processors */
320c681e 177struct mtx dt_lock; /* lock for GDT and LDT */
2abaa030 178
ed721f0f
SZ		 179u_int base_memory;
180
984263bc
MD		 181static int
182sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
183{
39d69dae
AH		 184 u_long pmem = ctob(physmem);
185
186 int error = sysctl_handle_long(oidp, &pmem, 0, req);
984263bc
MD		 187 return (error);
188}
189
39d69dae 190SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 191 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
984263bc
MD		 192
193static int
194sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
195{
196 int error = sysctl_handle_int(oidp, 0,
12e4aaff 197 ctob(physmem - vmstats.v_wire_count), req);
984263bc
MD		 198 return (error);
199}
200
201SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
202 0, 0, sysctl_hw_usermem, "IU", "");
203
204static int
205sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
206{
207 int error = sysctl_handle_int(oidp, 0,
208 i386_btop(avail_end - avail_start), req);
209 return (error);
210}
211
212SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
213 0, 0, sysctl_hw_availpages, "I", "");
214
1bda0d3d
MD		 215vm_paddr_t Maxmem;
216vm_paddr_t Realmem;
984263bc 217
ff1a75a1 218vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH		 219vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
220
984263bc
MD		 221
222static vm_offset_t buffer_sva, buffer_eva;
223vm_offset_t clean_sva, clean_eva;
224static vm_offset_t pager_sva, pager_eva;
225static struct trapframe proc0_tf;
226
227static void
f123d5a1 228cpu_startup(void *dummy)
984263bc 229{
c9faf524 230 caddr_t v;
984263bc 231 vm_size_t size = 0;
e4846942 232 vm_offset_t firstaddr;
984263bc 233
984263bc
MD		 234 /*
235 * Good {morning,afternoon,evening,night}.
236 */
26be20a0 237 kprintf("%s", version);
984263bc
MD		 238 startrtclock();
239 printcpuinfo();
240 panicifcpuunsupported();
241#ifdef PERFMON
242 perfmon_init();
243#endif
15dc6550 244 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
MD		 245 (intmax_t)Realmem,
246 (intmax_t)Realmem / 1024 / 1024);
984263bc
MD		 247 /*
248 * Display any holes after the first chunk of extended memory.
249 */
250 if (bootverbose) {
251 int indx;
252
26be20a0 253 kprintf("Physical memory chunk(s):\n");
984263bc 254 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 255 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 256
26be20a0 257 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
984263bc
MD		 258 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
259 size1 / PAGE_SIZE);
260 }
261 }
262
263 /*
984263bc
MD		 264 * Allocate space for system data structures.
265 * The first available kernel virtual address is in "v".
266 * As pages of kernel virtual memory are allocated, "v" is incremented.
267 * As pages of memory are allocated and cleared,
268 * "firstaddr" is incremented.
269 * An index into the kernel page table corresponding to the
270 * virtual memory address maintained in "v" is kept in "mapaddr".
271 */
272
273 /*
274 * Make two passes. The first pass calculates how much memory is
275 * needed and allocates it. The second pass assigns virtual
276 * addresses to the various data structures.
277 */
278 firstaddr = 0;
279again:
280 v = (caddr_t)firstaddr;
281
282#define valloc(name, type, num) \
283 (name) = (type *)v; v = (caddr_t)((name)+(num))
284#define valloclim(name, type, num, lim) \
285 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
286
984263bc
MD		 287 /*
288 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
289 * For the first 64MB of ram nominally allocate sufficient buffers to
290 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
291 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
292 * the buffer cache we limit the eventual kva reservation to
293 * maxbcache bytes.
294 *
295 * factor represents the 1/4 x ram conversion.
296 */
297 if (nbuf == 0) {
298 int factor = 4 * BKVASIZE / 1024;
299 int kbytes = physmem * (PAGE_SIZE / 1024);
300
301 nbuf = 50;
302 if (kbytes > 4096)
303 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
304 if (kbytes > 65536)
305 nbuf += (kbytes - 65536) * 2 / (factor * 5);
306 if (maxbcache && nbuf > maxbcache / BKVASIZE)
307 nbuf = maxbcache / BKVASIZE;
308 }
309
310 /*
311 * Do not allow the buffer_map to be more then 1/2 the size of the
312 * kernel_map.
313 */
e4846942
MD		 314 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
315 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
26be20a0 316 kprintf("Warning: nbufs capped at %d\n", nbuf);
984263bc
MD		 317 }
318
948209ce
MD		 319 /* limit to 128 on i386 */
320 nswbuf = max(min(nbuf/4, 128), 16);
984263bc
MD		 321#ifdef NSWBUF_MIN
322 if (nswbuf < NSWBUF_MIN)
323 nswbuf = NSWBUF_MIN;
324#endif
325#ifdef DIRECTIO
326 ffs_rawread_setup();
327#endif
328
329 valloc(swbuf, struct buf, nswbuf);
330 valloc(buf, struct buf, nbuf);
984263bc
MD		 331
332 /*
333 * End of first pass, size has been calculated so allocate memory
334 */
335 if (firstaddr == 0) {
336 size = (vm_size_t)(v - firstaddr);
e4846942 337 firstaddr = kmem_alloc(&kernel_map, round_page(size));
984263bc
MD		 338 if (firstaddr == 0)
339 panic("startup: no room for tables");
340 goto again;
341 }
342
343 /*
344 * End of second pass, addresses have been assigned
345 */
346 if ((vm_size_t)(v - firstaddr) != size)
347 panic("startup: table size inconsistency");
348
e4846942
MD		 349 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
350 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
351 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
352 (nbuf*BKVASIZE));
353 buffer_map.system_map = 1;
354 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
355 (nswbuf*MAXPHYS) + pager_map_size);
356 pager_map.system_map = 1;
984263bc 357
984263bc
MD		 358#if defined(USERCONFIG)
359 userconfig();
360 cninit(); /* the preferred console may have changed */
361#endif
362
15dc6550 363 kprintf("avail memory = %ju (%ju MB)\n",
79d182b0
MD		 364 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
365 (intmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
366 1024 / 1024);
984263bc
MD		 367
368 /*
369 * Set up buffers, so they can be used to read disk labels.
370 */
371 bufinit();
372 vm_pager_bufferinit();
d883128f
SZ		 373}
374
375static void
376cpu_finish(void *dummy __unused)
377{
378 cpu_setregs();
379}
380
381static void
382pic_finish(void *dummy __unused)
383{
384 /* Log ELCR information */
385 elcr_dump();
be1519b3 386
d904d4d9
SZ		 387 /* Log MPTABLE information */
388 mptable_pci_int_dump();
389
be1519b3
SZ		 390 /* Finalize PIC */
391 MachIntrABI.finalize();
984263bc
MD		 392}
393
984263bc
MD		 394/*
395 * Send an interrupt to process.
396 *
397 * Stack is set up to allow sigcode stored
398 * at top to call routine, followed by kcall
399 * to sigreturn routine below. After sigreturn
400 * resets the signal mask, the stack, and the
401 * frame pointer, it returns to the user
402 * specified pc, psl.
403 */
984263bc 404void
f123d5a1 405sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 406{
065b709a
SS		 407 struct lwp *lp = curthread->td_lwp;
408 struct proc *p = lp->lwp_proc;
984263bc
MD		 409 struct trapframe *regs;
410 struct sigacts *psp = p->p_sigacts;
411 struct sigframe sf, *sfp;
412 int oonstack;
413
065b709a
SS		 414 regs = lp->lwp_md.md_regs;
415 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
MD		 416
417 /* save user context */
418 bzero(&sf, sizeof(struct sigframe));
419 sf.sf_uc.uc_sigmask = *mask;
065b709a 420 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 421 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 422 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 423
ce3d8c4d
MD		 424 /* make the size of the saved context visible to userland */
425 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
426
984263bc 427 /* Allocate and validate space for the signal handler context. */
4643740a 428 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 429 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS		 430 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
431 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
432 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 433 } else {
984263bc 434 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 435 }
984263bc
MD		 436
437 /* Translate the signal is appropriate */
438 if (p->p_sysent->sv_sigtbl) {
439 if (sig <= p->p_sysent->sv_sigsize)
440 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
441 }
442
443 /* Build the argument list for the signal handler. */
444 sf.sf_signum = sig;
445 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 446 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
984263bc
MD		 447 /* Signal handler installed with SA_SIGINFO. */
448 sf.sf_siginfo = (register_t)&sfp->sf_si;
449 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
450
451 /* fill siginfo structure */
452 sf.sf_si.si_signo = sig;
453 sf.sf_si.si_code = code;
454 sf.sf_si.si_addr = (void*)regs->tf_err;
455 }
456 else {
457 /* Old FreeBSD-style arguments. */
458 sf.sf_siginfo = code;
459 sf.sf_addr = regs->tf_err;
460 sf.sf_ahu.sf_handler = catcher;
461 }
462
463 /*
464 * If we're a vm86 process, we want to save the segment registers.
465 * We also change eflags to be our emulated eflags, not the actual
466 * eflags.
467 */
468 if (regs->tf_eflags & PSL_VM) {
469 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 470 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD		 471
472 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
473 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
474 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
475 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
476
477 if (vm86->vm86_has_vme == 0)
478 sf.sf_uc.uc_mcontext.mc_eflags =
479 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
480 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
481
482 /*
483 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
484 * syscalls made by the signal handler. This just avoids
485 * wasting time for our lazy fixup of such faults. PSL_NT
486 * does nothing in vm86 mode, but vm86 programs can set it
487 * almost legitimately in probes for old cpu types.
488 */
489 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
490 }
491
492 /*
1b251f0a
MD		 493 * Save the FPU state and reinit the FP unit
494 */
495 npxpush(&sf.sf_uc.uc_mcontext);
496
497 /*
984263bc
MD		 498 * Copy the sigframe out to the user's stack.
499 */
500 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
501 /*
502 * Something is wrong with the stack pointer.
503 * ...Kill the process.
504 */
b276424c 505 sigexit(lp, SIGILL);
984263bc
MD		 506 }
507
508 regs->tf_esp = (int)sfp;
509 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE		 510
511 /*
512 * i386 abi specifies that the direction flag must be cleared
513 * on function entry
514 */
515 regs->tf_eflags &= ~(PSL_T|PSL_D);
516
984263bc
MD		 517 regs->tf_cs = _ucodesel;
518 regs->tf_ds = _udatasel;
519 regs->tf_es = _udatasel;
dd4ad62d
MD		 520
521 /*
522 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD		 523 * the userland program might be using both.
524 *
525 * However, if a T_PROTFLT occured the segment registers could be
526 * totally broken. They must be reset in order to be able to
527 * return to userland.
dd4ad62d 528 */
4e7c41c5
MD		 529 if (regs->tf_trapno == T_PROTFLT) {
530 regs->tf_fs = _udatasel;
531 regs->tf_gs = _udatasel;
532 }
984263bc
MD		 533 regs->tf_ss = _udatasel;
534}
535
536/*
4a22e893 537 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD		 538 * VM context. Remove any items that would otherwise create a privilage
539 * issue.
4a22e893 540 *
4e7c41c5
MD		 541 * XXX at the moment we allow userland to set the resume flag. Is this a
542 * bad idea?
4a22e893
MD		 543 */
544int
545cpu_sanitize_frame(struct trapframe *frame)
546{
547 frame->tf_cs = _ucodesel;
548 frame->tf_ds = _udatasel;
4e7c41c5
MD		 549 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
550#if 0
4a22e893 551 frame->tf_fs = _udatasel;
4e7c41c5
MD		 552 frame->tf_gs = _udatasel;
553#endif
4a22e893 554 frame->tf_ss = _udatasel;
4e7c41c5 555 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD		 556 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
557 return(0);
558}
559
4e7c41c5
MD		 560int
561cpu_sanitize_tls(struct savetls *tls)
562{
563 struct segment_descriptor *desc;
564 int i;
565
566 for (i = 0; i < NGTLS; ++i) {
567 desc = &tls->tls[i];
568 if (desc->sd_dpl == 0 && desc->sd_type == 0)
569 continue;
570 if (desc->sd_def32 == 0)
571 return(ENXIO);
572 if (desc->sd_type != SDT_MEMRWA)
573 return(ENXIO);
574 if (desc->sd_dpl != SEL_UPL)
575 return(ENXIO);
576 if (desc->sd_xx != 0 || desc->sd_p != 1)
577 return(ENXIO);
578 }
579 return(0);
580}
581
4a22e893 582/*
65957d54 583 * sigreturn(ucontext_t *sigcntxp)
41c20dac 584 *
984263bc
MD		 585 * System call to cleanup state after a signal
586 * has been taken. Reset signal mask and
587 * stack state from context left by sendsig (above).
588 * Return to previous pc and psl as specified by
589 * context left by sendsig. Check carefully to
590 * make sure that the user has not modified the
591 * state to gain improper privileges.
3919ced0
MD		 592 *
593 * MPSAFE
984263bc
MD		 594 */
595#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
596#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
597
598int
753fd850 599sys_sigreturn(struct sigreturn_args *uap)
984263bc 600{
065b709a 601 struct lwp *lp = curthread->td_lwp;
984263bc 602 struct trapframe *regs;
1b251f0a 603 ucontext_t uc;
984263bc 604 ucontext_t *ucp;
1b251f0a
MD		 605 int cs;
606 int eflags;
607 int error;
984263bc 608
1b251f0a
MD		 609 /*
610 * We have to copy the information into kernel space so userland
611 * can't modify it while we are sniffing it.
612 */
065b709a 613 regs = lp->lwp_md.md_regs;
1b251f0a
MD		 614 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
615 if (error)
616 return (error);
617 ucp = &uc;
984263bc
MD		 618 eflags = ucp->uc_mcontext.mc_eflags;
619
620 if (eflags & PSL_VM) {
621 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
622 struct vm86_kernel *vm86;
623
624 /*
625 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
626 * set up the vm86 area, and we can't enter vm86 mode.
627 */
065b709a 628 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 629 return (EINVAL);
065b709a 630 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD		 631 if (vm86->vm86_inited == 0)
632 return (EINVAL);
633
634 /* go back to user mode if both flags are set */
635 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 636 trapsignal(lp, SIGBUS, 0);
984263bc
MD		 637
638 if (vm86->vm86_has_vme) {
639 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
640 (eflags & VME_USERCHANGE) | PSL_VM;
641 } else {
642 vm86->vm86_eflags = eflags; /* save VIF, VIP */
e2742650
MD		 643 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
644 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 645 }
4e7c41c5 646 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
984263bc
MD		 647 tf->tf_eflags = eflags;
648 tf->tf_vm86_ds = tf->tf_ds;
649 tf->tf_vm86_es = tf->tf_es;
650 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 651 tf->tf_vm86_gs = tf->tf_gs;
984263bc
MD		 652 tf->tf_ds = _udatasel;
653 tf->tf_es = _udatasel;
4e7c41c5 654#if 0
984263bc 655 tf->tf_fs = _udatasel;
4e7c41c5
MD		 656 tf->tf_gs = _udatasel;
657#endif
984263bc
MD		 658 } else {
659 /*
660 * Don't allow users to change privileged or reserved flags.
661 */
662 /*
663 * XXX do allow users to change the privileged flag PSL_RF.
664 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
665 * should sometimes set it there too. tf_eflags is kept in
666 * the signal context during signal handling and there is no
667 * other place to remember it, so the PSL_RF bit may be
668 * corrupted by the signal handler without us knowing.
669 * Corruption of the PSL_RF bit at worst causes one more or
670 * one less debugger trap, so allowing it is fairly harmless.
671 */
672 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 673 kprintf("sigreturn: eflags = 0x%x\n", eflags);
984263bc
MD		 674 return(EINVAL);
675 }
676
677 /*
678 * Don't allow users to load a valid privileged %cs. Let the
679 * hardware check for invalid selectors, excess privilege in
680 * other selectors, invalid %eip's and invalid %esp's.
681 */
682 cs = ucp->uc_mcontext.mc_cs;
683 if (!CS_SECURE(cs)) {
26be20a0 684 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 685 trapsignal(lp, SIGBUS, T_PROTFLT);
984263bc
MD		 686 return(EINVAL);
687 }
4e7c41c5 688 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
MD		 689 }
690
4b486183 691 /*
1b251f0a
MD		 692 * Restore the FPU state from the frame
693 */
3919ced0 694 crit_enter();
1b251f0a
MD		 695 npxpop(&ucp->uc_mcontext);
696
984263bc 697 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 698 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 699 else
065b709a 700 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 701
065b709a
SS		 702 lp->lwp_sigmask = ucp->uc_sigmask;
703 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 704 crit_exit();
984263bc
MD		 705 return(EJUSTRETURN);
706}
707
708/*
a722be49
MD		 709 * Stack frame on entry to function. %eax will contain the function vector,
710 * %ecx will contain the function data. flags, ecx, and eax will have
711 * already been pushed on the stack.
712 */
713struct upc_frame {
714 register_t eax;
715 register_t ecx;
0a455ac5 716 register_t edx;
a722be49
MD		 717 register_t flags;
718 register_t oldip;
719};
720
721void
722sendupcall(struct vmupcall *vu, int morepending)
723{
065b709a 724 struct lwp *lp = curthread->td_lwp;
a722be49
MD		 725 struct trapframe *regs;
726 struct upcall upcall;
727 struct upc_frame upc_frame;
6e58b5df 728 int crit_count = 0;
a722be49
MD		 729
730 /*
69c61fbe
MD		 731 * If we are a virtual kernel running an emulated user process
732 * context, switch back to the virtual kernel context before
733 * trying to post the signal.
734 */
39005e16 735 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 736 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 737 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD		 738 }
739
740 /*
a722be49
MD		 741 * Get the upcall data structure
742 */
065b709a 743 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD		 744 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
745 ) {
a722be49 746 vu->vu_pending = 0;
26be20a0 747 kprintf("bad upcall address\n");
a722be49
MD		 748 return;
749 }
750
751 /*
752 * If the data structure is already marked pending or has a critical
753 * section count, mark the data structure as pending and return
754 * without doing an upcall. vu_pending is left set.
755 */
6e58b5df
MD		 756 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
757 if (upcall.upc_pending < vu->vu_pending) {
758 upcall.upc_pending = vu->vu_pending;
065b709a 759 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 760 sizeof(upcall.upc_pending));
a722be49
MD		 761 }
762 return;
763 }
764
765 /*
766 * We can run this upcall now, clear vu_pending.
767 *
768 * Bump our critical section count and set or clear the
769 * user pending flag depending on whether more upcalls are
770 * pending. The user will be responsible for calling
771 * upc_dispatch(-1) to process remaining upcalls.
772 */
773 vu->vu_pending = 0;
6e58b5df 774 upcall.upc_pending = morepending;
f9235b6d 775 ++crit_count;
065b709a 776 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD		 777 sizeof(upcall.upc_pending));
778 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
779 sizeof(int));
a722be49
MD		 780
781 /*
782 * Construct a stack frame and issue the upcall
783 */
065b709a 784 regs = lp->lwp_md.md_regs;
a722be49
MD		 785 upc_frame.eax = regs->tf_eax;
786 upc_frame.ecx = regs->tf_ecx;
0a455ac5 787 upc_frame.edx = regs->tf_edx;
a722be49
MD		 788 upc_frame.flags = regs->tf_eflags;
789 upc_frame.oldip = regs->tf_eip;
790 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
791 sizeof(upc_frame)) != 0) {
26be20a0 792 kprintf("bad stack on upcall\n");
a722be49
MD		 793 } else {
794 regs->tf_eax = (register_t)vu->vu_func;
795 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 796 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD		 797 regs->tf_eip = (register_t)vu->vu_ctx;
798 regs->tf_esp -= sizeof(upc_frame);
799 }
800}
801
802/*
803 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD		 804 * we have to return EJUSTRETURN in order to prevent eax and edx from
805 * being overwritten by the syscall return value.
a722be49
MD		 806 *
807 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
808 * and the function pointer in %eax.
809 */
810int
d678dc17 811fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD		 812{
813 struct upc_frame upc_frame;
065b709a 814 struct lwp *lp = curthread->td_lwp;
a722be49
MD		 815 struct trapframe *regs;
816 int error;
6e58b5df
MD		 817 struct upcall upcall;
818 int crit_count;
a722be49 819
065b709a 820 regs = lp->lwp_md.md_regs;
a722be49 821
065b709a 822 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD		 823 if (error == 0) {
824 if (vu) {
825 /*
826 * This jumps us to the next ready context.
827 */
828 vu->vu_pending = 0;
065b709a 829 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD		 830 crit_count = 0;
831 if (error == 0)
832 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 833 ++crit_count;
a722be49 834 if (error == 0)
6e58b5df 835 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD		 836 regs->tf_eax = (register_t)vu->vu_func;
837 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 838 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD		 839 regs->tf_eip = (register_t)vu->vu_ctx;
840 regs->tf_esp = (register_t)rsp;
841 } else {
842 /*
843 * This returns us to the originally interrupted code.
844 */
845 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
846 regs->tf_eax = upc_frame.eax;
847 regs->tf_ecx = upc_frame.ecx;
0a455ac5 848 regs->tf_edx = upc_frame.edx;
6e58b5df
MD		 849 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
850 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD		 851 regs->tf_eip = upc_frame.oldip;
852 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
853 }
854 }
855 if (error == 0)
856 error = EJUSTRETURN;
857 return(error);
858}
859
860/*
984263bc
MD		 861 * Machine dependent boot() routine
862 *
863 * I haven't seen anything to put here yet
864 * Possibly some stuff might be grafted back here from boot()
865 */
866void
867cpu_boot(int howto)
868{
869}
870
871/*
872 * Shutdown the CPU as much as possible
873 */
874void
875cpu_halt(void)
876{
877 for (;;)
1184892f 878 __asm__ __volatile("hlt");
984263bc
MD		 879}
880
881/*
8ad65e08
MD		 882 * cpu_idle() represents the idle LWKT. You cannot return from this function
883 * (unless you want to blow things up!). Instead we look for runnable threads
884 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 885 *
26a0694b 886 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD		 887 * the critical section before doing anything else. lwkt_switch() will
888 * check for pending interrupts due to entering and exiting its own
889 * critical section.
26a0694b 890 *
7d4d6fdb 891 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
7d4d6fdb 892 *
46e562ce
MD		 893 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
894 * 1 to just use hlt and for debugging purposes.
984263bc 895 */
46e562ce 896static int cpu_idle_hlt = 2;
60f945af
MD		 897static int cpu_idle_hltcnt;
898static int cpu_idle_spincnt;
be71787b 899static u_int cpu_idle_repeat = 4;
984263bc
MD		 900SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
901 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD		 902SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
903 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
904SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
905 &cpu_idle_spincnt, 0, "Idle loop entry spins");
be71787b
MD		 906SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
907 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 908
f9d8cd12
MD		 909static void
910cpu_idle_default_hook(void)
911{
912 /*
913 * We must guarentee that hlt is exactly the instruction
914 * following the sti.
915 */
916 __asm __volatile("sti; hlt");
917}
918
919/* Other subsystems (e.g., ACPI) can hook this later. */
920void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
921
984263bc
MD		 922void
923cpu_idle(void)
924{
be71787b 925 globaldata_t gd = mycpu;
10662728 926 struct thread *td __debugvar = gd->gd_curthread;
be71787b
MD		 927 int reqflags;
928 int quick;
a2a5ad0d 929
26a0694b 930 crit_exit();
f9235b6d 931 KKASSERT(td->td_critcount == 0);
8ad65e08 932 for (;;) {
a2a5ad0d
MD		 933 /*
934 * See if there are any LWKTs ready to go.
935 */
8ad65e08 936 lwkt_switch();
a2a5ad0d
MD		 937
938 /*
be71787b
MD		 939 * When halting inside a cli we must check for reqflags
940 * races, particularly [re]schedule requests. Running
941 * splz() does the job.
942 *
943 * cpu_idle_hlt:
944 * 0 Never halt, just spin
945 *
946 * 1 Always use HLT (or MONITOR/MWAIT if avail).
947 * This typically eats more power than the
948 * ACPI halt.
949 *
950 * 2 Use HLT/MONITOR/MWAIT up to a point and then
951 * use the ACPI halt (default). This is a hybrid
952 * approach. See machdep.cpu_idle_repeat.
953 *
954 * 3 Always use the ACPI halt. This typically
955 * eats the least amount of power but the cpu
956 * will be slow waking up. Slows down e.g.
957 * compiles and other pipe/event oriented stuff.
958 *
959 *
960 * NOTE: Interrupts are enabled and we are not in a critical
961 * section.
962 *
963 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
964 * don't bother capping gd_idle_repeat, it is ok if
965 * it overflows.
a2a5ad0d 966 */
be71787b
MD		 967 ++gd->gd_idle_repeat;
968 reqflags = gd->gd_reqflags;
969 quick = (cpu_idle_hlt == 1) ||
970 (cpu_idle_hlt < 3 &&
971 gd->gd_idle_repeat < cpu_idle_repeat);
972
973 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
974 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
975 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
976 ++cpu_idle_hltcnt;
977 } else if (cpu_idle_hlt) {
a2a5ad0d
MD		 978 __asm __volatile("cli");
979 splz();
be71787b
MD		 980 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
981 if (quick)
7d4d6fdb
MD		 982 cpu_idle_default_hook();
983 else
984 cpu_idle_hook();
985 }
7d4d6fdb 986 __asm __volatile("sti");
60f945af 987 ++cpu_idle_hltcnt;
8ad65e08 988 } else {
60f945af 989 splz();
c5724852 990 __asm __volatile("sti");
60f945af 991 ++cpu_idle_spincnt;
8ad65e08 992 }
984263bc
MD		 993 }
994}
995
7ad8cc6c
SW		 996#ifdef SMP
997
984263bc 998/*
06615ccb
MD		 999 * This routine is called if a spinlock has been held through the
1000 * exponential backoff period and is seriously contested. On a real cpu
1001 * we let it spin.
1002 */
1003void
1004cpu_spinlock_contested(void)
1005{
1006 cpu_pause();
1007}
1008
7ad8cc6c
SW		 1009#endif
1010
06615ccb 1011/*
984263bc
MD		 1012 * Clear registers on exec
1013 */
1014void
08f2f1bb 1015exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 1016{
08f2f1bb
SS		 1017 struct thread *td = curthread;
1018 struct lwp *lp = td->td_lwp;
1019 struct pcb *pcb = td->td_pcb;
bb3cd951 1020 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 1021
984263bc
MD		 1022 /* was i386_user_cleanup() in NetBSD */
1023 user_ldt_free(pcb);
984263bc
MD		 1024
1025 bzero((char *)regs, sizeof(struct trapframe));
1026 regs->tf_eip = entry;
1027 regs->tf_esp = stack;
1028 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1029 regs->tf_ss = _udatasel;
1030 regs->tf_ds = _udatasel;
1031 regs->tf_es = _udatasel;
1032 regs->tf_fs = _udatasel;
4e7c41c5 1033 regs->tf_gs = _udatasel;
984263bc
MD		 1034 regs->tf_cs = _ucodesel;
1035
1036 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1037 regs->tf_ebx = ps_strings;
1038
1039 /*
1040 * Reset the hardware debug registers if they were in use.
1041 * They won't have any meaning for the newly exec'd process.
1042 */
1043 if (pcb->pcb_flags & PCB_DBREGS) {
1044 pcb->pcb_dr0 = 0;
1045 pcb->pcb_dr1 = 0;
1046 pcb->pcb_dr2 = 0;
1047 pcb->pcb_dr3 = 0;
1048 pcb->pcb_dr6 = 0;
1049 pcb->pcb_dr7 = 0;
08f2f1bb 1050 if (pcb == td->td_pcb) {
984263bc
MD		 1051 /*
1052 * Clear the debug registers on the running
1053 * CPU, otherwise they will end up affecting
1054 * the next process we switch to.
1055 */
1056 reset_dbregs();
1057 }
1058 pcb->pcb_flags &= ~PCB_DBREGS;
1059 }
1060
1061 /*
1062 * Initialize the math emulator (if any) for the current process.
1063 * Actually, just clear the bit that says that the emulator has
1064 * been initialized. Initialization is delayed until the process
1065 * traps to the emulator (if it is done at all) mainly because
1066 * emulators don't provide an entry point for initialization.
1067 */
08f2f1bb 1068 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD		 1069
1070 /*
a02705a9
MD		 1071 * note: do not set CR0_TS here. npxinit() must do it after clearing
1072 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1073 * in npxdna().
984263bc 1074 */
a02705a9
MD		 1075 crit_enter();
1076 load_cr0(rcr0() | CR0_MP);
984263bc
MD		 1077
1078#if NNPX > 0
1079 /* Initialize the npx (if any) for the current process. */
1080 npxinit(__INITIAL_NPXCW__);
1081#endif
a02705a9 1082 crit_exit();
984263bc 1083
90b9818c
MD		 1084 /*
1085 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD		 1086 * handled in execve simply by setting the 64 bit syscall
1087 * return value to 0.
90b9818c 1088 */
984263bc
MD		 1089}
1090
1091void
1092cpu_setregs(void)
1093{
1094 unsigned int cr0;
1095
1096 cr0 = rcr0();
1097 cr0 |= CR0_NE; /* Done by npxinit() */
1098 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1099 cr0 |= CR0_WP | CR0_AM;
984263bc
MD		 1100 load_cr0(cr0);
1101 load_gs(_udatasel);
1102}
1103
1104static int
1105sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1106{
1107 int error;
1108 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1109 req);
1110 if (!error && req->newptr)
1111 resettodr();
1112 return (error);
1113}
1114
1115SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1116 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1117
1118SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1119 CTLFLAG_RW, &disable_rtc_set, 0, "");
1120
1121SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1122 CTLFLAG_RD, &bootinfo, bootinfo, "");
1123
1124SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1125 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1126
b13267a5 1127extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1128SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1129 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD		 1130
1131/*
1132 * Initialize 386 and configure to run kernel
1133 */
1134
1135/*
1136 * Initialize segments & interrupt table
1137 */
1138
1139int _default_ldt;
1140union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1141static struct gate_descriptor idt0[NIDT];
1142struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1143union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD		 1144
1145/* table descriptors - used to load tables by cpu */
984263bc 1146struct region_descriptor r_gdt, r_idt;
984263bc 1147
984263bc
MD		 1148#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1149extern int has_f00f_bug;
1150#endif
1151
1152static struct i386tss dblfault_tss;
1153static char dblfault_stack[PAGE_SIZE];
1154
1155extern struct user *proc0paddr;
1156
1157
1158/* software prototypes -- in more palatable form */
1159struct soft_segment_descriptor gdt_segs[] = {
1160/* GNULL_SEL 0 Null Descriptor */
1161{ 0x0, /* segment base address */
1162 0x0, /* length */
1163 0, /* segment type */
1164 0, /* segment descriptor priority level */
1165 0, /* segment descriptor present */
1166 0, 0,
1167 0, /* default 32 vs 16 bit size */
1168 0 /* limit granularity (byte/page units)*/ },
1169/* GCODE_SEL 1 Code Descriptor for kernel */
1170{ 0x0, /* segment base address */
1171 0xfffff, /* length - all address space */
1172 SDT_MEMERA, /* segment type */
1173 0, /* segment descriptor priority level */
1174 1, /* segment descriptor present */
1175 0, 0,
1176 1, /* default 32 vs 16 bit size */
1177 1 /* limit granularity (byte/page units)*/ },
1178/* GDATA_SEL 2 Data Descriptor for kernel */
1179{ 0x0, /* segment base address */
1180 0xfffff, /* length - all address space */
1181 SDT_MEMRWA, /* segment type */
1182 0, /* segment descriptor priority level */
1183 1, /* segment descriptor present */
1184 0, 0,
1185 1, /* default 32 vs 16 bit size */
1186 1 /* limit granularity (byte/page units)*/ },
1187/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1188{ 0x0, /* segment base address */
1189 0xfffff, /* length - all address space */
1190 SDT_MEMRWA, /* segment type */
1191 0, /* segment descriptor priority level */
1192 1, /* segment descriptor present */
1193 0, 0,
1194 1, /* default 32 vs 16 bit size */
1195 1 /* limit granularity (byte/page units)*/ },
1196/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1197{
1198 0x0, /* segment base address */
1199 sizeof(struct i386tss)-1,/* length - all address space */
1200 SDT_SYS386TSS, /* segment type */
1201 0, /* segment descriptor priority level */
1202 1, /* segment descriptor present */
1203 0, 0,
1204 0, /* unused - default 32 vs 16 bit size */
1205 0 /* limit granularity (byte/page units)*/ },
1206/* GLDT_SEL 5 LDT Descriptor */
1207{ (int) ldt, /* segment base address */
1208 sizeof(ldt)-1, /* length - all address space */
1209 SDT_SYSLDT, /* segment type */
1210 SEL_UPL, /* segment descriptor priority level */
1211 1, /* segment descriptor present */
1212 0, 0,
1213 0, /* unused - default 32 vs 16 bit size */
1214 0 /* limit granularity (byte/page units)*/ },
1215/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1216{ (int) ldt, /* segment base address */
1217 (512 * sizeof(union descriptor)-1), /* length */
1218 SDT_SYSLDT, /* segment type */
1219 0, /* segment descriptor priority level */
1220 1, /* segment descriptor present */
1221 0, 0,
1222 0, /* unused - default 32 vs 16 bit size */
1223 0 /* limit granularity (byte/page units)*/ },
1224/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1225{ 0x0, /* segment base address */
1226 0x0, /* length - all address space */
1227 0, /* segment type */
1228 0, /* segment descriptor priority level */
1229 0, /* segment descriptor present */
1230 0, 0,
1231 0, /* default 32 vs 16 bit size */
1232 0 /* limit granularity (byte/page units)*/ },
1233/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1234{ 0x400, /* segment base address */
1235 0xfffff, /* length */
1236 SDT_MEMRWA, /* segment type */
1237 0, /* segment descriptor priority level */
1238 1, /* segment descriptor present */
1239 0, 0,
1240 1, /* default 32 vs 16 bit size */
1241 1 /* limit granularity (byte/page units)*/ },
1242/* GPANIC_SEL 9 Panic Tss Descriptor */
1243{ (int) &dblfault_tss, /* segment base address */
1244 sizeof(struct i386tss)-1,/* length - all address space */
1245 SDT_SYS386TSS, /* segment type */
1246 0, /* segment descriptor priority level */
1247 1, /* segment descriptor present */
1248 0, 0,
1249 0, /* unused - default 32 vs 16 bit size */
1250 0 /* limit granularity (byte/page units)*/ },
1251/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1252{ 0, /* segment base address (overwritten) */
1253 0xfffff, /* length */
1254 SDT_MEMERA, /* segment type */
1255 0, /* segment descriptor priority level */
1256 1, /* segment descriptor present */
1257 0, 0,
1258 0, /* default 32 vs 16 bit size */
1259 1 /* limit granularity (byte/page units)*/ },
1260/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1261{ 0, /* segment base address (overwritten) */
1262 0xfffff, /* length */
1263 SDT_MEMERA, /* segment type */
1264 0, /* segment descriptor priority level */
1265 1, /* segment descriptor present */
1266 0, 0,
1267 0, /* default 32 vs 16 bit size */
1268 1 /* limit granularity (byte/page units)*/ },
1269/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1270{ 0, /* segment base address (overwritten) */
1271 0xfffff, /* length */
1272 SDT_MEMRWA, /* segment type */
1273 0, /* segment descriptor priority level */
1274 1, /* segment descriptor present */
1275 0, 0,
1276 1, /* default 32 vs 16 bit size */
1277 1 /* limit granularity (byte/page units)*/ },
1278/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1279{ 0, /* segment base address (overwritten) */
1280 0xfffff, /* length */
1281 SDT_MEMRWA, /* segment type */
1282 0, /* segment descriptor priority level */
1283 1, /* segment descriptor present */
1284 0, 0,
1285 0, /* default 32 vs 16 bit size */
1286 1 /* limit granularity (byte/page units)*/ },
1287/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1288{ 0, /* segment base address (overwritten) */
1289 0xfffff, /* length */
1290 SDT_MEMRWA, /* segment type */
1291 0, /* segment descriptor priority level */
1292 1, /* segment descriptor present */
1293 0, 0,
1294 0, /* default 32 vs 16 bit size */
1295 1 /* limit granularity (byte/page units)*/ },
806bf111
MD		 1296/* GTLS_START 15 TLS */
1297{ 0x0, /* segment base address */
1298 0x0, /* length */
1299 0, /* segment type */
1300 0, /* segment descriptor priority level */
1301 0, /* segment descriptor present */
1302 0, 0,
1303 0, /* default 32 vs 16 bit size */
1304 0 /* limit granularity (byte/page units)*/ },
1305/* GTLS_START+1 16 TLS */
1306{ 0x0, /* segment base address */
1307 0x0, /* length */
1308 0, /* segment type */
1309 0, /* segment descriptor priority level */
1310 0, /* segment descriptor present */
1311 0, 0,
1312 0, /* default 32 vs 16 bit size */
1313 0 /* limit granularity (byte/page units)*/ },
1314/* GTLS_END 17 TLS */
1315{ 0x0, /* segment base address */
1316 0x0, /* length */
1317 0, /* segment type */
1318 0, /* segment descriptor priority level */
1319 0, /* segment descriptor present */
1320 0, 0,
1321 0, /* default 32 vs 16 bit size */
1322 0 /* limit granularity (byte/page units)*/ },
efba76b4
SW		 1323/* GNDIS_SEL 18 NDIS Descriptor */
1324{ 0x0, /* segment base address */
1325 0x0, /* length */
1326 0, /* segment type */
1327 0, /* segment descriptor priority level */
1328 0, /* segment descriptor present */
1329 0, 0,
1330 0, /* default 32 vs 16 bit size */
1331 0 /* limit granularity (byte/page units)*/ },
984263bc
MD		 1332};
1333
1334static struct soft_segment_descriptor ldt_segs[] = {
1335 /* Null Descriptor - overwritten by call gate */
1336{ 0x0, /* segment base address */
1337 0x0, /* length - all address space */
1338 0, /* segment type */
1339 0, /* segment descriptor priority level */
1340 0, /* segment descriptor present */
1341 0, 0,
1342 0, /* default 32 vs 16 bit size */
1343 0 /* limit granularity (byte/page units)*/ },
1344 /* Null Descriptor - overwritten by call gate */
1345{ 0x0, /* segment base address */
1346 0x0, /* length - all address space */
1347 0, /* segment type */
1348 0, /* segment descriptor priority level */
1349 0, /* segment descriptor present */
1350 0, 0,
1351 0, /* default 32 vs 16 bit size */
1352 0 /* limit granularity (byte/page units)*/ },
1353 /* Null Descriptor - overwritten by call gate */
1354{ 0x0, /* segment base address */
1355 0x0, /* length - all address space */
1356 0, /* segment type */
1357 0, /* segment descriptor priority level */
1358 0, /* segment descriptor present */
1359 0, 0,
1360 0, /* default 32 vs 16 bit size */
1361 0 /* limit granularity (byte/page units)*/ },
1362 /* Code Descriptor for user */
1363{ 0x0, /* segment base address */
1364 0xfffff, /* length - all address space */
1365 SDT_MEMERA, /* segment type */
1366 SEL_UPL, /* segment descriptor priority level */
1367 1, /* segment descriptor present */
1368 0, 0,
1369 1, /* default 32 vs 16 bit size */
1370 1 /* limit granularity (byte/page units)*/ },
1371 /* Null Descriptor - overwritten by call gate */
1372{ 0x0, /* segment base address */
1373 0x0, /* length - all address space */
1374 0, /* segment type */
1375 0, /* segment descriptor priority level */
1376 0, /* segment descriptor present */
1377 0, 0,
1378 0, /* default 32 vs 16 bit size */
1379 0 /* limit granularity (byte/page units)*/ },
1380 /* Data Descriptor for user */
1381{ 0x0, /* segment base address */
1382 0xfffff, /* length - all address space */
1383 SDT_MEMRWA, /* segment type */
1384 SEL_UPL, /* segment descriptor priority level */
1385 1, /* segment descriptor present */
1386 0, 0,
1387 1, /* default 32 vs 16 bit size */
1388 1 /* limit granularity (byte/page units)*/ },
1389};
1390
1391void
f123d5a1 1392setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD		 1393{
1394 struct gate_descriptor *ip;
1395
1396 ip = idt + idx;
1397 ip->gd_looffset = (int)func;
1398 ip->gd_selector = selec;
1399 ip->gd_stkcpy = 0;
1400 ip->gd_xx = 0;
1401 ip->gd_type = typ;
1402 ip->gd_dpl = dpl;
1403 ip->gd_p = 1;
1404 ip->gd_hioffset = ((int)func)>>16 ;
1405}
1406
1407#define IDTVEC(name) __CONCAT(X,name)
1408
1409extern inthand_t
1410 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1411 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1412 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD		 1413 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1414 IDTVEC(xmm), IDTVEC(syscall),
1415 IDTVEC(rsvd0);
a64ba182 1416extern inthand_t
f9a13fc4 1417 IDTVEC(int0x80_syscall);
984263bc 1418
f7bc9806
MD		 1419#ifdef DEBUG_INTERRUPTS
1420extern inthand_t *Xrsvdary[256];
1421#endif
1422
984263bc 1423void
f123d5a1 1424sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD		 1425{
1426 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1427 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1428 ssd->ssd_type = sd->sd_type;
1429 ssd->ssd_dpl = sd->sd_dpl;
1430 ssd->ssd_p = sd->sd_p;
1431 ssd->ssd_def32 = sd->sd_def32;
1432 ssd->ssd_gran = sd->sd_gran;
1433}
1434
984263bc
MD		 1435/*
1436 * Populate the (physmap) array with base/bound pairs describing the
1437 * available physical memory in the system, then test this memory and
1438 * build the phys_avail array describing the actually-available memory.
1439 *
1440 * If we cannot accurately determine the physical memory map, then use
1441 * value from the 0xE801 call, and failing that, the RTC.
1442 *
1443 * Total memory size may be set by the kernel environment variable
1444 * hw.physmem or the compile-time define MAXMEM.
1445 */
1446static void
1447getmemsize(int first)
1448{
b24cd69c 1449 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD		 1450 int hasbrokenint12;
1451 u_int basemem, extmem;
1452 struct vm86frame vmf;
1453 struct vm86context vmc;
ff1a75a1
MD		 1454 vm_offset_t pa;
1455 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1456 pt_entry_t *pte;
555da584 1457 quad_t maxmem;
984263bc
MD		 1458 struct {
1459 u_int64_t base;
1460 u_int64_t length;
1461 u_int32_t type;
1462 } *smap;
28abdbbb 1463 quad_t dcons_addr, dcons_size;
984263bc 1464
984263bc
MD		 1465 bzero(&vmf, sizeof(struct vm86frame));
1466 bzero(physmap, sizeof(physmap));
1467 basemem = 0;
1468
1469 /*
1470 * Some newer BIOSes has broken INT 12H implementation which cause
1471 * kernel panic immediately. In this case, we need to scan SMAP
1472 * with INT 15:E820 first, then determine base memory size.
1473 */
2ed482dc
MN		 1474 hasbrokenint12 = 0;
1475 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD		 1476 if (hasbrokenint12) {
1477 goto int15e820;
1478 }
1479
1480 /*
7febcc6e
MD		 1481 * Perform "base memory" related probes & setup. If we get a crazy
1482 * value give the bios some scribble space just in case.
984263bc
MD		 1483 */
1484 vm86_intcall(0x12, &vmf);
1485 basemem = vmf.vmf_ax;
1486 if (basemem > 640) {
26be20a0 1487 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD		 1488 "truncating to < 640K\n", basemem);
1489 basemem = 636;
984263bc
MD		 1490 }
1491
1492 /*
1493 * XXX if biosbasemem is now < 640, there is a `hole'
1494 * between the end of base memory and the start of
1495 * ISA memory. The hole may be empty or it may
1496 * contain BIOS code or data. Map it read/write so
1497 * that the BIOS can write to it. (Memory from 0 to
1498 * the physical end of the kernel is mapped read-only
1499 * to begin with and then parts of it are remapped.
1500 * The parts that aren't remapped form holes that
1501 * remain read-only and are unused by the kernel.
1502 * The base memory area is below the physical end of
1503 * the kernel and right now forms a read-only hole.
1504 * The part of it from PAGE_SIZE to
1505 * (trunc_page(biosbasemem * 1024) - 1) will be
1506 * remapped and used by the kernel later.)
1507 *
1508 * This code is similar to the code used in
1509 * pmap_mapdev, but since no memory needs to be
1510 * allocated we simply change the mapping.
1511 */
1512 for (pa = trunc_page(basemem * 1024);
1513 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1514 pte = vtopte(pa + KERNBASE);
984263bc
MD		 1515 *pte = pa | PG_RW | PG_V;
1516 }
1517
1518 /*
1519 * if basemem != 640, map pages r/w into vm86 page table so
1520 * that the bios can scribble on it.
1521 */
b5b32410 1522 pte = vm86paddr;
984263bc
MD		 1523 for (i = basemem / 4; i < 160; i++)
1524 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1525
1526int15e820:
1527 /*
1528 * map page 1 R/W into the kernel page table so we can use it
1529 * as a buffer. The kernel will unmap this page later.
1530 */
b5b32410 1531 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD		 1532 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1533
1534 /*
1535 * get memory map with INT 15:E820
1536 */
1537#define SMAPSIZ sizeof(*smap)
1538#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1539
1540 vmc.npages = 0;
1541 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1542 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1543
1544 physmap_idx = 0;
1545 vmf.vmf_ebx = 0;
1546 do {
1547 vmf.vmf_eax = 0xE820;
1548 vmf.vmf_edx = SMAP_SIG;
1549 vmf.vmf_ecx = SMAPSIZ;
1550 i = vm86_datacall(0x15, &vmf, &vmc);
1551 if (i || vmf.vmf_eax != SMAP_SIG)
1552 break;
1553 if (boothowto & RB_VERBOSE)
26be20a0 1554 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD		 1555 smap->type,
1556 *(u_int32_t *)((char *)&smap->base + 4),
1557 (u_int32_t)smap->base,
1558 *(u_int32_t *)((char *)&smap->length + 4),
1559 (u_int32_t)smap->length);
1560
1561 if (smap->type != 0x01)
1562 goto next_run;
1563
1564 if (smap->length == 0)
1565 goto next_run;
1566
1bda0d3d
MD		 1567 Realmem += smap->length;
1568
1569 if (smap->base >= 0xffffffffLLU) {
9c3db322 1570 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1571 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD		 1572 goto next_run;
1573 }
1574
1575 for (i = 0; i <= physmap_idx; i += 2) {
1576 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD		 1577 if (boothowto & RB_VERBOSE) {
1578 kprintf("Overlapping or non-montonic "
1579 "memory region, ignoring "
1580 "second region\n");
1581 }
1582 Realmem -= smap->length;
984263bc
MD		 1583 goto next_run;
1584 }
1585 }
1586
1587 if (smap->base == physmap[physmap_idx + 1]) {
1588 physmap[physmap_idx + 1] += smap->length;
1589 goto next_run;
1590 }
1591
1592 physmap_idx += 2;
ff1a75a1 1593 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD		 1594 kprintf("Too many segments in the physical "
1595 "address map, giving up\n");
984263bc
MD		 1596 break;
1597 }
1598 physmap[physmap_idx] = smap->base;
1599 physmap[physmap_idx + 1] = smap->base + smap->length;
1600next_run:
6b08710e 1601 ; /* fix GCC3.x warning */
984263bc
MD		 1602 } while (vmf.vmf_ebx != 0);
1603
1604 /*
1605 * Perform "base memory" related probes & setup based on SMAP
1606 */
1607 if (basemem == 0) {
1608 for (i = 0; i <= physmap_idx; i += 2) {
1609 if (physmap[i] == 0x00000000) {
1610 basemem = physmap[i + 1] / 1024;
1611 break;
1612 }
1613 }
1614
1615 if (basemem == 0) {
1616 basemem = 640;
1617 }
1618
1619 if (basemem > 640) {
1bda0d3d
MD		 1620 kprintf("Preposterous BIOS basemem of %uK, "
1621 "truncating to 640K\n", basemem);
984263bc
MD		 1622 basemem = 640;
1623 }
1624
1625 for (pa = trunc_page(basemem * 1024);
1626 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1627 pte = vtopte(pa + KERNBASE);
984263bc
MD		 1628 *pte = pa | PG_RW | PG_V;
1629 }
1630
b5b32410 1631 pte = vm86paddr;
984263bc
MD		 1632 for (i = basemem / 4; i < 160; i++)
1633 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1634 }
1635
1636 if (physmap[1] != 0)
1637 goto physmap_done;
1638
1639 /*
1640 * If we failed above, try memory map with INT 15:E801
1641 */
1642 vmf.vmf_ax = 0xE801;
1643 if (vm86_intcall(0x15, &vmf) == 0) {
1644 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1645 } else {
1646#if 0
1647 vmf.vmf_ah = 0x88;
1648 vm86_intcall(0x15, &vmf);
1649 extmem = vmf.vmf_ax;
1650#else
1651 /*
1652 * Prefer the RTC value for extended memory.
1653 */
1654 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1655#endif
1656 }
1657
1658 /*
1659 * Special hack for chipsets that still remap the 384k hole when
1660 * there's 16MB of memory - this really confuses people that
1661 * are trying to use bus mastering ISA controllers with the
1662 * "16MB limit"; they only have 16MB, but the remapping puts
1663 * them beyond the limit.
1664 *
1665 * If extended memory is between 15-16MB (16-17MB phys address range),
1666 * chop it to 15MB.
1667 */
1668 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1669 extmem = 15 * 1024;
1670
1671 physmap[0] = 0;
1672 physmap[1] = basemem * 1024;
1673 physmap_idx = 2;
1674 physmap[physmap_idx] = 0x100000;
1675 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1676
1677physmap_done:
1678 /*
1679 * Now, physmap contains a map of physical memory.
1680 */
1681
ed721f0f 1682 base_memory = physmap[1];
984263bc 1683#ifdef SMP
17a9f566 1684 /* make hole for AP bootstrap code YYY */
ed721f0f 1685 physmap[1] = mp_bootaddress(base_memory);
7d676a89 1686#endif
984263bc 1687
1876681a
SZ		 1688 /* Save EBDA address, if any */
1689 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1690 ebda_addr <<= 4;
984263bc
MD		 1691
1692 /*
1693 * Maxmem isn't the "maximum memory", it's one larger than the
1694 * highest page of the physical address space. It should be
1695 * called something like "Maxphyspage". We may adjust this
1696 * based on ``hw.physmem'' and the results of the memory test.
1697 */
1698 Maxmem = atop(physmap[physmap_idx + 1]);
1699
1700#ifdef MAXMEM
1701 Maxmem = MAXMEM / 4;
1702#endif
1703
555da584
MD		 1704 if (kgetenv_quad("hw.physmem", &maxmem))
1705 Maxmem = atop(maxmem);
984263bc
MD		 1706
1707 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1708 (boothowto & RB_VERBOSE))
26be20a0 1709 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD		 1710
1711 /*
1712 * If Maxmem has been increased beyond what the system has detected,
1713 * extend the last memory segment to the new limit.
1714 */
1715 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1716 physmap[physmap_idx + 1] = ptoa(Maxmem);
1717
1718 /* call pmap initialization to make new kernel address space */
1719 pmap_bootstrap(first, 0);
1720
1721 /*
1722 * Size up each available chunk of physical memory.
1723 */
1724 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1725 pa_indx = 0;
b24cd69c 1726 da_indx = 1;
984263bc
MD		 1727 phys_avail[pa_indx++] = physmap[0];
1728 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH		 1729 dump_avail[da_indx] = physmap[0];
1730
b5b32410 1731 pte = CMAP1;
984263bc
MD		 1732
1733 /*
28abdbbb
HS		 1734 * Get dcons buffer address
1735 */
bc01a404
MD		 1736 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1737 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS		 1738 dcons_addr = 0;
1739
1740 /*
984263bc
MD		 1741 * physmap is in bytes, so when converting to page boundaries,
1742 * round up the start address and round down the end address.
1743 */
1744 for (i = 0; i <= physmap_idx; i += 2) {
1745 vm_offset_t end;
1746
1747 end = ptoa(Maxmem);
1748 if (physmap[i + 1] < end)
1749 end = trunc_page(physmap[i + 1]);
1750 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1751 int tmp, page_bad, full;
984263bc
MD		 1752#if 0
1753 int *ptr = 0;
1754#else
1755 int *ptr = (int *)CADDR1;
1756#endif
b24cd69c 1757 full = FALSE;
984263bc
MD		 1758
1759 /*
1760 * block out kernel memory as not available.
1761 */
1762 if (pa >= 0x100000 && pa < first)
b24cd69c 1763 goto do_dump_avail;
984263bc 1764
28abdbbb
HS		 1765 /*
1766 * block out dcons buffer
1767 */
1768 if (dcons_addr > 0
1769 && pa >= trunc_page(dcons_addr)
1770 && pa < dcons_addr + dcons_size)
b24cd69c 1771 goto do_dump_avail;
28abdbbb 1772
984263bc
MD		 1773 page_bad = FALSE;
1774
1775 /*
1776 * map page into kernel: valid, read/write,non-cacheable
1777 */
1778 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1779 cpu_invltlb();
984263bc
MD		 1780
1781 tmp = *(int *)ptr;
1782 /*
1783 * Test for alternating 1's and 0's
1784 */
1785 *(volatile int *)ptr = 0xaaaaaaaa;
1786 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1787 page_bad = TRUE;
1788 }
1789 /*
1790 * Test for alternating 0's and 1's
1791 */
1792 *(volatile int *)ptr = 0x55555555;
1793 if (*(volatile int *)ptr != 0x55555555) {
1794 page_bad = TRUE;
1795 }
1796 /*
1797 * Test for all 1's
1798 */
1799 *(volatile int *)ptr = 0xffffffff;
1800 if (*(volatile int *)ptr != 0xffffffff) {
1801 page_bad = TRUE;
1802 }
1803 /*
1804 * Test for all 0's
1805 */
1806 *(volatile int *)ptr = 0x0;
1807 if (*(volatile int *)ptr != 0x0) {
1808 page_bad = TRUE;
1809 }
1810 /*
1811 * Restore original value.
1812 */
1813 *(int *)ptr = tmp;
1814
1815 /*
1816 * Adjust array of valid/good pages.
1817 */
1818 if (page_bad == TRUE) {
1819 continue;
1820 }
1821 /*
1822 * If this good page is a continuation of the
1823 * previous set of good pages, then just increase
1824 * the end pointer. Otherwise start a new chunk.
1825 * Note that "end" points one higher than end,
1826 * making the range >= start and < end.
1827 * If we're also doing a speculative memory
1828 * test and we at or past the end, bump up Maxmem
1829 * so that we keep going. The first bad page
1830 * will terminate the loop.
1831 */
1832 if (phys_avail[pa_indx] == pa) {
1833 phys_avail[pa_indx] += PAGE_SIZE;
1834 } else {
1835 pa_indx++;
ff1a75a1 1836 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1837 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1838 pa_indx--;
b24cd69c
AH		 1839 full = TRUE;
1840 goto do_dump_avail;
984263bc
MD		 1841 }
1842 phys_avail[pa_indx++] = pa; /* start */
1843 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1844 }
1845 physmem++;
b24cd69c
AH		 1846do_dump_avail:
1847 if (dump_avail[da_indx] == pa) {
1848 dump_avail[da_indx] += PAGE_SIZE;
1849 } else {
1850 da_indx++;
1851 if (da_indx >= PHYSMAP_ENTRIES*2) {
1852 da_indx--;
1853 goto do_next;
1854 }
1855 dump_avail[da_indx++] = pa; /* start */
1856 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1857 }
1858do_next:
1859 if (full)
1860 break;
1861
984263bc
MD		 1862 }
1863 }
1864 *pte = 0;
0f7a3396 1865 cpu_invltlb();
984263bc
MD		 1866
1867 /*
1868 * XXX
1869 * The last chunk must contain at least one page plus the message
1870 * buffer to avoid complicating other code (message buffer address
1871 * calculation, etc.).
1872 */
1873 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1874 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1875 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1876 phys_avail[pa_indx--] = 0;
1877 phys_avail[pa_indx--] = 0;
1878 }
1879
1880 Maxmem = atop(phys_avail[pa_indx]);
1881
1882 /* Trim off space for the message buffer. */
1883 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1884
1885 avail_end = phys_avail[pa_indx];
1886}
1887
30c5f287
MN		 1888struct machintr_abi MachIntrABI;
1889
f7bc9806
MD		 1890/*
1891 * IDT VECTORS:
1892 * 0 Divide by zero
1893 * 1 Debug
1894 * 2 NMI
1895 * 3 BreakPoint
1896 * 4 OverFlow
1897 * 5 Bound-Range
1898 * 6 Invalid OpCode
1899 * 7 Device Not Available (x87)
1900 * 8 Double-Fault
1901 * 9 Coprocessor Segment overrun (unsupported, reserved)
1902 * 10 Invalid-TSS
1903 * 11 Segment not present
1904 * 12 Stack
1905 * 13 General Protection
1906 * 14 Page Fault
1907 * 15 Reserved
1908 * 16 x87 FP Exception pending
1909 * 17 Alignment Check
1910 * 18 Machine Check
1911 * 19 SIMD floating point
1912 * 20-31 reserved
1913 * 32-255 INTn/external sources
1914 */
984263bc 1915void
17a9f566 1916init386(int first)
984263bc
MD		 1917{
1918 struct gate_descriptor *gdp;
1919 int gsel_tss, metadata_missing, off, x;
85100692 1920 struct mdglobaldata *gd;
984263bc
MD		 1921
1922 /*
1923 * Prevent lowering of the ipl if we call tsleep() early.
1924 */
85100692 1925 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1926 bzero(gd, sizeof(*gd));
984263bc 1927
85100692 1928 gd->mi.gd_curthread = &thread0;
4e7c41c5 1929 thread0.td_gd = &gd->mi;
984263bc
MD		 1930
1931 atdevbase = ISA_HOLE_START + KERNBASE;
1932
1933 metadata_missing = 0;
1934 if (bootinfo.bi_modulep) {
1935 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1936 preload_bootstrap_relocate(KERNBASE);
1937 } else {
1938 metadata_missing = 1;
1939 }
1940 if (bootinfo.bi_envp)
1941 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1942
27af435a
SZ		 1943 if (boothowto & RB_VERBOSE)
1944 bootverbose++;
1945
c5cc06e3 1946 /*
10db3cc6 1947 * Default MachIntrABI to ICU
30c5f287
MN		 1948 */
1949 MachIntrABI = MachIntrABI_ICU;
1e7aaefa 1950
d745d2b8
SZ		 1951 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1952 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1d6d7089 1953 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
30c5f287
MN		 1954
1955 /*
e6dee928
SZ		 1956 * Some of the virtaul machines do not work w/ I/O APIC
1957 * enabled. If the user does not explicitly enable or
1958 * disable the I/O APIC (ioapic_enable < 0), then we
1959 * disable I/O APIC on all virtual machines.
1960 */
1961 if (ioapic_enable < 0) {
1962 if (cpu_feature2 & CPUID2_VMM)
1963 ioapic_enable = 0;
1964 else
1965 ioapic_enable = 1;
1966 }
1967
1968 /*
b45759e1
MD		 1969 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1970 * and ncpus_fit_mask remain 0.
c5cc06e3 1971 */
4e8e646b 1972 ncpus = 1;
c5cc06e3 1973 ncpus2 = 1;
b45759e1 1974 ncpus_fit = 1;
984263bc
MD		 1975 /* Init basic tunables, hz etc */
1976 init_param1();
1977
1978 /*
1979 * make gdt memory segments, the code segment goes up to end of the
1980 * page with etext in it, the data segment goes to the end of
1981 * the address space
1982 */
1983 /*
1984 * XXX text protection is temporarily (?) disabled. The limit was
1985 * i386_btop(round_page(etext)) - 1.
1986 */
1987 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1988 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1989
984263bc
MD		 1990 gdt_segs[GPRIV_SEL].ssd_limit =
1991 atop(sizeof(struct privatespace) - 1);
8ad65e08 1992 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1993 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1994 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1995
85100692 1996 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1997
84b592ba
MD		 1998 /*
1999 * Note: on both UP and SMP curthread must be set non-NULL
2000 * early in the boot sequence because the system assumes
2001 * that 'curthread' is never NULL.
2002 */
984263bc
MD		 2003
2004 for (x = 0; x < NGDT; x++) {
2005#ifdef BDE_DEBUGGER
2006 /* avoid overwriting db entries with APM ones */
2007 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
2008 continue;
2009#endif
2010 ssdtosd(&gdt_segs[x], &gdt[x].sd);
2011 }
2012
2013 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2014 r_gdt.rd_base = (int) gdt;
2015 lgdt(&r_gdt);
2016
73e4f7b9
MD		 2017 mi_gdinit(&gd->mi, 0);
2018 cpu_gdinit(gd, 0);
6bf59cd2 2019 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 2020 safepri = TDPRI_MAX;
73e4f7b9 2021
984263bc
MD		 2022 /* make ldt memory segments */
2023 /*
88181b08 2024 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD		 2025 * should be spelled ...MAX_USER...
2026 */
88181b08
MD		 2027 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
2028 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
b370aff7 2029 for (x = 0; x < NELEM(ldt_segs); x++)
984263bc
MD		 2030 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2031
2032 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2033 lldt(_default_ldt);
17a9f566 2034 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD		 2035 /* spinlocks and the BGL */
2036 init_locks();
984263bc 2037
2f839e54
MD		 2038 /*
2039 * Setup the hardware exception table. Most exceptions use
2040 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
2041 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
2042 * an 'interrupt trap gate', which disables interrupts on entry,
2043 * in order to be able to poll the appropriate CRn register to
2044 * determine the fault address.
2045 */
f7bc9806
MD		 2046 for (x = 0; x < NIDT; x++) {
2047#ifdef DEBUG_INTERRUPTS
2048 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049#else
2050 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051#endif
2052 }
984263bc
MD		 2053 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2054 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2055 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2056 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2057 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2058 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2059 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2060 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2061 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2062 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2063 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2064 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2065 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2066 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2067 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2068 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD		 2069 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2070 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2071 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2072 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2073 setidt(0x80, &IDTVEC(int0x80_syscall),
2074 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2075
2076 r_idt.rd_limit = sizeof(idt0) - 1;
2077 r_idt.rd_base = (int) idt;
2078 lidt(&r_idt);
2079
2080 /*
2081 * Initialize the console before we print anything out.
2082 */
2083 cninit();
2084
2085 if (metadata_missing)
26be20a0 2086 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2087
984263bc 2088#if NISA >0
e24dd6e0 2089 elcr_probe();
984263bc
MD		 2090 isa_defaultirq();
2091#endif
2092 rand_initialize();
2093
a3dd9120
SZ		 2094 /*
2095 * Initialize IRQ mapping
2096 *
2097 * NOTE:
2098 * SHOULD be after elcr_probe()
2099 */
2100 MachIntrABI_ICU.initmap();
a3dd9120 2101 MachIntrABI_IOAPIC.initmap();
a3dd9120 2102
984263bc
MD		 2103#ifdef DDB
2104 kdb_init();
2105 if (boothowto & RB_KDB)
2106 Debugger("Boot flags requested debugger");
2107#endif
2108
2109 finishidentcpu(); /* Final stage of CPU initialization */
2110 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2111 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2112 initializecpu(); /* Initialize CPU registers */
2113
b7c628e4
MD		 2114 /*
2115 * make an initial tss so cpu can get interrupt stack on syscall!
2116 * The 16 bytes is to save room for a VM86 context.
2117 */
17a9f566
MD		 2118 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2119 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2120 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD		 2121 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2122 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2123 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD		 2124 ltr(gsel_tss);
2125
2126 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2127 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2128 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2129 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2130 dblfault_tss.tss_cr3 = (int)IdlePTD;
2131 dblfault_tss.tss_eip = (int) dblfault_handler;
2132 dblfault_tss.tss_eflags = PSL_KERNEL;
2133 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2134 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2135 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2136 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2137 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2138
2139 vm86_initialize();
2140 getmemsize(first);
2141 init_param2(physmem);
2142
2143 /* now running on new page tables, configured,and u/iom is accessible */
2144
2145 /* Map the message buffer. */
2146 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2147 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2148
2149 msgbufinit(msgbufp, MSGBUF_SIZE);
2150
2151 /* make a call gate to reenter kernel with */
2152 gdp = &ldt[LSYS5CALLS_SEL].gd;
2153
2154 x = (int) &IDTVEC(syscall);
2155 gdp->gd_looffset = x++;
2156 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2157 gdp->gd_stkcpy = 1;
2158 gdp->gd_type = SDT_SYS386CGT;
2159 gdp->gd_dpl = SEL_UPL;
2160 gdp->gd_p = 1;
2161 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2162
2163 /* XXX does this work? */
2164 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2165 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2166
2167 /* transfer to user mode */
2168
2169 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2170 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2171
2172 /* setup proc 0's pcb */
b7c628e4
MD		 2173 thread0.td_pcb->pcb_flags = 0;
2174 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2175 thread0.td_pcb->pcb_ext = 0;
08f2f1bb 2176 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD		 2177}
2178
8ad65e08 2179/*
17a9f566
MD		 2180 * Initialize machine-dependant portions of the global data structure.
2181 * Note that the global data area and cpu0's idlestack in the private
2182 * data space were allocated in locore.
ef0fdad1
MD		 2183 *
2184 * Note: the idlethread's cpl is 0
73e4f7b9
MD		 2185 *
2186 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD		 2187 */
2188void
85100692 2189cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2190{
7d0bac62 2191 if (cpu)
a2a5ad0d 2192 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2193
f470d0c8
MD		 2194 lwkt_init_thread(&gd->mi.gd_idlethread,
2195 gd->mi.gd_prvspace->idlestack,
d3d32139 2196 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2197 0, &gd->mi);
a2a5ad0d
MD		 2198 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2199 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2200 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2201 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD		 2202}
2203
0cd275af
MD		 2204int
2205is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2206{
2207 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2208 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2209 return (TRUE);
2210 }
2211 return (FALSE);
2212}
2213
12e4aaff
MD		 2214struct globaldata *
2215globaldata_find(int cpu)
2216{
2217 KKASSERT(cpu >= 0 && cpu < ncpus);
2218 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2219}
2220
984263bc
MD		 2221#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2222static void f00f_hack(void *unused);
ba39e2e0 2223SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD		 2224
2225static void
17a9f566
MD		 2226f00f_hack(void *unused)
2227{
984263bc 2228 struct gate_descriptor *new_idt;
984263bc
MD		 2229 vm_offset_t tmp;
2230
2231 if (!has_f00f_bug)
2232 return;
2233
26be20a0 2234 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD		 2235
2236 r_idt.rd_limit = sizeof(idt0) - 1;
2237
e4846942 2238 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD		 2239 if (tmp == 0)
2240 panic("kmem_alloc returned 0");
2241 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2242 panic("kmem_alloc returned non-page-aligned memory");
2243 /* Put the first seven entries in the lower page */
2244 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2245 bcopy(idt, new_idt, sizeof(idt0));
2246 r_idt.rd_base = (int)new_idt;
2247 lidt(&r_idt);
2248 idt = new_idt;
e4846942 2249 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD		 2250 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2251 panic("vm_map_protect failed");
2252 return;
2253}
2254#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2255
2256int
08f2f1bb 2257ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2258{
08f2f1bb 2259 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD		 2260 return (0);
2261}
2262
2263int
e9182c58 2264ptrace_single_step(struct lwp *lp)
984263bc 2265{
e9182c58 2266 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD		 2267 return (0);
2268}
2269
f123d5a1 2270int
e9182c58 2271fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2272{
984263bc
MD		 2273 struct trapframe *tp;
2274
d64d3805
MD		 2275 if ((tp = lp->lwp_md.md_regs) == NULL)
2276 return EINVAL;
4e7c41c5 2277 regs->r_gs = tp->tf_gs;
984263bc
MD		 2278 regs->r_fs = tp->tf_fs;
2279 regs->r_es = tp->tf_es;
2280 regs->r_ds = tp->tf_ds;
2281 regs->r_edi = tp->tf_edi;
2282 regs->r_esi = tp->tf_esi;
2283 regs->r_ebp = tp->tf_ebp;
2284 regs->r_ebx = tp->tf_ebx;
2285 regs->r_edx = tp->tf_edx;
2286 regs->r_ecx = tp->tf_ecx;
2287 regs->r_eax = tp->tf_eax;
2288 regs->r_eip = tp->tf_eip;
2289 regs->r_cs = tp->tf_cs;
2290 regs->r_eflags = tp->tf_eflags;
2291 regs->r_esp = tp->tf_esp;
2292 regs->r_ss = tp->tf_ss;
984263bc
MD		 2293 return (0);
2294}
2295
2296int
e9182c58 2297set_regs(struct lwp *lp, struct reg *regs)
984263bc 2298{
984263bc
MD		 2299 struct trapframe *tp;
2300
e9182c58 2301 tp = lp->lwp_md.md_regs;
984263bc
MD		 2302 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2303 !CS_SECURE(regs->r_cs))
2304 return (EINVAL);
4e7c41c5 2305 tp->tf_gs = regs->r_gs;
984263bc
MD		 2306 tp->tf_fs = regs->r_fs;
2307 tp->tf_es = regs->r_es;
2308 tp->tf_ds = regs->r_ds;
2309 tp->tf_edi = regs->r_edi;
2310 tp->tf_esi = regs->r_esi;
2311 tp->tf_ebp = regs->r_ebp;
2312 tp->tf_ebx = regs->r_ebx;
2313 tp->tf_edx = regs->r_edx;
2314 tp->tf_ecx = regs->r_ecx;
2315 tp->tf_eax = regs->r_eax;
2316 tp->tf_eip = regs->r_eip;
2317 tp->tf_cs = regs->r_cs;
2318 tp->tf_eflags = regs->r_eflags;
2319 tp->tf_esp = regs->r_esp;
2320 tp->tf_ss = regs->r_ss;
984263bc
MD		 2321 return (0);
2322}
2323
642a6e88 2324#ifndef CPU_DISABLE_SSE
984263bc 2325static void
f123d5a1 2326fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2327{
c9faf524
RG		 2328 struct env87 *penv_87 = &sv_87->sv_env;
2329 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD		 2330 int i;
2331
2332 /* FPU control/status */
2333 penv_87->en_cw = penv_xmm->en_cw;
2334 penv_87->en_sw = penv_xmm->en_sw;
2335 penv_87->en_tw = penv_xmm->en_tw;
2336 penv_87->en_fip = penv_xmm->en_fip;
2337 penv_87->en_fcs = penv_xmm->en_fcs;
2338 penv_87->en_opcode = penv_xmm->en_opcode;
2339 penv_87->en_foo = penv_xmm->en_foo;
2340 penv_87->en_fos = penv_xmm->en_fos;
2341
2342 /* FPU registers */
2343 for (i = 0; i < 8; ++i)
2344 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD		 2345}
2346
2347static void
f123d5a1 2348set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2349{
c9faf524
RG		 2350 struct env87 *penv_87 = &sv_87->sv_env;
2351 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD		 2352 int i;
2353
2354 /* FPU control/status */
2355 penv_xmm->en_cw = penv_87->en_cw;
2356 penv_xmm->en_sw = penv_87->en_sw;
2357 penv_xmm->en_tw = penv_87->en_tw;
2358 penv_xmm->en_fip = penv_87->en_fip;
2359 penv_xmm->en_fcs = penv_87->en_fcs;
2360 penv_xmm->en_opcode = penv_87->en_opcode;
2361 penv_xmm->en_foo = penv_87->en_foo;
2362 penv_xmm->en_fos = penv_87->en_fos;
2363
2364 /* FPU registers */
2365 for (i = 0; i < 8; ++i)
2366 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2367}
642a6e88 2368#endif /* CPU_DISABLE_SSE */
984263bc
MD		 2369
2370int
e9182c58 2371fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2372{
d64d3805
MD		 2373 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2374 return EINVAL;
642a6e88 2375#ifndef CPU_DISABLE_SSE
984263bc 2376 if (cpu_fxsr) {
e9182c58
SZ		 2377 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2378 (struct save87 *)fpregs);
984263bc
MD		 2379 return (0);
2380 }
642a6e88 2381#endif /* CPU_DISABLE_SSE */
e9182c58 2382 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD		 2383 return (0);
2384}
2385
2386int
e9182c58 2387set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2388{
642a6e88 2389#ifndef CPU_DISABLE_SSE
984263bc
MD		 2390 if (cpu_fxsr) {
2391 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2392 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD		 2393 return (0);
2394 }
642a6e88 2395#endif /* CPU_DISABLE_SSE */
e9182c58 2396 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD		 2397 return (0);
2398}
2399
2400int
e9182c58 2401fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2402{
d64d3805
MD		 2403 struct pcb *pcb;
2404
e9182c58 2405 if (lp == NULL) {
984263bc
MD		 2406 dbregs->dr0 = rdr0();
2407 dbregs->dr1 = rdr1();
2408 dbregs->dr2 = rdr2();
2409 dbregs->dr3 = rdr3();
2410 dbregs->dr4 = rdr4();
2411 dbregs->dr5 = rdr5();
2412 dbregs->dr6 = rdr6();
2413 dbregs->dr7 = rdr7();
d64d3805
MD		 2414 return (0);
2415 }
2416 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2417 return EINVAL;
2418 dbregs->dr0 = pcb->pcb_dr0;
2419 dbregs->dr1 = pcb->pcb_dr1;
2420 dbregs->dr2 = pcb->pcb_dr2;
2421 dbregs->dr3 = pcb->pcb_dr3;
2422 dbregs->dr4 = 0;
2423 dbregs->dr5 = 0;
2424 dbregs->dr6 = pcb->pcb_dr6;
2425 dbregs->dr7 = pcb->pcb_dr7;
984263bc
MD		 2426 return (0);
2427}
2428
2429int
e9182c58 2430set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2431{
e9182c58 2432 if (lp == NULL) {
984263bc
MD		 2433 load_dr0(dbregs->dr0);
2434 load_dr1(dbregs->dr1);
2435 load_dr2(dbregs->dr2);
2436 load_dr3(dbregs->dr3);
2437 load_dr4(dbregs->dr4);
2438 load_dr5(dbregs->dr5);
2439 load_dr6(dbregs->dr6);
2440 load_dr7(dbregs->dr7);
e9182c58
SZ		 2441 } else {
2442 struct pcb *pcb;
2443 struct ucred *ucred;
2444 int i;
2445 uint32_t mask1, mask2;
2446
984263bc
MD		 2447 /*
2448 * Don't let an illegal value for dr7 get set. Specifically,
2449 * check for undefined settings. Setting these bit patterns
2450 * result in undefined behaviour and can lead to an unexpected
2451 * TRCTRAP.
2452 */
2453 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2454 i++, mask1 <<= 2, mask2 <<= 2)
2455 if ((dbregs->dr7 & mask1) == mask2)
2456 return (EINVAL);
2457
e9182c58
SZ		 2458 pcb = lp->lwp_thread->td_pcb;
2459 ucred = lp->lwp_proc->p_ucred;
2460
984263bc
MD		 2461 /*
2462 * Don't let a process set a breakpoint that is not within the
2463 * process's address space. If a process could do this, it
2464 * could halt the system by setting a breakpoint in the kernel
2465 * (if ddb was enabled). Thus, we need to check to make sure
2466 * that no breakpoints are being enabled for addresses outside
2467 * process's address space, unless, perhaps, we were called by
2468 * uid 0.
2469 *
2470 * XXX - what about when the watched area of the user's
2471 * address space is written into from within the kernel
2472 * ... wouldn't that still cause a breakpoint to be generated
2473 * from within kernel mode?
2474 */
e9182c58 2475
895c1f85 2476 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD		 2477 if (dbregs->dr7 & 0x3) {
2478 /* dr0 is enabled */
88181b08 2479 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2480 return (EINVAL);
2481 }
e9182c58 2482
984263bc
MD		 2483 if (dbregs->dr7 & (0x3<<2)) {
2484 /* dr1 is enabled */
88181b08 2485 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2486 return (EINVAL);
2487 }
e9182c58 2488
984263bc
MD		 2489 if (dbregs->dr7 & (0x3<<4)) {
2490 /* dr2 is enabled */
88181b08 2491 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2492 return (EINVAL);
2493 }
e9182c58 2494
984263bc
MD		 2495 if (dbregs->dr7 & (0x3<<6)) {
2496 /* dr3 is enabled */
88181b08 2497 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2498 return (EINVAL);
2499 }
2500 }
e9182c58 2501
984263bc
MD		 2502 pcb->pcb_dr0 = dbregs->dr0;
2503 pcb->pcb_dr1 = dbregs->dr1;
2504 pcb->pcb_dr2 = dbregs->dr2;
2505 pcb->pcb_dr3 = dbregs->dr3;
2506 pcb->pcb_dr6 = dbregs->dr6;
2507 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2508
984263bc
MD		 2509 pcb->pcb_flags |= PCB_DBREGS;
2510 }
2511
2512 return (0);
2513}
2514
2515/*
2516 * Return > 0 if a hardware breakpoint has been hit, and the
2517 * breakpoint was in user space. Return 0, otherwise.
2518 */
2519int
2520user_dbreg_trap(void)
2521{
2522 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2523 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2524 int nbp; /* number of breakpoints that triggered */
2525 caddr_t addr[4]; /* breakpoint addresses */
2526 int i;
2527
2528 dr7 = rdr7();
2529 if ((dr7 & 0x000000ff) == 0) {
2530 /*
2531 * all GE and LE bits in the dr7 register are zero,
2532 * thus the trap couldn't have been caused by the
2533 * hardware debug registers
2534 */
2535 return 0;
2536 }
2537
2538 nbp = 0;
2539 dr6 = rdr6();
2540 bp = dr6 & 0x0000000f;
2541
2542 if (!bp) {
2543 /*
2544 * None of the breakpoint bits are set meaning this
2545 * trap was not caused by any of the debug registers
2546 */
2547 return 0;
2548 }
2549
2550 /*
2551 * at least one of the breakpoints were hit, check to see
2552 * which ones and if any of them are user space addresses
2553 */
2554
2555 if (bp & 0x01) {
2556 addr[nbp++] = (caddr_t)rdr0();
2557 }
2558 if (bp & 0x02) {
2559 addr[nbp++] = (caddr_t)rdr1();
2560 }
2561 if (bp & 0x04) {
2562 addr[nbp++] = (caddr_t)rdr2();
2563 }
2564 if (bp & 0x08) {
2565 addr[nbp++] = (caddr_t)rdr3();
2566 }
2567
2568 for (i=0; i<nbp; i++) {
2569 if (addr[i] <
88181b08 2570 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD		 2571 /*
2572 * addr[i] is in user space
2573 */
2574 return nbp;
2575 }
2576 }
2577
2578 /*
2579 * None of the breakpoints are in user space.
2580 */
2581 return 0;
2582}
2583
2584
2585#ifndef DDB
2586void
2587Debugger(const char *msg)
2588{
26be20a0 2589 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD		 2590}
2591#endif /* no DDB */
2592
984263bc
MD		 2593#ifdef DDB
2594
2595/*
2596 * Provide inb() and outb() as functions. They are normally only
2597 * available as macros calling inlined functions, thus cannot be
2598 * called inside DDB.
2599 *
2600 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2601 */
2602
2603#undef inb
2604#undef outb
2605
2606/* silence compiler warnings */
2607u_char inb(u_int);
2608void outb(u_int, u_char);
2609
2610u_char
2611inb(u_int port)
2612{
2613 u_char data;
2614 /*
2615 * We use %%dx and not %1 here because i/o is done at %dx and not at
2616 * %edx, while gcc generates inferior code (movw instead of movl)
2617 * if we tell it to load (u_short) port.
2618 */
2619 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2620 return (data);
2621}
2622
2623void
2624outb(u_int port, u_char data)
2625{
2626 u_char al;
2627 /*
2628 * Use an unnecessary assignment to help gcc's register allocator.
2629 * This make a large difference for gcc-1.40 and a tiny difference
2630 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2631 * best results. gcc-2.6.0 can't handle this.
2632 */
2633 al = data;
2634 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2635}
2636
2637#endif /* DDB */
8a8d5d85
MD		 2638
2639
2640
2641#include "opt_cpu.h"
8a8d5d85
MD		 2642
2643
2644/*
2645 * initialize all the SMP locks
2646 */
2647
97359a5b 2648/* critical region when masking or unmasking interupts */
b1af91cb 2649struct spinlock_deprecated imen_spinlock;
8a8d5d85 2650
8a8d5d85 2651/* critical region for old style disable_intr/enable_intr */
b1af91cb 2652struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD		 2653
2654/* critical region around INTR() routines */
b1af91cb 2655struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD		 2656
2657/* lock region used by kernel profiling */
b1af91cb 2658struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD		 2659
2660/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2661struct spinlock_deprecated com_spinlock;
8a8d5d85 2662
8a8d5d85 2663/* lock regions around the clock hardware */
b1af91cb 2664struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD		 2665
2666/* lock around the MP rendezvous */
b1af91cb 2667struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD		 2668
2669static void
2670init_locks(void)
2671{
b5d16701 2672#ifdef SMP
8a8d5d85 2673 /*
b5d16701 2674 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD		 2675 * This uses a LOGICAL cpu ID, ie BSP == 0.
2676 */
8a8d5d85
MD		 2677 cpu_get_initial_mplock();
2678#endif
41a01a4d 2679 /* DEPRECATED */
8a8d5d85 2680 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD		 2681 spin_lock_init(&intr_spinlock);
2682 spin_lock_init(&mpintr_spinlock);
2683 spin_lock_init(&imen_spinlock);
2684 spin_lock_init(&smp_rv_spinlock);
2685 spin_lock_init(&com_spinlock);
2686 spin_lock_init(&clock_spinlock);
41a01a4d
MD		 2687
2688 /* our token pool needs to work early */
2689 lwkt_token_pool_init();
8a8d5d85 2690}
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