[dragonfly.git] / sys / dev / netif / bge / if_bgevar.h

/*
 * Copyright (c) 2001 Wind River Systems
 * Copyright (c) 1997, 1998, 1999, 2001
 *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Bill Paul.
 * 4. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
 */

#ifndef _IF_BGEVAR_H_
#define _IF_BGEVAR_H_

/*
 * Tigon general information block. This resides in host memory
 * and contains the status counters, ring control blocks and
 * producer pointers.
 */

struct bge_gib {
	struct bge_stats	bge_stats;
	struct bge_rcb		bge_tx_rcb[16];
	struct bge_rcb		bge_std_rx_rcb;
	struct bge_rcb		bge_jumbo_rx_rcb;
	struct bge_rcb		bge_mini_rx_rcb;
	struct bge_rcb		bge_return_rcb;
};

#define BGE_MIN_FRAMELEN	60
#define BGE_MAX_FRAMELEN	1536
#define BGE_JUMBO_FRAMELEN	9018
#define BGE_JUMBO_MTU		(BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)

#define BGE_TIMEOUT		5000
#define BGE_FIRMWARE_TIMEOUT	100000
#define BGE_TXCONS_UNSET	0xFFFF	/* impossible value */

/*
 * Other utility macros.
 */
#define BGE_INC(x, y)		(x) = ((x) + 1) % (y)

/*
 * Register access macros. The Tigon always uses memory mapped register
 * accesses and all registers must be accessed with 32 bit operations.
 */

#define CSR_WRITE_4(sc, reg, val)	\
	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)

#define CSR_READ_4(sc, reg)		\
	bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)

#define BGE_SETBIT(sc, reg, x)	\
	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

#define BGE_CLRBIT(sc, reg, x)	\
	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

#define BGE_MEMWIN_READ(sc, x, val)				\
do {								\
	pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
	    (0xFFFF0000 & x), 4);				\
	val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
} while(0)

#define BGE_MEMWIN_WRITE(sc, x, val)				\
do {								\
	pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
	    (0xFFFF0000 & x), 4);				\
	CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
} while(0)

#define RCB_WRITE_4(sc, rcb, offset, val)			\
	bus_space_write_4(sc->bge_btag, sc->bge_bhandle,	\
			  rcb + offsetof(struct bge_rcb, offset), val)

/*
 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
 * values are tuneable. They control the actual amount of buffers
 * allocated for the standard, mini and jumbo receive rings.
 */

#define BGE_SSLOTS	256
#define BGE_MSLOTS	256
#define BGE_JSLOTS	384

#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
#define BGE_JLEN (BGE_JRAWLEN + \
	(sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t)))
#define BGE_JPAGESZ PAGE_SIZE
#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)

struct bge_softc;

struct bge_jslot {
	struct bge_softc	*bge_sc;
	void			*bge_buf;
	bus_addr_t		bge_paddr;
	int			bge_inuse;
	int			bge_slot;
	SLIST_ENTRY(bge_jslot)	jslot_link;
};

/*
 * Ring structures. Most of these reside in host memory and we tell
 * the NIC where they are via the ring control blocks. The exceptions
 * are the tx and command rings, which live in NIC memory and which
 * we access via the shared memory window.
 */
struct bge_ring_data {
	struct bge_rx_bd	*bge_rx_std_ring;
	bus_addr_t		bge_rx_std_ring_paddr;
	struct bge_rx_bd	*bge_rx_jumbo_ring;
	bus_addr_t		bge_rx_jumbo_ring_paddr;
	struct bge_rx_bd	*bge_rx_return_ring;
	bus_addr_t		bge_rx_return_ring_paddr;
	struct bge_tx_bd	*bge_tx_ring;
	bus_addr_t		bge_tx_ring_paddr;
	struct bge_status_block	*bge_status_block;
	bus_addr_t		bge_status_block_paddr;
	struct bge_stats	*bge_stats;
	bus_addr_t		bge_stats_paddr;
	void			*bge_jumbo_buf;
	struct bge_gib		bge_info;
};

struct bge_rxchain {
	struct mbuf	*bge_mbuf;
	bus_addr_t	bge_paddr;
};

/*
 * Mbuf pointers. We need these to keep track of the virtual addresses
 * of our mbuf chains since we can only convert from physical to virtual,
 * not the other way around.
 */
struct bge_chain_data {
	bus_dma_tag_t		bge_parent_tag;
	bus_dma_tag_t		bge_rx_std_ring_tag;
	bus_dma_tag_t		bge_rx_jumbo_ring_tag;
	bus_dma_tag_t		bge_rx_return_ring_tag;
	bus_dma_tag_t		bge_tx_ring_tag;
	bus_dma_tag_t		bge_status_tag;
	bus_dma_tag_t		bge_stats_tag;
	bus_dma_tag_t		bge_jumbo_tag;
	bus_dma_tag_t		bge_tx_mtag;	/* TX mbuf DMA tag */
	bus_dma_tag_t		bge_rx_mtag;	/* RX mbuf DMA tag */
	bus_dmamap_t		bge_rx_tmpmap;
	bus_dmamap_t		bge_tx_dmamap[BGE_TX_RING_CNT];
	bus_dmamap_t		bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
	bus_dmamap_t		bge_rx_std_ring_map;
	bus_dmamap_t		bge_rx_jumbo_ring_map;
	bus_dmamap_t		bge_tx_ring_map;
	bus_dmamap_t		bge_rx_return_ring_map;
	bus_dmamap_t		bge_status_map;
	bus_dmamap_t		bge_stats_map;
	bus_dmamap_t		bge_jumbo_map;
	struct mbuf		*bge_tx_chain[BGE_TX_RING_CNT];
	struct bge_rxchain	bge_rx_std_chain[BGE_STD_RX_RING_CNT];
	struct bge_rxchain	bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
	/* Stick the jumbo mem management stuff here too. */
	struct bge_jslot	bge_jslots[BGE_JSLOTS];
};

struct bge_softc {
	struct arpcom		arpcom;		/* interface info */
	device_t		bge_dev;
	device_t		bge_miibus;
	bus_space_handle_t	bge_bhandle;
	bus_space_tag_t		bge_btag;
	void			*bge_intrhand;
	struct resource		*bge_irq;
	int			bge_irq_type;
	int			bge_irq_rid;
	struct resource		*bge_res;
	struct ifmedia		bge_ifmedia;	/* TBI media info */
	int			bge_pcixcap;
	int			bge_pciecap;
	int			bge_msicap;
	uint32_t		bge_pci_miscctl;
	uint32_t		bge_status_tag;
	uint32_t		bge_flags;	/* BGE_FLAG_ */
#define BGE_FLAG_TBI		0x00000001
#define BGE_FLAG_JUMBO		0x00000002
#define BGE_FLAG_ONESHOT_MSI	0x00000004
#define BGE_FLAG_TSO		0x00000008
#define BGE_FLAG_MII_SERDES	0x00000010
#define	BGE_FLAG_CPMU		0x00000020
#define BGE_FLAG_PCIX		0x00000200
#define BGE_FLAG_PCIE		0x00000400
#define BGE_FLAG_5700_FAMILY	0x00001000
#define BGE_FLAG_5705_PLUS	0x00002000
#define BGE_FLAG_5714_FAMILY	0x00004000
#define BGE_FLAG_575X_PLUS	0x00008000
#define BGE_FLAG_5755_PLUS	0x00010000
#define BGE_FLAG_MAXADDR_40BIT	0x00020000
#define BGE_FLAG_RX_ALIGNBUG	0x00100000
#define BGE_FLAG_NO_EEPROM	0x10000000
#define BGE_FLAG_5788		0x20000000
#define BGE_FLAG_SHORTDMA	0x40000000
#define BGE_FLAG_STATUS_TAG	0x80000000

	uint32_t		bge_chipid;
	uint32_t		bge_asicrev;
	uint32_t		bge_chiprev;
	struct bge_ring_data	bge_ldata;	/* rings */
	struct bge_chain_data	bge_cdata;	/* mbufs */
	uint16_t		bge_tx_saved_considx;
	uint16_t		bge_rx_saved_considx;
	uint16_t		bge_ev_saved_considx;
	uint16_t		bge_return_ring_cnt;
	uint16_t		bge_std;	/* current std ring head */
	uint16_t		bge_jumbo;	/* current jumo ring head */
	SLIST_HEAD(__bge_jfreehead, bge_jslot)	bge_jfree_listhead;
	struct lwkt_serialize	bge_jslot_serializer;
	uint32_t		bge_stat_ticks;
	uint32_t		bge_rx_coal_ticks;
	uint32_t		bge_tx_coal_ticks;
	uint32_t		bge_rx_coal_bds;
	uint32_t		bge_tx_coal_bds;
	uint32_t		bge_rx_coal_ticks_int;
	uint32_t		bge_tx_coal_ticks_int;
	uint32_t		bge_rx_coal_bds_int;
	uint32_t		bge_tx_coal_bds_int;
	uint32_t		bge_tx_prodidx;
	uint32_t		bge_tx_buf_ratio;
	uint32_t		bge_mi_mode;
	int			bge_force_defrag;
	int			bge_mbox_reorder;
	int			bge_if_flags;
	int			bge_txcnt;
	int			bge_txspare;
	int			bge_txrsvd;
	int			bge_link;
	int			bge_link_evt;
	struct callout		bge_stat_timer;

	struct sysctl_ctx_list	bge_sysctl_ctx;
	struct sysctl_oid	*bge_sysctl_tree;

	int			bge_phyno;
	uint32_t		bge_coal_chg;
#define BGE_RX_COAL_TICKS_CHG		0x01
#define BGE_TX_COAL_TICKS_CHG		0x02
#define BGE_RX_COAL_BDS_CHG		0x04
#define BGE_TX_COAL_BDS_CHG		0x08
#define BGE_RX_COAL_TICKS_INT_CHG	0x10
#define BGE_TX_COAL_TICKS_INT_CHG	0x20
#define BGE_RX_COAL_BDS_INT_CHG		0x40
#define BGE_TX_COAL_BDS_INT_CHG		0x80

	void			(*bge_link_upd)(struct bge_softc *, uint32_t);
	uint32_t		bge_link_chg;
};

#define BGE_NSEG_NEW		40
#define BGE_NSEG_SPARE		5
#define BGE_NSEG_SPARE_TSO	33
#define BGE_NSEG_RSVD		16
#define BGE_NSEG_RSVD_TSO	4

/* RX coalesce ticks, unit: us */
#define BGE_RX_COAL_TICKS_MIN	0
#define BGE_RX_COAL_TICKS_DEF	160
#define BGE_RX_COAL_TICKS_MAX	1023

/* TX coalesce ticks, unit: us */
#define BGE_TX_COAL_TICKS_MIN	0
#define BGE_TX_COAL_TICKS_DEF	1023
#define BGE_TX_COAL_TICKS_MAX	1023

/* RX coalesce BDs */
#define BGE_RX_COAL_BDS_MIN	1
#define BGE_RX_COAL_BDS_DEF	80
#define BGE_RX_COAL_BDS_MAX	255

/* TX coalesce BDs */
#define BGE_TX_COAL_BDS_MIN	1
#define BGE_TX_COAL_BDS_DEF	128
#define BGE_TX_COAL_BDS_MAX	255

#endif	/* !_IF_BGEVAR_H_ */
Commit	Line	Data
8ff8bce6 SZ	1	/*
	2	* Copyright (c) 2001 Wind River Systems
	3	* Copyright (c) 1997, 1998, 1999, 2001
	4	* Bill Paul <wpaul@windriver.com>. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	* 1. Redistributions of source code must retain the above copyright
	10	* notice, this list of conditions and the following disclaimer.
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	* 3. All advertising materials mentioning features or use of this software
	15	* must display the following acknowledgement:
	16	* This product includes software developed by Bill Paul.
	17	* 4. Neither the name of the author nor the names of any co-contributors
	18	* may be used to endorse or promote products derived from this software
	19	* without specific prior written permission.
	20	*
	21	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
	22	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	24	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
	25	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	26	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	27	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	28	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	29	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	30	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	31	* THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	* $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
	34	* $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
	35	*/
	36
	37	#ifndef _IF_BGEVAR_H_
	38	#define _IF_BGEVAR_H_
	39
	40	/*
	41	* Tigon general information block. This resides in host memory
	42	* and contains the status counters, ring control blocks and
	43	* producer pointers.
	44	*/
	45
	46	struct bge_gib {
	47	struct bge_stats bge_stats;
	48	struct bge_rcb bge_tx_rcb[16];
	49	struct bge_rcb bge_std_rx_rcb;
	50	struct bge_rcb bge_jumbo_rx_rcb;
	51	struct bge_rcb bge_mini_rx_rcb;
	52	struct bge_rcb bge_return_rcb;
	53	};
	54
	55	#define BGE_MIN_FRAMELEN 60
	56	#define BGE_MAX_FRAMELEN 1536
	57	#define BGE_JUMBO_FRAMELEN 9018
	58	#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
	59
	60	#define BGE_TIMEOUT 5000
1dfb1558	61	#define BGE_FIRMWARE_TIMEOUT 100000
8ff8bce6 SZ	62	#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
	63
	64	/*
	65	* Other utility macros.
	66	*/
	67	#define BGE_INC(x, y) (x) = ((x) + 1) % (y)
	68
	69	/*
	70	* Register access macros. The Tigon always uses memory mapped register
	71	* accesses and all registers must be accessed with 32 bit operations.
	72	*/
	73
	74	#define CSR_WRITE_4(sc, reg, val) \
	75	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
	76
	77	#define CSR_READ_4(sc, reg) \
	78	bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
	79
	80	#define BGE_SETBIT(sc, reg, x) \
	81	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| x))
	82
	83	#define BGE_CLRBIT(sc, reg, x) \
	84	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
	85
	86	#define BGE_MEMWIN_READ(sc, x, val) \
	87	do { \
	88	pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
	89	(0xFFFF0000 & x), 4); \
	90	val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
	91	} while(0)
	92
	93	#define BGE_MEMWIN_WRITE(sc, x, val) \
	94	do { \
	95	pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
	96	(0xFFFF0000 & x), 4); \
	97	CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
	98	} while(0)
	99
	100	#define RCB_WRITE_4(sc, rcb, offset, val) \
	101	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
	102	rcb + offsetof(struct bge_rcb, offset), val)
	103
	104	/*
	105	* Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
	106	* values are tuneable. They control the actual amount of buffers
	107	* allocated for the standard, mini and jumbo receive rings.
	108	*/
	109
	110	#define BGE_SSLOTS 256
	111	#define BGE_MSLOTS 256
	112	#define BGE_JSLOTS 384
	113
	114	#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
	115	#define BGE_JLEN (BGE_JRAWLEN + \
	116	(sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t)))
	117	#define BGE_JPAGESZ PAGE_SIZE
	118	#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
	119	#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
	120
	121	struct bge_softc;
	122
	123	struct bge_jslot {
	124	struct bge_softc *bge_sc;
	125	void *bge_buf;
126	bus_addr_t bge_paddr;
127	int bge_inuse;
128	int bge_slot;
129	SLIST_ENTRY(bge_jslot) jslot_link;
130	};
131
132	/*
133	* Ring structures. Most of these reside in host memory and we tell
134	* the NIC where they are via the ring control blocks. The exceptions
135	* are the tx and command rings, which live in NIC memory and which
136	* we access via the shared memory window.
137	*/
138	struct bge_ring_data {
139	struct bge_rx_bd *bge_rx_std_ring;
140	bus_addr_t bge_rx_std_ring_paddr;
141	struct bge_rx_bd *bge_rx_jumbo_ring;
142	bus_addr_t bge_rx_jumbo_ring_paddr;
143	struct bge_rx_bd *bge_rx_return_ring;
144	bus_addr_t bge_rx_return_ring_paddr;
145	struct bge_tx_bd *bge_tx_ring;
146	bus_addr_t bge_tx_ring_paddr;
147	struct bge_status_block *bge_status_block;
148	bus_addr_t bge_status_block_paddr;
149	struct bge_stats *bge_stats;
150	bus_addr_t bge_stats_paddr;
151	void *bge_jumbo_buf;
152	struct bge_gib bge_info;
153	};
154
155	struct bge_rxchain {
156	struct mbuf *bge_mbuf;
157	bus_addr_t bge_paddr;
158	};
159
160	/*
161	* Mbuf pointers. We need these to keep track of the virtual addresses
162	* of our mbuf chains since we can only convert from physical to virtual,
163	* not the other way around.
164	*/
165	struct bge_chain_data {
166	bus_dma_tag_t bge_parent_tag;
167	bus_dma_tag_t bge_rx_std_ring_tag;
168	bus_dma_tag_t bge_rx_jumbo_ring_tag;
169	bus_dma_tag_t bge_rx_return_ring_tag;
170	bus_dma_tag_t bge_tx_ring_tag;
171	bus_dma_tag_t bge_status_tag;
172	bus_dma_tag_t bge_stats_tag;
173	bus_dma_tag_t bge_jumbo_tag;
174	bus_dma_tag_t bge_tx_mtag; /* TX mbuf DMA tag */
175	bus_dma_tag_t bge_rx_mtag; /* RX mbuf DMA tag */
176	bus_dmamap_t bge_rx_tmpmap;
177	bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
178	bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
179	bus_dmamap_t bge_rx_std_ring_map;
180	bus_dmamap_t bge_rx_jumbo_ring_map;
181	bus_dmamap_t bge_tx_ring_map;
182	bus_dmamap_t bge_rx_return_ring_map;
183	bus_dmamap_t bge_status_map;
184	bus_dmamap_t bge_stats_map;
185	bus_dmamap_t bge_jumbo_map;
186	struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
187	struct bge_rxchain bge_rx_std_chain[BGE_STD_RX_RING_CNT];
188	struct bge_rxchain bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
189	/* Stick the jumbo mem management stuff here too. */
190	struct bge_jslot bge_jslots[BGE_JSLOTS];
191	};
192
193	struct bge_softc {
194	struct arpcom arpcom; /* interface info */
195	device_t bge_dev;
196	device_t bge_miibus;
197	bus_space_handle_t bge_bhandle;
198	bus_space_tag_t bge_btag;
199	void *bge_intrhand;
200	struct resource *bge_irq;
308dcd8e SZ	201	int bge_irq_type;
308dcd8e SZ	202	int bge_irq_rid;
8ff8bce6 SZ	203	struct resource *bge_res;
	204	struct ifmedia bge_ifmedia; /* TBI media info */
	205	int bge_pcixcap;
	206	int bge_pciecap;
308dcd8e	207	int bge_msicap;
8ff8bce6 SZ	208	uint32_t bge_pci_miscctl;
	209	uint32_t bge_status_tag;
	210	uint32_t bge_flags; /* BGE_FLAG_ */
	211	#define BGE_FLAG_TBI 0x00000001
	212	#define BGE_FLAG_JUMBO 0x00000002
308dcd8e	213	#define BGE_FLAG_ONESHOT_MSI 0x00000004
e92f005c	214	#define BGE_FLAG_TSO 0x00000008
8ff8bce6 SZ	215	#define BGE_FLAG_MII_SERDES 0x00000010
	216	#define BGE_FLAG_CPMU 0x00000020
	217	#define BGE_FLAG_PCIX 0x00000200
	218	#define BGE_FLAG_PCIE 0x00000400
	219	#define BGE_FLAG_5700_FAMILY 0x00001000
	220	#define BGE_FLAG_5705_PLUS 0x00002000
	221	#define BGE_FLAG_5714_FAMILY 0x00004000
	222	#define BGE_FLAG_575X_PLUS 0x00008000
	223	#define BGE_FLAG_5755_PLUS 0x00010000
	224	#define BGE_FLAG_MAXADDR_40BIT 0x00020000
	225	#define BGE_FLAG_RX_ALIGNBUG 0x00100000
	226	#define BGE_FLAG_NO_EEPROM 0x10000000
	227	#define BGE_FLAG_5788 0x20000000
	228	#define BGE_FLAG_SHORTDMA 0x40000000
	229	#define BGE_FLAG_STATUS_TAG 0x80000000
	230
	231	uint32_t bge_chipid;
	232	uint32_t bge_asicrev;
	233	uint32_t bge_chiprev;
	234	struct bge_ring_data bge_ldata; /* rings */
	235	struct bge_chain_data bge_cdata; /* mbufs */
	236	uint16_t bge_tx_saved_considx;
	237	uint16_t bge_rx_saved_considx;
	238	uint16_t bge_ev_saved_considx;
	239	uint16_t bge_return_ring_cnt;
	240	uint16_t bge_std; /* current std ring head */
	241	uint16_t bge_jumbo; /* current jumo ring head */
	242	SLIST_HEAD(__bge_jfreehead, bge_jslot) bge_jfree_listhead;
	243	struct lwkt_serialize bge_jslot_serializer;
	244	uint32_t bge_stat_ticks;
	245	uint32_t bge_rx_coal_ticks;
	246	uint32_t bge_tx_coal_ticks;
	247	uint32_t bge_rx_coal_bds;
	248	uint32_t bge_tx_coal_bds;
	249	uint32_t bge_rx_coal_ticks_int;
	250	uint32_t bge_tx_coal_ticks_int;
	251	uint32_t bge_rx_coal_bds_int;
	252	uint32_t bge_tx_coal_bds_int;
	253	uint32_t bge_tx_prodidx;
	254	uint32_t bge_tx_buf_ratio;
	255	uint32_t bge_mi_mode;
	256	int bge_force_defrag;
	257	int bge_mbox_reorder;
	258	int bge_if_flags;
	259	int bge_txcnt;
e92f005c SZ	260	int bge_txspare;
e92f005c SZ	261	int bge_txrsvd;
8ff8bce6 SZ	262	int bge_link;
	263	int bge_link_evt;
	264	struct callout bge_stat_timer;
	265
	266	struct sysctl_ctx_list bge_sysctl_ctx;
	267	struct sysctl_oid *bge_sysctl_tree;
	268
	269	int bge_phyno;
	270	uint32_t bge_coal_chg;
	271	#define BGE_RX_COAL_TICKS_CHG 0x01
	272	#define BGE_TX_COAL_TICKS_CHG 0x02
	273	#define BGE_RX_COAL_BDS_CHG 0x04
	274	#define BGE_TX_COAL_BDS_CHG 0x08
	275	#define BGE_RX_COAL_TICKS_INT_CHG 0x10
	276	#define BGE_TX_COAL_TICKS_INT_CHG 0x20
	277	#define BGE_RX_COAL_BDS_INT_CHG 0x40
	278	#define BGE_TX_COAL_BDS_INT_CHG 0x80
	279
	280	void (bge_link_upd)(struct bge_softc , uint32_t);
	281	uint32_t bge_link_chg;
	282	};
	283
e92f005c	284	#define BGE_NSEG_NEW 40
8ff8bce6	285	#define BGE_NSEG_SPARE 5
e92f005c	286	#define BGE_NSEG_SPARE_TSO 33
8ff8bce6	287	#define BGE_NSEG_RSVD 16
e92f005c	288	#define BGE_NSEG_RSVD_TSO 4
8ff8bce6 SZ	289
	290	/* RX coalesce ticks, unit: us */
	291	#define BGE_RX_COAL_TICKS_MIN 0
	292	#define BGE_RX_COAL_TICKS_DEF 160
	293	#define BGE_RX_COAL_TICKS_MAX 1023
	294
	295	/* TX coalesce ticks, unit: us */
	296	#define BGE_TX_COAL_TICKS_MIN 0
	297	#define BGE_TX_COAL_TICKS_DEF 1023
	298	#define BGE_TX_COAL_TICKS_MAX 1023
	299
	300	/* RX coalesce BDs */
	301	#define BGE_RX_COAL_BDS_MIN 1
	302	#define BGE_RX_COAL_BDS_DEF 80
	303	#define BGE_RX_COAL_BDS_MAX 255
	304
	305	/* TX coalesce BDs */
	306	#define BGE_TX_COAL_BDS_MIN 1
	307	#define BGE_TX_COAL_BDS_DEF 128
	308	#define BGE_TX_COAL_BDS_MAX 255
	309
	310	#endif /* !_IF_BGEVAR_H_ */