| Commit | Line | Data |
|---|---|---|
| 8c10bfcf MD |
1 | /* |
| 2 | * Copyright (c) 2003,2004 The DragonFly Project. All rights reserved. | |
| 3 | * | |
| 4 | * This code is derived from software contributed to The DragonFly Project | |
| 5 | * by Matthew Dillon <dillon@backplane.com> | |
| 6 | * | |
| 7 | * Redistribution and use in source and binary forms, with or without | |
| 8 | * modification, are permitted provided that the following conditions | |
| 9 | * are met: | |
| 10 | * | |
| 11 | * 1. Redistributions of source code must retain the above copyright | |
| 12 | * notice, this list of conditions and the following disclaimer. | |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 14 | * notice, this list of conditions and the following disclaimer in | |
| 15 | * the documentation and/or other materials provided with the | |
| 16 | * distribution. | |
| 17 | * 3. Neither the name of The DragonFly Project nor the names of its | |
| 18 | * contributors may be used to endorse or promote products derived | |
| 19 | * from this software without specific, prior written permission. | |
| 20 | * | |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
| 24 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
| 25 | * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 26 | * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
| 27 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 28 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED | |
| 29 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
| 31 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 32 | * SUCH DAMAGE. | |
| 33 | * | |
| 8a8d5d85 | 34 | * Copyright (c) 1997, by Steve Passe, All rights reserved. |
| 984263bc MD |
35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without | |
| 37 | * modification, are permitted provided that the following conditions | |
| 38 | * are met: | |
| 39 | * 1. Redistributions of source code must retain the above copyright | |
| 40 | * notice, this list of conditions and the following disclaimer. | |
| 41 | * 2. The name of the developer may NOT be used to endorse or promote products | |
| 42 | * derived from this software without specific prior written permission. | |
| 43 | * | |
| 44 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
| 45 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 46 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 47 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | |
| 48 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 49 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 50 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 51 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 53 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 54 | * SUCH DAMAGE. | |
| 55 | * | |
| 56 | * $FreeBSD: src/sys/i386/isa/apic_ipl.s,v 1.27.2.2 2000/09/30 02:49:35 ps Exp $ | |
| a7231bde | 57 | * $DragonFly: src/sys/platform/pc32/apic/apic_ipl.s,v 1.17 2006/11/07 18:50:06 dillon Exp $ |
| 984263bc MD |
58 | */ |
| 59 | ||
| 06f5be02 MD |
60 | #include "use_npx.h" |
| 61 | ||
| 62 | #include <machine/asmacros.h> | |
| 63 | #include <machine/segments.h> | |
| 06f5be02 MD |
64 | #include <machine/lock.h> |
| 65 | #include <machine/psl.h> | |
| 66 | #include <machine/trap.h> | |
| 06f5be02 | 67 | |
| bdc560a1 MD |
68 | #include "apicreg.h" |
| 69 | #include "apic_ipl.h" | |
| 06f5be02 MD |
70 | #include "assym.s" |
| 71 | ||
| 72 | #ifdef APIC_IO | |
| bdc560a1 | 73 | |
| 984263bc MD |
74 | .text |
| 75 | SUPERALIGN_TEXT | |
| 76 | ||
| 984263bc | 77 | /* |
| df308fcd MD |
78 | * Functions to enable and disable a hardware interrupt. The |
| 79 | * IRQ number is passed as an argument. | |
| 984263bc | 80 | */ |
| 37e7efec | 81 | ENTRY(APIC_INTRDIS) |
| 97359a5b | 82 | APIC_IMASK_LOCK /* enter critical reg */ |
| 8a8d5d85 MD |
83 | movl 4(%esp),%eax |
| 84 | 1: | |
| 3d911e0a | 85 | shll $IOAPIC_IM_SZSHIFT, %eax |
| ea689d1c | 86 | orl $IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax) |
| 3d911e0a SZ |
87 | movl CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx |
| 88 | movl CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx | |
| 984263bc | 89 | testl %edx, %edx |
| 8a8d5d85 MD |
90 | jz 2f |
| 91 | movl %ecx, (%edx) /* target register index */ | |
| d2dd4a9f SZ |
92 | orl $IOART_INTMASK, IOAPIC_WINDOW(%edx) |
| 93 | /* set intmask in target apic reg */ | |
| 8a8d5d85 | 94 | 2: |
| 97359a5b | 95 | APIC_IMASK_UNLOCK /* exit critical reg */ |
| 984263bc MD |
96 | ret |
| 97 | ||
| 37e7efec | 98 | ENTRY(APIC_INTREN) |
| 97359a5b | 99 | APIC_IMASK_LOCK /* enter critical reg */ |
| 8a8d5d85 MD |
100 | movl 4(%esp), %eax /* mask into %eax */ |
| 101 | 1: | |
| 3d911e0a | 102 | shll $IOAPIC_IM_SZSHIFT, %eax |
| ea689d1c | 103 | andl $~IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax) |
| 3d911e0a SZ |
104 | movl CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx |
| 105 | movl CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx | |
| 984263bc | 106 | testl %edx, %edx |
| 8a8d5d85 | 107 | jz 2f |
| 984263bc | 108 | movl %ecx, (%edx) /* write the target register index */ |
| d2dd4a9f SZ |
109 | andl $~IOART_INTMASK, IOAPIC_WINDOW(%edx) |
| 110 | /* clear mask bit */ | |
| 8a8d5d85 | 111 | 2: |
| 97359a5b | 112 | APIC_IMASK_UNLOCK /* exit critical reg */ |
| 984263bc MD |
113 | ret |
| 114 | ||
| 984263bc MD |
115 | /****************************************************************************** |
| 116 | * | |
| 117 | */ | |
| 118 | ||
| 119 | /* | |
| 120 | * u_int io_apic_write(int apic, int select); | |
| 121 | */ | |
| 122 | ENTRY(io_apic_read) | |
| 123 | movl 4(%esp), %ecx /* APIC # */ | |
| 2954c92f | 124 | movl ioapic, %eax |
| 984263bc MD |
125 | movl (%eax,%ecx,4), %edx /* APIC base register address */ |
| 126 | movl 8(%esp), %eax /* target register index */ | |
| 127 | movl %eax, (%edx) /* write the target register index */ | |
| d2dd4a9f | 128 | movl IOAPIC_WINDOW(%edx), %eax /* read the APIC register data */ |
| 984263bc MD |
129 | ret /* %eax = register value */ |
| 130 | ||
| 131 | /* | |
| 132 | * void io_apic_write(int apic, int select, int value); | |
| 133 | */ | |
| 134 | ENTRY(io_apic_write) | |
| 135 | movl 4(%esp), %ecx /* APIC # */ | |
| 2954c92f | 136 | movl ioapic, %eax |
| 984263bc MD |
137 | movl (%eax,%ecx,4), %edx /* APIC base register address */ |
| 138 | movl 8(%esp), %eax /* target register index */ | |
| 139 | movl %eax, (%edx) /* write the target register index */ | |
| 140 | movl 12(%esp), %eax /* target register value */ | |
| d2dd4a9f | 141 | movl %eax, IOAPIC_WINDOW(%edx) /* write the APIC register data */ |
| 984263bc MD |
142 | ret /* %eax = void */ |
| 143 | ||
| 144 | /* | |
| 145 | * Send an EOI to the local APIC. | |
| 146 | */ | |
| 147 | ENTRY(apic_eoi) | |
| 2954c92f | 148 | movl $0, lapic+0xb0 |
| 984263bc | 149 | ret |
| ef0fdad1 | 150 | |
| 06f5be02 | 151 | #endif |