IO APIC: Get rid of apic_imen
[dragonfly.git] / sys / platform / pc32 / apic / apic_vector.s
CommitLineData
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1/*
2 * from: vector.s, 386BSD 0.1 unknown origin
3 * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
21ce0dfa 4 * $DragonFly: src/sys/platform/pc32/apic/apic_vector.s,v 1.39 2008/08/02 01:14:43 dillon Exp $
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5 */
6
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7#include "use_npx.h"
8#include "opt_auto_eoi.h"
9
10#include <machine/asmacros.h>
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11#include <machine/lock.h>
12#include <machine/psl.h>
13#include <machine/trap.h>
06f5be02 14
a9295349 15#include <machine_base/icu/icu.h>
21ce0dfa 16#include <bus/isa/isa.h>
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17
18#include "assym.s"
984263bc 19
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20#include "apicreg.h"
21#include "apic_ipl.h"
984263bc 22#include <machine/smp.h>
a9295349 23#include <machine_base/isa/intr_machdep.h>
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24
25/* convert an absolute IRQ# into a bitmask */
8a8d5d85 26#define IRQ_LBIT(irq_num) (1 << (irq_num))
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27
28/* make an index into the IO APIC from the IRQ# */
29#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
30
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31#ifdef SMP
32#define MPLOCKED lock ;
33#else
34#define MPLOCKED
35#endif
36
984263bc 37/*
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38 * Push an interrupt frame in a format acceptable to doreti, reload
39 * the segment registers for the kernel.
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40 */
41#define PUSH_FRAME \
42 pushl $0 ; /* dummy error code */ \
43 pushl $0 ; /* dummy trap type */ \
4e7c41c5 44 pushl $0 ; /* dummy xflags type */ \
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45 pushal ; \
46 pushl %ds ; /* save data and extra segments ... */ \
47 pushl %es ; \
8a8d5d85 48 pushl %fs ; \
4e7c41c5 49 pushl %gs ; \
c885c20e 50 cld ; \
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51 mov $KDSEL,%ax ; \
52 mov %ax,%ds ; \
53 mov %ax,%es ; \
4e7c41c5 54 mov %ax,%gs ; \
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55 mov $KPSEL,%ax ; \
56 mov %ax,%fs ; \
984263bc 57
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58#define PUSH_DUMMY \
59 pushfl ; /* phys int frame / flags */ \
60 pushl %cs ; /* phys int frame / cs */ \
61 pushl 12(%esp) ; /* original caller eip */ \
62 pushl $0 ; /* dummy error code */ \
63 pushl $0 ; /* dummy trap type */ \
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64 pushl $0 ; /* dummy xflags type */ \
65 subl $13*4,%esp ; /* pushal + 4 seg regs (dummy) + CPL */ \
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66
67/*
68 * Warning: POP_FRAME can only be used if there is no chance of a
69 * segment register being changed (e.g. by procfs), which is why syscalls
70 * have to use doreti.
71 */
984263bc 72#define POP_FRAME \
4e7c41c5 73 popl %gs ; \
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74 popl %fs ; \
75 popl %es ; \
76 popl %ds ; \
77 popal ; \
4e7c41c5 78 addl $3*4,%esp ; /* dummy xflags, trap & error codes */ \
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79
80#define POP_DUMMY \
4e7c41c5 81 addl $19*4,%esp ; \
984263bc 82
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83#define IOAPICADDR(irq_num) \
84 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ADDR
85#define REDIRIDX(irq_num) \
86 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ENTIDX
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87#define IOAPICFLAGS(irq_num) \
88 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_FLAGS
8a8d5d85 89
984263bc 90#define MASK_IRQ(irq_num) \
97359a5b 91 APIC_IMASK_LOCK ; /* into critical reg */ \
ea689d1c 92 testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
984263bc 93 jne 7f ; /* masked, don't mask */ \
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94 orl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
95 /* set the mask bit */ \
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96 movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
97 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
98 movl %eax, (%ecx) ; /* write the index */ \
bda48b43 99 orl $IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* set the mask */ \
984263bc 1007: ; /* already masked */ \
97359a5b 101 APIC_IMASK_UNLOCK ; \
8a8d5d85 102
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103/*
104 * Test to see whether we are handling an edge or level triggered INT.
105 * Level-triggered INTs must still be masked as we don't clear the source,
106 * and the EOI cycle would cause redundant INTs to occur.
107 */
108#define MASK_LEVEL_IRQ(irq_num) \
0f546930 109 testl $IOAPIC_IM_FLAG_LEVEL, IOAPICFLAGS(irq_num) ; \
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110 jz 9f ; /* edge, don't mask */ \
111 MASK_IRQ(irq_num) ; \
8a8d5d85 1129: ; \
984263bc 113
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114/*
115 * Test to see if the source is currntly masked, clear if so.
116 */
ea689d1c 117#define UNMASK_IRQ(irq_num) \
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118 cmpl $0,%eax ; \
119 jnz 8f ; \
97359a5b 120 APIC_IMASK_LOCK ; /* into critical reg */ \
ea689d1c 121 testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
984263bc 122 je 7f ; /* bit clear, not masked */ \
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123 andl $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
124 /* clear mask bit */ \
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125 movl IOAPICADDR(irq_num),%ecx ; /* ioapic addr */ \
126 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
127 movl %eax,(%ecx) ; /* write the index */ \
bda48b43 128 andl $~IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* clear the mask */ \
984263bc 1297: ; \
97359a5b 130 APIC_IMASK_UNLOCK ; \
477d3c1c 1318: ; \
984263bc 132
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133#ifdef APIC_IO
134
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135/*
136 * Fast interrupt call handlers run in the following sequence:
137 *
138 * - Push the trap frame required by doreti
139 * - Mask the interrupt and reenable its source
140 * - If we cannot take the interrupt set its fpending bit and
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141 * doreti. Note that we cannot mess with mp_lock at all
142 * if we entered from a critical section!
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143 * - If we can take the interrupt clear its fpending bit,
144 * call the handler, then unmask and doreti.
145 *
146 * YYY can cache gd base opitner instead of using hidden %fs prefixes.
147 */
148
149#define FAST_INTR(irq_num, vec_name) \
150 .text ; \
151 SUPERALIGN_TEXT ; \
152IDTVEC(vec_name) ; \
153 PUSH_FRAME ; \
4e7c41c5 154 FAKE_MCOUNT(15*4(%esp)) ; \
8a8d5d85 155 MASK_LEVEL_IRQ(irq_num) ; \
35408d22 156 movl $0, lapic_eoi ; \
8a8d5d85 157 movl PCPU(curthread),%ebx ; \
38787eef 158 movl $0,%eax ; /* CURRENT CPL IN FRAME (REMOVED) */ \
984263bc 159 pushl %eax ; \
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160 testl $-1,TD_NEST_COUNT(%ebx) ; \
161 jne 1f ; \
8a8d5d85 162 cmpl $TDPRI_CRIT,TD_PRI(%ebx) ; \
38787eef 163 jl 2f ; \
8a8d5d85 1641: ; \
545a1cd3 165 /* in critical section, make interrupt pending */ \
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166 /* set the pending bit and return, leave interrupt masked */ \
167 orl $IRQ_LBIT(irq_num),PCPU(fpending) ; \
235957ed 168 orl $RQF_INTPEND,PCPU(reqflags) ; \
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169 jmp 5f ; \
1702: ; \
171 /* clear pending bit, run handler */ \
8a8d5d85 172 andl $~IRQ_LBIT(irq_num),PCPU(fpending) ; \
477d3c1c 173 pushl $irq_num ; \
c7eb0589 174 pushl %esp ; /* pass frame by reference */ \
477d3c1c 175 call ithread_fast_handler ; /* returns 0 to unmask */ \
c7eb0589 176 addl $8, %esp ; \
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177 UNMASK_IRQ(irq_num) ; \
1785: ; \
179 MEXITCOUNT ; \
180 jmp doreti ; \
984263bc 181
8a8d5d85 182/*
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183 * Slow interrupt call handlers run in the following sequence:
184 *
185 * - Push the trap frame required by doreti.
186 * - Mask the interrupt and reenable its source.
187 * - If we cannot take the interrupt set its ipending bit and
188 * doreti. In addition to checking for a critical section
189 * and cpl mask we also check to see if the thread is still
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190 * running. Note that we cannot mess with mp_lock at all
191 * if we entered from a critical section!
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192 * - If we can take the interrupt clear its ipending bit
193 * and schedule the thread. Leave interrupts masked and doreti.
8a8d5d85 194 *
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195 * Note that calls to sched_ithd() are made with interrupts enabled
196 * and outside a critical section. YYY sched_ithd may preempt us
03aa8d99 197 * synchronously (fix interrupt stacking).
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198 *
199 * YYY can cache gd base pointer instead of using hidden %fs
200 * prefixes.
201 */
202
10ff1029 203#define SLOW_INTR(irq_num, vec_name, maybe_extra_ipending) \
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204 .text ; \
205 SUPERALIGN_TEXT ; \
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206IDTVEC(vec_name) ; \
207 PUSH_FRAME ; \
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208 maybe_extra_ipending ; \
209; \
984263bc 210 MASK_LEVEL_IRQ(irq_num) ; \
1e9de339 211 incl PCPU(cnt) + V_INTR ; \
35408d22 212 movl $0, lapic_eoi ; \
2954c92f 213 movl PCPU(curthread),%ebx ; \
38787eef 214 movl $0,%eax ; /* CURRENT CPL IN FRAME (REMOVED) */ \
8a8d5d85 215 pushl %eax ; /* cpl do restore */ \
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216 testl $-1,TD_NEST_COUNT(%ebx) ; \
217 jne 1f ; \
8f41e33b 218 cmpl $TDPRI_CRIT,TD_PRI(%ebx) ; \
38787eef 219 jl 2f ; \
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2201: ; \
221 /* set the pending bit and return, leave the interrupt masked */ \
222 orl $IRQ_LBIT(irq_num), PCPU(ipending) ; \
235957ed 223 orl $RQF_INTPEND,PCPU(reqflags) ; \
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224 jmp 5f ; \
2252: ; \
8a8d5d85 226 /* set running bit, clear pending bit, run handler */ \
8a8d5d85 227 andl $~IRQ_LBIT(irq_num), PCPU(ipending) ; \
1be5027b 228 incl TD_NEST_COUNT(%ebx) ; \
984263bc 229 sti ; \
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230 pushl $irq_num ; \
231 call sched_ithd ; \
ef0fdad1 232 addl $4,%esp ; \
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233 cli ; \
234 decl TD_NEST_COUNT(%ebx) ; \
8a8d5d85 2355: ; \
984263bc 236 MEXITCOUNT ; \
2954c92f 237 jmp doreti ; \
8a8d5d85 238
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239/*
240 * Wrong interrupt call handlers. We program these into APIC vectors
241 * that should otherwise never occur. For example, we program the SLOW
242 * vector for irq N with this when we program the FAST vector with the
243 * real interrupt.
244 *
245 * XXX for now all we can do is EOI it. We can't call do_wrongintr
246 * (yet) because we could be in a critical section.
247 */
248#define WRONGINTR(irq_num,vec_name) \
249 .text ; \
250 SUPERALIGN_TEXT ; \
251IDTVEC(vec_name) ; \
252 PUSH_FRAME ; \
253 movl $0, lapic_eoi ; /* End Of Interrupt to APIC */ \
254 /*pushl $irq_num ;*/ \
255 /*call do_wrongintr ;*/ \
256 /*addl $4,%esp ;*/ \
257 POP_FRAME ; \
258 iret ; \
984263bc 259
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260#endif
261
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262/*
263 * Handle "spurious INTerrupts".
264 * Notes:
265 * This is different than the "spurious INTerrupt" generated by an
266 * 8259 PIC for missing INTs. See the APIC documentation for details.
267 * This routine should NOT do an 'EOI' cycle.
268 */
269 .text
270 SUPERALIGN_TEXT
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271 .globl Xspuriousint
272Xspuriousint:
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273
274 /* No EOI cycle used here */
275
276 iret
277
278
279/*
280 * Handle TLB shootdowns.
281 */
282 .text
283 SUPERALIGN_TEXT
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284 .globl Xinvltlb
285Xinvltlb:
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286 pushl %eax
287
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288 movl %cr3, %eax /* invalidate the TLB */
289 movl %eax, %cr3
290
291 ss /* stack segment, avoid %ds load */
292 movl $0, lapic_eoi /* End Of Interrupt to APIC */
293
294 popl %eax
295 iret
296
297
984263bc 298/*
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299 * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
300 *
301 * - Signals its receipt.
302 * - Waits for permission to restart.
bd8015ca 303 * - Processing pending IPIQ events while waiting.
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304 * - Signals its restart.
305 */
306
307 .text
308 SUPERALIGN_TEXT
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309 .globl Xcpustop
310Xcpustop:
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311 pushl %ebp
312 movl %esp, %ebp
313 pushl %eax
314 pushl %ecx
315 pushl %edx
316 pushl %ds /* save current data segment */
317 pushl %fs
318
319 movl $KDSEL, %eax
320 mov %ax, %ds /* use KERNEL data segment */
321 movl $KPSEL, %eax
322 mov %ax, %fs
323
324 movl $0, lapic_eoi /* End Of Interrupt to APIC */
325
2954c92f 326 movl PCPU(cpuid), %eax
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327 imull $PCB_SIZE, %eax
328 leal CNAME(stoppcbs)(%eax), %eax
329 pushl %eax
330 call CNAME(savectx) /* Save process context */
331 addl $4, %esp
332
333
2954c92f 334 movl PCPU(cpuid), %eax
984263bc 335
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336 /*
337 * Indicate that we have stopped and loop waiting for permission
338 * to start again. We must still process IPI events while in a
339 * stopped state.
340 */
97359a5b 341 MPLOCKED
2954c92f 342 btsl %eax, stopped_cpus /* stopped_cpus |= (1<<id) */
984263bc 3431:
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344 andl $~RQF_IPIQ,PCPU(reqflags)
345 pushl %eax
346 call lwkt_smp_stopped
347 popl %eax
2954c92f 348 btl %eax, started_cpus /* while (!(started_cpus & (1<<id))) */
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349 jnc 1b
350
97359a5b 351 MPLOCKED
2954c92f 352 btrl %eax, started_cpus /* started_cpus &= ~(1<<id) */
97359a5b 353 MPLOCKED
2954c92f 354 btrl %eax, stopped_cpus /* stopped_cpus &= ~(1<<id) */
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355
356 test %eax, %eax
357 jnz 2f
358
359 movl CNAME(cpustop_restartfunc), %eax
360 test %eax, %eax
361 jz 2f
362 movl $0, CNAME(cpustop_restartfunc) /* One-shot */
363
364 call *%eax
3652:
366 popl %fs
367 popl %ds /* restore previous data segment */
368 popl %edx
369 popl %ecx
370 popl %eax
371 movl %ebp, %esp
372 popl %ebp
373 iret
374
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375 /*
376 * For now just have one ipiq IPI, but what we really want is
377 * to have one for each source cpu to the APICs don't get stalled
378 * backlogging the requests.
379 */
380 .text
381 SUPERALIGN_TEXT
382 .globl Xipiq
383Xipiq:
384 PUSH_FRAME
385 movl $0, lapic_eoi /* End Of Interrupt to APIC */
4e7c41c5 386 FAKE_MCOUNT(15*4(%esp))
96728c05 387
b785701b 388 incl PCPU(cnt) + V_IPI
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389 movl PCPU(curthread),%ebx
390 cmpl $TDPRI_CRIT,TD_PRI(%ebx)
391 jge 1f
88c4d2f6 392 subl $8,%esp /* make same as interrupt frame */
c7eb0589 393 pushl %esp /* pass frame by reference */
03aa8d99 394 incl PCPU(intr_nesting_level)
96728c05 395 addl $TDPRI_CRIT,TD_PRI(%ebx)
88c4d2f6 396 call lwkt_process_ipiq_frame
96728c05 397 subl $TDPRI_CRIT,TD_PRI(%ebx)
03aa8d99 398 decl PCPU(intr_nesting_level)
c7eb0589 399 addl $12,%esp
38787eef 400 pushl $0 /* CPL for frame (REMOVED) */
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401 MEXITCOUNT
402 jmp doreti
4031:
235957ed 404 orl $RQF_IPIQ,PCPU(reqflags)
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405 MEXITCOUNT
406 POP_FRAME
407 iret
984263bc 408
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409 .text
410 SUPERALIGN_TEXT
411 .globl Xtimer
412Xtimer:
413 PUSH_FRAME
414 movl $0, lapic_eoi /* End Of Interrupt to APIC */
415 FAKE_MCOUNT(15*4(%esp))
416
b785701b 417 incl PCPU(cnt) + V_TIMER
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418 movl PCPU(curthread),%ebx
419 cmpl $TDPRI_CRIT,TD_PRI(%ebx)
420 jge 1f
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421 testl $-1,TD_NEST_COUNT(%ebx)
422 jne 1f
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423 subl $8,%esp /* make same as interrupt frame */
424 pushl %esp /* pass frame by reference */
425 incl PCPU(intr_nesting_level)
426 addl $TDPRI_CRIT,TD_PRI(%ebx)
427 call lapic_timer_process_frame
428 subl $TDPRI_CRIT,TD_PRI(%ebx)
429 decl PCPU(intr_nesting_level)
430 addl $12,%esp
431 pushl $0 /* CPL for frame (REMOVED) */
432 MEXITCOUNT
433 jmp doreti
4341:
435 orl $RQF_TIMER,PCPU(reqflags)
436 MEXITCOUNT
437 POP_FRAME
438 iret
439
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440#ifdef APIC_IO
441
984263bc 442MCOUNT_LABEL(bintr)
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443 FAST_INTR(0,apic_fastintr0)
444 FAST_INTR(1,apic_fastintr1)
445 FAST_INTR(2,apic_fastintr2)
446 FAST_INTR(3,apic_fastintr3)
447 FAST_INTR(4,apic_fastintr4)
448 FAST_INTR(5,apic_fastintr5)
449 FAST_INTR(6,apic_fastintr6)
450 FAST_INTR(7,apic_fastintr7)
451 FAST_INTR(8,apic_fastintr8)
452 FAST_INTR(9,apic_fastintr9)
453 FAST_INTR(10,apic_fastintr10)
454 FAST_INTR(11,apic_fastintr11)
455 FAST_INTR(12,apic_fastintr12)
456 FAST_INTR(13,apic_fastintr13)
457 FAST_INTR(14,apic_fastintr14)
458 FAST_INTR(15,apic_fastintr15)
459 FAST_INTR(16,apic_fastintr16)
460 FAST_INTR(17,apic_fastintr17)
461 FAST_INTR(18,apic_fastintr18)
462 FAST_INTR(19,apic_fastintr19)
463 FAST_INTR(20,apic_fastintr20)
464 FAST_INTR(21,apic_fastintr21)
465 FAST_INTR(22,apic_fastintr22)
466 FAST_INTR(23,apic_fastintr23)
984263bc 467
8a8d5d85 468 /* YYY what is this garbage? */
984263bc 469
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470 SLOW_INTR(0,apic_slowintr0,)
471 SLOW_INTR(1,apic_slowintr1,)
472 SLOW_INTR(2,apic_slowintr2,)
473 SLOW_INTR(3,apic_slowintr3,)
474 SLOW_INTR(4,apic_slowintr4,)
475 SLOW_INTR(5,apic_slowintr5,)
476 SLOW_INTR(6,apic_slowintr6,)
477 SLOW_INTR(7,apic_slowintr7,)
478 SLOW_INTR(8,apic_slowintr8,)
479 SLOW_INTR(9,apic_slowintr9,)
480 SLOW_INTR(10,apic_slowintr10,)
481 SLOW_INTR(11,apic_slowintr11,)
482 SLOW_INTR(12,apic_slowintr12,)
483 SLOW_INTR(13,apic_slowintr13,)
484 SLOW_INTR(14,apic_slowintr14,)
485 SLOW_INTR(15,apic_slowintr15,)
486 SLOW_INTR(16,apic_slowintr16,)
487 SLOW_INTR(17,apic_slowintr17,)
488 SLOW_INTR(18,apic_slowintr18,)
489 SLOW_INTR(19,apic_slowintr19,)
490 SLOW_INTR(20,apic_slowintr20,)
491 SLOW_INTR(21,apic_slowintr21,)
492 SLOW_INTR(22,apic_slowintr22,)
493 SLOW_INTR(23,apic_slowintr23,)
8a8d5d85 494
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495 WRONGINTR(0,apic_wrongintr0)
496 WRONGINTR(1,apic_wrongintr1)
497 WRONGINTR(2,apic_wrongintr2)
498 WRONGINTR(3,apic_wrongintr3)
499 WRONGINTR(4,apic_wrongintr4)
500 WRONGINTR(5,apic_wrongintr5)
501 WRONGINTR(6,apic_wrongintr6)
502 WRONGINTR(7,apic_wrongintr7)
503 WRONGINTR(8,apic_wrongintr8)
504 WRONGINTR(9,apic_wrongintr9)
505 WRONGINTR(10,apic_wrongintr10)
506 WRONGINTR(11,apic_wrongintr11)
507 WRONGINTR(12,apic_wrongintr12)
508 WRONGINTR(13,apic_wrongintr13)
509 WRONGINTR(14,apic_wrongintr14)
510 WRONGINTR(15,apic_wrongintr15)
511 WRONGINTR(16,apic_wrongintr16)
512 WRONGINTR(17,apic_wrongintr17)
513 WRONGINTR(18,apic_wrongintr18)
514 WRONGINTR(19,apic_wrongintr19)
515 WRONGINTR(20,apic_wrongintr20)
516 WRONGINTR(21,apic_wrongintr21)
517 WRONGINTR(22,apic_wrongintr22)
518 WRONGINTR(23,apic_wrongintr23)
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519MCOUNT_LABEL(eintr)
520
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521#endif
522
984263bc 523 .data
ef0fdad1 524
984263bc 525/* variables used by stop_cpus()/restart_cpus()/Xcpustop */
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526 .globl stopped_cpus, started_cpus
527stopped_cpus:
984263bc 528 .long 0
2954c92f 529started_cpus:
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530 .long 0
531
984263bc 532 .globl CNAME(cpustop_restartfunc)
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533CNAME(cpustop_restartfunc):
534 .long 0
535
984263bc 536 .text
06f5be02 537