bce: Split out frontend for interrupt handler
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
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1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
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31 */
32
33/*
34 * The following controllers are supported by this driver:
35 * BCM5706C A2, A3
d0092544 36 * BCM5706S A2, A3
43c2aeb0 37 * BCM5708C B1, B2
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38 * BCM5708S B1, B2
39 * BCM5709C A1, C0
40 * BCM5716 C0
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41 *
42 * The following controllers are not supported by this driver:
43 * BCM5706C A0, A1
d0092544 44 * BCM5706S A0, A1
43c2aeb0 45 * BCM5708C A0, B0
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46 * BCM5708S A0, B0
47 * BCM5709C A0, B0, B1
48 * BCM5709S A0, A1, B0, B1, B2, C0
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49 */
50
51#include "opt_bce.h"
52#include "opt_polling.h"
53
54#include <sys/param.h>
55#include <sys/bus.h>
56#include <sys/endian.h>
57#include <sys/kernel.h>
9db4b353 58#include <sys/interrupt.h>
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59#include <sys/mbuf.h>
60#include <sys/malloc.h>
61#include <sys/queue.h>
62#ifdef BCE_DEBUG
63#include <sys/random.h>
64#endif
65#include <sys/rman.h>
66#include <sys/serialize.h>
67#include <sys/socket.h>
68#include <sys/sockio.h>
69#include <sys/sysctl.h>
70
71#include <net/bpf.h>
72#include <net/ethernet.h>
73#include <net/if.h>
74#include <net/if_arp.h>
75#include <net/if_dl.h>
76#include <net/if_media.h>
77#include <net/if_types.h>
78#include <net/ifq_var.h>
79#include <net/vlan/if_vlan_var.h>
b637f170 80#include <net/vlan/if_vlan_ether.h>
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81
82#include <dev/netif/mii_layer/mii.h>
83#include <dev/netif/mii_layer/miivar.h>
84
85#include <bus/pci/pcireg.h>
86#include <bus/pci/pcivar.h>
87
88#include "miibus_if.h"
89
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90#include <dev/netif/bce/if_bcereg.h>
91#include <dev/netif/bce/if_bcefw.h>
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92
93/****************************************************************************/
94/* BCE Debug Options */
95/****************************************************************************/
96#ifdef BCE_DEBUG
97
98static uint32_t bce_debug = BCE_WARN;
99
100/*
101 * 0 = Never
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
107 * 268435456 = 1 in 8
108 * 536870912 = 1 in 4
109 * 1073741824 = 1 in 2
110 *
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
113 *
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
116 *
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
119 *
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
122 *
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
125 */
126static int bce_debug_l2fhdr_status_check = 0;
127static int bce_debug_unexpected_attention = 0;
128static int bce_debug_mbuf_allocation_failure = 0;
129static int bce_debug_dma_map_addr_failure = 0;
130static int bce_debug_bootcode_running_failure = 0;
131
132#endif /* BCE_DEBUG */
133
134
135/****************************************************************************/
136/* PCI Device ID Table */
137/* */
138/* Used by bce_probe() to identify the devices supported by this driver. */
139/****************************************************************************/
140#define BCE_DEVDESC_MAX 64
141
142static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
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148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
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152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
154
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
160
161 /* BCM5708C controllers and OEM boards. */
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162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
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168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
170
171 /* BCM5708S controllers and OEM boards. */
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172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
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178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
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180
181 /* BCM5709C controllers and OEM boards. */
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182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
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186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
188
189 /* BCM5709S controllers and OEM boards. */
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190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
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194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
196
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
200
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201 { 0, 0, 0, 0, NULL }
202};
203
204
205/****************************************************************************/
206/* Supported Flash NVRAM device data. */
207/****************************************************************************/
208static const struct flash_spec flash_table[] =
209{
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210#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211#define NONBUFFERED_FLAGS (BCE_NV_WREN)
212
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213 /* Slow EEPROM */
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217 "EEPROM - slow"},
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 "Entry 0001"},
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239 "Entry 0100"},
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
d0092544 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
256 /* Fast EEPROM */
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
d0092544 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
260 "EEPROM - fast"},
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265 "Entry 1001"},
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270 "Entry 1010"},
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280 "Entry 1100"},
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
d0092544 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285 "Entry 1101"},
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
d0092544 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
296};
297
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298/*
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
303 * driver.
304 */
305static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
312};
313
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314
315/****************************************************************************/
316/* DragonFly device entry points. */
317/****************************************************************************/
318static int bce_probe(device_t);
319static int bce_attach(device_t);
320static int bce_detach(device_t);
321static void bce_shutdown(device_t);
322
323/****************************************************************************/
324/* BCE Debug Data Structure Dump Routines */
325/****************************************************************************/
326#ifdef BCE_DEBUG
327static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334static void bce_dump_tx_chain(struct bce_softc *, int, int);
335static void bce_dump_rx_chain(struct bce_softc *, int, int);
336static void bce_dump_status_block(struct bce_softc *);
337static void bce_dump_driver_state(struct bce_softc *);
338static void bce_dump_stats_block(struct bce_softc *) __unused;
339static void bce_dump_hw_state(struct bce_softc *);
340static void bce_dump_txp_state(struct bce_softc *);
341static void bce_dump_rxp_state(struct bce_softc *) __unused;
342static void bce_dump_tpat_state(struct bce_softc *) __unused;
343static void bce_freeze_controller(struct bce_softc *) __unused;
344static void bce_unfreeze_controller(struct bce_softc *) __unused;
345static void bce_breakpoint(struct bce_softc *);
346#endif /* BCE_DEBUG */
347
348
349/****************************************************************************/
350/* BCE Register/Memory Access Routines */
351/****************************************************************************/
352static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
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354static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355static uint32_t bce_shmem_rd(struct bce_softc *, u32);
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356static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357static int bce_miibus_read_reg(device_t, int, int);
358static int bce_miibus_write_reg(device_t, int, int, int);
359static void bce_miibus_statchg(device_t);
360
361
362/****************************************************************************/
363/* BCE NVRAM Access Routines */
364/****************************************************************************/
365static int bce_acquire_nvram_lock(struct bce_softc *);
366static int bce_release_nvram_lock(struct bce_softc *);
367static void bce_enable_nvram_access(struct bce_softc *);
368static void bce_disable_nvram_access(struct bce_softc *);
369static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
370 uint32_t);
371static int bce_init_nvram(struct bce_softc *);
372static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373static int bce_nvram_test(struct bce_softc *);
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374
375/****************************************************************************/
376/* BCE DMA Allocate/Free Routines */
377/****************************************************************************/
378static int bce_dma_alloc(struct bce_softc *);
379static void bce_dma_free(struct bce_softc *);
380static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
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381
382/****************************************************************************/
383/* BCE Firmware Synchronization and Load */
384/****************************************************************************/
385static int bce_fw_sync(struct bce_softc *, uint32_t);
386static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
387 uint32_t, uint32_t);
388static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
389 struct fw_info *);
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390static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392static void bce_start_rxp_cpu(struct bce_softc *);
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393static void bce_init_rxp_cpu(struct bce_softc *);
394static void bce_init_txp_cpu(struct bce_softc *);
395static void bce_init_tpat_cpu(struct bce_softc *);
396static void bce_init_cp_cpu(struct bce_softc *);
397static void bce_init_com_cpu(struct bce_softc *);
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398static void bce_init_cpus(struct bce_softc *);
399
400static void bce_stop(struct bce_softc *);
401static int bce_reset(struct bce_softc *, uint32_t);
402static int bce_chipinit(struct bce_softc *);
403static int bce_blockinit(struct bce_softc *);
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404static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
405 uint32_t *, int);
314a2fcc 406static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
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407static void bce_probe_pci_caps(struct bce_softc *);
408static void bce_print_adapter_info(struct bce_softc *);
409static void bce_get_media(struct bce_softc *);
43c2aeb0 410
d0092544 411static void bce_init_tx_context(struct bce_softc *);
43c2aeb0 412static int bce_init_tx_chain(struct bce_softc *);
d0092544 413static void bce_init_rx_context(struct bce_softc *);
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414static int bce_init_rx_chain(struct bce_softc *);
415static void bce_free_rx_chain(struct bce_softc *);
416static void bce_free_tx_chain(struct bce_softc *);
417
418static int bce_encap(struct bce_softc *, struct mbuf **);
419static void bce_start(struct ifnet *);
420static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421static void bce_watchdog(struct ifnet *);
422static int bce_ifmedia_upd(struct ifnet *);
423static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424static void bce_init(void *);
425static void bce_mgmt_init(struct bce_softc *);
426
5b609aa3 427static int bce_init_ctx(struct bce_softc *);
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428static void bce_get_mac_addr(struct bce_softc *);
429static void bce_set_mac_addr(struct bce_softc *);
430static void bce_phy_intr(struct bce_softc *);
431static void bce_rx_intr(struct bce_softc *, int);
432static void bce_tx_intr(struct bce_softc *);
433static void bce_disable_intr(struct bce_softc *);
d0092544 434static void bce_enable_intr(struct bce_softc *, int);
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435
436#ifdef DEVICE_POLLING
437static void bce_poll(struct ifnet *, enum poll_cmd, int);
438#endif
eac57ffb
SZ
439static void bce_intr(struct bce_softc *);
440static void bce_intr_legacy(void *);
441static void bce_intr_msi(void *);
442static void bce_intr_msi_oneshot(void *);
43c2aeb0
SZ
443static void bce_set_rx_mode(struct bce_softc *);
444static void bce_stats_update(struct bce_softc *);
445static void bce_tick(void *);
446static void bce_tick_serialized(struct bce_softc *);
d0092544 447static void bce_pulse(void *);
43c2aeb0
SZ
448static void bce_add_sysctls(struct bce_softc *);
449
bdeb8fff
SZ
450static void bce_coal_change(struct bce_softc *);
451static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
452static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
453static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
454static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
455static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
456static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
457static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
458static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
459static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
460 uint32_t *, uint32_t);
461
3fb4bb6c
SZ
462/*
463 * NOTE:
464 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
465 * takes 1023 as the TX ticks limit. However, using 1023 will
466 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
467 * there is _no_ network activity on the NIC.
3fb4bb6c
SZ
468 */
469static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
470static uint32_t bce_tx_bds = 255; /* bcm: 20 */
471static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
472static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
1af951ab
SZ
473static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
474static uint32_t bce_rx_bds = 128; /* bcm: 6 */
475static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
476static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
bdeb8fff 477
83ce3dce
SZ
478static int bce_msi_enable = 1;
479
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SZ
480TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
481TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
482TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
483TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
484TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
485TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
486TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
487TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
83ce3dce 488TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
43c2aeb0
SZ
489
490/****************************************************************************/
491/* DragonFly device dispatch table. */
492/****************************************************************************/
493static device_method_t bce_methods[] = {
494 /* Device interface */
495 DEVMETHOD(device_probe, bce_probe),
496 DEVMETHOD(device_attach, bce_attach),
497 DEVMETHOD(device_detach, bce_detach),
498 DEVMETHOD(device_shutdown, bce_shutdown),
499
500 /* bus interface */
501 DEVMETHOD(bus_print_child, bus_generic_print_child),
502 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
503
504 /* MII interface */
505 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
506 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
507 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
508
509 { 0, 0 }
510};
511
512static driver_t bce_driver = {
513 "bce",
514 bce_methods,
515 sizeof(struct bce_softc)
516};
517
518static devclass_t bce_devclass;
519
43c2aeb0 520
d0092544 521DECLARE_DUMMY_MODULE(if_bce);
1be78fa8 522MODULE_DEPEND(bce, miibus, 1, 1, 1);
aa2b9d05
SW
523DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
524DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
43c2aeb0
SZ
525
526
527/****************************************************************************/
528/* Device probe function. */
529/* */
530/* Compares the device to the driver's list of supported devices and */
531/* reports back to the OS whether this is the right driver for the device. */
532/* */
533/* Returns: */
534/* BUS_PROBE_DEFAULT on success, positive value on failure. */
535/****************************************************************************/
536static int
537bce_probe(device_t dev)
538{
539 struct bce_type *t;
540 uint16_t vid, did, svid, sdid;
541
542 /* Get the data for the device to be probed. */
543 vid = pci_get_vendor(dev);
544 did = pci_get_device(dev);
545 svid = pci_get_subvendor(dev);
546 sdid = pci_get_subdevice(dev);
547
548 /* Look through the list of known devices for a match. */
549 for (t = bce_devs; t->bce_name != NULL; ++t) {
550 if (vid == t->bce_vid && did == t->bce_did &&
551 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
552 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
553 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
554 char *descbuf;
555
556 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
557
558 /* Print out the device identity. */
559 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
560 t->bce_name,
561 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
562
563 device_set_desc_copy(dev, descbuf);
564 kfree(descbuf, M_TEMP);
565 return 0;
566 }
567 }
568 return ENXIO;
569}
570
571
572/****************************************************************************/
d0092544
SZ
573/* PCI Capabilities Probe Function. */
574/* */
575/* Walks the PCI capabiites list for the device to find what features are */
576/* supported. */
577/* */
578/* Returns: */
579/* None. */
580/****************************************************************************/
581static void
582bce_print_adapter_info(struct bce_softc *sc)
583{
584 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
585
586 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
587 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
588
589 /* Bus info. */
590 if (sc->bce_flags & BCE_PCIE_FLAG) {
591 kprintf("Bus (PCIe x%d, ", sc->link_width);
592 switch (sc->link_speed) {
593 case 1:
594 kprintf("2.5Gbps); ");
595 break;
596 case 2:
597 kprintf("5Gbps); ");
598 break;
599 default:
600 kprintf("Unknown link speed); ");
601 break;
602 }
603 } else {
604 kprintf("Bus (PCI%s, %s, %dMHz); ",
605 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
606 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
607 sc->bus_speed_mhz);
608 }
609
610 /* Firmware version and device features. */
bc30d40d 611 kprintf("B/C (%s)", sc->bce_bc_ver);
cff16e71
SZ
612
613 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
614 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
615 kprintf("; Flags(");
616 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
bc30d40d 617 kprintf("MFW[%s]", sc->bce_mfw_ver);
cff16e71
SZ
618 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
619 kprintf(" 2.5G");
620 kprintf(")");
621 }
622 kprintf("\n");
d0092544
SZ
623}
624
625
626/****************************************************************************/
627/* PCI Capabilities Probe Function. */
628/* */
629/* Walks the PCI capabiites list for the device to find what features are */
630/* supported. */
631/* */
632/* Returns: */
633/* None. */
634/****************************************************************************/
635static void
636bce_probe_pci_caps(struct bce_softc *sc)
637{
638 device_t dev = sc->bce_dev;
639 uint8_t ptr;
640
641 if (pci_is_pcix(dev))
642 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
643
644 ptr = pci_get_pciecap_ptr(dev);
645 if (ptr) {
646 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
647
648 sc->link_speed = link_status & 0xf;
649 sc->link_width = (link_status >> 4) & 0x3f;
650 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
651 sc->bce_flags |= BCE_PCIE_FLAG;
652 }
653}
654
655
656/****************************************************************************/
43c2aeb0
SZ
657/* Device attach function. */
658/* */
659/* Allocates device resources, performs secondary chip identification, */
660/* resets and initializes the hardware, and initializes driver instance */
661/* variables. */
662/* */
663/* Returns: */
664/* 0 on success, positive value on failure. */
665/****************************************************************************/
666static int
667bce_attach(device_t dev)
668{
669 struct bce_softc *sc = device_get_softc(dev);
670 struct ifnet *ifp = &sc->arpcom.ac_if;
671 uint32_t val;
83ce3dce 672 u_int irq_flags;
eac57ffb 673 void (*irq_handle)(void *);
7fb43956 674 int rid, rc = 0;
bc30d40d 675 int i, j;
43c2aeb0
SZ
676
677 sc->bce_dev = dev;
678 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
679
680 pci_enable_busmaster(dev);
681
d0092544
SZ
682 bce_probe_pci_caps(sc);
683
43c2aeb0
SZ
684 /* Allocate PCI memory resources. */
685 rid = PCIR_BAR(0);
686 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
687 RF_ACTIVE | PCI_RF_DENSE);
688 if (sc->bce_res_mem == NULL) {
689 device_printf(dev, "PCI memory allocation failed\n");
690 return ENXIO;
691 }
692 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
693 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
694
695 /* Allocate PCI IRQ resources. */
7fb43956
SZ
696 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
697 &sc->bce_irq_rid, &irq_flags);
83ce3dce
SZ
698
699 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
700 &sc->bce_irq_rid, irq_flags);
43c2aeb0
SZ
701 if (sc->bce_res_irq == NULL) {
702 device_printf(dev, "PCI map interrupt failed\n");
703 rc = ENXIO;
704 goto fail;
705 }
706
707 /*
708 * Configure byte swap and enable indirect register access.
709 * Rely on CPU to do target byte swapping on big endian systems.
710 * Access to registers outside of PCI configurtion space are not
711 * valid until this is done.
712 */
713 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
714 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
715 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
716
717 /* Save ASIC revsion info. */
718 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
719
720 /* Weed out any non-production controller revisions. */
bc30d40d 721 switch (BCE_CHIP_ID(sc)) {
43c2aeb0
SZ
722 case BCE_CHIP_ID_5706_A0:
723 case BCE_CHIP_ID_5706_A1:
724 case BCE_CHIP_ID_5708_A0:
725 case BCE_CHIP_ID_5708_B0:
d0092544
SZ
726 case BCE_CHIP_ID_5709_A0:
727 case BCE_CHIP_ID_5709_B0:
728 case BCE_CHIP_ID_5709_B1:
729#ifdef foo
730 /* 5709C B2 seems to work fine */
731 case BCE_CHIP_ID_5709_B2:
732#endif
43c2aeb0
SZ
733 device_printf(dev, "Unsupported chip id 0x%08x!\n",
734 BCE_CHIP_ID(sc));
735 rc = ENODEV;
736 goto fail;
737 }
738
eac57ffb
SZ
739 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
740 irq_handle = bce_intr_legacy;
741 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
742 irq_handle = bce_intr_msi;
743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
744 irq_handle = bce_intr_msi_oneshot;
745 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
746 }
747 } else {
748 panic("%s: unsupported intr type %d\n",
749 device_get_nameunit(dev), sc->bce_irq_type);
750 }
751
43c2aeb0
SZ
752 /*
753 * Find the base address for shared memory access.
754 * Newer versions of bootcode use a signature and offset
755 * while older versions use a fixed address.
756 */
757 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
d0092544
SZ
758 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
759 BCE_SHM_HDR_SIGNATURE_SIG) {
760 /* Multi-port devices use different offsets in shared memory. */
761 sc->bce_shmem_base = REG_RD_IND(sc,
762 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
763 } else {
43c2aeb0 764 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
d0092544 765 }
43c2aeb0
SZ
766 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
767
d0092544 768 /* Fetch the bootcode revision. */
bc30d40d
SZ
769 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
770 for (i = 0, j = 0; i < 3; i++) {
771 uint8_t num;
772 int k, skip0;
773
774 num = (uint8_t)(val >> (24 - (i * 8)));
775 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
776 if (num >= k || !skip0 || k == 1) {
777 sc->bce_bc_ver[j++] = (num / k) + '0';
778 skip0 = 0;
779 }
780 }
781 if (i != 2)
782 sc->bce_bc_ver[j++] = '.';
783 }
d0092544 784
bc30d40d
SZ
785 /* Check if any management firwmare is running. */
786 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
787 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
d0092544
SZ
788 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
789
bc30d40d
SZ
790 /* Allow time for firmware to enter the running state. */
791 for (i = 0; i < 30; i++) {
792 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
793 if (val & BCE_CONDITION_MFW_RUN_MASK)
794 break;
795 DELAY(10000);
796 }
797 }
798
799 /* Check the current bootcode state. */
800 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
801 BCE_CONDITION_MFW_RUN_MASK;
802 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
803 val != BCE_CONDITION_MFW_RUN_NONE) {
804 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
805
806 for (i = 0, j = 0; j < 3; j++) {
807 val = bce_reg_rd_ind(sc, addr + j * 4);
808 val = bswap32(val);
809 memcpy(&sc->bce_mfw_ver[i], &val, 4);
810 i += 4;
811 }
812 }
813
43c2aeb0
SZ
814 /* Get PCI bus information (speed and type). */
815 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
816 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
817 uint32_t clkreg;
818
819 sc->bce_flags |= BCE_PCIX_FLAG;
820
821 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
822 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
823 switch (clkreg) {
824 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
825 sc->bus_speed_mhz = 133;
826 break;
827
828 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
829 sc->bus_speed_mhz = 100;
830 break;
831
832 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
833 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
834 sc->bus_speed_mhz = 66;
835 break;
836
837 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
838 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
839 sc->bus_speed_mhz = 50;
840 break;
841
842 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
844 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
845 sc->bus_speed_mhz = 33;
846 break;
847 }
848 } else {
849 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
850 sc->bus_speed_mhz = 66;
851 else
852 sc->bus_speed_mhz = 33;
853 }
854
855 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
856 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
857
43c2aeb0
SZ
858 /* Reset the controller. */
859 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
860 if (rc != 0)
861 goto fail;
862
863 /* Initialize the controller. */
864 rc = bce_chipinit(sc);
865 if (rc != 0) {
866 device_printf(dev, "Controller initialization failed!\n");
867 goto fail;
868 }
869
870 /* Perform NVRAM test. */
871 rc = bce_nvram_test(sc);
872 if (rc != 0) {
873 device_printf(dev, "NVRAM test failed!\n");
874 goto fail;
875 }
876
877 /* Fetch the permanent Ethernet MAC address. */
878 bce_get_mac_addr(sc);
879
880 /*
881 * Trip points control how many BDs
882 * should be ready before generating an
883 * interrupt while ticks control how long
884 * a BD can sit in the chain before
885 * generating an interrupt. Set the default
886 * values for the RX and TX rings.
887 */
888
889#ifdef BCE_DRBUG
890 /* Force more frequent interrupts. */
891 sc->bce_tx_quick_cons_trip_int = 1;
892 sc->bce_tx_quick_cons_trip = 1;
893 sc->bce_tx_ticks_int = 0;
894 sc->bce_tx_ticks = 0;
895
896 sc->bce_rx_quick_cons_trip_int = 1;
897 sc->bce_rx_quick_cons_trip = 1;
898 sc->bce_rx_ticks_int = 0;
899 sc->bce_rx_ticks = 0;
900#else
bdeb8fff
SZ
901 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
902 sc->bce_tx_quick_cons_trip = bce_tx_bds;
903 sc->bce_tx_ticks_int = bce_tx_ticks_int;
904 sc->bce_tx_ticks = bce_tx_ticks;
905
906 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
907 sc->bce_rx_quick_cons_trip = bce_rx_bds;
908 sc->bce_rx_ticks_int = bce_rx_ticks_int;
909 sc->bce_rx_ticks = bce_rx_ticks;
43c2aeb0
SZ
910#endif
911
912 /* Update statistics once every second. */
913 sc->bce_stats_ticks = 1000000 & 0xffff00;
914
d0092544
SZ
915 /* Find the media type for the adapter. */
916 bce_get_media(sc);
43c2aeb0
SZ
917
918 /* Allocate DMA memory resources. */
919 rc = bce_dma_alloc(sc);
920 if (rc != 0) {
921 device_printf(dev, "DMA resource allocation failed!\n");
922 goto fail;
923 }
924
925 /* Initialize the ifnet interface. */
926 ifp->if_softc = sc;
927 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
928 ifp->if_ioctl = bce_ioctl;
929 ifp->if_start = bce_start;
930 ifp->if_init = bce_init;
931 ifp->if_watchdog = bce_watchdog;
932#ifdef DEVICE_POLLING
933 ifp->if_poll = bce_poll;
934#endif
935 ifp->if_mtu = ETHERMTU;
936 ifp->if_hwassist = BCE_IF_HWASSIST;
937 ifp->if_capabilities = BCE_IF_CAPABILITIES;
938 ifp->if_capenable = ifp->if_capabilities;
939 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
940 ifq_set_ready(&ifp->if_snd);
941
942 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
943 ifp->if_baudrate = IF_Gbps(2.5);
944 else
945 ifp->if_baudrate = IF_Gbps(1);
946
947 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
948 sc->mbuf_alloc_size = MCLBYTES;
949
950 /* Look for our PHY. */
951 rc = mii_phy_probe(dev, &sc->bce_miibus,
952 bce_ifmedia_upd, bce_ifmedia_sts);
953 if (rc != 0) {
954 device_printf(dev, "PHY probe failed!\n");
955 goto fail;
956 }
957
958 /* Attach to the Ethernet interface list. */
959 ether_ifattach(ifp, sc->eaddr, NULL);
960
6ac77363
SZ
961 callout_init_mp(&sc->bce_tick_callout);
962 callout_init_mp(&sc->bce_pulse_callout);
43c2aeb0
SZ
963
964 /* Hookup IRQ last. */
eac57ffb 965 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
43c2aeb0
SZ
966 &sc->bce_intrhand, ifp->if_serializer);
967 if (rc != 0) {
968 device_printf(dev, "Failed to setup IRQ!\n");
969 ether_ifdetach(ifp);
970 goto fail;
971 }
972
9db4b353
SZ
973 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
974 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
975
43c2aeb0
SZ
976 /* Print some important debugging info. */
977 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
978
979 /* Add the supported sysctls to the kernel. */
980 bce_add_sysctls(sc);
981
d0092544
SZ
982 /*
983 * The chip reset earlier notified the bootcode that
984 * a driver is present. We now need to start our pulse
985 * routine so that the bootcode is reminded that we're
986 * still running.
987 */
988 bce_pulse(sc);
989
43c2aeb0
SZ
990 /* Get the firmware running so IPMI still works */
991 bce_mgmt_init(sc);
992
b51a4d98
SZ
993 if (bootverbose)
994 bce_print_adapter_info(sc);
d0092544 995
43c2aeb0
SZ
996 return 0;
997fail:
998 bce_detach(dev);
999 return(rc);
1000}
1001
1002
1003/****************************************************************************/
1004/* Device detach function. */
1005/* */
1006/* Stops the controller, resets the controller, and releases resources. */
1007/* */
1008/* Returns: */
1009/* 0 on success, positive value on failure. */
1010/****************************************************************************/
1011static int
1012bce_detach(device_t dev)
1013{
1014 struct bce_softc *sc = device_get_softc(dev);
1015
1016 if (device_is_attached(dev)) {
1017 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1018 uint32_t msg;
43c2aeb0
SZ
1019
1020 /* Stop and reset the controller. */
1021 lwkt_serialize_enter(ifp->if_serializer);
d0092544 1022 callout_stop(&sc->bce_pulse_callout);
43c2aeb0 1023 bce_stop(sc);
d0092544
SZ
1024 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1025 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1026 else
1027 msg = BCE_DRV_MSG_CODE_UNLOAD;
1028 bce_reset(sc, msg);
43c2aeb0
SZ
1029 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1030 lwkt_serialize_exit(ifp->if_serializer);
1031
1032 ether_ifdetach(ifp);
1033 }
1034
1035 /* If we have a child device on the MII bus remove it too. */
1036 if (sc->bce_miibus)
1037 device_delete_child(dev, sc->bce_miibus);
1038 bus_generic_detach(dev);
1039
1040 if (sc->bce_res_irq != NULL) {
83ce3dce
SZ
1041 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1042 sc->bce_res_irq);
43c2aeb0
SZ
1043 }
1044
7fb43956 1045 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
43c2aeb0 1046 pci_release_msi(dev);
43c2aeb0
SZ
1047
1048 if (sc->bce_res_mem != NULL) {
1049 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1050 sc->bce_res_mem);
1051 }
1052
1053 bce_dma_free(sc);
1054
1055 if (sc->bce_sysctl_tree != NULL)
1056 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1057
1058 return 0;
1059}
1060
1061
1062/****************************************************************************/
1063/* Device shutdown function. */
1064/* */
1065/* Stops and resets the controller. */
1066/* */
1067/* Returns: */
1068/* Nothing */
1069/****************************************************************************/
1070static void
1071bce_shutdown(device_t dev)
1072{
1073 struct bce_softc *sc = device_get_softc(dev);
1074 struct ifnet *ifp = &sc->arpcom.ac_if;
d0092544 1075 uint32_t msg;
43c2aeb0
SZ
1076
1077 lwkt_serialize_enter(ifp->if_serializer);
1078 bce_stop(sc);
d0092544
SZ
1079 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1080 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1081 else
1082 msg = BCE_DRV_MSG_CODE_UNLOAD;
1083 bce_reset(sc, msg);
43c2aeb0
SZ
1084 lwkt_serialize_exit(ifp->if_serializer);
1085}
1086
1087
1088/****************************************************************************/
1089/* Indirect register read. */
1090/* */
1091/* Reads NetXtreme II registers using an index/data register pair in PCI */
1092/* configuration space. Using this mechanism avoids issues with posted */
1093/* reads but is much slower than memory-mapped I/O. */
1094/* */
1095/* Returns: */
1096/* The value of the register. */
1097/****************************************************************************/
1098static uint32_t
1099bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1100{
1101 device_t dev = sc->bce_dev;
1102
1103 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1104#ifdef BCE_DEBUG
1105 {
1106 uint32_t val;
1107 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1108 DBPRINT(sc, BCE_EXCESSIVE,
1109 "%s(); offset = 0x%08X, val = 0x%08X\n",
1110 __func__, offset, val);
1111 return val;
1112 }
1113#else
1114 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1115#endif
1116}
1117
1118
1119/****************************************************************************/
1120/* Indirect register write. */
1121/* */
1122/* Writes NetXtreme II registers using an index/data register pair in PCI */
1123/* configuration space. Using this mechanism avoids issues with posted */
1124/* writes but is muchh slower than memory-mapped I/O. */
1125/* */
1126/* Returns: */
1127/* Nothing. */
1128/****************************************************************************/
1129static void
1130bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1131{
1132 device_t dev = sc->bce_dev;
1133
1134 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1135 __func__, offset, val);
1136
1137 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1138 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1139}
1140
1141
1142/****************************************************************************/
bc30d40d
SZ
1143/* Shared memory write. */
1144/* */
1145/* Writes NetXtreme II shared memory region. */
1146/* */
1147/* Returns: */
1148/* Nothing. */
1149/****************************************************************************/
1150static void
1151bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1152{
1153 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1154}
1155
1156
1157/****************************************************************************/
1158/* Shared memory read. */
1159/* */
1160/* Reads NetXtreme II shared memory region. */
1161/* */
1162/* Returns: */
1163/* The 32 bit value read. */
1164/****************************************************************************/
1165static u32
1166bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1167{
1168 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1169}
1170
1171
1172/****************************************************************************/
43c2aeb0
SZ
1173/* Context memory write. */
1174/* */
1175/* The NetXtreme II controller uses context memory to track connection */
1176/* information for L2 and higher network protocols. */
1177/* */
1178/* Returns: */
1179/* Nothing. */
1180/****************************************************************************/
1181static void
d0092544
SZ
1182bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1183 uint32_t ctx_val)
43c2aeb0 1184{
d0092544
SZ
1185 uint32_t idx, offset = ctx_offset + cid_addr;
1186 uint32_t val, retry_cnt = 5;
43c2aeb0 1187
d0092544
SZ
1188 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1189 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1190 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1191 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1192
1193 for (idx = 0; idx < retry_cnt; idx++) {
1194 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1195 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1196 break;
1197 DELAY(5);
1198 }
1199
1200 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1201 device_printf(sc->bce_dev,
1202 "Unable to write CTX memory: "
1203 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1204 cid_addr, ctx_offset);
1205 }
1206 } else {
1207 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1208 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1209 }
43c2aeb0
SZ
1210}
1211
1212
1213/****************************************************************************/
1214/* PHY register read. */
1215/* */
1216/* Implements register reads on the MII bus. */
1217/* */
1218/* Returns: */
1219/* The value of the register. */
1220/****************************************************************************/
1221static int
1222bce_miibus_read_reg(device_t dev, int phy, int reg)
1223{
1224 struct bce_softc *sc = device_get_softc(dev);
1225 uint32_t val;
1226 int i;
1227
1228 /* Make sure we are accessing the correct PHY address. */
1229 if (phy != sc->bce_phy_addr) {
1230 DBPRINT(sc, BCE_VERBOSE,
1231 "Invalid PHY address %d for PHY read!\n", phy);
1232 return 0;
1233 }
1234
1235 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1236 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1237 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1238
1239 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1240 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1241
1242 DELAY(40);
1243 }
1244
1245 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1246 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1247 BCE_EMAC_MDIO_COMM_START_BUSY;
1248 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1249
1250 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1251 DELAY(10);
1252
1253 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1254 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1255 DELAY(5);
1256
1257 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1258 val &= BCE_EMAC_MDIO_COMM_DATA;
1259 break;
1260 }
1261 }
1262
1263 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1264 if_printf(&sc->arpcom.ac_if,
1265 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1266 phy, reg);
1267 val = 0x0;
1268 } else {
1269 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1270 }
1271
1272 DBPRINT(sc, BCE_EXCESSIVE,
1273 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1274 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1275
1276 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1277 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1278 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1279
1280 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1281 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1282
1283 DELAY(40);
1284 }
1285 return (val & 0xffff);
1286}
1287
1288
1289/****************************************************************************/
1290/* PHY register write. */
1291/* */
1292/* Implements register writes on the MII bus. */
1293/* */
1294/* Returns: */
1295/* The value of the register. */
1296/****************************************************************************/
1297static int
1298bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1299{
1300 struct bce_softc *sc = device_get_softc(dev);
1301 uint32_t val1;
1302 int i;
1303
1304 /* Make sure we are accessing the correct PHY address. */
1305 if (phy != sc->bce_phy_addr) {
1306 DBPRINT(sc, BCE_WARN,
1307 "Invalid PHY address %d for PHY write!\n", phy);
1308 return(0);
1309 }
1310
1311 DBPRINT(sc, BCE_EXCESSIVE,
1312 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1313 __func__, phy, (uint16_t)(reg & 0xffff),
1314 (uint16_t)(val & 0xffff));
1315
1316 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1317 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1318 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1319
1320 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1321 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1322
1323 DELAY(40);
1324 }
1325
1326 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1327 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1328 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1329 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1330
1331 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1332 DELAY(10);
1333
1334 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1335 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1336 DELAY(5);
1337 break;
1338 }
1339 }
1340
1341 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1342 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1343
1344 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1345 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1346 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1347
1348 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1349 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1350
1351 DELAY(40);
1352 }
1353 return 0;
1354}
1355
1356
1357/****************************************************************************/
1358/* MII bus status change. */
1359/* */
1360/* Called by the MII bus driver when the PHY establishes link to set the */
1361/* MAC interface registers. */
1362/* */
1363/* Returns: */
1364/* Nothing. */
1365/****************************************************************************/
1366static void
1367bce_miibus_statchg(device_t dev)
1368{
1369 struct bce_softc *sc = device_get_softc(dev);
1370 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1371
1372 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1373 mii->mii_media_active);
1374
1375#ifdef BCE_DEBUG
1376 /* Decode the interface media flags. */
1377 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1378 switch(IFM_TYPE(mii->mii_media_active)) {
1379 case IFM_ETHER:
1380 kprintf("Ethernet )");
1381 break;
1382 default:
1383 kprintf("Unknown )");
1384 break;
1385 }
1386
1387 kprintf(" Media Options: ( ");
1388 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1389 case IFM_AUTO:
1390 kprintf("Autoselect )");
1391 break;
1392 case IFM_MANUAL:
1393 kprintf("Manual )");
1394 break;
1395 case IFM_NONE:
1396 kprintf("None )");
1397 break;
1398 case IFM_10_T:
1399 kprintf("10Base-T )");
1400 break;
1401 case IFM_100_TX:
1402 kprintf("100Base-TX )");
1403 break;
1404 case IFM_1000_SX:
1405 kprintf("1000Base-SX )");
1406 break;
1407 case IFM_1000_T:
1408 kprintf("1000Base-T )");
1409 break;
1410 default:
1411 kprintf("Other )");
1412 break;
1413 }
1414
1415 kprintf(" Global Options: (");
1416 if (mii->mii_media_active & IFM_FDX)
1417 kprintf(" FullDuplex");
1418 if (mii->mii_media_active & IFM_HDX)
1419 kprintf(" HalfDuplex");
1420 if (mii->mii_media_active & IFM_LOOP)
1421 kprintf(" Loopback");
1422 if (mii->mii_media_active & IFM_FLAG0)
1423 kprintf(" Flag0");
1424 if (mii->mii_media_active & IFM_FLAG1)
1425 kprintf(" Flag1");
1426 if (mii->mii_media_active & IFM_FLAG2)
1427 kprintf(" Flag2");
1428 kprintf(" )\n");
1429#endif
1430
1431 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1432
1433 /*
1434 * Set MII or GMII interface based on the speed negotiated
1435 * by the PHY.
1436 */
1437 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1438 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1439 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1440 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1441 } else {
1442 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1443 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1444 }
1445
1446 /*
1447 * Set half or full duplex based on the duplicity negotiated
1448 * by the PHY.
1449 */
1450 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1451 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1452 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1453 } else {
1454 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1455 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1456 }
1457}
1458
1459
1460/****************************************************************************/
1461/* Acquire NVRAM lock. */
1462/* */
1463/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1464/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1465/* for use by the driver. */
1466/* */
1467/* Returns: */
1468/* 0 on success, positive value on failure. */
1469/****************************************************************************/
1470static int
1471bce_acquire_nvram_lock(struct bce_softc *sc)
1472{
1473 uint32_t val;
1474 int j;
1475
1476 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1477
1478 /* Request access to the flash interface. */
1479 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1480 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1481 val = REG_RD(sc, BCE_NVM_SW_ARB);
1482 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1483 break;
1484
1485 DELAY(5);
1486 }
1487
1488 if (j >= NVRAM_TIMEOUT_COUNT) {
1489 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1490 return EBUSY;
1491 }
1492 return 0;
1493}
1494
1495
1496/****************************************************************************/
1497/* Release NVRAM lock. */
1498/* */
1499/* When the caller is finished accessing NVRAM the lock must be released. */
1500/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1501/* for use by the driver. */
1502/* */
1503/* Returns: */
1504/* 0 on success, positive value on failure. */
1505/****************************************************************************/
1506static int
1507bce_release_nvram_lock(struct bce_softc *sc)
1508{
1509 int j;
1510 uint32_t val;
1511
1512 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1513
1514 /*
1515 * Relinquish nvram interface.
1516 */
1517 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1518
1519 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1520 val = REG_RD(sc, BCE_NVM_SW_ARB);
1521 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1522 break;
1523
1524 DELAY(5);
1525 }
1526
1527 if (j >= NVRAM_TIMEOUT_COUNT) {
1528 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1529 return EBUSY;
1530 }
1531 return 0;
1532}
1533
1534
43c2aeb0
SZ
1535/****************************************************************************/
1536/* Enable NVRAM access. */
1537/* */
1538/* Before accessing NVRAM for read or write operations the caller must */
1539/* enabled NVRAM access. */
1540/* */
1541/* Returns: */
1542/* Nothing. */
1543/****************************************************************************/
1544static void
1545bce_enable_nvram_access(struct bce_softc *sc)
1546{
1547 uint32_t val;
1548
1549 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1550
1551 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1552 /* Enable both bits, even on read. */
1553 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1554 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1555}
1556
1557
1558/****************************************************************************/
1559/* Disable NVRAM access. */
1560/* */
1561/* When the caller is finished accessing NVRAM access must be disabled. */
1562/* */
1563/* Returns: */
1564/* Nothing. */
1565/****************************************************************************/
1566static void
1567bce_disable_nvram_access(struct bce_softc *sc)
1568{
1569 uint32_t val;
1570
1571 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1572
1573 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1574
1575 /* Disable both bits, even after read. */
1576 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1577 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1578}
1579
1580
43c2aeb0
SZ
1581/****************************************************************************/
1582/* Read a dword (32 bits) from NVRAM. */
1583/* */
1584/* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1585/* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1586/* */
1587/* Returns: */
1588/* 0 on success and the 32 bit value read, positive value on failure. */
1589/****************************************************************************/
1590static int
1591bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1592 uint32_t cmd_flags)
1593{
1594 uint32_t cmd;
1595 int i, rc = 0;
1596
1597 /* Build the command word. */
1598 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1599
1600 /* Calculate the offset for buffered flash. */
d0092544 1601 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
43c2aeb0
SZ
1602 offset = ((offset / sc->bce_flash_info->page_size) <<
1603 sc->bce_flash_info->page_bits) +
1604 (offset % sc->bce_flash_info->page_size);
1605 }
1606
1607 /*
1608 * Clear the DONE bit separately, set the address to read,
1609 * and issue the read.
1610 */
1611 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1612 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1613 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1614
1615 /* Wait for completion. */
1616 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1617 uint32_t val;
1618
1619 DELAY(5);
1620
1621 val = REG_RD(sc, BCE_NVM_COMMAND);
1622 if (val & BCE_NVM_COMMAND_DONE) {
1623 val = REG_RD(sc, BCE_NVM_READ);
1624
1625 val = be32toh(val);
1626 memcpy(ret_val, &val, 4);
1627 break;
1628 }
1629 }
1630
1631 /* Check for errors. */
1632 if (i >= NVRAM_TIMEOUT_COUNT) {
1633 if_printf(&sc->arpcom.ac_if,
1634 "Timeout error reading NVRAM at offset 0x%08X!\n",
1635 offset);
1636 rc = EBUSY;
1637 }
1638 return rc;
1639}
1640
1641
43c2aeb0
SZ
1642/****************************************************************************/
1643/* Initialize NVRAM access. */
1644/* */
1645/* Identify the NVRAM device in use and prepare the NVRAM interface to */
1646/* access that device. */
1647/* */
1648/* Returns: */
1649/* 0 on success, positive value on failure. */
1650/****************************************************************************/
1651static int
1652bce_init_nvram(struct bce_softc *sc)
1653{
1654 uint32_t val;
1655 int j, entry_count, rc = 0;
1656 const struct flash_spec *flash;
1657
1658 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1659
d0092544
SZ
1660 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1661 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1662 sc->bce_flash_info = &flash_5709;
1663 goto bce_init_nvram_get_flash_size;
1664 }
1665
43c2aeb0
SZ
1666 /* Determine the selected interface. */
1667 val = REG_RD(sc, BCE_NVM_CFG1);
1668
1669 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1670
1671 /*
1672 * Flash reconfiguration is required to support additional
1673 * NVRAM devices not directly supported in hardware.
1674 * Check if the flash interface was reconfigured
1675 * by the bootcode.
1676 */
1677
1678 if (val & 0x40000000) {
1679 /* Flash interface reconfigured by bootcode. */
1680
1681 DBPRINT(sc, BCE_INFO_LOAD,
1682 "%s(): Flash WAS reconfigured.\n", __func__);
1683
1684 for (j = 0, flash = flash_table; j < entry_count;
1685 j++, flash++) {
1686 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1687 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1688 sc->bce_flash_info = flash;
1689 break;
1690 }
1691 }
1692 } else {
1693 /* Flash interface not yet reconfigured. */
1694 uint32_t mask;
1695
1696 DBPRINT(sc, BCE_INFO_LOAD,
1697 "%s(): Flash was NOT reconfigured.\n", __func__);
1698
1699 if (val & (1 << 23))
1700 mask = FLASH_BACKUP_STRAP_MASK;
1701 else
1702 mask = FLASH_STRAP_MASK;
1703
1704 /* Look for the matching NVRAM device configuration data. */
1705 for (j = 0, flash = flash_table; j < entry_count;
1706 j++, flash++) {
1707 /* Check if the device matches any of the known devices. */
1708 if ((val & mask) == (flash->strapping & mask)) {
1709 /* Found a device match. */
1710 sc->bce_flash_info = flash;
1711
1712 /* Request access to the flash interface. */
1713 rc = bce_acquire_nvram_lock(sc);
1714 if (rc != 0)
1715 return rc;
1716
1717 /* Reconfigure the flash interface. */
1718 bce_enable_nvram_access(sc);
1719 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1720 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1721 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1722 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1723 bce_disable_nvram_access(sc);
1724 bce_release_nvram_lock(sc);
1725 break;
1726 }
1727 }
1728 }
1729
1730 /* Check if a matching device was found. */
1731 if (j == entry_count) {
1732 sc->bce_flash_info = NULL;
1733 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
d819a615 1734 return ENODEV;
43c2aeb0
SZ
1735 }
1736
d0092544 1737bce_init_nvram_get_flash_size:
43c2aeb0 1738 /* Write the flash config data to the shared memory interface. */
bc30d40d
SZ
1739 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1740 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
43c2aeb0
SZ
1741 if (val)
1742 sc->bce_flash_size = val;
1743 else
1744 sc->bce_flash_size = sc->bce_flash_info->total_size;
1745
1746 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1747 __func__, sc->bce_flash_info->total_size);
1748
1749 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1750
1751 return rc;
1752}
1753
1754
1755/****************************************************************************/
1756/* Read an arbitrary range of data from NVRAM. */
1757/* */
1758/* Prepares the NVRAM interface for access and reads the requested data */
1759/* into the supplied buffer. */
1760/* */
1761/* Returns: */
1762/* 0 on success and the data read, positive value on failure. */
1763/****************************************************************************/
1764static int
1765bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1766 int buf_size)
1767{
1768 uint32_t cmd_flags, offset32, len32, extra;
1769 int rc = 0;
1770
1771 if (buf_size == 0)
1772 return 0;
1773
1774 /* Request access to the flash interface. */
1775 rc = bce_acquire_nvram_lock(sc);
1776 if (rc != 0)
1777 return rc;
1778
1779 /* Enable access to flash interface */
1780 bce_enable_nvram_access(sc);
1781
1782 len32 = buf_size;
1783 offset32 = offset;
1784 extra = 0;
1785
1786 cmd_flags = 0;
1787
1788 /* XXX should we release nvram lock if read_dword() fails? */
1789 if (offset32 & 3) {
1790 uint8_t buf[4];
1791 uint32_t pre_len;
1792
1793 offset32 &= ~3;
1794 pre_len = 4 - (offset & 3);
1795
1796 if (pre_len >= len32) {
1797 pre_len = len32;
1798 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1799 } else {
1800 cmd_flags = BCE_NVM_COMMAND_FIRST;
1801 }
1802
1803 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1804 if (rc)
1805 return rc;
1806
1807 memcpy(ret_buf, buf + (offset & 3), pre_len);
1808
1809 offset32 += 4;
1810 ret_buf += pre_len;
1811 len32 -= pre_len;
1812 }
1813
1814 if (len32 & 3) {
1815 extra = 4 - (len32 & 3);
1816 len32 = (len32 + 4) & ~3;
1817 }
1818
1819 if (len32 == 4) {
1820 uint8_t buf[4];
1821
1822 if (cmd_flags)
1823 cmd_flags = BCE_NVM_COMMAND_LAST;
1824 else
1825 cmd_flags = BCE_NVM_COMMAND_FIRST |
1826 BCE_NVM_COMMAND_LAST;
1827
1828 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1829
1830 memcpy(ret_buf, buf, 4 - extra);
1831 } else if (len32 > 0) {
1832 uint8_t buf[4];
1833
1834 /* Read the first word. */
1835 if (cmd_flags)
1836 cmd_flags = 0;
1837 else
1838 cmd_flags = BCE_NVM_COMMAND_FIRST;
1839
1840 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1841
1842 /* Advance to the next dword. */
1843 offset32 += 4;
1844 ret_buf += 4;
1845 len32 -= 4;
1846
1847 while (len32 > 4 && rc == 0) {
1848 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1849
1850 /* Advance to the next dword. */
1851 offset32 += 4;
1852 ret_buf += 4;
1853 len32 -= 4;
1854 }
1855
1856 if (rc)
d0092544 1857 goto bce_nvram_read_locked_exit;
43c2aeb0
SZ
1858
1859 cmd_flags = BCE_NVM_COMMAND_LAST;
1860 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1861
1862 memcpy(ret_buf, buf, 4 - extra);
1863 }
1864
d0092544 1865bce_nvram_read_locked_exit:
43c2aeb0
SZ
1866 /* Disable access to flash interface and release the lock. */
1867 bce_disable_nvram_access(sc);
1868 bce_release_nvram_lock(sc);
1869
1870 return rc;
1871}
1872
1873
43c2aeb0
SZ
1874/****************************************************************************/
1875/* Verifies that NVRAM is accessible and contains valid data. */
1876/* */
1877/* Reads the configuration data from NVRAM and verifies that the CRC is */
1878/* correct. */
1879/* */
1880/* Returns: */
1881/* 0 on success, positive value on failure. */
1882/****************************************************************************/
1883static int
1884bce_nvram_test(struct bce_softc *sc)
1885{
1886 uint32_t buf[BCE_NVRAM_SIZE / 4];
1887 uint32_t magic, csum;
1888 uint8_t *data = (uint8_t *)buf;
1889 int rc = 0;
1890
1891 /*
1892 * Check that the device NVRAM is valid by reading
1893 * the magic value at offset 0.
1894 */
1895 rc = bce_nvram_read(sc, 0, data, 4);
1896 if (rc != 0)
1897 return rc;
1898
1899 magic = be32toh(buf[0]);
1900 if (magic != BCE_NVRAM_MAGIC) {
1901 if_printf(&sc->arpcom.ac_if,
1902 "Invalid NVRAM magic value! Expected: 0x%08X, "
1903 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1904 return ENODEV;
1905 }
1906
1907 /*
1908 * Verify that the device NVRAM includes valid
1909 * configuration data.
1910 */
1911 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1912 if (rc != 0)
1913 return rc;
1914
1915 csum = ether_crc32_le(data, 0x100);
1916 if (csum != BCE_CRC32_RESIDUAL) {
1917 if_printf(&sc->arpcom.ac_if,
1918 "Invalid Manufacturing Information NVRAM CRC! "
1919 "Expected: 0x%08X, Found: 0x%08X\n",
1920 BCE_CRC32_RESIDUAL, csum);
1921 return ENODEV;
1922 }
1923
1924 csum = ether_crc32_le(data + 0x100, 0x100);
1925 if (csum != BCE_CRC32_RESIDUAL) {
1926 if_printf(&sc->arpcom.ac_if,
1927 "Invalid Feature Configuration Information "
1928 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1929 BCE_CRC32_RESIDUAL, csum);
1930 rc = ENODEV;
1931 }
1932 return rc;
1933}
1934
1935
1936/****************************************************************************/
d0092544
SZ
1937/* Identifies the current media type of the controller and sets the PHY */
1938/* address. */
1939/* */
1940/* Returns: */
1941/* Nothing. */
1942/****************************************************************************/
1943static void
1944bce_get_media(struct bce_softc *sc)
1945{
1946 uint32_t val;
1947
1948 sc->bce_phy_addr = 1;
1949
1950 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1951 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1952 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1953 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1954 uint32_t strap;
1955
1956 /*
1957 * The BCM5709S is software configurable
1958 * for Copper or SerDes operation.
1959 */
1960 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1961 return;
1962 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1963 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1964 return;
1965 }
1966
1967 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1968 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1969 } else {
1970 strap =
1971 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1972 }
1973
1974 if (pci_get_function(sc->bce_dev) == 0) {
1975 switch (strap) {
1976 case 0x4:
1977 case 0x5:
1978 case 0x6:
1979 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1980 break;
1981 }
1982 } else {
1983 switch (strap) {
1984 case 0x1:
1985 case 0x2:
1986 case 0x4:
1987 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1988 break;
1989 }
1990 }
1991 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1992 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1993 }
1994
1995 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1996 sc->bce_flags |= BCE_NO_WOL_FLAG;
1997 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1998 sc->bce_phy_addr = 2;
bc30d40d 1999 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
d0092544
SZ
2000 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2001 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2002 }
2003 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2004 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2005 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2006 }
2007}
2008
2009
2010/****************************************************************************/
43c2aeb0
SZ
2011/* Free any DMA memory owned by the driver. */
2012/* */
2013/* Scans through each data structre that requires DMA memory and frees */
2014/* the memory if allocated. */
2015/* */
2016/* Returns: */
2017/* Nothing. */
2018/****************************************************************************/
2019static void
2020bce_dma_free(struct bce_softc *sc)
2021{
2022 int i;
2023
2024 /* Destroy the status block. */
2025 if (sc->status_tag != NULL) {
2026 if (sc->status_block != NULL) {
2027 bus_dmamap_unload(sc->status_tag, sc->status_map);
2028 bus_dmamem_free(sc->status_tag, sc->status_block,
2029 sc->status_map);
2030 }
2031 bus_dma_tag_destroy(sc->status_tag);
2032 }
2033
2034
2035 /* Destroy the statistics block. */
2036 if (sc->stats_tag != NULL) {
2037 if (sc->stats_block != NULL) {
2038 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2039 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2040 sc->stats_map);
2041 }
2042 bus_dma_tag_destroy(sc->stats_tag);
2043 }
2044
d0092544
SZ
2045 /* Destroy the CTX DMA stuffs. */
2046 if (sc->ctx_tag != NULL) {
2047 for (i = 0; i < sc->ctx_pages; i++) {
2048 if (sc->ctx_block[i] != NULL) {
2049 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2050 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2051 sc->ctx_map[i]);
2052 }
2053 }
2054 bus_dma_tag_destroy(sc->ctx_tag);
2055 }
2056
43c2aeb0
SZ
2057 /* Destroy the TX buffer descriptor DMA stuffs. */
2058 if (sc->tx_bd_chain_tag != NULL) {
2059 for (i = 0; i < TX_PAGES; i++) {
2060 if (sc->tx_bd_chain[i] != NULL) {
2061 bus_dmamap_unload(sc->tx_bd_chain_tag,
2062 sc->tx_bd_chain_map[i]);
2063 bus_dmamem_free(sc->tx_bd_chain_tag,
2064 sc->tx_bd_chain[i],
2065 sc->tx_bd_chain_map[i]);
2066 }
2067 }
2068 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2069 }
2070
2071 /* Destroy the RX buffer descriptor DMA stuffs. */
2072 if (sc->rx_bd_chain_tag != NULL) {
2073 for (i = 0; i < RX_PAGES; i++) {
2074 if (sc->rx_bd_chain[i] != NULL) {
2075 bus_dmamap_unload(sc->rx_bd_chain_tag,
2076 sc->rx_bd_chain_map[i]);
2077 bus_dmamem_free(sc->rx_bd_chain_tag,
2078 sc->rx_bd_chain[i],
2079 sc->rx_bd_chain_map[i]);
2080 }
2081 }
2082 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2083 }
2084
2085 /* Destroy the TX mbuf DMA stuffs. */
2086 if (sc->tx_mbuf_tag != NULL) {
2087 for (i = 0; i < TOTAL_TX_BD; i++) {
2088 /* Must have been unloaded in bce_stop() */
2089 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2090 bus_dmamap_destroy(sc->tx_mbuf_tag,
2091 sc->tx_mbuf_map[i]);
2092 }
2093 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2094 }
2095
2096 /* Destroy the RX mbuf DMA stuffs. */
2097 if (sc->rx_mbuf_tag != NULL) {
2098 for (i = 0; i < TOTAL_RX_BD; i++) {
2099 /* Must have been unloaded in bce_stop() */
2100 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2101 bus_dmamap_destroy(sc->rx_mbuf_tag,
2102 sc->rx_mbuf_map[i]);
2103 }
c36fd9ee 2104 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
43c2aeb0
SZ
2105 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2106 }
2107
2108 /* Destroy the parent tag */
2109 if (sc->parent_tag != NULL)
2110 bus_dma_tag_destroy(sc->parent_tag);
2111}
2112
2113
2114/****************************************************************************/
2115/* Get DMA memory from the OS. */
2116/* */
2117/* Validates that the OS has provided DMA buffers in response to a */
2118/* bus_dmamap_load() call and saves the physical address of those buffers. */
2119/* When the callback is used the OS will return 0 for the mapping function */
2120/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2121/* failures back to the caller. */
2122/* */
2123/* Returns: */
2124/* Nothing. */
2125/****************************************************************************/
2126static void
2127bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2128{
2129 bus_addr_t *busaddr = arg;
2130
2131 /*
2132 * Simulate a mapping failure.
2133 * XXX not correct.
2134 */
2135 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2136 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2137 __FILE__, __LINE__);
2138 error = ENOMEM);
2139
2140 /* Check for an error and signal the caller that an error occurred. */
2141 if (error)
2142 return;
2143
2144 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2145 *busaddr = segs->ds_addr;
2146}
2147
2148
43c2aeb0
SZ
2149/****************************************************************************/
2150/* Allocate any DMA memory needed by the driver. */
2151/* */
2152/* Allocates DMA memory needed for the various global structures needed by */
2153/* hardware. */
2154/* */
cffea833 2155/* Memory alignment requirements: */
d0092544
SZ
2156/* -----------------+----------+----------+----------+----------+ */
2157/* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2158/* -----------------+----------+----------+----------+----------+ */
2159/* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2160/* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2161/* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2162/* PG Buffers | none | none | none | none | */
2163/* TX Buffers | none | none | none | none | */
2164/* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2165/* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2166/* -----------------+----------+----------+----------+----------+ */
cffea833
SZ
2167/* */
2168/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2169/* */
43c2aeb0
SZ
2170/* Returns: */
2171/* 0 for success, positive value for failure. */
2172/****************************************************************************/
2173static int
2174bce_dma_alloc(struct bce_softc *sc)
2175{
2176 struct ifnet *ifp = &sc->arpcom.ac_if;
2177 int i, j, rc = 0;
d0092544
SZ
2178 bus_addr_t busaddr, max_busaddr;
2179 bus_size_t status_align, stats_align;
2180
2181 /*
2182 * The embedded PCIe to PCI-X bridge (EPB)
2183 * in the 5708 cannot address memory above
2184 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2185 */
2186 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2187 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2188 else
2189 max_busaddr = BUS_SPACE_MAXADDR;
2190
2191 /*
2192 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2193 */
2194 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2195 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2196 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2197 if (sc->ctx_pages == 0)
2198 sc->ctx_pages = 1;
2199 if (sc->ctx_pages > BCE_CTX_PAGES) {
2200 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2201 sc->ctx_pages);
2202 return ENOMEM;
2203 }
2204 status_align = 16;
2205 stats_align = 16;
2206 } else {
2207 status_align = 8;
2208 stats_align = 8;
2209 }
43c2aeb0
SZ
2210
2211 /*
2212 * Allocate the parent bus DMA tag appropriate for PCI.
2213 */
2214 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
d0092544 2215 max_busaddr, BUS_SPACE_MAXADDR,
43c2aeb0 2216 NULL, NULL,
45010e4d 2217 BUS_SPACE_MAXSIZE_32BIT, 0,
43c2aeb0
SZ
2218 BUS_SPACE_MAXSIZE_32BIT,
2219 0, &sc->parent_tag);
2220 if (rc != 0) {
2221 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2222 return rc;
2223 }
2224
2225 /*
4a458e9d 2226 * Allocate status block.
43c2aeb0 2227 */
4a458e9d 2228 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2229 status_align, BCE_STATUS_BLK_SZ,
4a458e9d
SZ
2230 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2231 &sc->status_tag, &sc->status_map,
2232 &sc->status_block_paddr);
2233 if (sc->status_block == NULL) {
2234 if_printf(ifp, "Could not allocate status block!\n");
2235 return ENOMEM;
43c2aeb0
SZ
2236 }
2237
43c2aeb0 2238 /*
4a458e9d 2239 * Allocate statistics block.
43c2aeb0 2240 */
4a458e9d 2241 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
d0092544 2242 stats_align, BCE_STATS_BLK_SZ,
4a458e9d
SZ
2243 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2244 &sc->stats_tag, &sc->stats_map,
2245 &sc->stats_block_paddr);
2246 if (sc->stats_block == NULL) {
2247 if_printf(ifp, "Could not allocate statistics block!\n");
2248 return ENOMEM;
43c2aeb0
SZ
2249 }
2250
43c2aeb0 2251 /*
d0092544
SZ
2252 * Allocate context block, if needed
2253 */
2254 if (sc->ctx_pages != 0) {
2255 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2256 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2257 NULL, NULL,
2258 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2259 0, &sc->ctx_tag);
2260 if (rc != 0) {
2261 if_printf(ifp, "Could not allocate "
2262 "context block DMA tag!\n");
2263 return rc;
2264 }
2265
2266 for (i = 0; i < sc->ctx_pages; i++) {
2267 rc = bus_dmamem_alloc(sc->ctx_tag,
2268 (void **)&sc->ctx_block[i],
2269 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2270 BUS_DMA_COHERENT,
2271 &sc->ctx_map[i]);
2272 if (rc != 0) {
2273 if_printf(ifp, "Could not allocate %dth context "
2274 "DMA memory!\n", i);
2275 return rc;
2276 }
2277
2278 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2279 sc->ctx_block[i], BCM_PAGE_SIZE,
2280 bce_dma_map_addr, &busaddr,
2281 BUS_DMA_WAITOK);
2282 if (rc != 0) {
2283 if (rc == EINPROGRESS) {
2284 panic("%s coherent memory loading "
2285 "is still in progress!", ifp->if_xname);
2286 }
2287 if_printf(ifp, "Could not map %dth context "
2288 "DMA memory!\n", i);
2289 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2290 sc->ctx_map[i]);
2291 sc->ctx_block[i] = NULL;
2292 return rc;
2293 }
2294 sc->ctx_paddr[i] = busaddr;
2295 }
2296 }
2297
2298 /*
43c2aeb0
SZ
2299 * Create a DMA tag for the TX buffer descriptor chain,
2300 * allocate and clear the memory, and fetch the
2301 * physical address of the block.
2302 */
4a458e9d
SZ
2303 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2304 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ
2305 NULL, NULL,
2306 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2307 0, &sc->tx_bd_chain_tag);
2308 if (rc != 0) {
2309 if_printf(ifp, "Could not allocate "
2310 "TX descriptor chain DMA tag!\n");
2311 return rc;
2312 }
2313
2314 for (i = 0; i < TX_PAGES; i++) {
2315 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2316 (void **)&sc->tx_bd_chain[i],
4a458e9d
SZ
2317 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2318 BUS_DMA_COHERENT,
2319 &sc->tx_bd_chain_map[i]);
43c2aeb0
SZ
2320 if (rc != 0) {
2321 if_printf(ifp, "Could not allocate %dth TX descriptor "
2322 "chain DMA memory!\n", i);
2323 return rc;
2324 }
2325
2326 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2327 sc->tx_bd_chain_map[i],
2328 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2329 bce_dma_map_addr, &busaddr,
2330 BUS_DMA_WAITOK);
2331 if (rc != 0) {
4a458e9d
SZ
2332 if (rc == EINPROGRESS) {
2333 panic("%s coherent memory loading "
2334 "is still in progress!", ifp->if_xname);
2335 }
43c2aeb0
SZ
2336 if_printf(ifp, "Could not map %dth TX descriptor "
2337 "chain DMA memory!\n", i);
2338 bus_dmamem_free(sc->tx_bd_chain_tag,
2339 sc->tx_bd_chain[i],
2340 sc->tx_bd_chain_map[i]);
2341 sc->tx_bd_chain[i] = NULL;
2342 return rc;
2343 }
2344
2345 sc->tx_bd_chain_paddr[i] = busaddr;
2346 /* DRC - Fix for 64 bit systems. */
2347 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2348 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2349 }
2350
2351 /* Create a DMA tag for TX mbufs. */
45010e4d
SZ
2352 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2353 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2354 NULL, NULL,
45010e4d 2355 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
43c2aeb0 2356 BCE_MAX_SEGMENTS, MCLBYTES,
45010e4d
SZ
2357 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2358 BUS_DMA_ONEBPAGE,
2359 &sc->tx_mbuf_tag);
43c2aeb0
SZ
2360 if (rc != 0) {
2361 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2362 return rc;
2363 }
2364
2365 /* Create DMA maps for the TX mbufs clusters. */
2366 for (i = 0; i < TOTAL_TX_BD; i++) {
45010e4d
SZ
2367 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2368 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
43c2aeb0
SZ
2369 &sc->tx_mbuf_map[i]);
2370 if (rc != 0) {
2371 for (j = 0; j < i; ++j) {
2372 bus_dmamap_destroy(sc->tx_mbuf_tag,
2373 sc->tx_mbuf_map[i]);
2374 }
2375 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2376 sc->tx_mbuf_tag = NULL;
2377
2378 if_printf(ifp, "Unable to create "
2379 "%dth TX mbuf DMA map!\n", i);
2380 return rc;
2381 }
2382 }
2383
2384 /*
2385 * Create a DMA tag for the RX buffer descriptor chain,
2386 * allocate and clear the memory, and fetch the physical
2387 * address of the blocks.
2388 */
4a458e9d
SZ
2389 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2390 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0
SZ
2391 NULL, NULL,
2392 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2393 0, &sc->rx_bd_chain_tag);
2394 if (rc != 0) {
2395 if_printf(ifp, "Could not allocate "
2396 "RX descriptor chain DMA tag!\n");
2397 return rc;
2398 }
2399
2400 for (i = 0; i < RX_PAGES; i++) {
2401 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2402 (void **)&sc->rx_bd_chain[i],
4a458e9d
SZ
2403 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2404 BUS_DMA_COHERENT,
43c2aeb0
SZ
2405 &sc->rx_bd_chain_map[i]);
2406 if (rc != 0) {
2407 if_printf(ifp, "Could not allocate %dth RX descriptor "
2408 "chain DMA memory!\n", i);
2409 return rc;
2410 }
2411
2412 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2413 sc->rx_bd_chain_map[i],
2414 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2415 bce_dma_map_addr, &busaddr,
2416 BUS_DMA_WAITOK);
2417 if (rc != 0) {
4a458e9d
SZ
2418 if (rc == EINPROGRESS) {
2419 panic("%s coherent memory loading "
2420 "is still in progress!", ifp->if_xname);
2421 }
43c2aeb0
SZ
2422 if_printf(ifp, "Could not map %dth RX descriptor "
2423 "chain DMA memory!\n", i);
2424 bus_dmamem_free(sc->rx_bd_chain_tag,
2425 sc->rx_bd_chain[i],
2426 sc->rx_bd_chain_map[i]);
2427 sc->rx_bd_chain[i] = NULL;
2428 return rc;
2429 }
2430
2431 sc->rx_bd_chain_paddr[i] = busaddr;
2432 /* DRC - Fix for 64 bit systems. */
2433 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2434 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2435 }
2436
2437 /* Create a DMA tag for RX mbufs. */
cffea833 2438 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
45010e4d 2439 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
43c2aeb0 2440 NULL, NULL,
45010e4d 2441 MCLBYTES, 1, MCLBYTES,
cffea833
SZ
2442 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2443 BUS_DMA_WAITOK,
45010e4d 2444 &sc->rx_mbuf_tag);
43c2aeb0
SZ
2445 if (rc != 0) {
2446 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2447 return rc;
2448 }
2449
c36fd9ee
SZ
2450 /* Create tmp DMA map for RX mbuf clusters. */
2451 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2452 &sc->rx_mbuf_tmpmap);
2453 if (rc != 0) {
2454 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2455 sc->rx_mbuf_tag = NULL;
2456
2457 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2458 return rc;
2459 }
2460
43c2aeb0
SZ
2461 /* Create DMA maps for the RX mbuf clusters. */
2462 for (i = 0; i < TOTAL_RX_BD; i++) {
2463 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2464 &sc->rx_mbuf_map[i]);
2465 if (rc != 0) {
2466 for (j = 0; j < i; ++j) {
2467 bus_dmamap_destroy(sc->rx_mbuf_tag,
2468 sc->rx_mbuf_map[j]);
2469 }
2470 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2471 sc->rx_mbuf_tag = NULL;
2472
2473 if_printf(ifp, "Unable to create "
2474 "%dth RX mbuf DMA map!\n", i);
2475 return rc;
2476 }
2477 }
2478 return 0;
2479}
2480
2481
2482/****************************************************************************/
2483/* Firmware synchronization. */
2484/* */
2485/* Before performing certain events such as a chip reset, synchronize with */
2486/* the firmware first. */
2487/* */
2488/* Returns: */
2489/* 0 for success, positive value for failure. */
2490/****************************************************************************/
2491static int
2492bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2493{
2494 int i, rc = 0;
2495 uint32_t val;
2496
2497 /* Don't waste any time if we've timed out before. */
2498 if (sc->bce_fw_timed_out)
2499 return EBUSY;
2500
2501 /* Increment the message sequence number. */
2502 sc->bce_fw_wr_seq++;
2503 msg_data |= sc->bce_fw_wr_seq;
2504
2505 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2506
2507 /* Send the message to the bootcode driver mailbox. */
bc30d40d 2508 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ
2509
2510 /* Wait for the bootcode to acknowledge the message. */
2511 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2512 /* Check for a response in the bootcode firmware mailbox. */
bc30d40d 2513 val = bce_shmem_rd(sc, BCE_FW_MB);
43c2aeb0
SZ
2514 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2515 break;
2516 DELAY(1000);
2517 }
2518
2519 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2520 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2521 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2522 if_printf(&sc->arpcom.ac_if,
2523 "Firmware synchronization timeout! "
2524 "msg_data = 0x%08X\n", msg_data);
2525
2526 msg_data &= ~BCE_DRV_MSG_CODE;
2527 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2528
bc30d40d 2529 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
43c2aeb0
SZ
2530
2531 sc->bce_fw_timed_out = 1;
2532 rc = EBUSY;
2533 }
2534 return rc;
2535}
2536
2537
2538/****************************************************************************/
2539/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2540/* */
2541/* Returns: */
2542/* Nothing. */
2543/****************************************************************************/
2544static void
2545bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2546 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2547{
2548 int i;
2549 uint32_t val;
2550
2551 for (i = 0; i < rv2p_code_len; i += 8) {
2552 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2553 rv2p_code++;
2554 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2555 rv2p_code++;
2556
2557 if (rv2p_proc == RV2P_PROC1) {
2558 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2559 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2560 } else {
2561 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2562 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2563 }
2564 }
2565
2566 /* Reset the processor, un-stall is done later. */
2567 if (rv2p_proc == RV2P_PROC1)
2568 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2569 else
2570 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2571}
2572
2573
2574/****************************************************************************/
2575/* Load RISC processor firmware. */
2576/* */
2577/* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2578/* associated with a particular processor. */
2579/* */
2580/* Returns: */
2581/* Nothing. */
2582/****************************************************************************/
2583static void
2584bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2585 struct fw_info *fw)
2586{
5d05a208 2587 uint32_t offset;
43c2aeb0
SZ
2588 int j;
2589
5d05a208 2590 bce_halt_cpu(sc, cpu_reg);
43c2aeb0
SZ
2591
2592 /* Load the Text area. */
2593 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2594 if (fw->text) {
2595 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2596 REG_WR_IND(sc, offset, fw->text[j]);
2597 }
2598
2599 /* Load the Data area. */
2600 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2601 if (fw->data) {
2602 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2603 REG_WR_IND(sc, offset, fw->data[j]);
2604 }
2605
2606 /* Load the SBSS area. */
2607 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2608 if (fw->sbss) {
2609 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2610 REG_WR_IND(sc, offset, fw->sbss[j]);
2611 }
2612
2613 /* Load the BSS area. */
2614 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2615 if (fw->bss) {
2616 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2617 REG_WR_IND(sc, offset, fw->bss[j]);
2618 }
2619
2620 /* Load the Read-Only area. */
2621 offset = cpu_reg->spad_base +
2622 (fw->rodata_addr - cpu_reg->mips_view_base);
2623 if (fw->rodata) {
2624 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2625 REG_WR_IND(sc, offset, fw->rodata[j]);
2626 }
2627
5d05a208 2628 /* Clear the pre-fetch instruction and set the FW start address. */
43c2aeb0
SZ
2629 REG_WR_IND(sc, cpu_reg->inst, 0);
2630 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
5d05a208
SZ
2631}
2632
2633
2634/****************************************************************************/
2635/* Starts the RISC processor. */
2636/* */
2637/* Assumes the CPU starting address has already been set. */
2638/* */
2639/* Returns: */
2640/* Nothing. */
2641/****************************************************************************/
2642static void
2643bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2644{
2645 uint32_t val;
43c2aeb0
SZ
2646
2647 /* Start the CPU. */
2648 val = REG_RD_IND(sc, cpu_reg->mode);
2649 val &= ~cpu_reg->mode_value_halt;
2650 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2651 REG_WR_IND(sc, cpu_reg->mode, val);
2652}
2653
2654
2655/****************************************************************************/
5d05a208
SZ
2656/* Halts the RISC processor. */
2657/* */
2658/* Returns: */
2659/* Nothing. */
2660/****************************************************************************/
2661static void
2662bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2663{
2664 uint32_t val;
2665
2666 /* Halt the CPU. */
2667 val = REG_RD_IND(sc, cpu_reg->mode);
2668 val |= cpu_reg->mode_value_halt;
2669 REG_WR_IND(sc, cpu_reg->mode, val);
2670 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2671}
2672
2673
2674/****************************************************************************/
2675/* Start the RX CPU. */
2676/* */
2677/* Returns: */
2678/* Nothing. */
2679/****************************************************************************/
2680static void
2681bce_start_rxp_cpu(struct bce_softc *sc)
2682{
2683 struct cpu_reg cpu_reg;
2684
2685 cpu_reg.mode = BCE_RXP_CPU_MODE;
2686 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2687 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2688 cpu_reg.state = BCE_RXP_CPU_STATE;
2689 cpu_reg.state_value_clear = 0xffffff;
2690 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2691 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2692 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2693 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2694 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2695 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2696 cpu_reg.mips_view_base = 0x8000000;
2697
2698 bce_start_cpu(sc, &cpu_reg);
2699}
2700
2701
2702/****************************************************************************/
d0092544 2703/* Initialize the RX CPU. */
43c2aeb0
SZ
2704/* */
2705/* Returns: */
2706/* Nothing. */
2707/****************************************************************************/
2708static void
d0092544 2709bce_init_rxp_cpu(struct bce_softc *sc)
43c2aeb0
SZ
2710{
2711 struct cpu_reg cpu_reg;
2712 struct fw_info fw;
2713
43c2aeb0
SZ
2714 cpu_reg.mode = BCE_RXP_CPU_MODE;
2715 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2716 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2717 cpu_reg.state = BCE_RXP_CPU_STATE;
2718 cpu_reg.state_value_clear = 0xffffff;
2719 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2720 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2721 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2722 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2723 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2724 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2725 cpu_reg.mips_view_base = 0x8000000;
2726
d0092544
SZ
2727 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2728 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2729 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2730 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2731 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2732 fw.start_addr = bce_RXP_b09FwStartAddr;
2733
2734 fw.text_addr = bce_RXP_b09FwTextAddr;
2735 fw.text_len = bce_RXP_b09FwTextLen;
2736 fw.text_index = 0;
2737 fw.text = bce_RXP_b09FwText;
2738
2739 fw.data_addr = bce_RXP_b09FwDataAddr;
2740 fw.data_len = bce_RXP_b09FwDataLen;
2741 fw.data_index = 0;
2742 fw.data = bce_RXP_b09FwData;
2743
2744 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2745 fw.sbss_len = bce_RXP_b09FwSbssLen;
2746 fw.sbss_index = 0;
2747 fw.sbss = bce_RXP_b09FwSbss;
2748
2749 fw.bss_addr = bce_RXP_b09FwBssAddr;
2750 fw.bss_len = bce_RXP_b09FwBssLen;
2751 fw.bss_index = 0;
2752 fw.bss = bce_RXP_b09FwBss;
2753
2754 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2755 fw.rodata_len = bce_RXP_b09FwRodataLen;
2756 fw.rodata_index = 0;
2757 fw.rodata = bce_RXP_b09FwRodata;
2758 } else {
2759 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2760 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2761 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2762 fw.start_addr = bce_RXP_b06FwStartAddr;
2763
2764 fw.text_addr = bce_RXP_b06FwTextAddr;
2765 fw.text_len = bce_RXP_b06FwTextLen;
2766 fw.text_index = 0;
2767 fw.text = bce_RXP_b06FwText;
2768
2769 fw.data_addr = bce_RXP_b06FwDataAddr;
2770 fw.data_len = bce_RXP_b06FwDataLen;
2771 fw.data_index = 0;
2772 fw.data = bce_RXP_b06FwData;
2773
2774 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2775 fw.sbss_len = bce_RXP_b06FwSbssLen;
2776 fw.sbss_index = 0;
2777 fw.sbss = bce_RXP_b06FwSbss;
2778
2779 fw.bss_addr = bce_RXP_b06FwBssAddr;
2780 fw.bss_len = bce_RXP_b06FwBssLen;
2781 fw.bss_index = 0;
2782 fw.bss = bce_RXP_b06FwBss;
2783
2784 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2785 fw.rodata_len = bce_RXP_b06FwRodataLen;
2786 fw.rodata_index = 0;
2787 fw.rodata = bce_RXP_b06FwRodata;
2788 }
43c2aeb0
SZ
2789
2790 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2791 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2792 /* Delay RXP start until initialization is complete. */
d0092544
SZ
2793}
2794
2795
2796/****************************************************************************/
2797/* Initialize the TX CPU. */
2798/* */
2799/* Returns: */
2800/* Nothing. */
2801/****************************************************************************/
2802static void
2803bce_init_txp_cpu(struct bce_softc *sc)
2804{
2805 struct cpu_reg cpu_reg;
2806 struct fw_info fw;
43c2aeb0 2807
43c2aeb0
SZ
2808 cpu_reg.mode = BCE_TXP_CPU_MODE;
2809 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2810 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2811 cpu_reg.state = BCE_TXP_CPU_STATE;
2812 cpu_reg.state_value_clear = 0xffffff;
2813 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2814 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2815 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2816 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2817 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2818 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2819 cpu_reg.mips_view_base = 0x8000000;
2820
d0092544
SZ
2821 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2822 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2823 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2824 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2825 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2826 fw.start_addr = bce_TXP_b09FwStartAddr;
2827
2828 fw.text_addr = bce_TXP_b09FwTextAddr;
2829 fw.text_len = bce_TXP_b09FwTextLen;
2830 fw.text_index = 0;
2831 fw.text = bce_TXP_b09FwText;
2832
2833 fw.data_addr = bce_TXP_b09FwDataAddr;
2834 fw.data_len = bce_TXP_b09FwDataLen;
2835 fw.data_index = 0;
2836 fw.data = bce_TXP_b09FwData;
2837
2838 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2839 fw.sbss_len = bce_TXP_b09FwSbssLen;
2840 fw.sbss_index = 0;
2841 fw.sbss = bce_TXP_b09FwSbss;
2842
2843 fw.bss_addr = bce_TXP_b09FwBssAddr;
2844 fw.bss_len = bce_TXP_b09FwBssLen;
2845 fw.bss_index = 0;
2846 fw.bss = bce_TXP_b09FwBss;
2847
2848 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2849 fw.rodata_len = bce_TXP_b09FwRodataLen;
2850 fw.rodata_index = 0;
2851 fw.rodata = bce_TXP_b09FwRodata;
2852 } else {
2853 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2854 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2855 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2856 fw.start_addr = bce_TXP_b06FwStartAddr;
2857
2858 fw.text_addr = bce_TXP_b06FwTextAddr;
2859 fw.text_len = bce_TXP_b06FwTextLen;
2860 fw.text_index = 0;
2861 fw.text = bce_TXP_b06FwText;
2862
2863 fw.data_addr = bce_TXP_b06FwDataAddr;
2864 fw.data_len = bce_TXP_b06FwDataLen;
2865 fw.data_index = 0;
2866 fw.data = bce_TXP_b06FwData;
2867
2868 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2869 fw.sbss_len = bce_TXP_b06FwSbssLen;
2870 fw.sbss_index = 0;
2871 fw.sbss = bce_TXP_b06FwSbss;
2872
2873 fw.bss_addr = bce_TXP_b06FwBssAddr;
2874 fw.bss_len = bce_TXP_b06FwBssLen;
2875 fw.bss_index = 0;
2876 fw.bss = bce_TXP_b06FwBss;
2877
2878 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2879 fw.rodata_len = bce_TXP_b06FwRodataLen;
2880 fw.rodata_index = 0;
2881 fw.rodata = bce_TXP_b06FwRodata;
2882 }
43c2aeb0
SZ
2883
2884 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2885 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2886 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ
2887}
2888
2889
2890/****************************************************************************/
2891/* Initialize the TPAT CPU. */
2892/* */
2893/* Returns: */
2894/* Nothing. */
2895/****************************************************************************/
2896static void
2897bce_init_tpat_cpu(struct bce_softc *sc)
2898{
2899 struct cpu_reg cpu_reg;
2900 struct fw_info fw;
43c2aeb0 2901
43c2aeb0
SZ
2902 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2903 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2904 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2905 cpu_reg.state = BCE_TPAT_CPU_STATE;
2906 cpu_reg.state_value_clear = 0xffffff;
2907 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2908 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2909 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2910 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2911 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2912 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2913 cpu_reg.mips_view_base = 0x8000000;
2914
d0092544
SZ
2915 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2916 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2917 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2918 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2919 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2920 fw.start_addr = bce_TPAT_b09FwStartAddr;
2921
2922 fw.text_addr = bce_TPAT_b09FwTextAddr;
2923 fw.text_len = bce_TPAT_b09FwTextLen;
2924 fw.text_index = 0;
2925 fw.text = bce_TPAT_b09FwText;
2926
2927 fw.data_addr = bce_TPAT_b09FwDataAddr;
2928 fw.data_len = bce_TPAT_b09FwDataLen;
2929 fw.data_index = 0;
2930 fw.data = bce_TPAT_b09FwData;
2931
2932 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2933 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2934 fw.sbss_index = 0;
2935 fw.sbss = bce_TPAT_b09FwSbss;
2936
2937 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2938 fw.bss_len = bce_TPAT_b09FwBssLen;
2939 fw.bss_index = 0;
2940 fw.bss = bce_TPAT_b09FwBss;
2941
2942 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2943 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2944 fw.rodata_index = 0;
2945 fw.rodata = bce_TPAT_b09FwRodata;
2946 } else {
2947 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2948 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2949 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2950 fw.start_addr = bce_TPAT_b06FwStartAddr;
2951
2952 fw.text_addr = bce_TPAT_b06FwTextAddr;
2953 fw.text_len = bce_TPAT_b06FwTextLen;
2954 fw.text_index = 0;
2955 fw.text = bce_TPAT_b06FwText;
2956
2957 fw.data_addr = bce_TPAT_b06FwDataAddr;
2958 fw.data_len = bce_TPAT_b06FwDataLen;
2959 fw.data_index = 0;
2960 fw.data = bce_TPAT_b06FwData;
2961
2962 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2963 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2964 fw.sbss_index = 0;
2965 fw.sbss = bce_TPAT_b06FwSbss;
2966
2967 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2968 fw.bss_len = bce_TPAT_b06FwBssLen;
2969 fw.bss_index = 0;
2970 fw.bss = bce_TPAT_b06FwBss;
2971
2972 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2973 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2974 fw.rodata_index = 0;
2975 fw.rodata = bce_TPAT_b06FwRodata;
2976 }
43c2aeb0 2977
d0092544
SZ
2978 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2979 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 2980 bce_start_cpu(sc, &cpu_reg);
d0092544 2981}
43c2aeb0 2982
43c2aeb0 2983
d0092544
SZ
2984/****************************************************************************/
2985/* Initialize the CP CPU. */
2986/* */
2987/* Returns: */
2988/* Nothing. */
2989/****************************************************************************/
2990static void
2991bce_init_cp_cpu(struct bce_softc *sc)
2992{
2993 struct cpu_reg cpu_reg;
2994 struct fw_info fw;
43c2aeb0 2995
d0092544
SZ
2996 cpu_reg.mode = BCE_CP_CPU_MODE;
2997 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2998 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2999 cpu_reg.state = BCE_CP_CPU_STATE;
3000 cpu_reg.state_value_clear = 0xffffff;
3001 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3002 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3003 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3004 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3005 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3006 cpu_reg.spad_base = BCE_CP_SCRATCH;
3007 cpu_reg.mips_view_base = 0x8000000;
43c2aeb0 3008
d0092544
SZ
3009 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3010 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3011 fw.ver_major = bce_CP_b09FwReleaseMajor;
3012 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3013 fw.ver_fix = bce_CP_b09FwReleaseFix;
3014 fw.start_addr = bce_CP_b09FwStartAddr;
3015
3016 fw.text_addr = bce_CP_b09FwTextAddr;
3017 fw.text_len = bce_CP_b09FwTextLen;
3018 fw.text_index = 0;
3019 fw.text = bce_CP_b09FwText;
3020
3021 fw.data_addr = bce_CP_b09FwDataAddr;
3022 fw.data_len = bce_CP_b09FwDataLen;
3023 fw.data_index = 0;
3024 fw.data = bce_CP_b09FwData;
3025
3026 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3027 fw.sbss_len = bce_CP_b09FwSbssLen;
3028 fw.sbss_index = 0;
3029 fw.sbss = bce_CP_b09FwSbss;
3030
3031 fw.bss_addr = bce_CP_b09FwBssAddr;
3032 fw.bss_len = bce_CP_b09FwBssLen;
3033 fw.bss_index = 0;
3034 fw.bss = bce_CP_b09FwBss;
3035
3036 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3037 fw.rodata_len = bce_CP_b09FwRodataLen;
3038 fw.rodata_index = 0;
3039 fw.rodata = bce_CP_b09FwRodata;
3040 } else {
3041 fw.ver_major = bce_CP_b06FwReleaseMajor;
3042 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3043 fw.ver_fix = bce_CP_b06FwReleaseFix;
3044 fw.start_addr = bce_CP_b06FwStartAddr;
3045
3046 fw.text_addr = bce_CP_b06FwTextAddr;
3047 fw.text_len = bce_CP_b06FwTextLen;
3048 fw.text_index = 0;
3049 fw.text = bce_CP_b06FwText;
3050
3051 fw.data_addr = bce_CP_b06FwDataAddr;
3052 fw.data_len = bce_CP_b06FwDataLen;
3053 fw.data_index = 0;
3054 fw.data = bce_CP_b06FwData;
3055
3056 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3057 fw.sbss_len = bce_CP_b06FwSbssLen;
3058 fw.sbss_index = 0;
3059 fw.sbss = bce_CP_b06FwSbss;
3060
3061 fw.bss_addr = bce_CP_b06FwBssAddr;
3062 fw.bss_len = bce_CP_b06FwBssLen;
3063 fw.bss_index = 0;
3064 fw.bss = bce_CP_b06FwBss;
3065
3066 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3067 fw.rodata_len = bce_CP_b06FwRodataLen;
3068 fw.rodata_index = 0;
3069 fw.rodata = bce_CP_b06FwRodata;
3070 }
43c2aeb0 3071
d0092544 3072 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
43c2aeb0 3073 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3074 bce_start_cpu(sc, &cpu_reg);
d0092544
SZ
3075}
3076
3077
3078/****************************************************************************/
3079/* Initialize the COM CPU. */
3080/* */
3081/* Returns: */
3082/* Nothing. */
3083/****************************************************************************/
3084static void
3085bce_init_com_cpu(struct bce_softc *sc)
3086{
3087 struct cpu_reg cpu_reg;
3088 struct fw_info fw;
43c2aeb0 3089
43c2aeb0
SZ
3090 cpu_reg.mode = BCE_COM_CPU_MODE;
3091 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3092 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3093 cpu_reg.state = BCE_COM_CPU_STATE;
3094 cpu_reg.state_value_clear = 0xffffff;
3095 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3096 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3097 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3098 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3099 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3100 cpu_reg.spad_base = BCE_COM_SCRATCH;
3101 cpu_reg.mips_view_base = 0x8000000;
3102
d0092544
SZ
3103 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3104 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3105 fw.ver_major = bce_COM_b09FwReleaseMajor;
3106 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3107 fw.ver_fix = bce_COM_b09FwReleaseFix;
3108 fw.start_addr = bce_COM_b09FwStartAddr;
3109
3110 fw.text_addr = bce_COM_b09FwTextAddr;
3111 fw.text_len = bce_COM_b09FwTextLen;
3112 fw.text_index = 0;
3113 fw.text = bce_COM_b09FwText;
3114
3115 fw.data_addr = bce_COM_b09FwDataAddr;
3116 fw.data_len = bce_COM_b09FwDataLen;
3117 fw.data_index = 0;
3118 fw.data = bce_COM_b09FwData;
3119
3120 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3121 fw.sbss_len = bce_COM_b09FwSbssLen;
3122 fw.sbss_index = 0;
3123 fw.sbss = bce_COM_b09FwSbss;
3124
3125 fw.bss_addr = bce_COM_b09FwBssAddr;
3126 fw.bss_len = bce_COM_b09FwBssLen;
3127 fw.bss_index = 0;
3128 fw.bss = bce_COM_b09FwBss;
3129
3130 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3131 fw.rodata_len = bce_COM_b09FwRodataLen;
3132 fw.rodata_index = 0;
3133 fw.rodata = bce_COM_b09FwRodata;
3134 } else {
3135 fw.ver_major = bce_COM_b06FwReleaseMajor;
3136 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3137 fw.ver_fix = bce_COM_b06FwReleaseFix;
3138 fw.start_addr = bce_COM_b06FwStartAddr;
3139
3140 fw.text_addr = bce_COM_b06FwTextAddr;
3141 fw.text_len = bce_COM_b06FwTextLen;
3142 fw.text_index = 0;
3143 fw.text = bce_COM_b06FwText;
3144
3145 fw.data_addr = bce_COM_b06FwDataAddr;
3146 fw.data_len = bce_COM_b06FwDataLen;
3147 fw.data_index = 0;
3148 fw.data = bce_COM_b06FwData;
3149
3150 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3151 fw.sbss_len = bce_COM_b06FwSbssLen;
3152 fw.sbss_index = 0;
3153 fw.sbss = bce_COM_b06FwSbss;
3154
3155 fw.bss_addr = bce_COM_b06FwBssAddr;
3156 fw.bss_len = bce_COM_b06FwBssLen;
3157 fw.bss_index = 0;
3158 fw.bss = bce_COM_b06FwBss;
3159
3160 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3161 fw.rodata_len = bce_COM_b06FwRodataLen;
3162 fw.rodata_index = 0;
3163 fw.rodata = bce_COM_b06FwRodata;
3164 }
43c2aeb0 3165
d0092544
SZ
3166 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3167 bce_load_cpu_fw(sc, &cpu_reg, &fw);
5d05a208 3168 bce_start_cpu(sc, &cpu_reg);
d0092544 3169}
43c2aeb0 3170
43c2aeb0 3171
d0092544
SZ
3172/****************************************************************************/
3173/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3174/* */
3175/* Loads the firmware for each CPU and starts the CPU. */
3176/* */
3177/* Returns: */
3178/* Nothing. */
3179/****************************************************************************/
3180static void
3181bce_init_cpus(struct bce_softc *sc)
3182{
3183 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3184 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
cff16e71
SZ
3185 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3186 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3187 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3188 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3189 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3190 } else {
3191 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3192 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3193 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3194 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3195 }
d0092544 3196 } else {
cff16e71
SZ
3197 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3198 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3199 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3200 sizeof(bce_rv2p_proc2), RV2P_PROC2);
d0092544 3201 }
43c2aeb0 3202
d0092544
SZ
3203 bce_init_rxp_cpu(sc);
3204 bce_init_txp_cpu(sc);
3205 bce_init_tpat_cpu(sc);
3206 bce_init_com_cpu(sc);
3207 bce_init_cp_cpu(sc);
43c2aeb0
SZ
3208}
3209
3210
3211/****************************************************************************/
3212/* Initialize context memory. */
3213/* */
3214/* Clears the memory associated with each Context ID (CID). */
3215/* */
3216/* Returns: */
3217/* Nothing. */
3218/****************************************************************************/
5b609aa3 3219static int
3a41a80b 3220bce_init_ctx(struct bce_softc *sc)
43c2aeb0 3221{
d0092544
SZ
3222 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3223 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3224 /* DRC: Replace this constant value with a #define. */
3225 int i, retry_cnt = 10;
3226 uint32_t val;
3227
3228 /*
3229 * BCM5709 context memory may be cached
3230 * in host memory so prepare the host memory
3231 * for access.
3232 */
3233 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3234 (1 << 12);
3235 val |= (BCM_PAGE_BITS - 8) << 16;
3236 REG_WR(sc, BCE_CTX_COMMAND, val);
3237
3238 /* Wait for mem init command to complete. */
3239 for (i = 0; i < retry_cnt; i++) {
3240 val = REG_RD(sc, BCE_CTX_COMMAND);
3241 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3242 break;
3243 DELAY(2);
3244 }
5b609aa3
SZ
3245 if (i == retry_cnt) {
3246 device_printf(sc->bce_dev,
3247 "Context memory initialization failed!\n");
3248 return ETIMEDOUT;
3249 }
d0092544
SZ
3250
3251 for (i = 0; i < sc->ctx_pages; i++) {
3252 int j;
43c2aeb0 3253
d0092544
SZ
3254 /*
3255 * Set the physical address of the context
3256 * memory cache.
3257 */
3258 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3259 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3260 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3261 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3262 BCE_ADDR_HI(sc->ctx_paddr[i]));
3263 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3264 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
43c2aeb0 3265
d0092544
SZ
3266 /*
3267 * Verify that the context memory write was successful.
3268 */
3269 for (j = 0; j < retry_cnt; j++) {
3270 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3271 if ((val &
3272 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3273 break;
3274 DELAY(5);
3275 }
5b609aa3
SZ
3276 if (j == retry_cnt) {
3277 device_printf(sc->bce_dev,
3278 "Failed to initialize context page!\n");
3279 return ETIMEDOUT;
3280 }
d0092544
SZ
3281 }
3282 } else {
3283 uint32_t vcid_addr, offset;
43c2aeb0 3284
d0092544
SZ
3285 /*
3286 * For the 5706/5708, context memory is local to
3287 * the controller, so initialize the controller
3288 * context memory.
3289 */
43c2aeb0 3290
d0092544
SZ
3291 vcid_addr = GET_CID_ADDR(96);
3292 while (vcid_addr) {
3293 vcid_addr -= PHY_CTX_SIZE;
43c2aeb0 3294
d0092544
SZ
3295 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3296 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
43c2aeb0 3297
3a41a80b 3298 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
d0092544
SZ
3299 CTX_WR(sc, 0x00, offset, 0);
3300
3301 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3302 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3a41a80b 3303 }
43c2aeb0 3304 }
5b609aa3 3305 return 0;
43c2aeb0
SZ
3306}
3307
3308
3309/****************************************************************************/
3310/* Fetch the permanent MAC address of the controller. */
3311/* */
3312/* Returns: */
3313/* Nothing. */
3314/****************************************************************************/
3315static void
3316bce_get_mac_addr(struct bce_softc *sc)
3317{
3318 uint32_t mac_lo = 0, mac_hi = 0;
3319
3320 /*
3321 * The NetXtreme II bootcode populates various NIC
3322 * power-on and runtime configuration items in a
3323 * shared memory area. The factory configured MAC
3324 * address is available from both NVRAM and the
3325 * shared memory area so we'll read the value from
3326 * shared memory for speed.
3327 */
3328
bc30d40d
SZ
3329 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3330 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
43c2aeb0
SZ
3331
3332 if (mac_lo == 0 && mac_hi == 0) {
3333 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3334 } else {
3335 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3336 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3337 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3338 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3339 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3340 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3341 }
3342
3343 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3344}
3345
3346
3347/****************************************************************************/
3348/* Program the MAC address. */
3349/* */
3350/* Returns: */
3351/* Nothing. */
3352/****************************************************************************/
3353static void
3354bce_set_mac_addr(struct bce_softc *sc)
3355{
3356 const uint8_t *mac_addr = sc->eaddr;
3357 uint32_t val;
3358
3359 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3360 sc->eaddr, ":");
3361
3362 val = (mac_addr[0] << 8) | mac_addr[1];
3363 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3364
3365 val = (mac_addr[2] << 24) |
3366 (mac_addr[3] << 16) |
3367 (mac_addr[4] << 8) |
3368 mac_addr[5];
3369 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3370}
3371
3372
3373/****************************************************************************/
3374/* Stop the controller. */
3375/* */
3376/* Returns: */
3377/* Nothing. */
3378/****************************************************************************/
3379static void
3380bce_stop(struct bce_softc *sc)
3381{
3382 struct ifnet *ifp = &sc->arpcom.ac_if;
43c2aeb0
SZ
3383
3384 ASSERT_SERIALIZED(ifp->if_serializer);
3385
d0092544 3386 callout_stop(&sc->bce_tick_callout);
43c2aeb0
SZ
3387
3388 /* Disable the transmit/receive blocks. */
d0092544 3389 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
43c2aeb0
SZ
3390 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3391 DELAY(20);
3392
3393 bce_disable_intr(sc);
3394
43c2aeb0
SZ
3395 /* Free the RX lists. */
3396 bce_free_rx_chain(sc);
3397
3398 /* Free TX buffers. */
3399 bce_free_tx_chain(sc);
3400
43c2aeb0 3401 sc->bce_link = 0;
bdeb8fff 3402 sc->bce_coalchg_mask = 0;
43c2aeb0
SZ
3403
3404 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3405 ifp->if_timer = 0;
43c2aeb0
SZ
3406}
3407
3408
3409static int
3410bce_reset(struct bce_softc *sc, uint32_t reset_code)
3411{
3412 uint32_t val;
3413 int i, rc = 0;
3414
3415 /* Wait for pending PCI transactions to complete. */
3416 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3417 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3418 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3419 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3420 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3421 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3422 DELAY(5);
3423
d0092544
SZ
3424 /* Disable DMA */
3425 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3426 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3427 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3428 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3429 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3430 }
3431
43c2aeb0
SZ
3432 /* Assume bootcode is running. */
3433 sc->bce_fw_timed_out = 0;
d8870c52 3434 sc->bce_drv_cardiac_arrest = 0;
43c2aeb0
SZ
3435
3436 /* Give the firmware a chance to prepare for the reset. */
3437 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3438 if (rc) {
3439 if_printf(&sc->arpcom.ac_if,
3440 "Firmware is not ready for reset\n");
3441 return rc;
3442 }
3443
3444 /* Set a firmware reminder that this is a soft reset. */
bc30d40d
SZ
3445 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3446 BCE_DRV_RESET_SIGNATURE_MAGIC);
43c2aeb0
SZ
3447
3448 /* Dummy read to force the chip to complete all current transactions. */
3449 val = REG_RD(sc, BCE_MISC_ID);
3450
3451 /* Chip reset. */
d0092544
SZ
3452 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3453 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3454 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3455 REG_RD(sc, BCE_MISC_COMMAND);
3456 DELAY(5);
3457
3458 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3459 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3460
3461 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3462 } else {
3463 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3464 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3465 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3466 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3467
3468 /* Allow up to 30us for reset to complete. */
3469 for (i = 0; i < 10; i++) {
3470 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3471 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3472 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3473 break;
3474 DELAY(10);
43c2aeb0 3475 }
43c2aeb0 3476
d0092544
SZ
3477 /* Check that reset completed successfully. */
3478 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3479 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3480 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3481 return EBUSY;
3482 }
43c2aeb0
SZ
3483 }
3484
3485 /* Make sure byte swapping is properly configured. */
3486 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3487 if (val != 0x01020304) {
3488 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3489 return ENODEV;
3490 }
3491
3492 /* Just completed a reset, assume that firmware is running again. */
3493 sc->bce_fw_timed_out = 0;
d8870c52 3494 sc->bce_drv_cardiac_arrest = 0;
43c2aeb0
SZ
3495
3496 /* Wait for the firmware to finish its initialization. */
3497 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3498 if (rc) {
3499 if_printf(&sc->arpcom.ac_if,
3500 "Firmware did not complete initialization!\n");
3501 }
3502 return rc;
3503}
3504
3505
3506static int
3507bce_chipinit(struct bce_softc *sc)
3508{
3509 uint32_t val;
3510 int rc = 0;
3511
3512 /* Make sure the interrupt is not active. */
3513 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
d0092544 3514 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
43c2aeb0
SZ
3515
3516 /*
3517 * Initialize DMA byte/word swapping, configure the number of DMA
3518 * channels and PCI clock compensation delay.
3519 */
3520 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3521 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3522#if BYTE_ORDER == BIG_ENDIAN
3523 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3524#endif
3525 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3526 DMA_READ_CHANS << 12 |
3527 DMA_WRITE_CHANS << 16;
3528
3529 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3530
3531 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3532 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3533
3534 /*
3535 * This setting resolves a problem observed on certain Intel PCI
3536 * chipsets that cannot handle multiple outstanding DMA operations.
3537 * See errata E9_5706A1_65.
3538 */
3539 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3540 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3541 !(sc->bce_flags & BCE_PCIX_FLAG))
3542 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3543
3544 REG_WR(sc, BCE_DMA_CONFIG, val);
3545
43c2aeb0
SZ
3546 /* Enable the RX_V2P and Context state machines before access. */
3547 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3548 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3549 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3550 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3551
3552 /* Initialize context mapping and zero out the quick contexts. */
5b609aa3
SZ
3553 rc = bce_init_ctx(sc);
3554 if (rc != 0)
3555 return rc;
43c2aeb0
SZ
3556
3557 /* Initialize the on-boards CPUs */
3558 bce_init_cpus(sc);
3559
5d05a208
SZ
3560 /* Enable management frames (NC-SI) to flow to the MCP. */
3561 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3562 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3563 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3564 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3565 }
3566
43c2aeb0
SZ
3567 /* Prepare NVRAM for access. */
3568 rc = bce_init_nvram(sc);
3569 if (rc != 0)
3570 return rc;
3571
3572 /* Set the kernel bypass block size */
3573 val = REG_RD(sc, BCE_MQ_CONFIG);
3574 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3575 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
d0092544
SZ
3576
3577 /* Enable bins used on the 5709/5716. */
3578 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3579 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3580 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3581 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3582 val |= BCE_MQ_CONFIG_HALT_DIS;
3583 }
3584
43c2aeb0
SZ
3585 REG_WR(sc, BCE_MQ_CONFIG, val);
3586
3587 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3588 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3589 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3590
3591 /* Set the page size and clear the RV2P processor stall bits. */
3592 val = (BCM_PAGE_BITS - 8) << 24;
3593 REG_WR(sc, BCE_RV2P_CONFIG, val);
3594
3595 /* Configure page size. */
3596 val = REG_RD(sc, BCE_TBDR_CONFIG);
3597 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3598 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3599 REG_WR(sc, BCE_TBDR_CONFIG, val);
3600
d0092544
SZ
3601 /* Set the perfect match control register to default. */
3602 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3603
43c2aeb0
SZ
3604 return 0;
3605}
3606
3607
3608/****************************************************************************/
3609/* Initialize the controller in preparation to send/receive traffic. */
3610/* */
3611/* Returns: */
3612/* 0 for success, positive value for failure. */
3613/****************************************************************************/
3614static int
3615bce_blockinit(struct bce_softc *sc)
3616{
3617 uint32_t reg, val;
3618 int rc = 0;
3619
3620 /* Load the hardware default MAC address. */
3621 bce_set_mac_addr(sc);
3622
3623 /* Set the Ethernet backoff seed value */
3624 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3625 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3626 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3627
3628 sc->last_status_idx = 0;
3629 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3630
3631 /* Set up link change interrupt generation. */
3632 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3633
3634 /* Program the physical address of the status block. */
3635 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3636 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3637
3638 /* Program the physical address of the statistics block. */
3639 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3640 BCE_ADDR_LO(sc->stats_block_paddr));
3641 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3642 BCE_ADDR_HI(sc->stats_block_paddr));
3643
3644 /* Program various host coalescing parameters. */
3645 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3646 (sc->bce_tx_quick_cons_trip_int << 16) |
3647 sc->bce_tx_quick_cons_trip);
3648 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3649 (sc->bce_rx_quick_cons_trip_int << 16) |
3650 sc->bce_rx_quick_cons_trip);
3651 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3652 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3653 REG_WR(sc, BCE_HC_TX_TICKS,
3654 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3655 REG_WR(sc, BCE_HC_RX_TICKS,
3656 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3657 REG_WR(sc, BCE_HC_COM_TICKS,
3658 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3659 REG_WR(sc, BCE_HC_CMD_TICKS,
3660 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3661 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3662 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
eac57ffb
SZ
3663
3664 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3665 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3666 if (bootverbose)
3667 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3668 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3669 }
3670 REG_WR(sc, BCE_HC_CONFIG, val);
43c2aeb0
SZ
3671
3672 /* Clear the internal statistics counters. */
3673 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3674
3675 /* Verify that bootcode is running. */
bc30d40d 3676 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
43c2aeb0
SZ
3677
3678 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3679 if_printf(&sc->arpcom.ac_if,
3680 "%s(%d): Simulating bootcode failure.\n",
3681 __FILE__, __LINE__);
3682 reg = 0);
3683
3684 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3685 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3686 if_printf(&sc->arpcom.ac_if,
3687 "Bootcode not running! Found: 0x%08X, "
3688 "Expected: 08%08X\n",
3689 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3690 BCE_DEV_INFO_SIGNATURE_MAGIC);
3691 return ENODEV;
3692 }
3693
d0092544
SZ
3694 /* Enable DMA */
3695 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3696 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3697 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3698 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3699 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
43c2aeb0
SZ
3700 }
3701
43c2aeb0
SZ
3702 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3703 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3704
3705 /* Enable link state change interrupt generation. */
3706 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3707
5d05a208
SZ
3708 /* Enable the RXP. */
3709 bce_start_rxp_cpu(sc);
3710
3711 /* Disable management frames (NC-SI) from flowing to the MCP. */
3712 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3713 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3714 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3715 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3716 }
3717
43c2aeb0 3718 /* Enable all remaining blocks in the MAC. */
d0092544
SZ
3719 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3720 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3721 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3722 BCE_MISC_ENABLE_DEFAULT_XI);
3723 } else {
3724 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3725 }
43c2aeb0
SZ
3726 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3727 DELAY(20);
3728
d0092544
SZ
3729 /* Save the current host coalescing block settings. */
3730 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3731
43c2aeb0
SZ
3732 return 0;
3733}
3734
3735
3736/****************************************************************************/
3737/* Encapsulate an mbuf cluster into the rx_bd chain. */
3738/* */
3739/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3740/* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3741/* necessary. */
3742/* */
3743/* Returns: */
3744/* 0 for success, positive value for failure. */
3745/****************************************************************************/
3746static int
c36fd9ee
SZ
3747bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3748 uint32_t *prod_bseq, int init)
43c2aeb0
SZ
3749{
3750 bus_dmamap_t map;
43c2aeb0
SZ
3751 bus_dma_segment_t seg;
3752 struct mbuf *m_new;
c36fd9ee 3753 int error, nseg;
43c2aeb0
SZ
3754#ifdef BCE_DEBUG
3755 uint16_t debug_chain_prod = *chain_prod;
3756#endif
3757
3758 /* Make sure the inputs are valid. */
3759 DBRUNIF((*chain_prod > MAX_RX_BD),
3760 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3761 "RX producer out of range: 0x%04X > 0x%04X\n",
3762 __FILE__, __LINE__,
3763 *chain_prod, (uint16_t)MAX_RX_BD));
3764
3765 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3766 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3767
c36fd9ee
SZ
3768 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3769 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3770 "Simulating mbuf allocation failure.\n",
3771 __FILE__, __LINE__);
3772 sc->mbuf_alloc_failed++;
3773 return ENOBUFS);
43c2aeb0 3774
c36fd9ee
SZ
3775 /* This is a new mbuf allocation. */
3776 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3777 if (m_new == NULL)
3778 return ENOBUFS;
3779 DBRUNIF(1, sc->rx_mbuf_alloc++);
43c2aeb0 3780
c36fd9ee 3781 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
43c2aeb0 3782
c36fd9ee
SZ
3783 /* Map the mbuf cluster into device memory. */
3784 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3785 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3786 BUS_DMA_NOWAIT);
3787 if (error) {
3788 m_freem(m_new);
3789 if (init) {
3790 if_printf(&sc->arpcom.ac_if,
3791 "Error mapping mbuf into RX chain!\n");
3792 }
43c2aeb0 3793 DBRUNIF(1, sc->rx_mbuf_alloc--);
c36fd9ee 3794 return error;
43c2aeb0
SZ
3795 }
3796
c36fd9ee
SZ
3797 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3798 bus_dmamap_unload(sc->rx_mbuf_tag,
3799 sc->rx_mbuf_map[*chain_prod]);
3800 }
3801
3802 map = sc->rx_mbuf_map[*chain_prod];
3803 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3804 sc->rx_mbuf_tmpmap = map;
3805
43c2aeb0
SZ
3806 /* Watch for overflow. */
3807 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3808 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3809 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3810 __FILE__, __LINE__, sc->free_rx_bd,
3811 (uint16_t)USABLE_RX_BD));
3812
3813 /* Update some debug statistic counters */
3814 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3815 sc->rx_low_watermark = sc->free_rx_bd);
3816 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3817
43c2aeb0
SZ
3818 /* Save the mbuf and update our counter. */
3819 sc->rx_mbuf_ptr[*chain_prod] = m_new;
314a2fcc 3820 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
43c2aeb0
SZ
3821 sc->free_rx_bd--;
3822