Merge from vendor branch GCC:
[dragonfly.git] / sys / dev / netif / wb / if_wb.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
ef203de8 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.14 2004/09/15 01:12:08 joerg Exp $
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34 *
35 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
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36 */
37
38/*
39 * Winbond fast ethernet PCI NIC driver
40 *
41 * Supports various cheap network adapters based on the Winbond W89C840F
42 * fast ethernet controller chip. This includes adapters manufactured by
43 * Winbond itself and some made by Linksys.
44 *
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
48 */
49
50/*
51 * The Winbond W89C840F chip is a bus master; in some ways it resembles
52 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
53 * one major difference which is that while the registers do many of
54 * the same things as a tulip adapter, the offsets are different: where
55 * tulip registers are typically spaced 8 bytes apart, the Winbond
56 * registers are spaced 4 bytes apart. The receiver filter is also
57 * programmed differently.
58 *
59 * Like the tulip, the Winbond chip uses small descriptors containing
60 * a status word, a control word and 32-bit areas that can either be used
61 * to point to two external data blocks, or to point to a single block
62 * and another descriptor in a linked list. Descriptors can be grouped
63 * together in blocks to form fixed length rings or can be chained
64 * together in linked lists. A single packet may be spread out over
65 * several descriptors if necessary.
66 *
67 * For the receive ring, this driver uses a linked list of descriptors,
68 * each pointing to a single mbuf cluster buffer, which us large enough
69 * to hold an entire packet. The link list is looped back to created a
70 * closed ring.
71 *
72 * For transmission, the driver creates a linked list of 'super descriptors'
73 * which each contain several individual descriptors linked toghether.
74 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
75 * abuse as fragment pointers. This allows us to use a buffer managment
76 * scheme very similar to that used in the ThunderLAN and Etherlink XL
77 * drivers.
78 *
79 * Autonegotiation is performed using the external PHY via the MII bus.
80 * The sample boards I have all use a Davicom PHY.
81 *
82 * Note: the author of the Linux driver for the Winbond chip alludes
83 * to some sort of flaw in the chip's design that seems to mandate some
84 * drastic workaround which signigicantly impairs transmit performance.
85 * I have no idea what he's on about: transmit performance with all
86 * three of my test boards seems fine.
87 */
88
89#include "opt_bdg.h"
90
91#include <sys/param.h>
92#include <sys/systm.h>
93#include <sys/sockio.h>
94#include <sys/mbuf.h>
95#include <sys/malloc.h>
96#include <sys/kernel.h>
97#include <sys/socket.h>
98#include <sys/queue.h>
99
100#include <net/if.h>
101#include <net/if_arp.h>
102#include <net/ethernet.h>
103#include <net/if_dl.h>
104#include <net/if_media.h>
105
106#include <net/bpf.h>
107
108#include <vm/vm.h> /* for vtophys */
109#include <vm/pmap.h> /* for vtophys */
110#include <machine/clock.h> /* for DELAY */
111#include <machine/bus_memio.h>
112#include <machine/bus_pio.h>
113#include <machine/bus.h>
114#include <machine/resource.h>
115#include <sys/bus.h>
116#include <sys/rman.h>
117
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118#include <bus/pci/pcireg.h>
119#include <bus/pci/pcivar.h>
984263bc 120
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121#include "../mii_layer/mii.h"
122#include "../mii_layer/miivar.h"
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123
124/* "controller miibus0" required. See GENERIC if you get errors here. */
125#include "miibus_if.h"
126
127#define WB_USEIOSPACE
128
1f2de5d4 129#include "if_wbreg.h"
984263bc 130
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131/*
132 * Various supported device vendors/types and their names.
133 */
134static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
139 { 0, 0, NULL }
140};
141
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142static int wb_probe (device_t);
143static int wb_attach (device_t);
144static int wb_detach (device_t);
984263bc 145
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146static void wb_bfree (caddr_t, u_int);
147static int wb_newbuf (struct wb_softc *,
984263bc 148 struct wb_chain_onefrag *,
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149 struct mbuf *);
150static int wb_encap (struct wb_softc *, struct wb_chain *,
151 struct mbuf *);
152
153static void wb_rxeof (struct wb_softc *);
154static void wb_rxeoc (struct wb_softc *);
155static void wb_txeof (struct wb_softc *);
156static void wb_txeoc (struct wb_softc *);
157static void wb_intr (void *);
158static void wb_tick (void *);
159static void wb_start (struct ifnet *);
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160static int wb_ioctl (struct ifnet *, u_long, caddr_t,
161 struct ucred *);
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162static void wb_init (void *);
163static void wb_stop (struct wb_softc *);
164static void wb_watchdog (struct ifnet *);
165static void wb_shutdown (device_t);
166static int wb_ifmedia_upd (struct ifnet *);
167static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *);
168
169static void wb_eeprom_putbyte (struct wb_softc *, int);
170static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *);
171static void wb_read_eeprom (struct wb_softc *, caddr_t, int,
172 int, int);
173static void wb_mii_sync (struct wb_softc *);
174static void wb_mii_send (struct wb_softc *, u_int32_t, int);
175static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *);
176static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *);
177
178static void wb_setcfg (struct wb_softc *, u_int32_t);
179static u_int8_t wb_calchash (caddr_t);
180static void wb_setmulti (struct wb_softc *);
181static void wb_reset (struct wb_softc *);
182static void wb_fixmedia (struct wb_softc *);
183static int wb_list_rx_init (struct wb_softc *);
184static int wb_list_tx_init (struct wb_softc *);
185
186static int wb_miibus_readreg (device_t, int, int);
187static int wb_miibus_writereg (device_t, int, int, int);
188static void wb_miibus_statchg (device_t);
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189
190#ifdef WB_USEIOSPACE
191#define WB_RES SYS_RES_IOPORT
192#define WB_RID WB_PCI_LOIO
193#else
194#define WB_RES SYS_RES_MEMORY
195#define WB_RID WB_PCI_LOMEM
196#endif
197
198static device_method_t wb_methods[] = {
199 /* Device interface */
200 DEVMETHOD(device_probe, wb_probe),
201 DEVMETHOD(device_attach, wb_attach),
202 DEVMETHOD(device_detach, wb_detach),
203 DEVMETHOD(device_shutdown, wb_shutdown),
204
205 /* bus interface, for miibus */
206 DEVMETHOD(bus_print_child, bus_generic_print_child),
207 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
208
209 /* MII interface */
210 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
211 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
212 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
213 { 0, 0 }
214};
215
216static driver_t wb_driver = {
217 "wb",
218 wb_methods,
219 sizeof(struct wb_softc)
220};
221
222static devclass_t wb_devclass;
223
32832096 224DECLARE_DUMMY_MODULE(if_wb);
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225DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
226DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
227
228#define WB_SETBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) | x)
231
232#define WB_CLRBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, \
234 CSR_READ_4(sc, reg) & ~x)
235
236#define SIO_SET(x) \
237 CSR_WRITE_4(sc, WB_SIO, \
238 CSR_READ_4(sc, WB_SIO) | x)
239
240#define SIO_CLR(x) \
241 CSR_WRITE_4(sc, WB_SIO, \
242 CSR_READ_4(sc, WB_SIO) & ~x)
243
244/*
245 * Send a read command and address to the EEPROM, check for ACK.
246 */
247static void wb_eeprom_putbyte(sc, addr)
248 struct wb_softc *sc;
249 int addr;
250{
3d0f5f54 251 int d, i;
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252
253 d = addr | WB_EECMD_READ;
254
255 /*
256 * Feed in each bit and stobe the clock.
257 */
258 for (i = 0x400; i; i >>= 1) {
259 if (d & i) {
260 SIO_SET(WB_SIO_EE_DATAIN);
261 } else {
262 SIO_CLR(WB_SIO_EE_DATAIN);
263 }
264 DELAY(100);
265 SIO_SET(WB_SIO_EE_CLK);
266 DELAY(150);
267 SIO_CLR(WB_SIO_EE_CLK);
268 DELAY(100);
269 }
270
271 return;
272}
273
274/*
275 * Read a word of data stored in the EEPROM at address 'addr.'
276 */
277static void wb_eeprom_getword(sc, addr, dest)
278 struct wb_softc *sc;
279 int addr;
280 u_int16_t *dest;
281{
3d0f5f54 282 int i;
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283 u_int16_t word = 0;
284
285 /* Enter EEPROM access mode. */
286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
287
288 /*
289 * Send address of word we want to read.
290 */
291 wb_eeprom_putbyte(sc, addr);
292
293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
294
295 /*
296 * Start reading bits from EEPROM.
297 */
298 for (i = 0x8000; i; i >>= 1) {
299 SIO_SET(WB_SIO_EE_CLK);
300 DELAY(100);
301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
302 word |= i;
303 SIO_CLR(WB_SIO_EE_CLK);
304 DELAY(100);
305 }
306
307 /* Turn off EEPROM access mode. */
308 CSR_WRITE_4(sc, WB_SIO, 0);
309
310 *dest = word;
311
312 return;
313}
314
315/*
316 * Read a sequence of words from the EEPROM.
317 */
318static void wb_read_eeprom(sc, dest, off, cnt, swap)
319 struct wb_softc *sc;
320 caddr_t dest;
321 int off;
322 int cnt;
323 int swap;
324{
325 int i;
326 u_int16_t word = 0, *ptr;
327
328 for (i = 0; i < cnt; i++) {
329 wb_eeprom_getword(sc, off + i, &word);
330 ptr = (u_int16_t *)(dest + (i * 2));
331 if (swap)
332 *ptr = ntohs(word);
333 else
334 *ptr = word;
335 }
336
337 return;
338}
339
340/*
341 * Sync the PHYs by setting data bit and strobing the clock 32 times.
342 */
343static void wb_mii_sync(sc)
344 struct wb_softc *sc;
345{
3d0f5f54 346 int i;
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347
348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
349
350 for (i = 0; i < 32; i++) {
351 SIO_SET(WB_SIO_MII_CLK);
352 DELAY(1);
353 SIO_CLR(WB_SIO_MII_CLK);
354 DELAY(1);
355 }
356
357 return;
358}
359
360/*
361 * Clock a series of bits through the MII.
362 */
363static void wb_mii_send(sc, bits, cnt)
364 struct wb_softc *sc;
365 u_int32_t bits;
366 int cnt;
367{
368 int i;
369
370 SIO_CLR(WB_SIO_MII_CLK);
371
372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
373 if (bits & i) {
374 SIO_SET(WB_SIO_MII_DATAIN);
375 } else {
376 SIO_CLR(WB_SIO_MII_DATAIN);
377 }
378 DELAY(1);
379 SIO_CLR(WB_SIO_MII_CLK);
380 DELAY(1);
381 SIO_SET(WB_SIO_MII_CLK);
382 }
383}
384
385/*
386 * Read an PHY register through the MII.
387 */
388static int wb_mii_readreg(sc, frame)
389 struct wb_softc *sc;
390 struct wb_mii_frame *frame;
391
392{
393 int i, ack, s;
394
395 s = splimp();
396
397 /*
398 * Set up frame for RX.
399 */
400 frame->mii_stdelim = WB_MII_STARTDELIM;
401 frame->mii_opcode = WB_MII_READOP;
402 frame->mii_turnaround = 0;
403 frame->mii_data = 0;
404
405 CSR_WRITE_4(sc, WB_SIO, 0);
406
407 /*
408 * Turn on data xmit.
409 */
410 SIO_SET(WB_SIO_MII_DIR);
411
412 wb_mii_sync(sc);
413
414 /*
415 * Send command/address info.
416 */
417 wb_mii_send(sc, frame->mii_stdelim, 2);
418 wb_mii_send(sc, frame->mii_opcode, 2);
419 wb_mii_send(sc, frame->mii_phyaddr, 5);
420 wb_mii_send(sc, frame->mii_regaddr, 5);
421
422 /* Idle bit */
423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
424 DELAY(1);
425 SIO_SET(WB_SIO_MII_CLK);
426 DELAY(1);
427
428 /* Turn off xmit. */
429 SIO_CLR(WB_SIO_MII_DIR);
430 /* Check for ack */
431 SIO_CLR(WB_SIO_MII_CLK);
432 DELAY(1);
433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
434 SIO_SET(WB_SIO_MII_CLK);
435 DELAY(1);
436 SIO_CLR(WB_SIO_MII_CLK);
437 DELAY(1);
438 SIO_SET(WB_SIO_MII_CLK);
439 DELAY(1);
440
441 /*
442 * Now try reading data bits. If the ack failed, we still
443 * need to clock through 16 cycles to keep the PHY(s) in sync.
444 */
445 if (ack) {
446 for(i = 0; i < 16; i++) {
447 SIO_CLR(WB_SIO_MII_CLK);
448 DELAY(1);
449 SIO_SET(WB_SIO_MII_CLK);
450 DELAY(1);
451 }
452 goto fail;
453 }
454
455 for (i = 0x8000; i; i >>= 1) {
456 SIO_CLR(WB_SIO_MII_CLK);
457 DELAY(1);
458 if (!ack) {
459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
460 frame->mii_data |= i;
461 DELAY(1);
462 }
463 SIO_SET(WB_SIO_MII_CLK);
464 DELAY(1);
465 }
466
467fail:
468
469 SIO_CLR(WB_SIO_MII_CLK);
470 DELAY(1);
471 SIO_SET(WB_SIO_MII_CLK);
472 DELAY(1);
473
474 splx(s);
475
476 if (ack)
477 return(1);
478 return(0);
479}
480
481/*
482 * Write to a PHY register through the MII.
483 */
484static int wb_mii_writereg(sc, frame)
485 struct wb_softc *sc;
486 struct wb_mii_frame *frame;
487
488{
489 int s;
490
491 s = splimp();
492 /*
493 * Set up frame for TX.
494 */
495
496 frame->mii_stdelim = WB_MII_STARTDELIM;
497 frame->mii_opcode = WB_MII_WRITEOP;
498 frame->mii_turnaround = WB_MII_TURNAROUND;
499
500 /*
501 * Turn on data output.
502 */
503 SIO_SET(WB_SIO_MII_DIR);
504
505 wb_mii_sync(sc);
506
507 wb_mii_send(sc, frame->mii_stdelim, 2);
508 wb_mii_send(sc, frame->mii_opcode, 2);
509 wb_mii_send(sc, frame->mii_phyaddr, 5);
510 wb_mii_send(sc, frame->mii_regaddr, 5);
511 wb_mii_send(sc, frame->mii_turnaround, 2);
512 wb_mii_send(sc, frame->mii_data, 16);
513
514 /* Idle bit. */
515 SIO_SET(WB_SIO_MII_CLK);
516 DELAY(1);
517 SIO_CLR(WB_SIO_MII_CLK);
518 DELAY(1);
519
520 /*
521 * Turn off xmit.
522 */
523 SIO_CLR(WB_SIO_MII_DIR);
524
525 splx(s);
526
527 return(0);
528}
529
530static int wb_miibus_readreg(dev, phy, reg)
531 device_t dev;
532 int phy, reg;
533{
534 struct wb_softc *sc;
535 struct wb_mii_frame frame;
536
537 sc = device_get_softc(dev);
538
539 bzero((char *)&frame, sizeof(frame));
540
541 frame.mii_phyaddr = phy;
542 frame.mii_regaddr = reg;
543 wb_mii_readreg(sc, &frame);
544
545 return(frame.mii_data);
546}
547
548static int wb_miibus_writereg(dev, phy, reg, data)
549 device_t dev;
550 int phy, reg, data;
551{
552 struct wb_softc *sc;
553 struct wb_mii_frame frame;
554
555 sc = device_get_softc(dev);
556
557 bzero((char *)&frame, sizeof(frame));
558
559 frame.mii_phyaddr = phy;
560 frame.mii_regaddr = reg;
561 frame.mii_data = data;
562
563 wb_mii_writereg(sc, &frame);
564
565 return(0);
566}
567
568static void wb_miibus_statchg(dev)
569 device_t dev;
570{
571 struct wb_softc *sc;
572 struct mii_data *mii;
573
574 sc = device_get_softc(dev);
575 mii = device_get_softc(sc->wb_miibus);
576 wb_setcfg(sc, mii->mii_media_active);
577
578 return;
579}
580
581static u_int8_t wb_calchash(addr)
582 caddr_t addr;
583{
584 u_int32_t crc, carry;
585 int i, j;
586 u_int8_t c;
587
588 /* Compute CRC for the address value. */
589 crc = 0xFFFFFFFF; /* initial value */
590
591 for (i = 0; i < 6; i++) {
592 c = *(addr + i);
593 for (j = 0; j < 8; j++) {
594 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
595 crc <<= 1;
596 c >>= 1;
597 if (carry)
598 crc = (crc ^ 0x04c11db6) | carry;
599 }
600 }
601
602 /*
603 * return the filter bit position
604 * Note: I arrived at the following nonsense
605 * through experimentation. It's not the usual way to
606 * generate the bit position but it's the only thing
607 * I could come up with that works.
608 */
609 return(~(crc >> 26) & 0x0000003F);
610}
611
612/*
613 * Program the 64-bit multicast hash filter.
614 */
615static void wb_setmulti(sc)
616 struct wb_softc *sc;
617{
618 struct ifnet *ifp;
619 int h = 0;
620 u_int32_t hashes[2] = { 0, 0 };
621 struct ifmultiaddr *ifma;
622 u_int32_t rxfilt;
623 int mcnt = 0;
624
625 ifp = &sc->arpcom.ac_if;
626
627 rxfilt = CSR_READ_4(sc, WB_NETCFG);
628
629 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
630 rxfilt |= WB_NETCFG_RX_MULTI;
631 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
632 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
633 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
634 return;
635 }
636
637 /* first, zot all the existing hash bits */
638 CSR_WRITE_4(sc, WB_MAR0, 0);
639 CSR_WRITE_4(sc, WB_MAR1, 0);
640
641 /* now program new ones */
642 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
643 ifma = ifma->ifma_link.le_next) {
644 if (ifma->ifma_addr->sa_family != AF_LINK)
645 continue;
646 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
647 if (h < 32)
648 hashes[0] |= (1 << h);
649 else
650 hashes[1] |= (1 << (h - 32));
651 mcnt++;
652 }
653
654 if (mcnt)
655 rxfilt |= WB_NETCFG_RX_MULTI;
656 else
657 rxfilt &= ~WB_NETCFG_RX_MULTI;
658
659 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
660 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
661 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
662
663 return;
664}
665
666/*
667 * The Winbond manual states that in order to fiddle with the
668 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
669 * first have to put the transmit and/or receive logic in the idle state.
670 */
671static void wb_setcfg(sc, media)
672 struct wb_softc *sc;
673 u_int32_t media;
674{
675 int i, restart = 0;
676
677 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
678 restart = 1;
679 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
680
681 for (i = 0; i < WB_TIMEOUT; i++) {
682 DELAY(10);
683 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
684 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
685 break;
686 }
687
688 if (i == WB_TIMEOUT)
689 printf("wb%d: failed to force tx and "
690 "rx to idle state\n", sc->wb_unit);
691 }
692
693 if (IFM_SUBTYPE(media) == IFM_10_T)
694 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
695 else
696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
697
698 if ((media & IFM_GMASK) == IFM_FDX)
699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
700 else
701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
702
703 if (restart)
704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
705
706 return;
707}
708
709static void wb_reset(sc)
710 struct wb_softc *sc;
711{
3d0f5f54 712 int i;
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MD
713 struct mii_data *mii;
714
715 CSR_WRITE_4(sc, WB_NETCFG, 0);
716 CSR_WRITE_4(sc, WB_BUSCTL, 0);
717 CSR_WRITE_4(sc, WB_TXADDR, 0);
718 CSR_WRITE_4(sc, WB_RXADDR, 0);
719
720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
722
723 for (i = 0; i < WB_TIMEOUT; i++) {
724 DELAY(10);
725 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
726 break;
727 }
728 if (i == WB_TIMEOUT)
729 printf("wb%d: reset never completed!\n", sc->wb_unit);
730
731 /* Wait a little while for the chip to get its brains in order. */
732 DELAY(1000);
733
734 if (sc->wb_miibus == NULL)
735 return;
736
737 mii = device_get_softc(sc->wb_miibus);
738 if (mii == NULL)
739 return;
740
741 if (mii->mii_instance) {
742 struct mii_softc *miisc;
743 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
744 miisc = LIST_NEXT(miisc, mii_list))
745 mii_phy_reset(miisc);
746 }
747
748 return;
749}
750
751static void wb_fixmedia(sc)
752 struct wb_softc *sc;
753{
754 struct mii_data *mii = NULL;
755 struct ifnet *ifp;
756 u_int32_t media;
757
758 if (sc->wb_miibus == NULL)
759 return;
760
761 mii = device_get_softc(sc->wb_miibus);
762 ifp = &sc->arpcom.ac_if;
763
764 mii_pollstat(mii);
765 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
766 media = mii->mii_media_active & ~IFM_10_T;
767 media |= IFM_100_TX;
768 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
769 media = mii->mii_media_active & ~IFM_100_TX;
770 media |= IFM_10_T;
771 } else
772 return;
773
774 ifmedia_set(&mii->mii_media, media);
775
776 return;
777}
778
779/*
780 * Probe for a Winbond chip. Check the PCI vendor and device
781 * IDs against our list and return a device name if we find a match.
782 */
783static int wb_probe(dev)
784 device_t dev;
785{
786 struct wb_type *t;
787
788 t = wb_devs;
789
790 while(t->wb_name != NULL) {
791 if ((pci_get_vendor(dev) == t->wb_vid) &&
792 (pci_get_device(dev) == t->wb_did)) {
793 device_set_desc(dev, t->wb_name);
794 return(0);
795 }
796 t++;
797 }
798
799 return(ENXIO);
800}
801
802/*
803 * Attach the interface. Allocate softc structures, do ifmedia
804 * setup and ethernet/BPF attach.
805 */
806static int wb_attach(dev)
807 device_t dev;
808{
809 int s;
810 u_char eaddr[ETHER_ADDR_LEN];
811 u_int32_t command;
812 struct wb_softc *sc;
813 struct ifnet *ifp;
814 int unit, error = 0, rid;
815
816 s = splimp();
817
818 sc = device_get_softc(dev);
819 unit = device_get_unit(dev);
ef203de8 820 callout_init(&sc->wb_stat_timer);
984263bc
MD
821
822 /*
823 * Handle power management nonsense.
824 */
825
826 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
827 if (command == 0x01) {
828
829 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
830 if (command & WB_PSTATE_MASK) {
831 u_int32_t iobase, membase, irq;
832
833 /* Save important PCI config data. */
834 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
835 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
836 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
837
838 /* Reset the power state. */
839 printf("wb%d: chip is in D%d power mode "
840 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
841 command &= 0xFFFFFFFC;
842 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
843
844 /* Restore PCI config data. */
845 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
846 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
847 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
848 }
849 }
850
851 /*
852 * Map control/status registers.
853 */
854 command = pci_read_config(dev, PCIR_COMMAND, 4);
855 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
856 pci_write_config(dev, PCIR_COMMAND, command, 4);
857 command = pci_read_config(dev, PCIR_COMMAND, 4);
858
859#ifdef WB_USEIOSPACE
860 if (!(command & PCIM_CMD_PORTEN)) {
861 printf("wb%d: failed to enable I/O ports!\n", unit);
862 error = ENXIO;
863 goto fail;
864 }
865#else
866 if (!(command & PCIM_CMD_MEMEN)) {
867 printf("wb%d: failed to enable memory mapping!\n", unit);
868 error = ENXIO;
869 goto fail;
870 }
871#endif
872
873 rid = WB_RID;
874 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
875 0, ~0, 1, RF_ACTIVE);
876
877 if (sc->wb_res == NULL) {
878 printf("wb%d: couldn't map ports/memory\n", unit);
879 error = ENXIO;
880 goto fail;
881 }
882
883 sc->wb_btag = rman_get_bustag(sc->wb_res);
884 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
885
886 /* Allocate interrupt */
887 rid = 0;
888 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
889 RF_SHAREABLE | RF_ACTIVE);
890
891 if (sc->wb_irq == NULL) {
892 printf("wb%d: couldn't map interrupt\n", unit);
893 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
894 error = ENXIO;
895 goto fail;
896 }
897
898 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
899 wb_intr, sc, &sc->wb_intrhand);
900
901 if (error) {
902 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
903 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
904 printf("wb%d: couldn't set up irq\n", unit);
905 goto fail;
906 }
907
908 /* Save the cache line size. */
909 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
910
911 /* Reset the adapter. */
912 wb_reset(sc);
913
914 /*
915 * Get station address from the EEPROM.
916 */
917 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
918
984263bc 919 sc->wb_unit = unit;
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MD
920
921 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
922 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
923
924 if (sc->wb_ldata == NULL) {
925 printf("wb%d: no memory for list buffers!\n", unit);
926 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
928 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
929 error = ENXIO;
930 goto fail;
931 }
932
933 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
934
935 ifp = &sc->arpcom.ac_if;
936 ifp->if_softc = sc;
cdb7d804 937 if_initname(ifp, "wb", unit);
984263bc
MD
938 ifp->if_mtu = ETHERMTU;
939 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
940 ifp->if_ioctl = wb_ioctl;
984263bc
MD
941 ifp->if_start = wb_start;
942 ifp->if_watchdog = wb_watchdog;
943 ifp->if_init = wb_init;
944 ifp->if_baudrate = 10000000;
945 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
946
947 /*
948 * Do MII setup.
949 */
950 if (mii_phy_probe(dev, &sc->wb_miibus,
951 wb_ifmedia_upd, wb_ifmedia_sts)) {
952 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
953 M_DEVBUF);
954 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
956 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
957 error = ENXIO;
958 goto fail;
959 }
960
961 /*
962 * Call MI attach routine.
963 */
0a8b5977 964 ether_ifattach(ifp, eaddr);
984263bc
MD
965
966fail:
967 if (error)
968 device_delete_child(dev, sc->wb_miibus);
969 splx(s);
970
971 return(error);
972}
973
974static int wb_detach(dev)
975 device_t dev;
976{
977 struct wb_softc *sc;
978 struct ifnet *ifp;
979 int s;
980
981 s = splimp();
982
983 sc = device_get_softc(dev);
984 ifp = &sc->arpcom.ac_if;
985
986 wb_stop(sc);
0a8b5977 987 ether_ifdetach(ifp);
984263bc
MD
988
989 /* Delete any miibus and phy devices attached to this interface */
990 bus_generic_detach(dev);
991 device_delete_child(dev, sc->wb_miibus);
992
993 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
995 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
996
997 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
998 M_DEVBUF);
999
1000 splx(s);
1001
1002 return(0);
1003}
1004
1005/*
1006 * Initialize the transmit descriptors.
1007 */
1008static int wb_list_tx_init(sc)
1009 struct wb_softc *sc;
1010{
1011 struct wb_chain_data *cd;
1012 struct wb_list_data *ld;
1013 int i;
1014
1015 cd = &sc->wb_cdata;
1016 ld = sc->wb_ldata;
1017
1018 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1019 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1020 if (i == (WB_TX_LIST_CNT - 1)) {
1021 cd->wb_tx_chain[i].wb_nextdesc =
1022 &cd->wb_tx_chain[0];
1023 } else {
1024 cd->wb_tx_chain[i].wb_nextdesc =
1025 &cd->wb_tx_chain[i + 1];
1026 }
1027 }
1028
1029 cd->wb_tx_free = &cd->wb_tx_chain[0];
1030 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1031
1032 return(0);
1033}
1034
1035
1036/*
1037 * Initialize the RX descriptors and allocate mbufs for them. Note that
1038 * we arrange the descriptors in a closed ring, so that the last descriptor
1039 * points back to the first.
1040 */
1041static int wb_list_rx_init(sc)
1042 struct wb_softc *sc;
1043{
1044 struct wb_chain_data *cd;
1045 struct wb_list_data *ld;
1046 int i;
1047
1048 cd = &sc->wb_cdata;
1049 ld = sc->wb_ldata;
1050
1051 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1052 cd->wb_rx_chain[i].wb_ptr =
1053 (struct wb_desc *)&ld->wb_rx_list[i];
1054 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1055 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1056 return(ENOBUFS);
1057 if (i == (WB_RX_LIST_CNT - 1)) {
1058 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1059 ld->wb_rx_list[i].wb_next =
1060 vtophys(&ld->wb_rx_list[0]);
1061 } else {
1062 cd->wb_rx_chain[i].wb_nextdesc =
1063 &cd->wb_rx_chain[i + 1];
1064 ld->wb_rx_list[i].wb_next =
1065 vtophys(&ld->wb_rx_list[i + 1]);
1066 }
1067 }
1068
1069 cd->wb_rx_head = &cd->wb_rx_chain[0];
1070
1071 return(0);
1072}
1073
1074static void wb_bfree(buf, size)
1075 caddr_t buf;
1076 u_int size;
1077{
1078 return;
1079}
1080
1081/*
1082 * Initialize an RX descriptor and attach an MBUF cluster.
1083 */
1084static int wb_newbuf(sc, c, m)
1085 struct wb_softc *sc;
1086 struct wb_chain_onefrag *c;
1087 struct mbuf *m;
1088{
1089 struct mbuf *m_new = NULL;
1090
1091 if (m == NULL) {
74f1caca 1092 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1093 if (m_new == NULL)
1094 return(ENOBUFS);
1095
1096 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
7eccf245 1097 m_new->m_flags |= M_EXT | M_EXT_OLD;
984263bc
MD
1098 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1099 m_new->m_len = WB_BUFBYTES;
7eccf245
MD
1100 m_new->m_ext.ext_nfree.old = wb_bfree;
1101 m_new->m_ext.ext_nref.old = wb_bfree;
984263bc
MD
1102 } else {
1103 m_new = m;
1104 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1105 m_new->m_data = m_new->m_ext.ext_buf;
1106 }
1107
1108 m_adj(m_new, sizeof(u_int64_t));
1109
1110 c->wb_mbuf = m_new;
1111 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1112 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1113 c->wb_ptr->wb_status = WB_RXSTAT;
1114
1115 return(0);
1116}
1117
1118/*
1119 * A frame has been uploaded: pass the resulting mbuf chain up to
1120 * the higher level protocols.
1121 */
1122static void wb_rxeof(sc)
1123 struct wb_softc *sc;
1124{
984263bc
MD
1125 struct mbuf *m = NULL;
1126 struct ifnet *ifp;
1127 struct wb_chain_onefrag *cur_rx;
1128 int total_len = 0;
1129 u_int32_t rxstat;
1130
1131 ifp = &sc->arpcom.ac_if;
1132
1133 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1134 WB_RXSTAT_OWN)) {
1135 struct mbuf *m0 = NULL;
1136
1137 cur_rx = sc->wb_cdata.wb_rx_head;
1138 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1139
1140 m = cur_rx->wb_mbuf;
1141
1142 if ((rxstat & WB_RXSTAT_MIIERR) ||
1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1144 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1145 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1146 !(rxstat & WB_RXSTAT_RXCMP)) {
1147 ifp->if_ierrors++;
1148 wb_newbuf(sc, cur_rx, m);
1149 printf("wb%x: receiver babbling: possible chip "
1150 "bug, forcing reset\n", sc->wb_unit);
1151 wb_fixmedia(sc);
1152 wb_reset(sc);
1153 wb_init(sc);
1154 return;
1155 }
1156
1157 if (rxstat & WB_RXSTAT_RXERR) {
1158 ifp->if_ierrors++;
1159 wb_newbuf(sc, cur_rx, m);
1160 break;
1161 }
1162
1163 /* No errors; receive the packet. */
1164 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1165
1166 /*
1167 * XXX The Winbond chip includes the CRC with every
1168 * received frame, and there's no way to turn this
1169 * behavior off (at least, I can't find anything in
1170 * the manual that explains how to do it) so we have
1171 * to trim off the CRC manually.
1172 */
1173 total_len -= ETHER_CRC_LEN;
1174
1175 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1176 total_len + ETHER_ALIGN, 0, ifp, NULL);
1177 wb_newbuf(sc, cur_rx, m);
1178 if (m0 == NULL) {
1179 ifp->if_ierrors++;
1180 break;
1181 }
1182 m_adj(m0, ETHER_ALIGN);
1183 m = m0;
1184
1185 ifp->if_ipackets++;
3013ac0e 1186 (*ifp->if_input)(ifp, m);
984263bc
MD
1187 }
1188}
1189
1190void wb_rxeoc(sc)
1191 struct wb_softc *sc;
1192{
1193 wb_rxeof(sc);
1194
1195 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1196 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1197 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1198 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1199 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1200
1201 return;
1202}
1203
1204/*
1205 * A frame was downloaded to the chip. It's safe for us to clean up
1206 * the list buffers.
1207 */
1208static void wb_txeof(sc)
1209 struct wb_softc *sc;
1210{
1211 struct wb_chain *cur_tx;
1212 struct ifnet *ifp;
1213
1214 ifp = &sc->arpcom.ac_if;
1215
1216 /* Clear the timeout timer. */
1217 ifp->if_timer = 0;
1218
1219 if (sc->wb_cdata.wb_tx_head == NULL)
1220 return;
1221
1222 /*
1223 * Go through our tx list and free mbufs for those
1224 * frames that have been transmitted.
1225 */
1226 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1227 u_int32_t txstat;
1228
1229 cur_tx = sc->wb_cdata.wb_tx_head;
1230 txstat = WB_TXSTATUS(cur_tx);
1231
1232 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1233 break;
1234
1235 if (txstat & WB_TXSTAT_TXERR) {
1236 ifp->if_oerrors++;
1237 if (txstat & WB_TXSTAT_ABORT)
1238 ifp->if_collisions++;
1239 if (txstat & WB_TXSTAT_LATECOLL)
1240 ifp->if_collisions++;
1241 }
1242
1243 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1244
1245 ifp->if_opackets++;
1246 m_freem(cur_tx->wb_mbuf);
1247 cur_tx->wb_mbuf = NULL;
1248
1249 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1250 sc->wb_cdata.wb_tx_head = NULL;
1251 sc->wb_cdata.wb_tx_tail = NULL;
1252 break;
1253 }
1254
1255 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1256 }
1257
1258 return;
1259}
1260
1261/*
1262 * TX 'end of channel' interrupt handler.
1263 */
1264static void wb_txeoc(sc)
1265 struct wb_softc *sc;
1266{
1267 struct ifnet *ifp;
1268
1269 ifp = &sc->arpcom.ac_if;
1270
1271 ifp->if_timer = 0;
1272
1273 if (sc->wb_cdata.wb_tx_head == NULL) {
1274 ifp->if_flags &= ~IFF_OACTIVE;
1275 sc->wb_cdata.wb_tx_tail = NULL;
1276 } else {
1277 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1278 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1279 ifp->if_timer = 5;
1280 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1281 }
1282 }
1283
1284 return;
1285}
1286
1287static void wb_intr(arg)
1288 void *arg;
1289{
1290 struct wb_softc *sc;
1291 struct ifnet *ifp;
1292 u_int32_t status;
1293
1294 sc = arg;
1295 ifp = &sc->arpcom.ac_if;
1296
1297 if (!(ifp->if_flags & IFF_UP))
1298 return;
1299
1300 /* Disable interrupts. */
1301 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1302
1303 for (;;) {
1304
1305 status = CSR_READ_4(sc, WB_ISR);
1306 if (status)
1307 CSR_WRITE_4(sc, WB_ISR, status);
1308
1309 if ((status & WB_INTRS) == 0)
1310 break;
1311
1312 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1313 ifp->if_ierrors++;
1314 wb_reset(sc);
1315 if (status & WB_ISR_RX_ERR)
1316 wb_fixmedia(sc);
1317 wb_init(sc);
1318 continue;
1319 }
1320
1321 if (status & WB_ISR_RX_OK)
1322 wb_rxeof(sc);
1323
1324 if (status & WB_ISR_RX_IDLE)
1325 wb_rxeoc(sc);
1326
1327 if (status & WB_ISR_TX_OK)
1328 wb_txeof(sc);
1329
1330 if (status & WB_ISR_TX_NOBUF)
1331 wb_txeoc(sc);
1332
1333 if (status & WB_ISR_TX_IDLE) {
1334 wb_txeof(sc);
1335 if (sc->wb_cdata.wb_tx_head != NULL) {
1336 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1337 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1338 }
1339 }
1340
1341 if (status & WB_ISR_TX_UNDERRUN) {
1342 ifp->if_oerrors++;
1343 wb_txeof(sc);
1344 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1345 /* Jack up TX threshold */
1346 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1347 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1348 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1349 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1350 }
1351
1352 if (status & WB_ISR_BUS_ERR) {
1353 wb_reset(sc);
1354 wb_init(sc);
1355 }
1356
1357 }
1358
1359 /* Re-enable interrupts. */
1360 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1361
1362 if (ifp->if_snd.ifq_head != NULL) {
1363 wb_start(ifp);
1364 }
1365
1366 return;
1367}
1368
1369static void wb_tick(xsc)
1370 void *xsc;
1371{
1372 struct wb_softc *sc;
1373 struct mii_data *mii;
1374 int s;
1375
1376 s = splimp();
1377
1378 sc = xsc;
1379 mii = device_get_softc(sc->wb_miibus);
1380
1381 mii_tick(mii);
1382
ef203de8 1383 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
984263bc
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1384
1385 splx(s);
1386
1387 return;
1388}
1389
1390/*
1391 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1392 * pointers to the fragment pointers.
1393 */
1394static int wb_encap(sc, c, m_head)
1395 struct wb_softc *sc;
1396 struct wb_chain *c;
1397 struct mbuf *m_head;
1398{
1399 int frag = 0;
1400 struct wb_desc *f = NULL;
1401 int total_len;
1402 struct mbuf *m;
1403
1404 /*
1405 * Start packing the mbufs in this chain into
1406 * the fragment pointers. Stop when we run out
1407 * of fragments or hit the end of the mbuf chain.
1408 */
1409 m = m_head;
1410 total_len = 0;
1411
1412 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1413 if (m->m_len != 0) {
1414 if (frag == WB_MAXFRAGS)
1415 break;
1416 total_len += m->m_len;
1417 f = &c->wb_ptr->wb_frag[frag];
1418 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1419 if (frag == 0) {
1420 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1421 f->wb_status = 0;
1422 } else
1423 f->wb_status = WB_TXSTAT_OWN;
1424 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1425 f->wb_data = vtophys(mtod(m, vm_offset_t));
1426 frag++;
1427 }
1428 }
1429
1430 /*
1431 * Handle special case: we used up all 16 fragments,
1432 * but we have more mbufs left in the chain. Copy the
1433 * data into an mbuf cluster. Note that we don't
1434 * bother clearing the values in the other fragment
1435 * pointers/counters; it wouldn't gain us anything,
1436 * and would waste cycles.
1437 */
1438 if (m != NULL) {
1439 struct mbuf *m_new = NULL;
1440
74f1caca 1441 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
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1442 if (m_new == NULL)
1443 return(1);
1444 if (m_head->m_pkthdr.len > MHLEN) {
74f1caca 1445 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
1446 if (!(m_new->m_flags & M_EXT)) {
1447 m_freem(m_new);
1448 return(1);
1449 }
1450 }
1451 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1452 mtod(m_new, caddr_t));
1453 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1454 m_freem(m_head);
1455 m_head = m_new;
1456 f = &c->wb_ptr->wb_frag[0];
1457 f->wb_status = 0;
1458 f->wb_data = vtophys(mtod(m_new, caddr_t));
1459 f->wb_ctl = total_len = m_new->m_len;
1460 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1461 frag = 1;
1462 }
1463
1464 if (total_len < WB_MIN_FRAMELEN) {
1465 f = &c->wb_ptr->wb_frag[frag];
1466 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1467 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1468 f->wb_ctl |= WB_TXCTL_TLINK;
1469 f->wb_status = WB_TXSTAT_OWN;
1470 frag++;
1471 }
1472
1473 c->wb_mbuf = m_head;
1474 c->wb_lastdesc = frag - 1;
1475 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1476 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1477
1478 return(0);
1479}
1480
1481/*
1482 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1483 * to the mbuf data regions directly in the transmit lists. We also save a
1484 * copy of the pointers since the transmit list fragment pointers are
1485 * physical addresses.
1486 */
1487
1488static void wb_start(ifp)
1489 struct ifnet *ifp;
1490{
1491 struct wb_softc *sc;
1492 struct mbuf *m_head = NULL;
1493 struct wb_chain *cur_tx = NULL, *start_tx;
1494
1495 sc = ifp->if_softc;
1496
1497 /*
1498 * Check for an available queue slot. If there are none,
1499 * punt.
1500 */
1501 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1502 ifp->if_flags |= IFF_OACTIVE;
1503 return;
1504 }
1505
1506 start_tx = sc->wb_cdata.wb_tx_free;
1507
1508 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1509 IF_DEQUEUE(&ifp->if_snd, m_head);
1510 if (m_head == NULL)
1511 break;
1512
1513 /* Pick a descriptor off the free list. */
1514 cur_tx = sc->wb_cdata.wb_tx_free;
1515 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1516
1517 /* Pack the data into the descriptor. */
1518 wb_encap(sc, cur_tx, m_head);
1519
1520 if (cur_tx != start_tx)
1521 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1522
1523 /*
1524 * If there's a BPF listener, bounce a copy of this frame
1525 * to him.
1526 */
1527 if (ifp->if_bpf)
1528 bpf_mtap(ifp, cur_tx->wb_mbuf);
1529 }
1530
1531 /*
1532 * If there are no packets queued, bail.
1533 */
1534 if (cur_tx == NULL)
1535 return;
1536
1537 /*
1538 * Place the request for the upload interrupt
1539 * in the last descriptor in the chain. This way, if
1540 * we're chaining several packets at once, we'll only
1541 * get an interupt once for the whole chain rather than
1542 * once for each packet.
1543 */
1544 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1545 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1546 sc->wb_cdata.wb_tx_tail = cur_tx;
1547
1548 if (sc->wb_cdata.wb_tx_head == NULL) {
1549 sc->wb_cdata.wb_tx_head = start_tx;
1550 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1551 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1552 } else {
1553 /*
1554 * We need to distinguish between the case where
1555 * the own bit is clear because the chip cleared it
1556 * and where the own bit is clear because we haven't
1557 * set it yet. The magic value WB_UNSET is just some
1558 * ramdomly chosen number which doesn't have the own
1559 * bit set. When we actually transmit the frame, the
1560 * status word will have _only_ the own bit set, so
1561 * the txeoc handler will be able to tell if it needs
1562 * to initiate another transmission to flush out pending
1563 * frames.
1564 */
1565 WB_TXOWN(start_tx) = WB_UNSENT;
1566 }
1567
1568 /*
1569 * Set a timeout in case the chip goes out to lunch.
1570 */
1571 ifp->if_timer = 5;
1572
1573 return;
1574}
1575
1576static void wb_init(xsc)
1577 void *xsc;
1578{
1579 struct wb_softc *sc = xsc;
1580 struct ifnet *ifp = &sc->arpcom.ac_if;
1581 int s, i;
1582 struct mii_data *mii;
1583
1584 s = splimp();
1585
1586 mii = device_get_softc(sc->wb_miibus);
1587
1588 /*
1589 * Cancel pending I/O and free all RX/TX buffers.
1590 */
1591 wb_stop(sc);
1592 wb_reset(sc);
1593
1594 sc->wb_txthresh = WB_TXTHRESH_INIT;
1595
1596 /*
1597 * Set cache alignment and burst length.
1598 */
1599#ifdef foo
1600 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1601 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1602 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1603#endif
1604
1605 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1606 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1607 switch(sc->wb_cachesize) {
1608 case 32:
1609 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1610 break;
1611 case 16:
1612 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1613 break;
1614 case 8:
1615 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1616 break;
1617 case 0:
1618 default:
1619 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1620 break;
1621 }
1622
1623 /* This doesn't tend to work too well at 100Mbps. */
1624 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1625
1626 /* Init our MAC address */
1627 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1628 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1629 }
1630
1631 /* Init circular RX list. */
1632 if (wb_list_rx_init(sc) == ENOBUFS) {
1633 printf("wb%d: initialization failed: no "
1634 "memory for rx buffers\n", sc->wb_unit);
1635 wb_stop(sc);
1636 (void)splx(s);
1637 return;
1638 }
1639
1640 /* Init TX descriptors. */
1641 wb_list_tx_init(sc);
1642
1643 /* If we want promiscuous mode, set the allframes bit. */
1644 if (ifp->if_flags & IFF_PROMISC) {
1645 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1646 } else {
1647 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1648 }
1649
1650 /*
1651 * Set capture broadcast bit to capture broadcast frames.
1652 */
1653 if (ifp->if_flags & IFF_BROADCAST) {
1654 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1655 } else {
1656 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1657 }
1658
1659 /*
1660 * Program the multicast filter, if necessary.
1661 */
1662 wb_setmulti(sc);
1663
1664 /*
1665 * Load the address of the RX list.
1666 */
1667 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1668 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1669
1670 /*
1671 * Enable interrupts.
1672 */
1673 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1674 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1675
1676 /* Enable receiver and transmitter. */
1677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1678 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1679
1680 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1681 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1682 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1683
1684 mii_mediachg(mii);
1685
1686 ifp->if_flags |= IFF_RUNNING;
1687 ifp->if_flags &= ~IFF_OACTIVE;
1688
1689 (void)splx(s);
1690
ef203de8 1691 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
984263bc
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1692}
1693
1694/*
1695 * Set media options.
1696 */
1697static int wb_ifmedia_upd(ifp)
1698 struct ifnet *ifp;
1699{
1700 struct wb_softc *sc;
1701
1702 sc = ifp->if_softc;
1703
1704 if (ifp->if_flags & IFF_UP)
1705 wb_init(sc);
1706
1707 return(0);
1708}
1709
1710/*
1711 * Report current media status.
1712 */
1713static void wb_ifmedia_sts(ifp, ifmr)
1714 struct ifnet *ifp;
1715 struct ifmediareq *ifmr;
1716{
1717 struct wb_softc *sc;
1718 struct mii_data *mii;
1719
1720 sc = ifp->if_softc;
1721
1722 mii = device_get_softc(sc->wb_miibus);
1723
1724 mii_pollstat(mii);
1725 ifmr->ifm_active = mii->mii_media_active;
1726 ifmr->ifm_status = mii->mii_media_status;
1727
1728 return;
1729}
1730
bd4539cc 1731static int wb_ioctl(ifp, command, data, cr)
984263bc
MD
1732 struct ifnet *ifp;
1733 u_long command;
1734 caddr_t data;
bd4539cc 1735 struct ucred *cr;
984263bc
MD
1736{
1737 struct wb_softc *sc = ifp->if_softc;
1738 struct mii_data *mii;
1739 struct ifreq *ifr = (struct ifreq *) data;
1740 int s, error = 0;
1741
1742 s = splimp();
1743
1744 switch(command) {
1745 case SIOCSIFADDR:
1746 case SIOCGIFADDR:
1747 case SIOCSIFMTU:
1748 error = ether_ioctl(ifp, command, data);
1749 break;
1750 case SIOCSIFFLAGS:
1751 if (ifp->if_flags & IFF_UP) {
1752 wb_init(sc);
1753 } else {
1754 if (ifp->if_flags & IFF_RUNNING)
1755 wb_stop(sc);
1756 }
1757 error = 0;
1758 break;
1759 case SIOCADDMULTI:
1760 case SIOCDELMULTI:
1761 wb_setmulti(sc);
1762 error = 0;
1763 break;
1764 case SIOCGIFMEDIA:
1765 case SIOCSIFMEDIA:
1766 mii = device_get_softc(sc->wb_miibus);
1767 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1768 break;
1769 default:
1770 error = EINVAL;
1771 break;
1772 }
1773
1774 (void)splx(s);
1775
1776 return(error);
1777}
1778
1779static void wb_watchdog(ifp)
1780 struct ifnet *ifp;
1781{
1782 struct wb_softc *sc;
1783
1784 sc = ifp->if_softc;
1785
1786 ifp->if_oerrors++;
1787 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1788#ifdef foo
1789 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1790 printf("wb%d: no carrier - transceiver cable problem?\n",
1791 sc->wb_unit);
1792#endif
1793 wb_stop(sc);
1794 wb_reset(sc);
1795 wb_init(sc);
1796
1797 if (ifp->if_snd.ifq_head != NULL)
1798 wb_start(ifp);
1799
1800 return;
1801}
1802
1803/*
1804 * Stop the adapter and free any mbufs allocated to the
1805 * RX and TX lists.
1806 */
1807static void wb_stop(sc)
1808 struct wb_softc *sc;
1809{
3d0f5f54 1810 int i;
984263bc
MD
1811 struct ifnet *ifp;
1812
1813 ifp = &sc->arpcom.ac_if;
1814 ifp->if_timer = 0;
1815
ef203de8 1816 callout_stop(&sc->wb_stat_timer);
984263bc
MD
1817
1818 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1819 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1820 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1821 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1822
1823 /*
1824 * Free data in the RX lists.
1825 */
1826 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1827 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1828 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1829 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1830 }
1831 }
1832 bzero((char *)&sc->wb_ldata->wb_rx_list,
1833 sizeof(sc->wb_ldata->wb_rx_list));
1834
1835 /*
1836 * Free the TX list buffers.
1837 */
1838 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1839 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1840 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1841 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1842 }
1843 }
1844
1845 bzero((char *)&sc->wb_ldata->wb_tx_list,
1846 sizeof(sc->wb_ldata->wb_tx_list));
1847
1848 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1849
1850 return;
1851}
1852
1853/*
1854 * Stop all chip I/O so that the kernel's probe routines don't
1855 * get confused by errant DMAs when rebooting.
1856 */
1857static void wb_shutdown(dev)
1858 device_t dev;
1859{
1860 struct wb_softc *sc;
1861
1862 sc = device_get_softc(dev);
1863 wb_stop(sc);
1864
1865 return;
1866}