kernel - Fix serious issue w/ smp_invltlb(), plus other issues (3)
[dragonfly.git] / sys / platform / pc32 / i386 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
c0c5de70 26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
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27 */
28
29#include "opt_cpu.h"
984263bc 30
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31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
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34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
984263bc 37#include <sys/cons.h> /* cngetc() */
37e7efec 38#include <sys/machintr.h>
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39
40#include <vm/vm.h>
41#include <vm/vm_param.h>
42#include <vm/pmap.h>
43#include <vm/vm_kern.h>
44#include <vm/vm_extern.h>
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45#include <sys/lock.h>
46#include <vm/vm_map.h>
47#include <sys/user.h>
48#ifdef GPROF
49#include <sys/gmon.h>
50#endif
984263bc 51
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52#include <sys/mplock2.h>
53
984263bc 54#include <machine/smp.h>
a9295349 55#include <machine_base/apic/apicreg.h>
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56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
90e8a35b 58#include <machine/cputypes.h>
a9295349 59#include <machine_base/apic/mpapic.h>
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60#include <machine/psl.h>
61#include <machine/segments.h>
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62#include <machine/tss.h>
63#include <machine/specialreg.h>
64#include <machine/globaldata.h>
9bbe2f36 65#include <machine/pmap_inval.h>
984263bc 66
984263bc 67#include <machine/md_var.h> /* setidt() */
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68#include <machine_base/icu/icu.h> /* IPIs */
69#include <machine_base/isa/intr_machdep.h> /* IPIs */
984263bc 70
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71#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72
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73#define WARMBOOT_TARGET 0
74#define WARMBOOT_OFF (KERNBASE + 0x0467)
75#define WARMBOOT_SEG (KERNBASE + 0x0469)
76
984263bc 77#define BIOS_BASE (0xf0000)
1df86978 78#define BIOS_BASE2 (0xe0000)
984263bc 79#define BIOS_SIZE (0x10000)
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80#define BIOS_COUNT (BIOS_SIZE/4)
81
82#define CMOS_REG (0x70)
83#define CMOS_DATA (0x71)
84#define BIOS_RESET (0x0f)
85#define BIOS_WARM (0x0a)
86
87#define PROCENTRY_FLAG_EN 0x01
88#define PROCENTRY_FLAG_BP 0x02
89#define IOAPICENTRY_FLAG_EN 0x01
90
91
92/* MP Floating Pointer Structure */
93typedef struct MPFPS {
94 char signature[4];
981bebd1 95 u_int32_t pap;
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96 u_char length;
97 u_char spec_rev;
98 u_char checksum;
99 u_char mpfb1;
100 u_char mpfb2;
101 u_char mpfb3;
102 u_char mpfb4;
103 u_char mpfb5;
104} *mpfps_t;
105
106/* MP Configuration Table Header */
107typedef struct MPCTH {
108 char signature[4];
109 u_short base_table_length;
110 u_char spec_rev;
111 u_char checksum;
112 u_char oem_id[8];
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
116 u_short entry_count;
117 void *apic_address;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
120 u_char reserved;
121} *mpcth_t;
122
123
124typedef struct PROCENTRY {
125 u_char type;
126 u_char apic_id;
127 u_char apic_version;
128 u_char cpu_flags;
129 u_long cpu_signature;
130 u_long feature_flags;
131 u_long reserved1;
132 u_long reserved2;
133} *proc_entry_ptr;
134
135typedef struct BUSENTRY {
136 u_char type;
137 u_char bus_id;
138 char bus_type[6];
139} *bus_entry_ptr;
140
141typedef struct IOAPICENTRY {
142 u_char type;
143 u_char apic_id;
144 u_char apic_version;
145 u_char apic_flags;
146 void *apic_address;
147} *io_apic_entry_ptr;
148
149typedef struct INTENTRY {
150 u_char type;
151 u_char int_type;
152 u_short int_flags;
153 u_char src_bus_id;
154 u_char src_bus_irq;
155 u_char dst_apic_id;
156 u_char dst_apic_int;
157} *int_entry_ptr;
158
159/* descriptions of MP basetable entries */
160typedef struct BASETABLE_ENTRY {
161 u_char type;
162 u_char length;
163 char name[16];
164} basetable_entry;
165
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166struct mptable_pos {
167 mpfps_t mp_fps;
168 mpcth_t mp_cth;
169 vm_size_t mp_cth_mapsz;
170};
171
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172typedef int (*mptable_iter_func)(void *, const void *, int);
173
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174/*
175 * this code MUST be enabled here and in mpboot.s.
176 * it follows the very early stages of AP boot by placing values in CMOS ram.
177 * it NORMALLY will never be needed and thus the primitive method for enabling.
178 *
984263bc 179 */
7d34994c 180#if defined(CHECK_POINTS)
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181#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
182#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183
184#define CHECK_INIT(D); \
185 CHECK_WRITE(0x34, (D)); \
186 CHECK_WRITE(0x35, (D)); \
187 CHECK_WRITE(0x36, (D)); \
188 CHECK_WRITE(0x37, (D)); \
189 CHECK_WRITE(0x38, (D)); \
190 CHECK_WRITE(0x39, (D));
191
192#define CHECK_PRINT(S); \
26be20a0 193 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
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194 (S), \
195 CHECK_READ(0x34), \
196 CHECK_READ(0x35), \
197 CHECK_READ(0x36), \
198 CHECK_READ(0x37), \
199 CHECK_READ(0x38), \
200 CHECK_READ(0x39));
201
202#else /* CHECK_POINTS */
203
204#define CHECK_INIT(D)
205#define CHECK_PRINT(S)
206
207#endif /* CHECK_POINTS */
208
209/*
210 * Values to send to the POST hardware.
211 */
212#define MP_BOOTADDRESS_POST 0x10
213#define MP_PROBE_POST 0x11
214#define MPTABLE_PASS1_POST 0x12
215
216#define MP_START_POST 0x13
217#define MP_ENABLE_POST 0x14
218#define MPTABLE_PASS2_POST 0x15
219
220#define START_ALL_APS_POST 0x16
221#define INSTALL_AP_TRAMP_POST 0x17
222#define START_AP_POST 0x18
223
224#define MP_ANNOUNCE_POST 0x19
225
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226/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227int current_postcode;
228
229/** XXX FIXME: what system files declare these??? */
230extern struct region_descriptor r_gdt, r_idt;
231
984263bc 232int mp_naps; /* # of Applications processors */
97359a5b 233#ifdef APIC_IO
4f6a8b30 234static int mp_nbusses; /* # of busses */
984263bc 235int mp_napics; /* # of IO APICs */
97359a5b 236#endif
97359a5b 237#ifdef APIC_IO
984263bc 238vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
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239u_int32_t *io_apic_versions;
240#endif
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241extern int nkpt;
242
243u_int32_t cpu_apic_versions[MAXCPU];
374133e3 244int64_t tsc0_offset;
0b698dca 245extern int64_t tsc_offsets[];
984263bc 246
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247extern u_long ebda_addr;
248
97359a5b 249#ifdef APIC_IO
8a8d5d85 250struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
97359a5b 251#endif
984263bc 252
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253/*
254 * APIC ID logical/physical mapping structures.
255 * We oversize these to simplify boot-time config.
256 */
257int cpu_num_to_apic_id[NAPICID];
97359a5b 258#ifdef APIC_IO
984263bc 259int io_num_to_apic_id[NAPICID];
97359a5b 260#endif
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261int apic_id_to_logical[NAPICID];
262
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263/* AP uses this during bootstrap. Do not staticize. */
264char *bootSTK;
265static int bootAP;
266
267/* Hotwire a 0->4MB V==P mapping */
268extern pt_entry_t *KPTphys;
269
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270/*
271 * SMP page table page. Setup by locore to point to a page table
272 * page from which we allocate per-cpu privatespace areas io_apics,
273 * and so forth.
274 */
275
276#define IO_MAPPING_START_INDEX \
277 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278
984263bc 279extern pt_entry_t *SMPpt;
f13b5eec 280static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
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281
282struct pcb stoppcbs[MAXCPU];
283
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284static basetable_entry basetable_entry_types[] =
285{
286 {0, 20, "Processor"},
287 {1, 8, "Bus"},
288 {2, 8, "I/O APIC"},
289 {3, 8, "I/O INT"},
290 {4, 8, "Local INT"}
291};
292
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293/*
294 * Local data and functions.
295 */
296
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297static u_int boot_address;
298static u_int base_memory;
41a01a4d 299static int mp_finish;
984263bc 300
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301static void mp_enable(u_int boot_addr);
302
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303static int mptable_iterate_entries(const mpcth_t,
304 mptable_iter_func, void *);
cb00b5c4 305static int mptable_probe(void);
34e6fa63 306static int mptable_search(void);
fa058384 307static int mptable_check(vm_paddr_t);
3aba8f73 308static int mptable_search_sig(u_int32_t target, int count);
44c36320 309static int mptable_hyperthread_fixup(u_int, int);
29bb1d92 310#ifdef APIC_IO
981bebd1 311static void mptable_pass1(struct mptable_pos *);
390b18b0 312static void mptable_pass2(struct mptable_pos *);
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313static void mptable_default(int type);
314static void mptable_fix(void);
29bb1d92 315#endif
fa058384 316static int mptable_map(struct mptable_pos *, vm_paddr_t);
981bebd1 317static void mptable_unmap(struct mptable_pos *);
a0eaef71 318static void mptable_imcr(struct mptable_pos *);
3aba8f73 319
281d9482
SZ
320static int mptable_lapic_probe(struct lapic_enumerator *);
321static void mptable_lapic_enumerate(struct lapic_enumerator *);
322static void mptable_lapic_default(void);
323
97359a5b 324#ifdef APIC_IO
984263bc 325static void setup_apic_irq_mapping(void);
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326static int apic_int_is_bus_type(int intr, int bus_type);
327#endif
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328static int start_all_aps(u_int boot_addr);
329static void install_ap_tramp(u_int boot_addr);
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330static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
331static int smitest(void);
984263bc 332
41a01a4d 333static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
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334cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
335SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
336
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337/*
338 * Calculate usable address in base memory for AP trampoline code.
339 */
340u_int
341mp_bootaddress(u_int basemem)
342{
343 POSTCODE(MP_BOOTADDRESS_POST);
344
c0c5de70 345 base_memory = basemem;
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346
347 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
348 if ((base_memory - boot_address) < bootMP_size)
349 boot_address -= 4096; /* not enough, lower by 4k */
350
351 return boot_address;
352}
353
354
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SZ
355static int
356mptable_probe(void)
357{
358 int mpfps_paddr;
359
360 mpfps_paddr = mptable_search();
361 if (mptable_check(mpfps_paddr))
362 return 0;
363
364 return mpfps_paddr;
365}
366
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367/*
368 * Look for an Intel MP spec table (ie, SMP capable hardware).
369 */
cb00b5c4 370static int
34e6fa63 371mptable_search(void)
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372{
373 int x;
984263bc 374 u_int32_t target;
f13b5eec
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375
376 /*
377 * Make sure our SMPpt[] page table is big enough to hold all the
378 * mappings we need.
379 */
380 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
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381
382 POSTCODE(MP_PROBE_POST);
383
384 /* see if EBDA exists */
1876681a 385 if (ebda_addr != 0) {
984263bc 386 /* search first 1K of EBDA */
1876681a 387 target = (u_int32_t)ebda_addr;
3aba8f73 388 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 389 return x;
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390 } else {
391 /* last 1K of base memory, effective 'top of base' passed in */
aeb48299 392 target = (u_int32_t)(base_memory - 0x400);
3aba8f73 393 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
aeb48299 394 return x;
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395 }
396
397 /* search the BIOS */
aeb48299 398 target = (u_int32_t)BIOS_BASE;
3aba8f73 399 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
aeb48299 400 return x;
984263bc 401
1df86978
SZ
402 /* search the extended BIOS */
403 target = (u_int32_t)BIOS_BASE2;
404 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
405 return x;
406
984263bc 407 /* nothing found */
984263bc 408 return 0;
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MD
409}
410
fa058384
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411struct mptable_check_cbarg {
412 int cpu_count;
413 int found_bsp;
414};
415
416static int
417mptable_check_callback(void *xarg, const void *pos, int type)
418{
419 const struct PROCENTRY *ent;
420 struct mptable_check_cbarg *arg = xarg;
421
422 if (type != 0)
423 return 0;
424 ent = pos;
425
426 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
427 return 0;
428 arg->cpu_count++;
429
430 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
431 if (arg->found_bsp) {
432 kprintf("more than one BSP in base MP table\n");
433 return EINVAL;
434 }
435 arg->found_bsp = 1;
436 }
437 return 0;
438}
439
440static int
441mptable_check(vm_paddr_t mpfps_paddr)
442{
443 struct mptable_pos mpt;
444 struct mptable_check_cbarg arg;
445 mpcth_t cth;
446 int error;
447
448 if (mpfps_paddr == 0)
449 return EOPNOTSUPP;
450
451 error = mptable_map(&mpt, mpfps_paddr);
452 if (error)
453 return error;
454
455 if (mpt.mp_fps->mpfb1 != 0)
456 goto done;
457
458 error = EINVAL;
459
460 cth = mpt.mp_cth;
461 if (cth == NULL)
462 goto done;
463 if (cth->apic_address == 0)
464 goto done;
465
466 bzero(&arg, sizeof(arg));
467 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
468 if (!error) {
469 if (arg.cpu_count == 0) {
470 kprintf("MP table contains no processor entries\n");
471 error = EINVAL;
472 } else if (!arg.found_bsp) {
473 kprintf("MP table does not contains BSP entry\n");
474 error = EINVAL;
475 }
476 }
477done:
478 mptable_unmap(&mpt);
479 return error;
480}
481
482static int
483mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
484{
485 int count, total_size;
486 const void *position;
487
488 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
489 total_size = cth->base_table_length - sizeof(struct MPCTH);
490 position = (const uint8_t *)cth + sizeof(struct MPCTH);
491 count = cth->entry_count;
492
493 while (count--) {
494 int type, error;
495
496 KKASSERT(total_size >= 0);
497 if (total_size == 0) {
498 kprintf("invalid base MP table, "
499 "entry count and length mismatch\n");
500 return EINVAL;
501 }
502
503 type = *(const uint8_t *)position;
504 switch (type) {
505 case 0: /* processor_entry */
506 case 1: /* bus_entry */
507 case 2: /* io_apic_entry */
508 case 3: /* int_entry */
509 case 4: /* int_entry */
510 break;
511 default:
512 kprintf("unknown base MP table entry type %d\n", type);
513 return EINVAL;
514 }
515
516 if (total_size < basetable_entry_types[type].length) {
517 kprintf("invalid base MP table length, "
518 "does not contain all entries\n");
519 return EINVAL;
520 }
521 total_size -= basetable_entry_types[type].length;
522
523 error = func(arg, position, type);
524 if (error)
525 return error;
526
527 position = (const uint8_t *)position +
528 basetable_entry_types[type].length;
529 }
530 return 0;
531}
532
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533
534/*
535 * Startup the SMP processors.
536 */
537void
538mp_start(void)
539{
540 POSTCODE(MP_START_POST);
50bc991e 541 mp_enable(boot_address);
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542}
543
544
545/*
546 * Print various information about the SMP system hardware and setup.
547 */
548void
549mp_announce(void)
550{
551 int x;
552
553 POSTCODE(MP_ANNOUNCE_POST);
554
26be20a0
SW
555 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
556 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
8629c4ea 557 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
984263bc 558 for (x = 1; x <= mp_naps; ++x) {
26be20a0 559 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
8629c4ea 560 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
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561 }
562
563#if defined(APIC_IO)
564 for (x = 0; x < mp_napics; ++x) {
26be20a0
SW
565 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
566 kprintf(", version: 0x%08x", io_apic_versions[x]);
d557216f 567 kprintf(", at 0x%08lx\n", io_apic_address[x]);
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568 }
569#else
26be20a0 570 kprintf(" Warning: APIC I/O disabled\n");
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571#endif /* APIC_IO */
572}
573
574/*
575 * AP cpu's call this to sync up protected mode.
7160572f
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576 *
577 * WARNING! We must ensure that the cpu is sufficiently initialized to
578 * be able to use to the FP for our optimized bzero/bcopy code before
579 * we enter more mainstream C code.
a44bdeec
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580 *
581 * WARNING! %fs is not set up on entry. This routine sets up %fs.
984263bc
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582 */
583void
584init_secondary(void)
585{
586 int gsel_tss;
587 int x, myid = bootAP;
588 u_int cr0;
8a8d5d85 589 struct mdglobaldata *md;
0f7a3396 590 struct privatespace *ps;
984263bc 591
0f7a3396
MD
592 ps = &CPU_prvspace[myid];
593
594 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
984263bc 595 gdt_segs[GPROC0_SEL].ssd_base =
0f7a3396
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596 (int) &ps->mdglobaldata.gd_common_tss;
597 ps->mdglobaldata.mi.gd_prvspace = ps;
984263bc
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598
599 for (x = 0; x < NGDT; x++) {
600 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
601 }
602
603 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
604 r_gdt.rd_base = (int) &gdt[myid * NGDT];
605 lgdt(&r_gdt); /* does magic intra-segment return */
606
607 lidt(&r_idt);
608
609 lldt(_default_ldt);
7b95be2a 610 mdcpu->gd_currentldt = _default_ldt;
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611
612 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
613 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
8a8d5d85 614
0f7a3396 615 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
8a8d5d85
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616
617 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
618 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
619 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
620 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
621 md->gd_common_tssd = *md->gd_tss_gdt;
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622 ltr(gsel_tss);
623
624 /*
625 * Set to a known state:
626 * Set by mpboot.s: CR0_PG, CR0_PE
627 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 */
629 cr0 = rcr0();
630 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
631 load_cr0(cr0);
7160572f 632 pmap_set_opt(); /* PSE/4MB pages, etc */
984263bc 633
7160572f
MD
634 /* set up CPU registers and state */
635 cpu_setregs();
636
637 /* set up FPU state on the AP */
638 npxinit(__INITIAL_NPXCW__);
639
640 /* set up SSE registers */
641 enable_sse();
984263bc
MD
642}
643
984263bc
MD
644/*******************************************************************
645 * local functions and data
646 */
647
648/*
649 * start the SMP system
650 */
651static void
652mp_enable(u_int boot_addr)
653{
984263bc
MD
654#if defined(APIC_IO)
655 int apic;
656 u_int ux;
657#endif /* APIC_IO */
981bebd1 658 vm_paddr_t mpfps_paddr;
f65c10b6 659 struct mptable_pos mpt;
984263bc
MD
660
661 POSTCODE(MP_ENABLE_POST);
662
281d9482 663 lapic_config();
984263bc 664
f65c10b6
SZ
665 mpfps_paddr = mptable_probe();
666 if (mpfps_paddr) {
667 mptable_map(&mpt, mpfps_paddr);
668 mptable_imcr(&mpt);
669 mptable_unmap(&mpt);
670 }
984263bc
MD
671#if defined(APIC_IO)
672
f65c10b6
SZ
673 if (!mpfps_paddr)
674 panic("no MP table, disable APIC_IO!\n");
675
676 mptable_map(&mpt, mpfps_paddr);
677
678 /*
679 * Examine the MP table for needed info
680 */
681 mptable_pass1(&mpt);
682 mptable_pass2(&mpt);
683
684 mptable_unmap(&mpt);
685
686 /* Post scan cleanup */
687 mptable_fix();
688
97359a5b
MD
689 setup_apic_irq_mapping();
690
984263bc
MD
691 /* fill the LOGICAL io_apic_versions table */
692 for (apic = 0; apic < mp_napics; ++apic) {
693 ux = io_apic_read(apic, IOAPIC_VER);
694 io_apic_versions[apic] = ux;
695 io_apic_set_id(apic, IO_TO_ID(apic));
696 }
697
698 /* program each IO APIC in the system */
699 for (apic = 0; apic < mp_napics; ++apic)
700 if (io_apic_setup(apic) < 0)
701 panic("IO APIC setup failure");
702
97359a5b
MD
703#endif /* APIC_IO */
704
705 /*
706 * These are required for SMP operation
707 */
708
984263bc
MD
709 /* install a 'Spurious INTerrupt' vector */
710 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
711 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
712
713 /* install an inter-CPU IPI for TLB invalidation */
714 setidt(XINVLTLB_OFFSET, Xinvltlb,
715 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716
96728c05
MD
717 /* install an inter-CPU IPI for IPIQ messaging */
718 setidt(XIPIQ_OFFSET, Xipiq,
719 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
78ea5a2a
SZ
720
721 /* install a timer vector */
722 setidt(XTIMER_OFFSET, Xtimer,
723 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc 724
984263bc
MD
725 /* install an inter-CPU IPI for CPU stop/restart */
726 setidt(XCPUSTOP_OFFSET, Xcpustop,
727 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
728
984263bc
MD
729 /* start each Application Processor */
730 start_all_aps(boot_addr);
731}
732
733
734/*
735 * look for the MP spec signature
736 */
737
738/* string defined by the Intel MP Spec as identifying the MP table */
739#define MP_SIG 0x5f504d5f /* _MP_ */
740#define NEXT(X) ((X) += 4)
741static int
3aba8f73 742mptable_search_sig(u_int32_t target, int count)
984263bc 743{
0f85efa2
SZ
744 vm_size_t map_size;
745 u_int32_t *addr;
746 int x, ret;
984263bc 747
aeb48299
SZ
748 KKASSERT(target != 0);
749
0f85efa2
SZ
750 map_size = count * sizeof(u_int32_t);
751 addr = pmap_mapdev((vm_paddr_t)target, map_size);
984263bc 752
aeb48299 753 ret = 0;
0f85efa2
SZ
754 for (x = 0; x < count; NEXT(x)) {
755 if (addr[x] == MP_SIG) {
756 /* make array index a byte index */
757 ret = target + (x * sizeof(u_int32_t));
758 break;
759 }
760 }
aeb48299 761
0f85efa2
SZ
762 pmap_unmapdev((vm_offset_t)addr, map_size);
763 return ret;
984263bc
MD
764}
765
766
984263bc
MD
767typedef struct BUSDATA {
768 u_char bus_id;
769 enum busTypes bus_type;
770} bus_datum;
771
772typedef struct INTDATA {
773 u_char int_type;
774 u_short int_flags;
775 u_char src_bus_id;
776 u_char src_bus_irq;
777 u_char dst_apic_id;
778 u_char dst_apic_int;
779 u_char int_vector;
780} io_int, local_int;
781
782typedef struct BUSTYPENAME {
783 u_char type;
784 char name[7];
785} bus_type_name;
786
29bb1d92
SW
787#ifdef APIC_IO
788
984263bc
MD
789static bus_type_name bus_type_table[] =
790{
791 {CBUS, "CBUS"},
792 {CBUSII, "CBUSII"},
793 {EISA, "EISA"},
794 {MCA, "MCA"},
795 {UNKNOWN_BUSTYPE, "---"},
796 {ISA, "ISA"},
797 {MCA, "MCA"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
802 {UNKNOWN_BUSTYPE, "---"},
803 {PCI, "PCI"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {XPRESS, "XPRESS"},
809 {UNKNOWN_BUSTYPE, "---"}
810};
811/* from MP spec v1.4, table 5-1 */
812static int default_data[7][5] =
813{
814/* nbus, id0, type0, id1, type1 */
815 {1, 0, ISA, 255, 255},
816 {1, 0, EISA, 255, 255},
817 {1, 0, EISA, 255, 255},
818 {1, 0, MCA, 255, 255},
819 {2, 0, ISA, 1, PCI},
820 {2, 0, EISA, 1, PCI},
821 {2, 0, MCA, 1, PCI}
822};
823
824
825/* the bus data */
826static bus_datum *bus_data;
827
828/* the IO INT data, one entry per possible APIC INTerrupt */
829static io_int *io_apic_ints;
984263bc 830static int nintrs;
4f6a8b30 831
97359a5b 832#endif
984263bc 833
a0873f07 834static int processor_entry (const struct PROCENTRY *entry, int cpu);
97359a5b 835#ifdef APIC_IO
c4717d5c
SZ
836static int bus_entry (const struct BUSENTRY *entry, int bus);
837static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
838static int int_entry (const struct INTENTRY *entry, int intr);
3ae0cd58 839static int lookup_bus_type (char *name);
29bb1d92 840#endif
984263bc 841
8658b5be
SZ
842#ifdef APIC_IO
843
844static int
845mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
846{
847 const struct IOAPICENTRY *ioapic_ent;
848
849 switch (type) {
850 case 1: /* bus_entry */
851 ++mp_nbusses;
852 break;
853
854 case 2: /* io_apic_entry */
855 ioapic_ent = pos;
856 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
857 io_apic_address[mp_napics++] =
858 (vm_offset_t)ioapic_ent->apic_address;
859 }
860 break;
861
862 case 3: /* int_entry */
863 ++nintrs;
864 break;
865 }
866 return 0;
867}
868
984263bc
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869/*
870 * 1st pass on motherboard's Intel MP specification table.
871 *
984263bc 872 * determines:
984263bc 873 * io_apic_address[N]
984263bc
MD
874 * mp_nbusses
875 * mp_napics
876 * nintrs
877 */
878static void
981bebd1 879mptable_pass1(struct mptable_pos *mpt)
984263bc 880{
981bebd1 881 mpfps_t fps;
8658b5be 882 int x;
984263bc
MD
883
884 POSTCODE(MPTABLE_PASS1_POST);
885
981bebd1
SZ
886 fps = mpt->mp_fps;
887 KKASSERT(fps != NULL);
f9c3b04f 888
984263bc 889 /* clear various tables */
8658b5be 890 for (x = 0; x < NAPICID; ++x)
984263bc 891 io_apic_address[x] = ~0; /* IO APIC address table */
984263bc 892
4f6a8b30 893 mp_nbusses = 0;
984263bc
MD
894 mp_napics = 0;
895 nintrs = 0;
984263bc
MD
896
897 /* check for use of 'default' configuration */
981bebd1 898 if (fps->mpfb1 != 0) {
984263bc 899 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
4f6a8b30 900 mp_nbusses = default_data[fps->mpfb1 - 1][0];
984263bc
MD
901 mp_napics = 1;
902 nintrs = 16;
8658b5be
SZ
903 } else {
904 int error;
905
906 error = mptable_iterate_entries(mpt->mp_cth,
907 mptable_ioapic_pass1_callback, NULL);
908 if (error)
909 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
984263bc 910 }
984263bc
MD
911}
912
c4717d5c
SZ
913struct mptable_ioapic2_cbarg {
914 int bus;
915 int apic;
916 int intr;
917};
918
919static int
920mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
921{
922 struct mptable_ioapic2_cbarg *arg = xarg;
923
924 switch (type) {
925 case 1:
926 if (bus_entry(pos, arg->bus))
927 ++arg->bus;
928 break;
929
930 case 2:
931 if (io_apic_entry(pos, arg->apic))
932 ++arg->apic;
933 break;
934
935 case 3:
936 if (int_entry(pos, arg->intr))
937 ++arg->intr;
938 break;
939 }
940 return 0;
941}
942
984263bc
MD
943/*
944 * 2nd pass on motherboard's Intel MP specification table.
945 *
946 * sets:
984263bc 947 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
984263bc
MD
948 * IO_TO_ID(N), logical IO to APIC ID table
949 * bus_data[N]
950 * io_apic_ints[N]
951 */
390b18b0 952static void
981bebd1 953mptable_pass2(struct mptable_pos *mpt)
984263bc 954{
c4717d5c 955 struct mptable_ioapic2_cbarg arg;
981bebd1 956 mpfps_t fps;
c4717d5c 957 int error, x;
984263bc
MD
958
959 POSTCODE(MPTABLE_PASS2_POST);
960
981bebd1
SZ
961 fps = mpt->mp_fps;
962 KKASSERT(fps != NULL);
963
984263bc
MD
964 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
965 M_DEVBUF, M_WAITOK);
966 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
e7b4468c 967 M_DEVBUF, M_WAITOK | M_ZERO);
1439c090 968 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984263bc
MD
969 M_DEVBUF, M_WAITOK);
970 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
971 M_DEVBUF, M_WAITOK);
972
c4717d5c
SZ
973 for (x = 0; x < mp_napics; x++)
974 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
984263bc
MD
975
976 /* clear various tables */
977 for (x = 0; x < NAPICID; ++x) {
97359a5b 978 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
984263bc
MD
979 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
980 }
981
982 /* clear bus data table */
983 for (x = 0; x < mp_nbusses; ++x)
984 bus_data[x].bus_id = 0xff;
985
986 /* clear IO APIC INT table */
987 for (x = 0; x < (nintrs + 1); ++x) {
988 io_apic_ints[x].int_type = 0xff;
989 io_apic_ints[x].int_vector = 0xff;
990 }
991
984263bc 992 /* check for use of 'default' configuration */
390b18b0
SZ
993 if (fps->mpfb1 != 0) {
994 mptable_default(fps->mpfb1);
995 return;
996 }
984263bc 997
c4717d5c
SZ
998 bzero(&arg, sizeof(arg));
999 error = mptable_iterate_entries(mpt->mp_cth,
1000 mptable_ioapic_pass2_callback, &arg);
1001 if (error)
1002 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
984263bc
MD
1003}
1004
29bb1d92
SW
1005#endif /* APIC_IO */
1006
984263bc
MD
1007/*
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1010 * in the table.
1011 *
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1014 *
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1018 */
44c36320
SZ
1019static int
1020mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
984263bc 1021{
44c36320 1022 int i, id, lcpus_max, logical_cpus;
984263bc 1023
984263bc 1024 if ((cpu_feature & CPUID_HTT) == 0)
44c36320 1025 return 0;
7ea07fd2
SZ
1026
1027 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1028 if (lcpus_max <= 1)
44c36320 1029 return 0;
984263bc 1030
90e8a35b 1031 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
7ea07fd2
SZ
1032 /*
1033 * INSTRUCTION SET REFERENCE, A-M (#253666)
1034 * Page 3-181, Table 3-20
1035 * "The nearest power-of-2 integer that is not smaller
1036 * than EBX[23:16] is the number of unique initial APIC
1037 * IDs reserved for addressing different logical
1038 * processors in a physical package."
1039 */
1040 for (i = 0; ; ++i) {
1041 if ((1 << i) >= lcpus_max) {
1042 lcpus_max = 1 << i;
1043 break;
1044 }
1045 }
1046 }
1047
44c36320
SZ
1048 KKASSERT(cpu_count != 0);
1049 if (cpu_count == lcpus_max) {
7ea07fd2 1050 /* We have nothing to fix */
44c36320
SZ
1051 return 0;
1052 } else if (cpu_count == 1) {
7ea07fd2
SZ
1053 /* XXX this may be incorrect */
1054 logical_cpus = lcpus_max;
1055 } else {
1056 int cur, prev, dist;
1057
1058 /*
1059 * Calculate the distances between two nearest
1060 * APIC IDs. If all such distances are same,
1061 * then it is the number of missing cpus that
1062 * we are going to fill later.
1063 */
1064 dist = cur = prev = -1;
1065 for (id = 0; id < MAXCPU; ++id) {
1066 if ((id_mask & 1 << id) == 0)
1067 continue;
1068
1069 cur = id;
1070 if (prev >= 0) {
1071 int new_dist = cur - prev;
1072
1073 if (dist < 0)
1074 dist = new_dist;
1075
1076 /*
1077 * Make sure that all distances
1078 * between two nearest APIC IDs
1079 * are same.
1080 */
1081 if (dist != new_dist)
44c36320 1082 return 0;
7ea07fd2
SZ
1083 }
1084 prev = cur;
1085 }
1086 if (dist == 1)
44c36320 1087 return 0;
7ea07fd2
SZ
1088
1089 /* Must be power of 2 */
1090 if (dist & (dist - 1))
44c36320 1091 return 0;
7ea07fd2
SZ
1092
1093 /* Can't exceed CPU package capacity */
1094 if (dist > lcpus_max)
1095 logical_cpus = lcpus_max;
1096 else
1097 logical_cpus = dist;
1098 }
1099
984263bc
MD
1100 /*
1101 * For each APIC ID of a CPU that is set in the mask,
1102 * scan the other candidate APIC ID's for this
1103 * physical processor. If any of those ID's are
1104 * already in the table, then kill the fixup.
1105 */
7ea07fd2 1106 for (id = 0; id < MAXCPU; id++) {
984263bc
MD
1107 if ((id_mask & 1 << id) == 0)
1108 continue;
1109 /* First, make sure we are on a logical_cpus boundary. */
1110 if (id % logical_cpus != 0)
44c36320 1111 return 0;
984263bc
MD
1112 for (i = id + 1; i < id + logical_cpus; i++)
1113 if ((id_mask & 1 << i) != 0)
44c36320 1114 return 0;
984263bc 1115 }
44c36320 1116 return logical_cpus;
984263bc 1117}
984263bc 1118
fa058384 1119static int
981bebd1
SZ
1120mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1121{
1122 mpfps_t fps = NULL;
1123 mpcth_t cth = NULL;
1124 vm_size_t cth_mapsz = 0;
1125
fa058384
SZ
1126 bzero(mpt, sizeof(*mpt));
1127
981bebd1
SZ
1128 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1129 if (fps->pap != 0) {
1130 /*
1131 * Map configuration table header to get
1132 * the base table size
1133 */
1134 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1135 cth_mapsz = cth->base_table_length;
1136 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1137
fa058384
SZ
1138 if (cth_mapsz < sizeof(*cth)) {
1139 kprintf("invalid base MP table length %d\n",
1140 (int)cth_mapsz);
1141 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1142 return EINVAL;
1143 }
1144
981bebd1
SZ
1145 /*
1146 * Map the base table
1147 */
1148 cth = pmap_mapdev(fps->pap, cth_mapsz);
1149 }
1150
1151 mpt->mp_fps = fps;
1152 mpt->mp_cth = cth;
1153 mpt->mp_cth_mapsz = cth_mapsz;
fa058384
SZ
1154
1155 return 0;
981bebd1
SZ
1156}
1157
1158static void
1159mptable_unmap(struct mptable_pos *mpt)
1160{
1161 if (mpt->mp_cth != NULL) {
1162 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1163 mpt->mp_cth = NULL;
1164 mpt->mp_cth_mapsz = 0;
1165 }
1166 if (mpt->mp_fps != NULL) {
1167 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1168 mpt->mp_fps = NULL;
1169 }
1170}
1171
97359a5b
MD
1172#ifdef APIC_IO
1173
984263bc
MD
1174void
1175assign_apic_irq(int apic, int intpin, int irq)
1176{
1177 int x;
1178
1179 if (int_to_apicintpin[irq].ioapic != -1)
1180 panic("assign_apic_irq: inconsistent table");
1181
1182 int_to_apicintpin[irq].ioapic = apic;
1183 int_to_apicintpin[irq].int_pin = intpin;
1184 int_to_apicintpin[irq].apic_address = ioapic[apic];
1185 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1186
1187 for (x = 0; x < nintrs; x++) {
1188 if ((io_apic_ints[x].int_type == 0 ||
1189 io_apic_ints[x].int_type == 3) &&
1190 io_apic_ints[x].int_vector == 0xff &&
1191 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1192 io_apic_ints[x].dst_apic_int == intpin)
1193 io_apic_ints[x].int_vector = irq;
1194 }
1195}
1196
1197void
1198revoke_apic_irq(int irq)
1199{
1200 int x;
1201 int oldapic;
1202 int oldintpin;
1203
1204 if (int_to_apicintpin[irq].ioapic == -1)
1205 panic("revoke_apic_irq: inconsistent table");
1206
1207 oldapic = int_to_apicintpin[irq].ioapic;
1208 oldintpin = int_to_apicintpin[irq].int_pin;
1209
1210 int_to_apicintpin[irq].ioapic = -1;
1211 int_to_apicintpin[irq].int_pin = 0;
1212 int_to_apicintpin[irq].apic_address = NULL;
1213 int_to_apicintpin[irq].redirindex = 0;
1214
1215 for (x = 0; x < nintrs; x++) {
1216 if ((io_apic_ints[x].int_type == 0 ||
1217 io_apic_ints[x].int_type == 3) &&
1218 io_apic_ints[x].int_vector != 0xff &&
1219 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1220 io_apic_ints[x].dst_apic_int == oldintpin)
1221 io_apic_ints[x].int_vector = 0xff;
1222 }
1223}
1224
1439c090
MD
1225/*
1226 * Allocate an IRQ
1227 */
984263bc
MD
1228static void
1229allocate_apic_irq(int intr)
1230{
1231 int apic;
1232 int intpin;
1233 int irq;
1234
1235 if (io_apic_ints[intr].int_vector != 0xff)
1236 return; /* Interrupt handler already assigned */
1237
1238 if (io_apic_ints[intr].int_type != 0 &&
1239 (io_apic_ints[intr].int_type != 3 ||
1240 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1241 io_apic_ints[intr].dst_apic_int == 0)))
1242 return; /* Not INT or ExtInt on != (0, 0) */
1243
1244 irq = 0;
1245 while (irq < APIC_INTMAPSIZE &&
1246 int_to_apicintpin[irq].ioapic != -1)
1247 irq++;
1248
1249 if (irq >= APIC_INTMAPSIZE)
1250 return; /* No free interrupt handlers */
1251
1252 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1253 intpin = io_apic_ints[intr].dst_apic_int;
1254
1255 assign_apic_irq(apic, intpin, irq);
4612bd39 1256 io_apic_setup_intpin(apic, intpin);
984263bc
MD
1257}
1258
1259
1260static void
1261swap_apic_id(int apic, int oldid, int newid)
1262{
1263 int x;
1264 int oapic;
1265
1266
1267 if (oldid == newid)
1268 return; /* Nothing to do */
1269
26be20a0 1270 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
984263bc
MD
1271 apic, oldid, newid);
1272
1273 /* Swap physical APIC IDs in interrupt entries */
1274 for (x = 0; x < nintrs; x++) {
1275 if (io_apic_ints[x].dst_apic_id == oldid)
1276 io_apic_ints[x].dst_apic_id = newid;
1277 else if (io_apic_ints[x].dst_apic_id == newid)
1278 io_apic_ints[x].dst_apic_id = oldid;
1279 }
1280
1281 /* Swap physical APIC IDs in IO_TO_ID mappings */
1282 for (oapic = 0; oapic < mp_napics; oapic++)
1283 if (IO_TO_ID(oapic) == newid)
1284 break;
1285
1286 if (oapic < mp_napics) {
26be20a0 1287 kprintf("Changing APIC ID for IO APIC #%d from "
984263bc
MD
1288 "%d to %d in MP table\n",
1289 oapic, newid, oldid);
1290 IO_TO_ID(oapic) = oldid;
1291 }
1292 IO_TO_ID(apic) = newid;
1293}
1294
1295
1296static void
1297fix_id_to_io_mapping(void)
1298{
1299 int x;
1300
1301 for (x = 0; x < NAPICID; x++)
1302 ID_TO_IO(x) = -1;
1303
1304 for (x = 0; x <= mp_naps; x++)
1305 if (CPU_TO_ID(x) < NAPICID)
1306 ID_TO_IO(CPU_TO_ID(x)) = x;
1307
1308 for (x = 0; x < mp_napics; x++)
1309 if (IO_TO_ID(x) < NAPICID)
1310 ID_TO_IO(IO_TO_ID(x)) = x;
1311}
1312
1313
1314static int
1315first_free_apic_id(void)
1316{
1317 int freeid, x;
1318
1319 for (freeid = 0; freeid < NAPICID; freeid++) {
1320 for (x = 0; x <= mp_naps; x++)
1321 if (CPU_TO_ID(x) == freeid)
1322 break;
1323 if (x <= mp_naps)
1324 continue;
1325 for (x = 0; x < mp_napics; x++)
1326 if (IO_TO_ID(x) == freeid)
1327 break;
1328 if (x < mp_napics)
1329 continue;
1330 return freeid;
1331 }
1332 return freeid;
1333}
1334
1335
1336static int
1337io_apic_id_acceptable(int apic, int id)
1338{
1339 int cpu; /* Logical CPU number */
1340 int oapic; /* Logical IO APIC number for other IO APIC */
1341
1342 if (id >= NAPICID)
1343 return 0; /* Out of range */
1344
1345 for (cpu = 0; cpu <= mp_naps; cpu++)
1346 if (CPU_TO_ID(cpu) == id)
1347 return 0; /* Conflict with CPU */
1348
1349 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1350 if (IO_TO_ID(oapic) == id)
1351 return 0; /* Conflict with other APIC */
1352
1353 return 1; /* ID is acceptable for IO APIC */
1354}
1355
1439c090
MD
1356static
1357io_int *
1358io_apic_find_int_entry(int apic, int pin)
1359{
1360 int x;
1361
1362 /* search each of the possible INTerrupt sources */
1363 for (x = 0; x < nintrs; ++x) {
1364 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1365 (pin == io_apic_ints[x].dst_apic_int))
1366 return (&io_apic_ints[x]);
1367 }
1368 return NULL;
1369}
1370
984263bc
MD
1371/*
1372 * parse an Intel MP specification table
1373 */
1374static void
3aba8f73 1375mptable_fix(void)
984263bc 1376{
4f6a8b30 1377 int x;
984263bc 1378 int id;
984263bc
MD
1379 int apic; /* IO APIC unit number */
1380 int freeid; /* Free physical APIC ID */
1381 int physid; /* Current physical IO APIC ID */
1439c090 1382 io_int *io14;
97359a5b
MD
1383 int bus_0 = 0; /* Stop GCC warning */
1384 int bus_pci = 0; /* Stop GCC warning */
1385 int num_pci_bus;
984263bc
MD
1386
1387 /*
1388 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1389 * did it wrong. The MP spec says that when more than 1 PCI bus
1390 * exists the BIOS must begin with bus entries for the PCI bus and use
1391 * actual PCI bus numbering. This implies that when only 1 PCI bus
1392 * exists the BIOS can choose to ignore this ordering, and indeed many
1393 * MP motherboards do ignore it. This causes a problem when the PCI
1394 * sub-system makes requests of the MP sub-system based on PCI bus
1395 * numbers. So here we look for the situation and renumber the
1396 * busses and associated INTs in an effort to "make it right".
1397 */
1398
1399 /* find bus 0, PCI bus, count the number of PCI busses */
1400 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1401 if (bus_data[x].bus_id == 0) {
1402 bus_0 = x;
1403 }
1404 if (bus_data[x].bus_type == PCI) {
1405 ++num_pci_bus;
1406 bus_pci = x;
1407 }
1408 }
1409 /*
1410 * bus_0 == slot of bus with ID of 0
1411 * bus_pci == slot of last PCI bus encountered
1412 */
1413
1414 /* check the 1 PCI bus case for sanity */
1415 /* if it is number 0 all is well */
1416 if (num_pci_bus == 1 &&
1417 bus_data[bus_pci].bus_id != 0) {
1418
1419 /* mis-numbered, swap with whichever bus uses slot 0 */
1420
1421 /* swap the bus entry types */
1422 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1423 bus_data[bus_0].bus_type = PCI;
1424
1425 /* swap each relavant INTerrupt entry */
1426 id = bus_data[bus_pci].bus_id;
1427 for (x = 0; x < nintrs; ++x) {
1428 if (io_apic_ints[x].src_bus_id == id) {
1429 io_apic_ints[x].src_bus_id = 0;
1430 }
1431 else if (io_apic_ints[x].src_bus_id == 0) {
1432 io_apic_ints[x].src_bus_id = id;
1433 }
1434 }
1435 }
1436
1437 /* Assign IO APIC IDs.
1438 *
1439 * First try the existing ID. If a conflict is detected, try
1440 * the ID in the MP table. If a conflict is still detected, find
1441 * a free id.
1442 *
1443 * We cannot use the ID_TO_IO table before all conflicts has been
1444 * resolved and the table has been corrected.
1445 */
1446 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1447
1448 /* First try to use the value set by the BIOS */
1449 physid = io_apic_get_id(apic);
1450 if (io_apic_id_acceptable(apic, physid)) {
1451 if (IO_TO_ID(apic) != physid)
1452 swap_apic_id(apic, IO_TO_ID(apic), physid);
1453 continue;
1454 }
1455
1456 /* Then check if the value in the MP table is acceptable */
1457 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1458 continue;
1459
1460 /* Last resort, find a free APIC ID and use it */
1461 freeid = first_free_apic_id();
1462 if (freeid >= NAPICID)
1463 panic("No free physical APIC IDs found");
1464
1465 if (io_apic_id_acceptable(apic, freeid)) {
1466 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1467 continue;
1468 }
1469 panic("Free physical APIC ID not usable");
1470 }
1471 fix_id_to_io_mapping();
1472
1473 /* detect and fix broken Compaq MP table */
1474 if (apic_int_type(0, 0) == -1) {
26be20a0 1475 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
984263bc
MD
1476 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1477 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1478 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1479 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1480 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1481 nintrs++;
ad12f88c 1482 } else if (apic_int_type(0, 0) == 0) {
26be20a0 1483 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
ad12f88c
HP
1484 for (x = 0; x < nintrs; ++x)
1485 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1486 (0 == io_apic_ints[x].dst_apic_int)) {
1487 io_apic_ints[x].int_type = 3;
1488 io_apic_ints[x].int_vector = 0xff;
1489 break;
1490 }
984263bc 1491 }
1439c090
MD
1492
1493 /*
1494 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1495 * controllers universally come in pairs. If IRQ 14 is specified
1496 * as an ISA interrupt, then IRQ 15 had better be too.
1497 *
1498 * [ Shuttle XPC / AMD Athlon X2 ]
1499 * The MPTable is missing an entry for IRQ 15. Note that the
1500 * ACPI table has an entry for both 14 and 15.
1501 */
1502 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
26be20a0 1503 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439c090
MD
1504 io14 = io_apic_find_int_entry(0, 14);
1505 io_apic_ints[nintrs] = *io14;
1506 io_apic_ints[nintrs].src_bus_irq = 15;
1507 io_apic_ints[nintrs].dst_apic_int = 15;
1508 nintrs++;
1509 }
984263bc
MD
1510}
1511
984263bc
MD
1512/* Assign low level interrupt handlers */
1513static void
1514setup_apic_irq_mapping(void)
1515{
1516 int x;
1517 int int_vector;
1518
1519 /* Clear array */
1520 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1521 int_to_apicintpin[x].ioapic = -1;
1522 int_to_apicintpin[x].int_pin = 0;
1523 int_to_apicintpin[x].apic_address = NULL;
1524 int_to_apicintpin[x].redirindex = 0;
ea689d1c
SZ
1525
1526 /* Default to masked */
1527 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
984263bc
MD
1528 }
1529
1530 /* First assign ISA/EISA interrupts */
1531 for (x = 0; x < nintrs; x++) {
1532 int_vector = io_apic_ints[x].src_bus_irq;
1533 if (int_vector < APIC_INTMAPSIZE &&
1534 io_apic_ints[x].int_vector == 0xff &&
1535 int_to_apicintpin[int_vector].ioapic == -1 &&
1536 (apic_int_is_bus_type(x, ISA) ||
1537 apic_int_is_bus_type(x, EISA)) &&
1538 io_apic_ints[x].int_type == 0) {
1539 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1540 io_apic_ints[x].dst_apic_int,
1541 int_vector);
1542 }
1543 }
1544
1545 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1546 for (x = 0; x < nintrs; x++) {
1547 if (io_apic_ints[x].dst_apic_int == 0 &&
1548 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1549 io_apic_ints[x].int_vector == 0xff &&
1550 int_to_apicintpin[0].ioapic == -1 &&
1551 io_apic_ints[x].int_type == 3) {
1552 assign_apic_irq(0, 0, 0);
1553 break;
1554 }
1555 }
4612bd39 1556 /* PCI interrupt assignment is deferred */
984263bc
MD
1557}
1558
97359a5b 1559#endif
984263bc 1560
a9112655
SZ
1561void
1562mp_set_cpuids(int cpu_id, int apic_id)
1563{
1564 CPU_TO_ID(cpu_id) = apic_id;
1565 ID_TO_CPU(apic_id) = cpu_id;
1566}
1567
984263bc 1568static int
a0873f07 1569processor_entry(const struct PROCENTRY *entry, int cpu)
984263bc 1570{
bd8aa7e2
SZ
1571 KKASSERT(cpu > 0);
1572
984263bc
MD
1573 /* check for usability */
1574 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1575 return 0;
1576
984263bc
MD
1577 /* check for BSP flag */
1578 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
a9112655 1579 mp_set_cpuids(0, entry->apic_id);
984263bc
MD
1580 return 0; /* its already been counted */
1581 }
1582
1583 /* add another AP to list, if less than max number of CPUs */
1584 else if (cpu < MAXCPU) {
a9112655 1585 mp_set_cpuids(cpu, entry->apic_id);
984263bc
MD
1586 return 1;
1587 }
1588
1589 return 0;
1590}
1591
4f6a8b30 1592#ifdef APIC_IO
984263bc
MD
1593
1594static int
c4717d5c 1595bus_entry(const struct BUSENTRY *entry, int bus)
984263bc
MD
1596{
1597 int x;
1598 char c, name[8];
1599
1600 /* encode the name into an index */
1601 for (x = 0; x < 6; ++x) {
1602 if ((c = entry->bus_type[x]) == ' ')
1603 break;
1604 name[x] = c;
1605 }
1606 name[x] = '\0';
1607
1608 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1609 panic("unknown bus type: '%s'", name);
1610
1611 bus_data[bus].bus_id = entry->bus_id;
1612 bus_data[bus].bus_type = x;
1613
1614 return 1;
1615}
1616
984263bc 1617static int
c4717d5c 1618io_apic_entry(const struct IOAPICENTRY *entry, int apic)
984263bc
MD
1619{
1620 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1621 return 0;
1622
1623 IO_TO_ID(apic) = entry->apic_id;
c163176b 1624 ID_TO_IO(entry->apic_id) = apic;
984263bc
MD
1625
1626 return 1;
1627}
1628
984263bc
MD
1629static int
1630lookup_bus_type(char *name)
1631{
1632 int x;
1633
1634 for (x = 0; x < MAX_BUSTYPE; ++x)
1635 if (strcmp(bus_type_table[x].name, name) == 0)
1636 return bus_type_table[x].type;
1637
1638 return UNKNOWN_BUSTYPE;
1639}
1640
984263bc 1641static int
c4717d5c 1642int_entry(const struct INTENTRY *entry, int intr)
984263bc
MD
1643{
1644 int apic;
1645
1646 io_apic_ints[intr].int_type = entry->int_type;
1647 io_apic_ints[intr].int_flags = entry->int_flags;
1648 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1649 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1650 if (entry->dst_apic_id == 255) {
1651 /* This signal goes to all IO APICS. Select an IO APIC
1652 with sufficient number of interrupt pins */
1653 for (apic = 0; apic < mp_napics; apic++)
1654 if (((io_apic_read(apic, IOAPIC_VER) &
1655 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1656 entry->dst_apic_int)
1657 break;
1658 if (apic < mp_napics)
1659 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1660 else
1661 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1662 } else
1663 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1664 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1665
1666 return 1;
1667}
1668
984263bc
MD
1669static int
1670apic_int_is_bus_type(int intr, int bus_type)
1671{
1672 int bus;
1673
1674 for (bus = 0; bus < mp_nbusses; ++bus)
1675 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1676 && ((int) bus_data[bus].bus_type == bus_type))
1677 return 1;
1678
1679 return 0;
1680}
1681
984263bc
MD
1682/*
1683 * Given a traditional ISA INT mask, return an APIC mask.
1684 */
1685u_int
1686isa_apic_mask(u_int isa_mask)
1687{
1688 int isa_irq;
1689 int apic_pin;
1690
1691#if defined(SKIP_IRQ15_REDIRECT)
1692 if (isa_mask == (1 << 15)) {
26be20a0 1693 kprintf("skipping ISA IRQ15 redirect\n");
984263bc
MD
1694 return isa_mask;
1695 }
1696#endif /* SKIP_IRQ15_REDIRECT */
1697
1698 isa_irq = ffs(isa_mask); /* find its bit position */
1699 if (isa_irq == 0) /* doesn't exist */
1700 return 0;
1701 --isa_irq; /* make it zero based */
1702
1703 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1704 if (apic_pin == -1)
1705 return 0;
1706
1707 return (1 << apic_pin); /* convert pin# to a mask */
1708}
1709
984263bc
MD
1710/*
1711 * Determine which APIC pin an ISA/EISA INT is attached to.
1712 */
1713#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1714#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1715#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1716#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1717
1718#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1719int
1720isa_apic_irq(int isa_irq)
1721{
1722 int intr;
1723
1724 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1725 if (INTTYPE(intr) == 0) { /* standard INT */
1726 if (SRCBUSIRQ(intr) == isa_irq) {
1727 if (apic_int_is_bus_type(intr, ISA) ||
1728 apic_int_is_bus_type(intr, EISA)) {
1729 if (INTIRQ(intr) == 0xff)
1730 return -1; /* unassigned */
1731 return INTIRQ(intr); /* found */
1732 }
1733 }
1734 }
1735 }
1736 return -1; /* NOT found */
1737}
1738
1739
1740/*
1741 * Determine which APIC pin a PCI INT is attached to.
1742 */
1743#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1744#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1745#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1746int
1747pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1748{
1749 int intr;
1750
1751 --pciInt; /* zero based */
1752
1439c090 1753 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
984263bc
MD
1754 if ((INTTYPE(intr) == 0) /* standard INT */
1755 && (SRCBUSID(intr) == pciBus)
1756 && (SRCBUSDEVICE(intr) == pciDevice)
1439c090 1757 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
984263bc 1758 if (apic_int_is_bus_type(intr, PCI)) {
4612bd39
AP
1759 if (INTIRQ(intr) == 0xff)
1760 allocate_apic_irq(intr);
1761 if (INTIRQ(intr) == 0xff)
984263bc
MD
1762 return -1; /* unassigned */
1763 return INTIRQ(intr); /* exact match */
1764 }
1439c090
MD
1765 }
1766 }
984263bc
MD
1767
1768 return -1; /* NOT found */
1769}
1770
1771int
1772next_apic_irq(int irq)
1773{
1774 int intr, ointr;
1775 int bus, bustype;
1776
1777 bus = 0;
1778 bustype = 0;
1779 for (intr = 0; intr < nintrs; intr++) {
1780 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1781 continue;
1782 bus = SRCBUSID(intr);
1783 bustype = apic_bus_type(bus);
1784 if (bustype != ISA &&
1785 bustype != EISA &&
1786 bustype != PCI)
1787 continue;
1788 break;
1789 }
1790 if (intr >= nintrs) {
1791 return -1;
1792 }
1793 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1794 if (INTTYPE(ointr) != 0)
1795 continue;
1796 if (bus != SRCBUSID(ointr))
1797 continue;
1798 if (bustype == PCI) {
1799 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1800 continue;
1801 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1802 continue;
1803 }
1804 if (bustype == ISA || bustype == EISA) {
1805 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1806 continue;
1807 }
1808 if (INTPIN(intr) == INTPIN(ointr))
1809 continue;
1810 break;
1811 }
1812 if (ointr >= nintrs) {
1813 return -1;
1814 }
1815 return INTIRQ(ointr);
1816}
1817#undef SRCBUSLINE
1818#undef SRCBUSDEVICE
1819#undef SRCBUSID
1820#undef SRCBUSIRQ
1821
1822#undef INTPIN
1823#undef INTIRQ
1824#undef INTAPIC
1825#undef INTTYPE
1826
97359a5b 1827#endif
984263bc
MD
1828
1829/*
1830 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1831 *
1832 * XXX FIXME:
1833 * Exactly what this means is unclear at this point. It is a solution
1834 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1835 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1836 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1837 * option.
1838 */
1839int
1840undirect_isa_irq(int rirq)
1841{
1842#if defined(READY)
1843 if (bootverbose)
26be20a0 1844 kprintf("Freeing redirected ISA irq %d.\n", rirq);
984263bc 1845 /** FIXME: tickle the MB redirector chip */
c044141b 1846 return /* XXX */;
984263bc
MD
1847#else
1848 if (bootverbose)
26be20a0 1849 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
984263bc
MD
1850 return 0;
1851#endif /* READY */
1852}
1853
1854
1855/*
1856 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1857 */
1858int
1859undirect_pci_irq(int rirq)
1860{
1861#if defined(READY)
1862 if (bootverbose)
26be20a0 1863 kprintf("Freeing redirected PCI irq %d.\n", rirq);
984263bc
MD
1864
1865 /** FIXME: tickle the MB redirector chip */
c044141b 1866 return /* XXX */;
984263bc
MD
1867#else
1868 if (bootverbose)
26be20a0 1869 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
984263bc
MD
1870 rirq);
1871 return 0;
1872#endif /* READY */
1873}
1874
1875
4f6a8b30
SZ
1876#ifdef APIC_IO
1877
984263bc
MD
1878/*
1879 * given a bus ID, return:
1880 * the bus type if found
1881 * -1 if NOT found
1882 */
1883int
1884apic_bus_type(int id)
1885{
1886 int x;
1887
1888 for (x = 0; x < mp_nbusses; ++x)
1889 if (bus_data[x].bus_id == id)
1890 return bus_data[x].bus_type;
1891
1892 return -1;
1893}
1894
984263bc
MD
1895/*
1896 * given a LOGICAL APIC# and pin#, return:
1897 * the associated src bus ID if found
1898 * -1 if NOT found
1899 */
1900int
1901apic_src_bus_id(int apic, int pin)
1902{
1903 int x;
1904
1905 /* search each of the possible INTerrupt sources */
1906 for (x = 0; x < nintrs; ++x)
1907 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1908 (pin == io_apic_ints[x].dst_apic_int))
1909 return (io_apic_ints[x].src_bus_id);
1910
1911 return -1; /* NOT found */
1912}
1913
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MD
1914/*
1915 * given a LOGICAL APIC# and pin#, return:
1916 * the associated src bus IRQ if found
1917 * -1 if NOT found
1918 */
1919int
1920apic_src_bus_irq(int apic, int pin)
1921{
1922 int x;
1923
1924 for (x = 0; x < nintrs; x++)
1925 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1926 (pin == io_apic_ints[x].dst_apic_int))
1927 return (io_apic_ints[x].src_bus_irq);
1928
1929 return -1; /* NOT found */
1930}
1931
1932
1933/*
1934 * given a LOGICAL APIC# and pin#, return:
1935 * the associated INTerrupt type if found
1936 * -1 if NOT found
1937 */
1938int
1939apic_int_type(int apic, int pin)
1940{
1941 int x;
1942
1943 /* search each of the possible INTerrupt sources */
1439c090 1944 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1945 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1946 (pin == io_apic_ints[x].dst_apic_int))
1947 return (io_apic_ints[x].int_type);
1439c090 1948 }
984263bc
MD
1949 return -1; /* NOT found */
1950}
1951
1439c090
MD
1952/*
1953 * Return the IRQ associated with an APIC pin
1954 */
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MD
1955int
1956apic_irq(int apic, int pin)
1957{
1958 int x;
1959 int res;
1960
1439c090 1961 for (x = 0; x < nintrs; ++x) {
984263bc
MD
1962 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1963 (pin == io_apic_ints[x].dst_apic_int)) {
1964 res = io_apic_ints[x].int_vector;
1965 if (res == 0xff)
1966 return -1;
1967 if (apic != int_to_apicintpin[res].ioapic)
1439c090 1968 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
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MD
1969 if (pin != int_to_apicintpin[res].int_pin)
1970 panic("apic_irq inconsistent table (2)");
1971 return res;
1972 }
1439c090 1973 }
984263bc
MD
1974 return -1;
1975}
1976
1977
1978/*
1979 * given a LOGICAL APIC# and pin#, return:
1980 * the associated trigger mode if found
1981 * -1 if NOT found
1982 */
1983int
1984apic_trigger(int apic, int pin)
1985{
1986 int x;
1987
1988 /* search each of the possible INTerrupt sources */
1989 for (x = 0; x < nintrs; ++x)
1990 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1991 (pin == io_apic_ints[x].dst_apic_int))
1992 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1993
1994 return -1; /* NOT found */
1995}
1996
1997
1998/*
1999 * given a LOGICAL APIC# and pin#, return:
2000 * the associated 'active' level if found
2001 * -1 if NOT found
2002 */
2003int
2004apic_polarity(int apic, int pin)
2005{
2006 int x;
2007
2008 /* search each of the possible INTerrupt sources */
2009 for (x = 0; x < nintrs; ++x)
2010 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2011 (pin == io_apic_ints[x].dst_apic_int))
2012 return (io_apic_ints[x].int_flags & 0x03);
2013
2014 return -1; /* NOT found */
2015}
2016
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MD
2017/*
2018 * set data according to MP defaults
2019 * FIXME: probably not complete yet...
2020 */
2021static void
3aba8f73 2022mptable_default(int type)
984263bc 2023{
984263bc
MD
2024 int io_apic_id;
2025 int pin;
984263bc
MD
2026
2027#if 0
26be20a0 2028 kprintf(" MP default config type: %d\n", type);
984263bc
MD
2029 switch (type) {
2030 case 1:
26be20a0 2031 kprintf(" bus: ISA, APIC: 82489DX\n");
984263bc
MD
2032 break;
2033 case 2:
26be20a0 2034 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2035 break;
2036 case 3:
26be20a0 2037 kprintf(" bus: EISA, APIC: 82489DX\n");
984263bc
MD
2038 break;
2039 case 4:
26be20a0 2040 kprintf(" bus: MCA, APIC: 82489DX\n");
984263bc
MD
2041 break;
2042 case 5:
26be20a0 2043 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
984263bc
MD
2044 break;
2045 case 6:
26be20a0 2046 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
984263bc
MD
2047 break;
2048 case 7:
26be20a0 2049 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
984263bc
MD
2050 break;
2051 default:
26be20a0 2052 kprintf(" future type\n");
984263bc
MD
2053 break;
2054 /* NOTREACHED */
2055 }
2056#endif /* 0 */
2057
984263bc
MD
2058 /* one and only IO APIC */
2059 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2060
2061 /*
2062 * sanity check, refer to MP spec section 3.6.6, last paragraph
2063 * necessary as some hardware isn't properly setting up the IO APIC
2064 */
2065#if defined(REALLY_ANAL_IOAPICID_VALUE)
2066 if (io_apic_id != 2) {
2067#else
2068 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2069#endif /* REALLY_ANAL_IOAPICID_VALUE */
2070 io_apic_set_id(0, 2);
2071 io_apic_id = 2;
2072 }
2073 IO_TO_ID(0) = io_apic_id;
2074 ID_TO_IO(io_apic_id) = 0;
984263bc
MD
2075
2076 /* fill out bus entries */
2077 switch (type) {
2078 case 1:
2079 case 2:
2080 case 3:
2081 case 4:
2082 case 5:
2083 case 6:
2084 case 7:
2085 bus_data[0].bus_id = default_data[type - 1][1];
2086 bus_data[0].bus_type = default_data[type - 1][2];
2087 bus_data[1].bus_id = default_data[type - 1][3];
2088 bus_data[1].bus_type = default_data[type - 1][4];
2089 break;
2090
2091 /* case 4: case 7: MCA NOT supported */
2092 default: /* illegal/reserved */
2093 panic("BAD default MP config: %d", type);
2094 /* NOTREACHED */
2095 }
2096
984263bc
MD
2097 /* general cases from MP v1.4, table 5-2 */
2098 for (pin = 0; pin < 16; ++pin) {
2099 io_apic_ints[pin].int_type = 0;
2100 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2101 io_apic_ints[pin].src_bus_id = 0;
2102 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2103 io_apic_ints[pin].dst_apic_id = io_apic_id;
2104 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2105 }
2106
2107 /* special cases from MP v1.4, table 5-2 */
2108 if (type == 2) {
2109 io_apic_ints[2].int_type = 0xff; /* N/C */
2110 io_apic_ints[13].int_type = 0xff; /* N/C */
2111#if !defined(APIC_MIXED_MODE)
2112 /** FIXME: ??? */
2113 panic("sorry, can't support type 2 default yet");
2114#endif /* APIC_MIXED_MODE */
2115 }
2116 else
2117 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2118
2119 if (type == 7)
2120 io_apic_ints[0].int_type = 0xff; /* N/C */
2121 else
2122 io_apic_ints[0].int_type = 3; /* vectored 8259 */
984263bc
MD
2123}
2124
29bb1d92
SW
2125#endif /* APIC_IO */
2126
984263bc 2127/*
f13b5eec
MD
2128 * Map a physical memory address representing I/O into KVA. The I/O
2129 * block is assumed not to cross a page boundary.
2130 */
2131void *
2132permanent_io_mapping(vm_paddr_t pa)
2133{
2134 vm_offset_t vaddr;
2135 int pgeflag;
2136 int i;
2137
2138 KKASSERT(pa < 0x100000000LL);
2139
2140 pgeflag = 0; /* not used for SMP yet */
2141
2142 /*
2143 * If the requested physical address has already been incidently
2144 * mapped, just use the existing mapping. Otherwise create a new
2145 * mapping.
2146 */
2147 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2148 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2149 ((vm_offset_t)pa & PG_FRAME)) {
2150 break;
2151 }
2152 }
2153 if (i == SMPpt_alloc_index) {
2154 if (i == NPTEPG - 2) {
2155 panic("permanent_io_mapping: We ran out of space"
2156 " in SMPpt[]!");
2157 }
5277b9f6 2158 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
f13b5eec
MD
2159 ((vm_offset_t)pa & PG_FRAME));
2160 ++SMPpt_alloc_index;
2161 }
2162 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2163 ((vm_offset_t)pa & PAGE_MASK);
2164 return ((void *)vaddr);
2165}
2166
2167/*
984263bc
MD
2168 * start each AP in our list
2169 */
2170static int
2171start_all_aps(u_int boot_addr)
2172{
b45759e1
MD
2173 int x, i, pg;
2174 int shift;
bb467734
MD
2175 int smicount;
2176 int smibest;
2177 int smilast;
984263bc
MD
2178 u_char mpbiosreason;
2179 u_long mpbioswarmvec;
8a8d5d85 2180 struct mdglobaldata *gd;
0f7a3396 2181 struct privatespace *ps;
984263bc
MD
2182 char *stack;
2183 uintptr_t kptbase;
2184
2185 POSTCODE(START_ALL_APS_POST);
2186
b52c8db0
SZ
2187 /* Initialize BSP's local APIC */
2188 apic_initialize(TRUE);
984263bc
MD
2189
2190 /* install the AP 1st level boot code */
2191 install_ap_tramp(boot_addr);
2192
2193
2194 /* save the current value of the warm-start vector */
2195 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
984263bc
MD
2196 outb(CMOS_REG, BIOS_RESET);
2197 mpbiosreason = inb(CMOS_DATA);
984263bc 2198
bb467734
MD
2199 /* setup a vector to our boot code */
2200 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2201 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2202 outb(CMOS_REG, BIOS_RESET);
2203 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2204
2205 /*
2206 * If we have a TSC we can figure out the SMI interrupt rate.
2207 * The SMI does not necessarily use a constant rate. Spend
2208 * up to 250ms trying to figure it out.
2209 */
2210 smibest = 0;
2211 if (cpu_feature & CPUID_TSC) {
2212 set_apic_timer(275000);
2213 smilast = read_apic_timer();
2214 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2215 smicount = smitest();
2216 if (smibest == 0 || smilast - smicount < smibest)
2217 smibest = smilast - smicount;
2218 smilast = smicount;
2219 }
2220 if (smibest > 250000)
2221 smibest = 0;
2222 if (smibest) {
2223 smibest = smibest * (int64_t)1000000 /
2224 get_apic_timer_frequency();
2225 }
2226 }
2227 if (smibest)
2228 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2229 1000000 / smibest, smibest);
2230
2231
984263bc
MD
2232 /* set up temporary P==V mapping for AP boot */
2233 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2234 kptbase = (uintptr_t)(void *)KPTphys;
a44bdeec 2235 for (x = 0; x < NKPT; x++) {
984263bc
MD
2236 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2237 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
a44bdeec 2238 }
0f7a3396 2239 cpu_invltlb();
984263bc
MD
2240
2241 /* start each AP */
2242 for (x = 1; x <= mp_naps; ++x) {
2243
2244 /* This is a bit verbose, it will go away soon. */
2245
2246 /* first page of AP's private space */
2247 pg = x * i386_btop(sizeof(struct privatespace));
2248
81c04d07 2249 /* allocate new private data page(s) */
e4846942 2250 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
81c04d07 2251 MDGLOBALDATA_BASEALLOC_SIZE);
984263bc 2252 /* wire it into the private page table page */
81c04d07
MD
2253 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2254 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2255 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2256 }
2257 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2258
2259 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2260 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2261 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2262 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
984263bc
MD
2263
2264 /* allocate and set up an idle stack data page */
e4846942 2265 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
8a8d5d85 2266 for (i = 0; i < UPAGES; i++) {
81c04d07 2267 SMPpt[pg + 4 + i] = (pt_entry_t)
b5b32410 2268 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
8a8d5d85 2269 }
984263bc 2270
8a8d5d85
MD
2271 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2272 bzero(gd, sizeof(*gd));
0f7a3396 2273 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
8a8d5d85 2274
984263bc 2275 /* prime data page for it to use */
8a8d5d85 2276 mi_gdinit(&gd->mi, x);
8ad65e08 2277 cpu_gdinit(gd, x);
81c04d07
MD
2278 gd->gd_CMAP1 = &SMPpt[pg + 0];
2279 gd->gd_CMAP2 = &SMPpt[pg + 1];
2280 gd->gd_CMAP3 = &SMPpt[pg + 2];
2281 gd->gd_PMAP1 = &SMPpt[pg + 3];
0f7a3396
MD
2282 gd->gd_CADDR1 = ps->CPAGE1;
2283 gd->gd_CADDR2 = ps->CPAGE2;
2284 gd->gd_CADDR3 = ps->CPAGE3;
2285 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
9388fcaa
MD
2286
2287 /*
2288 * Per-cpu pmap for get_ptbase().
2289 */
2290 gd->gd_GDADDR1= (unsigned *)
2291 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2292 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2293
e4846942 2294 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
96728c05 2295 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
984263bc 2296
8a8d5d85
MD
2297 /*
2298 * Setup the AP boot stack
2299 */
0f7a3396 2300 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
984263bc
MD
2301 bootAP = x;
2302
2303 /* attempt to start the Application Processor */
2304 CHECK_INIT(99); /* setup checkpoints */
bb467734 2305 if (!start_ap(gd, boot_addr, smibest)) {
26be20a0 2306 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
984263bc
MD
2307 CHECK_PRINT("trace"); /* show checkpoints */
2308 /* better panic as the AP may be running loose */
26be20a0 2309 kprintf("panic y/n? [y] ");
984263bc
MD
2310 if (cngetc() != 'n')
2311 panic("bye-bye");
2312 }
2313 CHECK_PRINT("trace"); /* show checkpoints */
2314
2315 /* record its version info */
2316 cpu_apic_versions[x] = cpu_apic_versions[0];
984263bc
MD
2317 }
2318
0f7a3396
MD
2319 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2320 ncpus = x;
2321
b45759e1
MD
2322 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2323 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2324 ;
2325 --shift;
2326 ncpus2_shift = shift;
2327 ncpus2 = 1 << shift;
90100055
JH
2328 ncpus2_mask = ncpus2 - 1;
2329
b45759e1
MD
2330 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2331 if ((1 << shift) < ncpus)
2332 ++shift;
2333 ncpus_fit = 1 << shift;
2334 ncpus_fit_mask = ncpus_fit - 1;
2335
984263bc 2336 /* build our map of 'other' CPUs */
0f7a3396 2337 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
e4846942 2338 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
96728c05 2339 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
984263bc
MD
2340
2341 /* fill in our (BSP) APIC version */
2342 cpu_apic_versions[0] = lapic.version;
2343
2344 /* restore the warmstart vector */
2345 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
984263bc
MD
2346 outb(CMOS_REG, BIOS_RESET);
2347 outb(CMOS_DATA, mpbiosreason);
984263bc
MD
2348
2349 /*
8a8d5d85
MD
2350 * NOTE! The idlestack for the BSP was setup by locore. Finish
2351 * up, clean out the P==V mapping we did earlier.
984263bc 2352 */
984263bc
MD
2353 for (x = 0; x < NKPT; x++)
2354 PTD[x] = 0;
2355 pmap_set_opt();
2356
2357 /* number of APs actually started */
8a8d5d85 2358 return ncpus - 1;
984263bc
MD
2359}
2360
984263bc
MD
2361/*
2362 * load the 1st level AP boot code into base memory.
2363 */
2364
2365/* targets for relocation */
2366extern void bigJump(void);
2367extern void bootCodeSeg(void);
2368extern void bootDataSeg(void);
2369extern void MPentry(void);
2370extern u_int MP_GDT;
2371extern u_int mp_gdtbase;
2372
2373static void
2374install_ap_tramp(u_int boot_addr)
2375{
2376 int x;
2377 int size = *(int *) ((u_long) & bootMP_size);
2378 u_char *src = (u_char *) ((u_long) bootMP);
2379 u_char *dst = (u_char *) boot_addr + KERNBASE;
2380 u_int boot_base = (u_int) bootMP;
2381 u_int8_t *dst8;
2382 u_int16_t *dst16;
2383 u_int32_t *dst32;
2384
2385 POSTCODE(INSTALL_AP_TRAMP_POST);
2386
2387 for (x = 0; x < size; ++x)
2388 *dst++ = *src++;
2389
2390 /*
2391 * modify addresses in code we just moved to basemem. unfortunately we
2392 * need fairly detailed info about mpboot.s for this to work. changes
2393 * to mpboot.s might require changes here.
2394 */
2395
2396 /* boot code is located in KERNEL space */
2397 dst = (u_char *) boot_addr + KERNBASE;
2398
2399 /* modify the lgdt arg */
2400 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2401 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2402
2403 /* modify the ljmp target for MPentry() */
2404 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2405 *dst32 = ((u_int) MPentry - KERNBASE);
2406
2407 /* modify the target for boot code segment */
2408 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2409 dst8 = (u_int8_t *) (dst16 + 1);
2410 *dst16 = (u_int) boot_addr & 0xffff;
2411 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2412
2413 /* modify the target for boot data segment */
2414 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2415 dst8 = (u_int8_t *) (dst16 + 1);
2416 *dst16 = (u_int) boot_addr & 0xffff;
2417 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2418}
2419
2420
2421/*
bb467734 2422 * This function starts the AP (application processor) identified
984263bc
MD
2423 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2424 * to accomplish this. This is necessary because of the nuances
2425 * of the different hardware we might encounter. It ain't pretty,
2426 * but it seems to work.
a108bf71
MD
2427 *
2428 * NOTE: eventually an AP gets to ap_init(), which is called just
2429 * before the AP goes into the LWKT scheduler's idle loop.
984263bc
MD
2430 */
2431static int
bb467734 2432start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
984263bc
MD
2433{
2434 int physical_cpu;
2435 int vector;
984263bc
MD
2436 u_long icr_lo, icr_hi;
2437
2438 POSTCODE(START_AP_POST);
2439
2440 /* get the PHYSICAL APIC ID# */
0f7a3396 2441 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
984263bc
MD
2442
2443 /* calculate the vector */
2444 vector = (boot_addr >> 12) & 0xff;
2445
bb467734
MD
2446 /* We don't want anything interfering */
2447 cpu_disable_intr();
2448
8a8d5d85
MD
2449 /* Make sure the target cpu sees everything */
2450 wbinvd();
984263bc
MD
2451
2452 /*
bb467734
MD
2453 * Try to detect when a SMI has occurred, wait up to 200ms.
2454 *
2455 * If a SMI occurs during an AP reset but before we issue
2456 * the STARTUP command, the AP may brick. To work around
2457 * this problem we hold off doing the AP startup until
2458 * after we have detected the SMI. Hopefully another SMI
2459 * will not occur before we finish the AP startup.
2460 *
2461 * Retries don't seem to help. SMIs have a window of opportunity
2462 * and if USB->legacy keyboard emulation is enabled in the BIOS
2463 * the interrupt rate can be quite high.
2464 *
2465 * NOTE: Don't worry about the L1 cache load, it might bloat
2466 * ldelta a little but ndelta will be so huge when the SMI
2467 * occurs the detection logic will still work fine.
2468 */
2469 if (smibest) {
2470 set_apic_timer(200000);
2471 smitest();
2472 }
2473
2474 /*
984263bc
MD
2475 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2476 * and running the target CPU. OR this INIT IPI might be latched (P5
2477 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2478 * ignored.
bb467734
MD
2479 *
2480 * see apic/apicreg.h for icr bit definitions.
2481 *
2482 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
984263bc
MD
2483 */
2484
bb467734
MD
2485 /*
2486 * Setup the address for the target AP. We can setup
2487 * icr_hi once and then just trigger operations with
2488 * icr_lo.
2489 */
984263bc
MD
2490 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2491 icr_hi |= (physical_cpu << 24);
bb467734 2492 icr_lo = lapic.icr_lo & 0xfff00000;
984263bc
MD
2493 lapic.icr_hi = icr_hi;
2494
bb467734
MD
2495 /*
2496 * Do an INIT IPI: assert RESET
2497 *
2498 * Use edge triggered mode to assert INIT
2499 */
984263bc 2500 lapic.icr_lo = icr_lo | 0x0000c500;
984263bc
MD
2501 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2502 /* spin */ ;
2503
bb467734
MD
2504 /*
2505 * The spec calls for a 10ms delay but we may have to use a
2506 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2507 * interrupt. We have other loops here too and dividing by 2
2508 * doesn't seem to be enough even after subtracting 350us,
2509 * so we divide by 4.
2510 *
2511 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2512 * interrupt was detected we use the full 10ms.
2513 */
2514 if (smibest == 0)
2515 u_sleep(10000);
2516 else if (smibest < 150 * 4 + 350)
2517 u_sleep(150);
2518 else if ((smibest - 350) / 4 < 10000)
2519 u_sleep((smibest - 350) / 4);
2520 else
2521 u_sleep(10000);
984263bc 2522
bb467734
MD
2523 /*
2524 * Do an INIT IPI: deassert RESET
2525 *
2526 * Use level triggered mode to deassert. It is unclear
2527 * why we need to do this.
2528 */
2529 lapic.icr_lo = icr_lo | 0x00008500;
984263bc
MD
2530 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2531 /* spin */ ;
bb467734 2532 u_sleep(150); /* wait 150us */
984263bc
MD
2533
2534 /*
bb467734 2535 * Next we do a STARTUP IPI: the previous INIT IPI might still be
984263bc
MD
2536 * latched, (P5 bug) this 1st STARTUP would then terminate
2537 * immediately, and the previously started INIT IPI would continue. OR
2538 * the previous INIT IPI has already run. and this STARTUP IPI will
2539 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2540 * will run.
2541 */
984263bc
MD
2542 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2543 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2544 /* spin */ ;
2545 u_sleep(200); /* wait ~200uS */
2546
2547 /*
bb467734 2548 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
984263bc
MD
2549 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2550 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2551 * recognized after hardware RESET or INIT IPI.
2552 */
984263bc
MD
2553 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2554 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2555 /* spin */ ;
bb467734
MD
2556
2557 /* Resume normal operation */
2558 cpu_enable_intr();
984263bc 2559
8a8d5d85 2560 /* wait for it to start, see ap_init() */
984263bc 2561 set_apic_timer(5000000);/* == 5 seconds */
8a8d5d85 2562 while (read_apic_timer()) {
0f7a3396 2563 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
984263bc 2564 return 1; /* return SUCCESS */
8a8d5d85 2565 }
bb467734 2566
984263bc
MD
2567 return 0; /* return FAILURE */
2568}
2569
bb467734
MD
2570static
2571int
2572smitest(void)
2573{
2574 int64_t ltsc;
2575 int64_t ntsc;
2576 int64_t ldelta;
2577 int64_t ndelta;
2578 int count;
2579
2580 ldelta = 0;
2581 ndelta = 0;
2582 while (read_apic_timer()) {
2583 ltsc = rdtsc();
2584 for (count = 0; count < 100; ++count)
2585 ntsc = rdtsc(); /* force loop to occur */
2586 if (ldelta) {
2587 ndelta = ntsc - ltsc;
2588 if (ldelta > ndelta)
2589 ldelta = ndelta;
2590 if (ndelta > ldelta * 2)
2591 break;
2592 } else {
2593 ldelta = ntsc - ltsc;
2594 }
2595 }
2596 return(read_apic_timer());
2597}
984263bc
MD
2598
2599/*
0f7a3396 2600 * Lazy flush the TLB on all other CPU's. DEPRECATED.
984263bc 2601 *
0f7a3396
MD
2602 * If for some reason we were unable to start all cpus we cannot safely
2603 * use broadcast IPIs.
984263bc 2604 */
7402df27
MD
2605
2606static cpumask_t smp_invltlb_req;
ecf9dec6 2607#define SMP_INVLTLB_DEBUG
7402df27 2608
984263bc
MD
2609void
2610smp_invltlb(void)
2611{
97359a5b 2612#ifdef SMP
7402df27 2613 struct mdglobaldata *md = mdcpu;
dd4ef322
MD
2614#ifdef SMP_INVLTLB_DEBUG
2615 long count = 0;
2616 long xcount = 0;
2617#endif
9bbe2f36 2618
7402df27
MD
2619 crit_enter_gd(&md->mi);
2620 md->gd_invltlb_ret = 0;
2621 ++md->mi.gd_cnt.v_smpinvltlb;
2622 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
dd4ef322
MD
2623#ifdef SMP_INVLTLB_DEBUG
2624again:
2625#endif
0f7a3396 2626 if (smp_startup_mask == smp_active_mask) {
984263bc 2627 all_but_self_ipi(XINVLTLB_OFFSET);
0f7a3396 2628 } else {
7402df27
MD
2629 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2630 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
0f7a3396 2631 }
dd4ef322
MD
2632
2633#ifdef SMP_INVLTLB_DEBUG
2634 if (xcount)
2635 kprintf("smp_invltlb: ipi sent\n");
2636#endif
7402df27
MD
2637 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2638 (smp_active_mask & ~md->mi.gd_cpumask)) {
2639 cpu_mfence();
2640 cpu_pause();
dd4ef322
MD
2641#ifdef SMP_INVLTLB_DEBUG
2642 /* DEBUGGING */
2643 if (++count == 400000000) {
2644 print_backtrace(-1);
2645 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2646 "rflags %016lx retry",
2647 (long)md->gd_invltlb_ret,
2648 (long)smp_invltlb_req,
2649 (long)read_eflags());
2650 __asm __volatile ("sti");
2651 ++xcount;
2652 if (xcount > 2)
2653 lwkt_process_ipiq();
2654 if (xcount > 3) {
2655 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2656 globaldata_t xgd;
2657 kprintf("bcpu %d\n", bcpu);
2658 xgd = globaldata_find(bcpu);
2659 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2660 }
2661 if (xcount > 5)
2662 panic("giving up");
2663 count = 0;
2664 goto again;
2665 }
2666#endif
7402df27
MD
2667 }
2668 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2669 crit_exit_gd(&md->mi);
9bbe2f36 2670#endif
984263bc
MD
2671}
2672
7402df27
MD
2673#ifdef SMP
2674
2675/*
2676 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2677 * bother to bump the critical section count or nested interrupt count
2678 * so only do very low level operations here.
2679 */
2680void
2681smp_invltlb_intr(void)
2682{
2683 struct mdglobaldata *md = mdcpu;
2684 struct mdglobaldata *omd;
2685 cpumask_t mask;
2686 int cpu;
2687
2688 mask = smp_invltlb_req;
2689 cpu_mfence();
2690 cpu_invltlb();
2691 while (mask) {
2692 cpu = bsfl(mask);
2693 mask &= ~(1 << cpu);
2694 omd = (struct mdglobaldata *)globaldata_find(cpu);
2695 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2696 }
2697}
2698
2699#endif
2700
984263bc
MD
2701/*
2702 * When called the executing CPU will send an IPI to all other CPUs
2703 * requesting that they halt execution.
2704 *
2705 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2706 *
2707 * - Signals all CPUs in map to stop.
2708 * - Waits for each to stop.
2709 *
2710 * Returns:
2711 * -1: error
2712 * 0: NA
2713 * 1: ok
2714 *
2715 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2716 * from executing at same time.
2717 */
2718int
2719stop_cpus(u_int map)
2720{
0f7a3396 2721 map &= smp_active_mask;
984263bc
MD
2722
2723 /* send the Xcpustop IPI to all CPUs in map */
2724 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2725
2726 while ((stopped_cpus & map) != map)
2727 /* spin */ ;
2728
2729 return 1;
2730}
2731
2732
2733/*
2734 * Called by a CPU to restart stopped CPUs.
2735 *
2736 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2737 *
2738 * - Signals all CPUs in map to restart.
2739 * - Waits for each to restart.
2740 *
2741 * Returns:
2742 * -1: error
2743 * 0: NA
2744 * 1: ok
2745 */
2746int
2747restart_cpus(u_int map)
2748{
0f7a3396
MD
2749 /* signal other cpus to restart */
2750 started_cpus = map & smp_active_mask;
984263bc
MD
2751
2752 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2753 /* spin */ ;
2754
2755 return 1;
2756}
2757
984263bc 2758/*
8a8d5d85
MD
2759 * This is called once the mpboot code has gotten us properly relocated
2760 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2761 * and when it returns the scheduler will call the real cpu_idle() main
2762 * loop for the idlethread. Interrupts are disabled on entry and should
2763 * remain disabled at return.
984263bc 2764 */
984263bc 2765void
8a8d5d85 2766ap_init(void)
984263bc
MD
2767{
2768 u_int apic_id;
2769
8a8d5d85 2770 /*
0f7a3396
MD
2771 * Adjust smp_startup_mask to signal the BSP that we have started
2772 * up successfully. Note that we do not yet hold the BGL. The BSP
2773 * is waiting for our signal.
2774 *
2775 * We can't set our bit in smp_active_mask yet because we are holding
2776 * interrupts physically disabled and remote cpus could deadlock
2777 * trying to send us an IPI.
8a8d5d85 2778 */
0f7a3396 2779 smp_startup_mask |= 1 << mycpu->gd_cpuid;
35238fa5 2780 cpu_mfence();
8a8d5d85
MD
2781
2782 /*
41a01a4d
MD
2783 * Interlock for finalization. Wait until mp_finish is non-zero,
2784 * then get the MP lock.
2785 *
2786 * Note: We are in a critical section.
2787 *
2788 * Note: We have to synchronize td_mpcount to our desired MP state
2789 * before calling cpu_try_mplock().
2790 *
2791 * Note: we are the idle thread, we can only spin.
2792 *
35238fa5
MD
2793 * Note: The load fence is memory volatile and prevents the compiler
2794 * from improperly caching mp_finish, and the cpu from improperly
2795 * caching it.
8a8d5d85 2796 */
41a01a4d 2797 while (mp_finish == 0)
35238fa5 2798 cpu_lfence();
d9ebdce5 2799 ++curthread->td_mpcount;
8a8d5d85
MD
2800 while (cpu_try_mplock() == 0)
2801 ;
2802
374133e3
MD
2803 if (cpu_feature & CPUID_TSC) {
2804 /*
2805 * The BSP is constantly updating tsc0_offset, figure out the
2806 * relative difference to synchronize ktrdump.
2807 */
2808 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2809 }
2810
984263bc
MD
2811 /* BSP may have changed PTD while we're waiting for the lock */
2812 cpu_invltlb();
2813
984263bc
MD
2814#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2815 lidt(&r_idt);
2816#endif
2817
2818 /* Build our map of 'other' CPUs. */
0f7a3396 2819 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
984263bc 2820
26be20a0 2821 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
984263bc 2822
984263bc
MD
2823 /* A quick check from sanity claus */
2824 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
8a8d5d85 2825 if (mycpu->gd_cpuid != apic_id) {
26be20a0
SW
2826 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2827 kprintf("SMP: apic_id = %d\n", apic_id);
2828 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
984263bc
MD
2829 panic("cpuid mismatch! boom!!");
2830 }
2831
b52c8db0
SZ
2832 /* Initialize AP's local APIC for irq's */
2833 apic_initialize(FALSE);
984263bc
MD
2834
2835 /* Set memory range attributes for this CPU to match the BSP */
2836 mem_range_AP_init();
2837
a2a5ad0d 2838 /*
4c9f5a7f
MD
2839 * Once we go active we must process any IPIQ messages that may
2840 * have been queued, because no actual IPI will occur until we
2841 * set our bit in the smp_active_mask. If we don't the IPI
2842 * message interlock could be left set which would also prevent
2843 * further IPIs.
2844 *
8a8d5d85
MD
2845 * The idle loop doesn't expect the BGL to be held and while
2846 * lwkt_switch() normally cleans things up this is a special case
2847 * because we returning almost directly into the idle loop.
41a01a4d
MD
2848 *
2849 * The idle thread is never placed on the runq, make sure
4c9f5a7f 2850 * nothing we've done put it there.
8a8d5d85 2851 */
96728c05 2852 KKASSERT(curthread->td_mpcount == 1);
41a01a4d 2853 smp_active_mask |= 1 << mycpu->gd_cpuid;
d19f6edf
MD
2854
2855 /*
2856 * Enable interrupts here. idle_restore will also do it, but
2857 * doing it here lets us clean up any strays that got posted to
2858 * the CPU during the AP boot while we are still in a critical
2859 * section.
2860 */
2861 __asm __volatile("sti; pause; pause"::);
2862 mdcpu->gd_fpending = 0;
d19f6edf 2863
4a19580d 2864 initclocks_pcpu(); /* clock interrupts (via IPIs) */
4c9f5a7f 2865 lwkt_process_ipiq();
d19f6edf
MD
2866
2867 /*
2868 * Releasing the mp lock lets the BSP finish up the SMP init
2869 */
96728c05 2870 rel_mplock();
41a01a4d 2871 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
984263bc
MD
2872}
2873
41a01a4d
MD
2874/*
2875 * Get SMP fully working before we start initializing devices.
2876 */
2877static
2878void
2879ap_finish(void)
2880{
2881 mp_finish = 1;
2882 if (bootverbose)
26be20a0 2883 kprintf("Finish MP startup\n");
374133e3
MD
2884 if (cpu_feature & CPUID_TSC)
2885 tsc0_offset = rdtsc();
2886 tsc_offsets[0] = 0;
41a01a4d 2887 rel_mplock();
374133e3 2888 while (smp_active_mask != smp_startup_mask) {
35238fa5 2889 cpu_lfence();
374133e3
MD
2890 if (cpu_feature & CPUID_TSC)
2891 tsc0_offset = rdtsc();
2892 }
4da43e1f 2893 while (try_mplock() == 0)
41a01a4d
MD
2894 ;
2895 if (bootverbose)
26be20a0 2896 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
41a01a4d
MD
2897}
2898
ba39e2e0 2899SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
41a01a4d 2900
96728c05
MD
2901void
2902cpu_send_ipiq(int dcpu)
2903{
41a01a4d
MD
2904 if ((1 << dcpu) & smp_active_mask)
2905 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
96728c05 2906}
41a01a4d
MD
2907
2908#if 0 /* single_apic_ipi_passive() not working yet */
2909/*
2910 * Returns 0 on failure, 1 on success
2911 */
2912int
2913cpu_send_ipiq_passive(int dcpu)
2914{
2915 int r = 0;
2916 if ((1 << dcpu) & smp_active_mask) {
2917 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2918 APIC_DELMODE_FIXED);
2919 }
2920 return(r);
2921}
2922#endif
2923
a0873f07
SZ
2924struct mptable_lapic_cbarg1 {
2925 int cpu_count;
44c36320
SZ
2926 int ht_fixup;
2927 u_int ht_apicid_mask;
a0873f07
SZ
2928};
2929
2930static int
2931mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2932{
2933 const struct PROCENTRY *ent;
2934 struct mptable_lapic_cbarg1 *arg = xarg;
2935
2936 if (type != 0)
2937 return 0;
2938 ent = pos;
2939
2940 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2941 return 0;
2942
2943 arg->cpu_count++;
44c36320
SZ
2944 if (ent->apic_id < 32) {
2945 arg->ht_apicid_mask |= 1 << ent->apic_id;
2946 } else if (arg->ht_fixup) {
2947 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2948 arg->ht_fixup = 0;
2949 }
a0873f07
SZ
2950 return 0;
2951}
2952
2953struct mptable_lapic_cbarg2 {
2954 int cpu;
44c36320 2955 int logical_cpus;
a0873f07
SZ
2956 int found_bsp;
2957};
2958
2959static int
2960mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2961{
2962 const struct PROCENTRY *ent;
2963 struct mptable_lapic_cbarg2 *arg = xarg;
2964
2965 if (type != 0)
2966 return 0;
2967 ent = pos;
2968
2969 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2970 KKASSERT(!arg->found_bsp);
2971 arg->found_bsp = 1;
2972 }
2973
2974 if (processor_entry(ent, arg->cpu))
2975 arg->cpu++;
2976
44c36320 2977 if (arg->logical_cpus) {
a0873f07
SZ
2978 struct PROCENTRY proc;
2979 int i;
2980
2981 /*
2982 * Create fake mptable processor entries
2983 * and feed them to processor_entry() to
2984 * enumerate the logical CPUs.
2985 */
2986 bzero(&proc, sizeof(proc));
2987 proc.type = 0;
2988 proc.cpu_flags = PROCENTRY_FLAG_EN;
2989 proc.apic_id = ent->apic_id;
2990
44c36320 2991 for (i = 1; i < arg->logical_cpus; i++) {
a0873f07
SZ
2992 proc.apic_id++;
2993 processor_entry(&proc, arg->cpu);
a0873f07
SZ
2994 arg->cpu++;
2995 }
2996 }
2997 return 0;
2998}
2999
322abba7 3000static void
281d9482
SZ
3001mptable_imcr(struct mptable_pos *mpt)
3002{
3003 /* record whether PIC or virtual-wire mode */
3004 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3005 mpt->mp_fps->mpfb2 & 0x80);
3006}
3007
3008struct mptable_lapic_enumerator {
3009 struct lapic_enumerator enumerator;
3010 vm_paddr_t mpfps_paddr;
3011};
3012
3013static void
322abba7
SZ
3014mptable_lapic_default(void)
3015{
3016 int ap_apicid, bsp_apicid;
3017
3018 mp_naps = 1; /* exclude BSP */
3019
3020 /* Map local apic before the id field is accessed */
84cc808b 3021 lapic_map(DEFAULT_APIC_BASE);
322abba7
SZ
3022
3023 bsp_apicid = APIC_ID(lapic.id);
3024 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3025
3026 /* BSP */
3027 mp_set_cpuids(0, bsp_apicid);
3028 /* one and only AP */
3029 mp_set_cpuids(1, ap_apicid);
3030}
3031
a0873f07
SZ
3032/*
3033 * Configure:
a0873f07 3034 * mp_naps
d787e80c 3035 * ID_TO_CPU(N), APIC ID to logical CPU table
a0873f07
SZ
3036 * CPU_TO_ID(N), logical CPU to APIC ID table
3037 */
3038static void
281d9482 3039mptable_lapic_enumerate(struct lapic_enumerator *e)
a0873f07 3040{
281d9482 3041 struct mptable_pos mpt;
322abba7
SZ
3042 struct mptable_lapic_cbarg1 arg1;
3043 struct mptable_lapic_cbarg2 arg2;
3044 mpcth_t cth;
44c36320 3045 int error, logical_cpus = 0;
5a16ccc3 3046 vm_offset_t lapic_addr;
281d9482
SZ
3047 vm_paddr_t mpfps_paddr;
3048
3049 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3050 KKASSERT(mpfps_paddr != 0);
a0873f07 3051
281d9482
SZ
3052 error = mptable_map(&mpt, mpfps_paddr);
3053 if (error)
3054 panic("mptable_lapic_enumerate mptable_map failed\n");
3055
3056 KKASSERT(mpt.mp_fps != NULL);
a0873f07 3057
322abba7
SZ
3058 /*
3059 * Check for use of 'default' configuration
3060 */
281d9482 3061 if (mpt.mp_fps->mpfb1 != 0) {
322abba7 3062 mptable_lapic_default();
281d9482 3063 mptable_unmap(&mpt);
322abba7
SZ
3064 return;
3065 }
a0873f07 3066
281d9482 3067 cth = mpt.mp_cth;
322abba7 3068 KKASSERT(cth != NULL);
a0873f07 3069
322abba7
SZ
3070 /* Save local apic address */
3071 lapic_addr = (vm_offset_t)cth->apic_address;
3072 KKASSERT(lapic_addr != 0);
a0873f07 3073
322abba7
SZ
3074 /*
3075 * Find out how many CPUs do we have
3076 */
3077 bzero(&arg1, sizeof(arg1));
44c36320
SZ
3078 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3079
322abba7
SZ
3080 error = mptable_iterate_entries(cth,
3081 mptable_lapic_pass1_callback, &arg1);
3082 if (error)
3083 panic("mptable_iterate_entries(lapic_pass1) failed\n");
322abba7 3084 KKASSERT(arg1.cpu_count != 0);
a0873f07 3085
322abba7 3086 /* See if we need to fixup HT logical CPUs. */
44c36320
SZ
3087 if (arg1.ht_fixup) {
3088 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3089 arg1.cpu_count);
3090 if (logical_cpus != 0)
3091 arg1.cpu_count *= logical_cpus;
3092 }
3093 mp_naps = arg1.cpu_count;
a0873f07 3094
44c36320 3095 /* Qualify the numbers again, after possible HT fixup */
322abba7
SZ
3096 if (mp_naps > MAXCPU) {
3097 kprintf("Warning: only using %d of %d available CPUs!\n",
3098 MAXCPU, mp_naps);
3099 mp_naps = MAXCPU;
a0873f07
SZ
3100 }
3101
322abba7 3102 --mp_naps; /* subtract the BSP */
a0873f07 3103
322abba7
SZ
3104 /*
3105 * Link logical CPU id to local apic id
3106 */
3107 bzero(&arg2, sizeof(arg2));
3108 arg2.cpu = 1;
44c36320 3109 arg2.logical_cpus = logical_cpus;
a0873f07 3110
322abba7
SZ
3111 error = mptable_iterate_entries(cth,
3112 mptable_lapic_pass2_callback, &arg2);
3113 if (error)
3114 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3115 KKASSERT(arg2.found_bsp);
a0873f07 3116
322abba7 3117 /* Map local apic */
84cc808b 3118 lapic_map(lapic_addr);
281d9482
SZ
3119
3120 mptable_unmap(&mpt);
3121}
3122
3123static int
3124mptable_lapic_probe(struct lapic_enumerator *e)
3125{
3126 vm_paddr_t mpfps_paddr;
3127
3128 mpfps_paddr = mptable_probe();
3129 if (mpfps_paddr == 0)
3130 return ENXIO;
3131
3132 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3133 return 0;
a0873f07 3134}
5a16ccc3 3135
281d9482
SZ
3136static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3137 .enumerator = {
3138 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3139 .lapic_probe = mptable_lapic_probe,
3140 .lapic_enumerate = mptable_lapic_enumerate
3141 }
3142};
3143
5a16ccc3 3144static void
281d9482 3145mptable_apic_register(void)
a0eaef71 3146{
281d9482 3147 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
a0eaef71 3148}
281d9482 3149SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);