kernel - Fix serious issue w/ smp_invltlb(), plus other issues (3)
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
CommitLineData
46d4e165
JG
1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29#include "opt_cpu.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
37#include <sys/cons.h> /* cngetc() */
38#include <sys/machintr.h>
39
684a93c4
MD
40#include <sys/mplock2.h>
41
46d4e165
JG
42#include <vm/vm.h>
43#include <vm/vm_param.h>
44#include <vm/pmap.h>
45#include <vm/vm_kern.h>
46#include <vm/vm_extern.h>
47#include <sys/lock.h>
48#include <vm/vm_map.h>
49#include <sys/user.h>
50#ifdef GPROF
51#include <sys/gmon.h>
52#endif
53
54#include <machine/smp.h>
55#include <machine_base/apic/apicreg.h>
56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
58#include <machine_base/apic/mpapic.h>
59#include <machine/psl.h>
60#include <machine/segments.h>
61#include <machine/tss.h>
62#include <machine/specialreg.h>
63#include <machine/globaldata.h>
9bbe2f36 64#include <machine/pmap_inval.h>
46d4e165
JG
65
66#include <machine/md_var.h> /* setidt() */
67#include <machine_base/icu/icu.h> /* IPIs */
68#include <machine_base/isa/intr_machdep.h> /* IPIs */
69
70#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71
72#define WARMBOOT_TARGET 0
73#define WARMBOOT_OFF (KERNBASE + 0x0467)
74#define WARMBOOT_SEG (KERNBASE + 0x0469)
75
76#define BIOS_BASE (0xf0000)
77#define BIOS_SIZE (0x10000)
78#define BIOS_COUNT (BIOS_SIZE/4)
79
80#define CMOS_REG (0x70)
81#define CMOS_DATA (0x71)
82#define BIOS_RESET (0x0f)
83#define BIOS_WARM (0x0a)
84
85#define PROCENTRY_FLAG_EN 0x01
86#define PROCENTRY_FLAG_BP 0x02
87#define IOAPICENTRY_FLAG_EN 0x01
88
89
90/* MP Floating Pointer Structure */
91typedef struct MPFPS {
92 char signature[4];
93 u_int32_t pap;
94 u_char length;
95 u_char spec_rev;
96 u_char checksum;
97 u_char mpfb1;
98 u_char mpfb2;
99 u_char mpfb3;
100 u_char mpfb4;
101 u_char mpfb5;
102} *mpfps_t;
103
104/* MP Configuration Table Header */
105typedef struct MPCTH {
106 char signature[4];
107 u_short base_table_length;
108 u_char spec_rev;
109 u_char checksum;
110 u_char oem_id[8];
111 u_char product_id[12];
a5f51ef3 112 u_int32_t oem_table_pointer;
46d4e165
JG
113 u_short oem_table_size;
114 u_short entry_count;
a5f51ef3 115 u_int32_t apic_address;
46d4e165
JG
116 u_short extended_table_length;
117 u_char extended_table_checksum;
118 u_char reserved;
119} *mpcth_t;
120
121
122typedef struct PROCENTRY {
123 u_char type;
124 u_char apic_id;
125 u_char apic_version;
126 u_char cpu_flags;
a5f51ef3
JG
127 u_int32_t cpu_signature;
128 u_int32_t feature_flags;
129 u_int32_t reserved1;
130 u_int32_t reserved2;
46d4e165
JG
131} *proc_entry_ptr;
132
133typedef struct BUSENTRY {
134 u_char type;
135 u_char bus_id;
136 char bus_type[6];
137} *bus_entry_ptr;
138
139typedef struct IOAPICENTRY {
140 u_char type;
141 u_char apic_id;
142 u_char apic_version;
143 u_char apic_flags;
a5f51ef3 144 u_int32_t apic_address;
46d4e165
JG
145} *io_apic_entry_ptr;
146
147typedef struct INTENTRY {
148 u_char type;
149 u_char int_type;
150 u_short int_flags;
151 u_char src_bus_id;
152 u_char src_bus_irq;
153 u_char dst_apic_id;
154 u_char dst_apic_int;
155} *int_entry_ptr;
156
157/* descriptions of MP basetable entries */
158typedef struct BASETABLE_ENTRY {
159 u_char type;
160 u_char length;
161 char name[16];
162} basetable_entry;
163
91f1c7a4
MN
164struct mptable_pos {
165 mpfps_t mp_fps;
166 mpcth_t mp_cth;
167 vm_size_t mp_cth_mapsz;
168};
169
8f54b133
MN
170typedef int (*mptable_iter_func)(void *, const void *, int);
171
46d4e165
JG
172/*
173 * this code MUST be enabled here and in mpboot.s.
174 * it follows the very early stages of AP boot by placing values in CMOS ram.
175 * it NORMALLY will never be needed and thus the primitive method for enabling.
176 *
177 */
178#if defined(CHECK_POINTS)
179#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
180#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181
182#define CHECK_INIT(D); \
183 CHECK_WRITE(0x34, (D)); \
184 CHECK_WRITE(0x35, (D)); \
185 CHECK_WRITE(0x36, (D)); \
186 CHECK_WRITE(0x37, (D)); \
187 CHECK_WRITE(0x38, (D)); \
188 CHECK_WRITE(0x39, (D));
189
190#define CHECK_PRINT(S); \
191 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
192 (S), \
193 CHECK_READ(0x34), \
194 CHECK_READ(0x35), \
195 CHECK_READ(0x36), \
196 CHECK_READ(0x37), \
197 CHECK_READ(0x38), \
198 CHECK_READ(0x39));
199
200#else /* CHECK_POINTS */
201
202#define CHECK_INIT(D)
203#define CHECK_PRINT(S)
204
205#endif /* CHECK_POINTS */
206
207/*
208 * Values to send to the POST hardware.
209 */
210#define MP_BOOTADDRESS_POST 0x10
211#define MP_PROBE_POST 0x11
212#define MPTABLE_PASS1_POST 0x12
213
214#define MP_START_POST 0x13
215#define MP_ENABLE_POST 0x14
216#define MPTABLE_PASS2_POST 0x15
217
218#define START_ALL_APS_POST 0x16
219#define INSTALL_AP_TRAMP_POST 0x17
220#define START_AP_POST 0x18
221
222#define MP_ANNOUNCE_POST 0x19
223
224static int need_hyperthreading_fixup;
225static u_int logical_cpus;
226u_int logical_cpus_mask;
227
699b0754
MN
228static int madt_probe_test;
229TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
230
46d4e165
JG
231/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
232int current_postcode;
233
234/** XXX FIXME: what system files declare these??? */
235extern struct region_descriptor r_gdt, r_idt;
236
46d4e165 237int mp_naps; /* # of Applications processors */
46d4e165 238#ifdef APIC_IO
c784234d 239static int mp_nbusses; /* # of busses */
46d4e165
JG
240int mp_napics; /* # of IO APICs */
241#endif
46d4e165
JG
242vm_offset_t cpu_apic_address;
243#ifdef APIC_IO
244vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
245u_int32_t *io_apic_versions;
246#endif
247extern int nkpt;
248
249u_int32_t cpu_apic_versions[MAXCPU];
250int64_t tsc0_offset;
251extern int64_t tsc_offsets[];
252
927c4c1f
MN
253extern u_long ebda_addr;
254
46d4e165
JG
255#ifdef APIC_IO
256struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
257#endif
258
259/*
260 * APIC ID logical/physical mapping structures.
261 * We oversize these to simplify boot-time config.
262 */
263int cpu_num_to_apic_id[NAPICID];
264#ifdef APIC_IO
265int io_num_to_apic_id[NAPICID];
266#endif
267int apic_id_to_logical[NAPICID];
268
269/* AP uses this during bootstrap. Do not staticize. */
270char *bootSTK;
271static int bootAP;
272
46d4e165
JG
273/*
274 * SMP page table page. Setup by locore to point to a page table
275 * page from which we allocate per-cpu privatespace areas io_apics,
276 * and so forth.
277 */
278
279#define IO_MAPPING_START_INDEX \
280 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
281
282extern pt_entry_t *SMPpt;
46d4e165
JG
283
284struct pcb stoppcbs[MAXCPU];
285
286extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
287
8f54b133
MN
288static basetable_entry basetable_entry_types[] =
289{
290 {0, 20, "Processor"},
291 {1, 8, "Bus"},
292 {2, 8, "I/O APIC"},
293 {3, 8, "I/O INT"},
294 {4, 8, "Local INT"}
295};
296
46d4e165
JG
297/*
298 * Local data and functions.
299 */
300
46d4e165
JG
301static u_int boot_address;
302static u_int base_memory;
303static int mp_finish;
304
46d4e165
JG
305static void mp_enable(u_int boot_addr);
306
8f54b133
MN
307static int mptable_iterate_entries(const mpcth_t,
308 mptable_iter_func, void *);
f804d15f 309static int mptable_probe(void);
8f54b133 310static int mptable_check(vm_paddr_t);
0eaa8172 311static long mptable_search_sig(u_int32_t target, int count);
46d4e165 312static void mptable_hyperthread_fixup(u_int id_mask);
91f1c7a4
MN
313static void mptable_pass1(struct mptable_pos *);
314static int mptable_pass2(struct mptable_pos *);
0eaa8172
MN
315static void mptable_default(int type);
316static void mptable_fix(void);
8f54b133 317static int mptable_map(struct mptable_pos *, vm_paddr_t);
91f1c7a4 318static void mptable_unmap(struct mptable_pos *);
0eaa8172 319
46d4e165
JG
320#ifdef APIC_IO
321static void setup_apic_irq_mapping(void);
322static int apic_int_is_bus_type(int intr, int bus_type);
323#endif
324static int start_all_aps(u_int boot_addr);
bfc09ba0 325#if 0
46d4e165 326static void install_ap_tramp(u_int boot_addr);
bfc09ba0 327#endif
bb467734
MD
328static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329static int smitest(void);
46d4e165
JG
330
331static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334static u_int bootMP_size;
335
336/*
337 * Calculate usable address in base memory for AP trampoline code.
338 */
339u_int
340mp_bootaddress(u_int basemem)
341{
342 POSTCODE(MP_BOOTADDRESS_POST);
343
46d4e165
JG
344 base_memory = basemem;
345
c855ebba
JG
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
46d4e165
JG
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
352
353 return mptramp_pagetables;
354}
355
356
357/*
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
359 */
f804d15f
MN
360static int
361mptable_probe(void)
46d4e165 362{
3a918cfd 363 long x;
46d4e165
JG
364 u_int32_t target;
365
366 /*
367 * Make sure our SMPpt[] page table is big enough to hold all the
368 * mappings we need.
369 */
370 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
371
372 POSTCODE(MP_PROBE_POST);
373
374 /* see if EBDA exists */
927c4c1f 375 if (ebda_addr != 0) {
46d4e165 376 /* search first 1K of EBDA */
927c4c1f 377 target = (u_int32_t)ebda_addr;
0eaa8172 378 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 379 return x;
46d4e165
JG
380 } else {
381 /* last 1K of base memory, effective 'top of base' passed in */
351254e7 382 target = (u_int32_t)(base_memory - 0x400);
0eaa8172 383 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 384 return x;
46d4e165
JG
385 }
386
387 /* search the BIOS */
351254e7 388 target = (u_int32_t)BIOS_BASE;
0eaa8172 389 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
351254e7 390 return x;
46d4e165
JG
391
392 /* nothing found */
46d4e165 393 return 0;
46d4e165
JG
394}
395
8f54b133
MN
396struct mptable_check_cbarg {
397 int cpu_count;
398 int found_bsp;
399};
400
401static int
402mptable_check_callback(void *xarg, const void *pos, int type)
403{
404 const struct PROCENTRY *ent;
405 struct mptable_check_cbarg *arg = xarg;
406
407 if (type != 0)
408 return 0;
409 ent = pos;
410
411 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
412 return 0;
413 arg->cpu_count++;
414
415 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
416 if (arg->found_bsp) {
417 kprintf("more than one BSP in base MP table\n");
418 return EINVAL;
419 }
420 arg->found_bsp = 1;
421 }
422 return 0;
423}
424
425static int
426mptable_check(vm_paddr_t mpfps_paddr)
427{
428 struct mptable_pos mpt;
429 struct mptable_check_cbarg arg;
430 mpcth_t cth;
431 int error;
432
433 if (mpfps_paddr == 0)
434 return EOPNOTSUPP;
435
436 error = mptable_map(&mpt, mpfps_paddr);
437 if (error)
438 return error;
439
440 if (mpt.mp_fps->mpfb1 != 0)
441 goto done;
442
443 error = EINVAL;
444
445 cth = mpt.mp_cth;
446 if (cth == NULL)
447 goto done;
448 if (cth->apic_address == 0)
449 goto done;
450
451 bzero(&arg, sizeof(arg));
452 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
453 if (!error) {
454 if (arg.cpu_count == 0) {
455 kprintf("MP table contains no processor entries\n");
456 error = EINVAL;
457 } else if (!arg.found_bsp) {
458 kprintf("MP table does not contains BSP entry\n");
459 error = EINVAL;
460 }
461 }
462done:
463 mptable_unmap(&mpt);
464 return error;
465}
466
467static int
468mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
469{
470 int count, total_size;
471 const void *position;
472
473 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
474 total_size = cth->base_table_length - sizeof(struct MPCTH);
475 position = (const uint8_t *)cth + sizeof(struct MPCTH);
476 count = cth->entry_count;
477
478 while (count--) {
479 int type, error;
480
481 KKASSERT(total_size >= 0);
482 if (total_size == 0) {
483 kprintf("invalid base MP table, "
484 "entry count and length mismatch\n");
485 return EINVAL;
486 }
487
488 type = *(const uint8_t *)position;
489 switch (type) {
490 case 0: /* processor_entry */
491 case 1: /* bus_entry */
492 case 2: /* io_apic_entry */
493 case 3: /* int_entry */
494 case 4: /* int_entry */
495 break;
496 default:
497 kprintf("unknown base MP table entry type %d\n", type);
498 return EINVAL;
499 }
500
501 if (total_size < basetable_entry_types[type].length) {
502 kprintf("invalid base MP table length, "
503 "does not contain all entries\n");
504 return EINVAL;
505 }
506 total_size -= basetable_entry_types[type].length;
507
508 error = func(arg, position, type);
509 if (error)
510 return error;
511
512 position = (const uint8_t *)position +
513 basetable_entry_types[type].length;
514 }
515 return 0;
516}
517
46d4e165
JG
518
519/*
520 * Startup the SMP processors.
521 */
522void
523mp_start(void)
524{
525 POSTCODE(MP_START_POST);
a0679cc7 526 mp_enable(boot_address);
46d4e165
JG
527}
528
529
530/*
531 * Print various information about the SMP system hardware and setup.
532 */
533void
534mp_announce(void)
535{
536 int x;
537
538 POSTCODE(MP_ANNOUNCE_POST);
539
540 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
541 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
542 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
bfc09ba0 543 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
46d4e165
JG
544 for (x = 1; x <= mp_naps; ++x) {
545 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
546 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
bfc09ba0 547 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
46d4e165
JG
548 }
549
550#if defined(APIC_IO)
551 for (x = 0; x < mp_napics; ++x) {
552 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
553 kprintf(", version: 0x%08x", io_apic_versions[x]);
bcdeeecd 554 kprintf(", at 0x%08lx\n", io_apic_address[x]);
46d4e165
JG
555 }
556#else
557 kprintf(" Warning: APIC I/O disabled\n");
558#endif /* APIC_IO */
559}
560
561/*
562 * AP cpu's call this to sync up protected mode.
563 *
ec073ddc 564 * WARNING! %gs is not set up on entry. This routine sets up %gs.
46d4e165
JG
565 */
566void
567init_secondary(void)
568{
569 int gsel_tss;
570 int x, myid = bootAP;
571 u_int64_t msr, cr0;
572 struct mdglobaldata *md;
573 struct privatespace *ps;
574
575 ps = &CPU_prvspace[myid];
576
577 gdt_segs[GPROC0_SEL].ssd_base =
578 (long) &ps->mdglobaldata.gd_common_tss;
579 ps->mdglobaldata.mi.gd_prvspace = ps;
580
581 /* We fill the 32-bit segment descriptors */
582 for (x = 0; x < NGDT; x++) {
583 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
584 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
585 }
586 /* And now a 64-bit one */
587 ssdtosyssd(&gdt_segs[GPROC0_SEL],
588 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
589
590 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
591 r_gdt.rd_base = (long) &gdt[myid * NGDT];
592 lgdt(&r_gdt); /* does magic intra-segment return */
593
ec073ddc
JG
594 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
595 wrmsr(MSR_FSBASE, 0); /* User value */
596 wrmsr(MSR_GSBASE, (u_int64_t)ps);
597 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
598
46d4e165
JG
599 lidt(&r_idt);
600
601#if 0
602 lldt(_default_ldt);
603 mdcpu->gd_currentldt = _default_ldt;
604#endif
605
606 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
607 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
608
609 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
610
611 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
612#if 0 /* JG XXX */
613 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
614#endif
615 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
616 md->gd_common_tssd = *md->gd_tss_gdt;
617#if 0 /* JG XXX */
618 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
619#endif
620 ltr(gsel_tss);
621
46d4e165
JG
622 /*
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
626 */
627 cr0 = rcr0();
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
629 load_cr0(cr0);
630
631 /* Set up the fast syscall stuff */
632 msr = rdmsr(MSR_EFER) | EFER_SCE;
633 wrmsr(MSR_EFER, msr);
634 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
635 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
636 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
637 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
638 wrmsr(MSR_STAR, msr);
639 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
640
641 pmap_set_opt(); /* PSE/4MB pages, etc */
642#if JGXXX
643 /* Initialize the PAT MSR. */
644 pmap_init_pat();
645#endif
646
647 /* set up CPU registers and state */
648 cpu_setregs();
649
650 /* set up SSE/NX registers */
651 initializecpu();
652
653 /* set up FPU state on the AP */
654 npxinit(__INITIAL_NPXCW__);
ec073ddc
JG
655
656 /* disable the APIC, just to be SURE */
657 lapic->svr &= ~APIC_SVR_ENABLE;
658
659 /* data returned to BSP */
660 cpu_apic_versions[0] = lapic->version;
46d4e165
JG
661}
662
663/*******************************************************************
664 * local functions and data
665 */
666
667/*
668 * start the SMP system
669 */
670static void
671mp_enable(u_int boot_addr)
672{
673 int x;
674#if defined(APIC_IO)
675 int apic;
676 u_int ux;
677#endif /* APIC_IO */
91f1c7a4 678 vm_paddr_t mpfps_paddr;
46d4e165
JG
679
680 POSTCODE(MP_ENABLE_POST);
681
8f54b133 682 if (madt_probe_test) {
699b0754 683 mpfps_paddr = 0;
8f54b133 684 } else {
699b0754 685 mpfps_paddr = mptable_probe();
8f54b133
MN
686 if (mptable_check(mpfps_paddr))
687 mpfps_paddr = 0;
688 }
8e4c6923 689
699b0754 690 if (mpfps_paddr) {
4ad5917f
MN
691 struct mptable_pos mpt;
692
699b0754 693 mptable_map(&mpt, mpfps_paddr);
f592025a 694
699b0754
MN
695 /*
696 * We can safely map physical memory into SMPpt after
697 * mptable_pass1() completes.
698 */
699 mptable_pass1(&mpt);
46d4e165 700
699b0754
MN
701 if (cpu_apic_address == 0)
702 panic("mp_enable: no local apic!\n");
9ad60dda 703
699b0754
MN
704 /* examine the MP table for needed info */
705 x = mptable_pass2(&mpt);
9ad60dda 706
699b0754 707 mptable_unmap(&mpt);
46d4e165 708
699b0754
MN
709 /*
710 * can't process default configs till the
711 * CPU APIC is pmapped
712 */
713 if (x)
714 mptable_default(x);
46d4e165 715
699b0754
MN
716 /* post scan cleanup */
717 mptable_fix();
e3dd742d
MD
718
719 /*
720 * lapic not mapped yet (pmap_init is called too late)
721 */
722 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
723 sizeof(struct LAPIC));
699b0754 724 } else {
4ad5917f
MN
725 vm_paddr_t madt_paddr;
726 int bsp_apic_id;
727
728 madt_paddr = madt_probe();
729 if (madt_paddr == 0)
699b0754 730 panic("mp_enable: madt_probe failed\n");
46d4e165 731
4ad5917f 732 cpu_apic_address = madt_pass1(madt_paddr);
699b0754
MN
733 if (cpu_apic_address == 0)
734 panic("mp_enable: no local apic (madt)!\n");
4ad5917f 735
ff76b364 736 /*
e3dd742d
MD
737 * lapic not mapped yet (pmap_init is called too late)
738 *
ff76b364
MN
739 * XXX: where is the best place to set lapic?
740 */
e3dd742d
MD
741 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
742 sizeof(struct LAPIC));
ff76b364
MN
743
744 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
4ad5917f
MN
745 if (madt_pass2(madt_paddr, bsp_apic_id))
746 panic("mp_enable: madt_pass2 failed\n");
699b0754 747 }
46d4e165
JG
748
749#if defined(APIC_IO)
750
751 setup_apic_irq_mapping();
752
753 /* fill the LOGICAL io_apic_versions table */
754 for (apic = 0; apic < mp_napics; ++apic) {
755 ux = io_apic_read(apic, IOAPIC_VER);
756 io_apic_versions[apic] = ux;
757 io_apic_set_id(apic, IO_TO_ID(apic));
758 }
759
760 /* program each IO APIC in the system */
761 for (apic = 0; apic < mp_napics; ++apic)
762 if (io_apic_setup(apic) < 0)
763 panic("IO APIC setup failure");
764
765#endif /* APIC_IO */
766
767 /*
768 * These are required for SMP operation
769 */
770
771 /* install a 'Spurious INTerrupt' vector */
772 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
a4f18b62 773 SDT_SYSIGT, SEL_KPL, 0);
46d4e165
JG
774
775 /* install an inter-CPU IPI for TLB invalidation */
776 setidt(XINVLTLB_OFFSET, Xinvltlb,
a4f18b62 777 SDT_SYSIGT, SEL_KPL, 0);
46d4e165
JG
778
779 /* install an inter-CPU IPI for IPIQ messaging */
780 setidt(XIPIQ_OFFSET, Xipiq,
a4f18b62 781 SDT_SYSIGT, SEL_KPL, 0);
46d4e165
JG
782
783 /* install a timer vector */
784 setidt(XTIMER_OFFSET, Xtimer,
a4f18b62 785 SDT_SYSIGT, SEL_KPL, 0);
46d4e165
JG
786
787 /* install an inter-CPU IPI for CPU stop/restart */
788 setidt(XCPUSTOP_OFFSET, Xcpustop,
a4f18b62 789 SDT_SYSIGT, SEL_KPL, 0);
46d4e165
JG
790
791 /* start each Application Processor */
792 start_all_aps(boot_addr);
793}
794
795
796/*
797 * look for the MP spec signature
798 */
799
800/* string defined by the Intel MP Spec as identifying the MP table */
801#define MP_SIG 0x5f504d5f /* _MP_ */
802#define NEXT(X) ((X) += 4)
3a918cfd 803static long
0eaa8172 804mptable_search_sig(u_int32_t target, int count)
46d4e165 805{
f592025a
MN
806 vm_size_t map_size;
807 u_int32_t *addr;
808 int x, ret;
46d4e165 809
351254e7
MN
810 KKASSERT(target != 0);
811
f592025a
MN
812 map_size = count * sizeof(u_int32_t);
813 addr = pmap_mapdev((vm_paddr_t)target, map_size);
46d4e165 814
351254e7 815 ret = 0;
f592025a
MN
816 for (x = 0; x < count; NEXT(x)) {
817 if (addr[x] == MP_SIG) {
818 /* make array index a byte index */
819 ret = target + (x * sizeof(u_int32_t));
820 break;
821 }
822 }
351254e7 823
f592025a
MN
824 pmap_unmapdev((vm_offset_t)addr, map_size);
825 return ret;
46d4e165
JG
826}
827
828
46d4e165
JG
829typedef struct BUSDATA {
830 u_char bus_id;
831 enum busTypes bus_type;
832} bus_datum;
833
834typedef struct INTDATA {
835 u_char int_type;
836 u_short int_flags;
837 u_char src_bus_id;
838 u_char src_bus_irq;
839 u_char dst_apic_id;
840 u_char dst_apic_int;
841 u_char int_vector;
842} io_int, local_int;
843
844typedef struct BUSTYPENAME {
845 u_char type;
846 char name[7];
847} bus_type_name;
848
67baedb9
MN
849#ifdef APIC_IO
850
46d4e165
JG
851static bus_type_name bus_type_table[] =
852{
853 {CBUS, "CBUS"},
854 {CBUSII, "CBUSII"},
855 {EISA, "EISA"},
856 {MCA, "MCA"},
857 {UNKNOWN_BUSTYPE, "---"},
858 {ISA, "ISA"},
859 {MCA, "MCA"},
860 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"},
862 {UNKNOWN_BUSTYPE, "---"},
863 {UNKNOWN_BUSTYPE, "---"},
864 {UNKNOWN_BUSTYPE, "---"},
865 {PCI, "PCI"},
866 {UNKNOWN_BUSTYPE, "---"},
867 {UNKNOWN_BUSTYPE, "---"},
868 {UNKNOWN_BUSTYPE, "---"},
869 {UNKNOWN_BUSTYPE, "---"},
870 {XPRESS, "XPRESS"},
871 {UNKNOWN_BUSTYPE, "---"}
872};
67baedb9 873
46d4e165
JG
874/* from MP spec v1.4, table 5-1 */
875static int default_data[7][5] =
876{
877/* nbus, id0, type0, id1, type1 */
878 {1, 0, ISA, 255, 255},
879 {1, 0, EISA, 255, 255},
880 {1, 0, EISA, 255, 255},
881 {1, 0, MCA, 255, 255},
882 {2, 0, ISA, 1, PCI},
883 {2, 0, EISA, 1, PCI},
884 {2, 0, MCA, 1, PCI}
885};
886
46d4e165
JG
887/* the bus data */
888static bus_datum *bus_data;
889
46d4e165
JG
890/* the IO INT data, one entry per possible APIC INTerrupt */
891static io_int *io_apic_ints;
892static int nintrs;
c784234d 893
46d4e165
JG
894#endif
895
896static int processor_entry (proc_entry_ptr entry, int cpu);
46d4e165 897#ifdef APIC_IO
c784234d 898static int bus_entry (bus_entry_ptr entry, int bus);
46d4e165
JG
899static int io_apic_entry (io_apic_entry_ptr entry, int apic);
900static int int_entry (int_entry_ptr entry, int intr);
46d4e165 901static int lookup_bus_type (char *name);
67baedb9 902#endif
46d4e165
JG
903
904
905/*
906 * 1st pass on motherboard's Intel MP specification table.
907 *
46d4e165
JG
908 * determines:
909 * cpu_apic_address (common to all CPUs)
910 * io_apic_address[N]
911 * mp_naps
912 * mp_nbusses
913 * mp_napics
914 * nintrs
0ecea546
MN
915 * need_hyperthreading_fixup
916 * logical_cpus
46d4e165
JG
917 */
918static void
91f1c7a4 919mptable_pass1(struct mptable_pos *mpt)
46d4e165
JG
920{
921#ifdef APIC_IO
922 int x;
923#endif
91f1c7a4 924 mpfps_t fps;
46d4e165
JG
925 mpcth_t cth;
926 int totalSize;
927 void* position;
928 int count;
929 int type;
930 u_int id_mask;
931
932 POSTCODE(MPTABLE_PASS1_POST);
933
91f1c7a4
MN
934 fps = mpt->mp_fps;
935 KKASSERT(fps != NULL);
9ad60dda 936
46d4e165
JG
937#ifdef APIC_IO
938 /* clear various tables */
939 for (x = 0; x < NAPICID; ++x) {
940 io_apic_address[x] = ~0; /* IO APIC address table */
941 }
942#endif
943
944 /* init everything to empty */
945 mp_naps = 0;
46d4e165 946#ifdef APIC_IO
c784234d 947 mp_nbusses = 0;
46d4e165
JG
948 mp_napics = 0;
949 nintrs = 0;
950#endif
951 id_mask = 0;
952
953 /* check for use of 'default' configuration */
91f1c7a4 954 if (fps->mpfb1 != 0) {
46d4e165
JG
955 /* use default addresses */
956 cpu_apic_address = DEFAULT_APIC_BASE;
957#ifdef APIC_IO
958 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
959#endif
960
961 /* fill in with defaults */
962 mp_naps = 2; /* includes BSP */
46d4e165 963#if defined(APIC_IO)
c784234d 964 mp_nbusses = default_data[fps->mpfb1 - 1][0];
46d4e165
JG
965 mp_napics = 1;
966 nintrs = 16;
967#endif /* APIC_IO */
968 }
969 else {
91f1c7a4
MN
970 cth = mpt->mp_cth;
971 if (cth == NULL)
46d4e165
JG
972 panic("MP Configuration Table Header MISSING!");
973
974 cpu_apic_address = (vm_offset_t) cth->apic_address;
975
976 /* walk the table, recording info of interest */
977 totalSize = cth->base_table_length - sizeof(struct MPCTH);
978 position = (u_char *) cth + sizeof(struct MPCTH);
979 count = cth->entry_count;
980
981 while (count--) {
982 switch (type = *(u_char *) position) {
983 case 0: /* processor_entry */
984 if (((proc_entry_ptr)position)->cpu_flags
985 & PROCENTRY_FLAG_EN) {
986 ++mp_naps;
987 id_mask |= 1 <<
988 ((proc_entry_ptr)position)->apic_id;
989 }
990 break;
991 case 1: /* bus_entry */
c784234d 992#ifdef APIC_IO
46d4e165 993 ++mp_nbusses;
c784234d 994#endif
46d4e165
JG
995 break;
996 case 2: /* io_apic_entry */
997#ifdef APIC_IO
998 if (((io_apic_entry_ptr)position)->apic_flags
999 & IOAPICENTRY_FLAG_EN)
1000 io_apic_address[mp_napics++] =
1001 (vm_offset_t)((io_apic_entry_ptr)
1002 position)->apic_address;
1003#endif
1004 break;
1005 case 3: /* int_entry */
1006#ifdef APIC_IO
1007 ++nintrs;
1008#endif
1009 break;
1010 case 4: /* int_entry */
1011 break;
1012 default:
1013 panic("mpfps Base Table HOSED!");
1014 /* NOTREACHED */
1015 }
1016
1017 totalSize -= basetable_entry_types[type].length;
1018 position = (uint8_t *)position +
1019 basetable_entry_types[type].length;
1020 }
1021 }
1022
1023 /* qualify the numbers */
1024 if (mp_naps > MAXCPU) {
1025 kprintf("Warning: only using %d of %d available CPUs!\n",
1026 MAXCPU, mp_naps);
1027 mp_naps = MAXCPU;
1028 }
1029
1030 /* See if we need to fixup HT logical CPUs. */
1031 mptable_hyperthread_fixup(id_mask);
46d4e165
JG
1032
1033 --mp_naps; /* subtract the BSP */
1034}
1035
1036
1037/*
1038 * 2nd pass on motherboard's Intel MP specification table.
1039 *
1040 * sets:
0ecea546 1041 * logical_cpus_mask
46d4e165
JG
1042 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
1043 * CPU_TO_ID(N), logical CPU to APIC ID table
1044 * IO_TO_ID(N), logical IO to APIC ID table
1045 * bus_data[N]
1046 * io_apic_ints[N]
1047 */
1048static int
91f1c7a4 1049mptable_pass2(struct mptable_pos *mpt)
46d4e165
JG
1050{
1051 struct PROCENTRY proc;
1052 int x;
91f1c7a4 1053 mpfps_t fps;
46d4e165
JG
1054 mpcth_t cth;
1055 int totalSize;
1056 void* position;
1057 int count;
1058 int type;
1059 int apic, bus, cpu, intr;
1060 int i;
1061
1062 POSTCODE(MPTABLE_PASS2_POST);
1063
91f1c7a4
MN
1064 fps = mpt->mp_fps;
1065 KKASSERT(fps != NULL);
1066
46d4e165
JG
1067 /* Initialize fake proc entry for use with HT fixup. */
1068 bzero(&proc, sizeof(proc));
1069 proc.type = 0;
1070 proc.cpu_flags = PROCENTRY_FLAG_EN;
1071
1072#ifdef APIC_IO
1073 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1074 M_DEVBUF, M_WAITOK);
1075 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1076 M_DEVBUF, M_WAITOK | M_ZERO);
1077 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1078 M_DEVBUF, M_WAITOK);
46d4e165
JG
1079 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1080 M_DEVBUF, M_WAITOK);
c784234d 1081#endif
46d4e165
JG
1082
1083#ifdef APIC_IO
1084 for (i = 0; i < mp_napics; i++) {
1085 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1086 }
1087#endif
1088
1089 /* clear various tables */
1090 for (x = 0; x < NAPICID; ++x) {
1091 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
1092#ifdef APIC_IO
1093 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1094 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1095#endif
1096 }
1097
c784234d 1098#ifdef APIC_IO
46d4e165
JG
1099 /* clear bus data table */
1100 for (x = 0; x < mp_nbusses; ++x)
1101 bus_data[x].bus_id = 0xff;
1102
46d4e165
JG
1103 /* clear IO APIC INT table */
1104 for (x = 0; x < (nintrs + 1); ++x) {
1105 io_apic_ints[x].int_type = 0xff;
1106 io_apic_ints[x].int_vector = 0xff;
1107 }
1108#endif
1109
46d4e165 1110 /* record whether PIC or virtual-wire mode */
91f1c7a4 1111 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
46d4e165
JG
1112
1113 /* check for use of 'default' configuration */
91f1c7a4
MN
1114 if (fps->mpfb1 != 0)
1115 return fps->mpfb1; /* return default configuration type */
46d4e165 1116
91f1c7a4
MN
1117 cth = mpt->mp_cth;
1118 if (cth == NULL)
46d4e165
JG
1119 panic("MP Configuration Table Header MISSING!");
1120
1121 /* walk the table, recording info of interest */
1122 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1123 position = (u_char *) cth + sizeof(struct MPCTH);
1124 count = cth->entry_count;
1125 apic = bus = intr = 0;
1126 cpu = 1; /* pre-count the BSP */
1127
1128 while (count--) {
1129 switch (type = *(u_char *) position) {
1130 case 0:
1131 if (processor_entry(position, cpu))
1132 ++cpu;
1133
1134 if (need_hyperthreading_fixup) {
1135 /*
1136 * Create fake mptable processor entries
1137 * and feed them to processor_entry() to
1138 * enumerate the logical CPUs.
1139 */
1140 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1141 for (i = 1; i < logical_cpus; i++) {
1142 proc.apic_id++;
1143 processor_entry(&proc, cpu);
1144 logical_cpus_mask |= (1 << cpu);
1145 cpu++;
1146 }
1147 }
1148 break;
1149 case 1:
c784234d 1150#ifdef APIC_IO
46d4e165
JG
1151 if (bus_entry(position, bus))
1152 ++bus;
c784234d 1153#endif
46d4e165
JG
1154 break;
1155 case 2:
1156#ifdef APIC_IO
1157 if (io_apic_entry(position, apic))
1158 ++apic;
1159#endif
1160 break;
1161 case 3:
1162#ifdef APIC_IO
1163 if (int_entry(position, intr))
1164 ++intr;
1165#endif
1166 break;
1167 case 4:
1168 /* int_entry(position); */
1169 break;
1170 default:
1171 panic("mpfps Base Table HOSED!");
1172 /* NOTREACHED */
1173 }
1174
1175 totalSize -= basetable_entry_types[type].length;
1176 position = (uint8_t *)position + basetable_entry_types[type].length;
1177 }
1178
bfa17615 1179 if (CPU_TO_ID(0) < 0)
46d4e165
JG
1180 panic("NO BSP found!");
1181
1182 /* report fact that its NOT a default configuration */
1183 return 0;
1184}
1185
91f1c7a4 1186
46d4e165
JG
1187/*
1188 * Check if we should perform a hyperthreading "fix-up" to
1189 * enumerate any logical CPU's that aren't already listed
1190 * in the table.
1191 *
1192 * XXX: We assume that all of the physical CPUs in the
1193 * system have the same number of logical CPUs.
1194 *
1195 * XXX: We assume that APIC ID's are allocated such that
1196 * the APIC ID's for a physical processor are aligned
1197 * with the number of logical CPU's in the processor.
1198 */
1199static void
1200mptable_hyperthread_fixup(u_int id_mask)
1201{
f5abf528 1202 int i, id, lcpus_max;
46d4e165 1203
46d4e165
JG
1204 if ((cpu_feature & CPUID_HTT) == 0)
1205 return;
f5abf528
MN
1206
1207 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1208 if (lcpus_max <= 1)
46d4e165
JG
1209 return;
1210
f5abf528
MN
1211 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1212 /*
1213 * INSTRUCTION SET REFERENCE, A-M (#253666)
1214 * Page 3-181, Table 3-20
1215 * "The nearest power-of-2 integer that is not smaller
1216 * than EBX[23:16] is the number of unique initial APIC
1217 * IDs reserved for addressing different logical
1218 * processors in a physical package."
1219 */
1220 for (i = 0; ; ++i) {
1221 if ((1 << i) >= lcpus_max) {
1222 lcpus_max = 1 << i;
1223 break;
1224 }
1225 }
1226 }
1227
1228 if (mp_naps == lcpus_max) {
1229 /* We have nothing to fix */
1230 return;
1231 } else if (mp_naps == 1) {
1232 /* XXX this may be incorrect */
1233 logical_cpus = lcpus_max;
1234 } else {
1235 int cur, prev, dist;
1236
1237 /*
1238 * Calculate the distances between two nearest
1239 * APIC IDs. If all such distances are same,
1240 * then it is the number of missing cpus that
1241 * we are going to fill later.
1242 */
1243 dist = cur = prev = -1;
1244 for (id = 0; id < MAXCPU; ++id) {
1245 if ((id_mask & 1 << id) == 0)
1246 continue;
1247
1248 cur = id;
1249 if (prev >= 0) {
1250 int new_dist = cur - prev;
1251
1252 if (dist < 0)
1253 dist = new_dist;
1254
1255 /*
1256 * Make sure that all distances
1257 * between two nearest APIC IDs
1258 * are same.
1259 */
1260 if (dist != new_dist)
1261 return;
1262 }
1263 prev = cur;
1264 }
1265 if (dist == 1)
1266 return;
1267
1268 /* Must be power of 2 */
1269 if (dist & (dist - 1))
1270 return;
1271
1272 /* Can't exceed CPU package capacity */
1273 if (dist > lcpus_max)
1274 logical_cpus = lcpus_max;
1275 else
1276 logical_cpus = dist;
1277 }
1278
46d4e165
JG
1279 /*
1280 * For each APIC ID of a CPU that is set in the mask,
1281 * scan the other candidate APIC ID's for this
1282 * physical processor. If any of those ID's are
1283 * already in the table, then kill the fixup.
1284 */
f5abf528 1285 for (id = 0; id < MAXCPU; id++) {
46d4e165
JG
1286 if ((id_mask & 1 << id) == 0)
1287 continue;
1288 /* First, make sure we are on a logical_cpus boundary. */
1289 if (id % logical_cpus != 0)
1290 return;
1291 for (i = id + 1; i < id + logical_cpus; i++)
1292 if ((id_mask & 1 << i) != 0)
1293 return;
1294 }
1295
1296 /*
1297 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1298 * mp_naps right now.
1299 */
1300 need_hyperthreading_fixup = 1;
1301 mp_naps *= logical_cpus;
1302}
1303
8f54b133 1304static int
91f1c7a4
MN
1305mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1306{
1307 mpfps_t fps = NULL;
1308 mpcth_t cth = NULL;
1309 vm_size_t cth_mapsz = 0;
1310
8f54b133
MN
1311 bzero(mpt, sizeof(*mpt));
1312
91f1c7a4
MN
1313 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1314 if (fps->pap != 0) {
1315 /*
1316 * Map configuration table header to get
1317 * the base table size
1318 */
1319 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1320 cth_mapsz = cth->base_table_length;
1321 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1322
8f54b133
MN
1323 if (cth_mapsz < sizeof(*cth)) {
1324 kprintf("invalid base MP table length %d\n",
1325 (int)cth_mapsz);
1326 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1327 return EINVAL;
1328 }
1329
91f1c7a4
MN
1330 /*
1331 * Map the base table
1332 */
1333 cth = pmap_mapdev(fps->pap, cth_mapsz);
1334 }
1335
1336 mpt->mp_fps = fps;
1337 mpt->mp_cth = cth;
1338 mpt->mp_cth_mapsz = cth_mapsz;
8f54b133
MN
1339
1340 return 0;
91f1c7a4
MN
1341}
1342
1343static void
1344mptable_unmap(struct mptable_pos *mpt)
1345{
1346 if (mpt->mp_cth != NULL) {
1347 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1348 mpt->mp_cth = NULL;
1349 mpt->mp_cth_mapsz = 0;
1350 }
1351 if (mpt->mp_fps != NULL) {
1352 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1353 mpt->mp_fps = NULL;
1354 }
1355}
1356
46d4e165
JG
1357#ifdef APIC_IO
1358
1359void
1360assign_apic_irq(int apic, int intpin, int irq)
1361{
1362 int x;
1363
1364 if (int_to_apicintpin[irq].ioapic != -1)
1365 panic("assign_apic_irq: inconsistent table");
1366
1367 int_to_apicintpin[irq].ioapic = apic;
1368 int_to_apicintpin[irq].int_pin = intpin;
1369 int_to_apicintpin[irq].apic_address = ioapic[apic];
1370 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1371
1372 for (x = 0; x < nintrs; x++) {
1373 if ((io_apic_ints[x].int_type == 0 ||
1374 io_apic_ints[x].int_type == 3) &&
1375 io_apic_ints[x].int_vector == 0xff &&
1376 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1377 io_apic_ints[x].dst_apic_int == intpin)
1378 io_apic_ints[x].int_vector = irq;
1379 }
1380}
1381
1382void
1383revoke_apic_irq(int irq)
1384{
1385 int x;
1386 int oldapic;
1387 int oldintpin;
1388
1389 if (int_to_apicintpin[irq].ioapic == -1)
1390 panic("revoke_apic_irq: inconsistent table");
1391
1392 oldapic = int_to_apicintpin[irq].ioapic;
1393 oldintpin = int_to_apicintpin[irq].int_pin;
1394
1395 int_to_apicintpin[irq].ioapic = -1;
1396 int_to_apicintpin[irq].int_pin = 0;
1397 int_to_apicintpin[irq].apic_address = NULL;
1398 int_to_apicintpin[irq].redirindex = 0;
1399
1400 for (x = 0; x < nintrs; x++) {
1401 if ((io_apic_ints[x].int_type == 0 ||
1402 io_apic_ints[x].int_type == 3) &&
1403 io_apic_ints[x].int_vector != 0xff &&
1404 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1405 io_apic_ints[x].dst_apic_int == oldintpin)
1406 io_apic_ints[x].int_vector = 0xff;
1407 }
1408}
1409
1410/*
1411 * Allocate an IRQ
1412 */
1413static void
1414allocate_apic_irq(int intr)
1415{
1416 int apic;
1417 int intpin;
1418 int irq;
1419
1420 if (io_apic_ints[intr].int_vector != 0xff)
1421 return; /* Interrupt handler already assigned */
1422
1423 if (io_apic_ints[intr].int_type != 0 &&
1424 (io_apic_ints[intr].int_type != 3 ||
1425 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1426 io_apic_ints[intr].dst_apic_int == 0)))
1427 return; /* Not INT or ExtInt on != (0, 0) */
1428
1429 irq = 0;
1430 while (irq < APIC_INTMAPSIZE &&
1431 int_to_apicintpin[irq].ioapic != -1)
1432 irq++;
1433
1434 if (irq >= APIC_INTMAPSIZE)
1435 return; /* No free interrupt handlers */
1436
1437 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1438 intpin = io_apic_ints[intr].dst_apic_int;
1439
1440 assign_apic_irq(apic, intpin, irq);
46d4e165
JG
1441}
1442
1443
1444static void
1445swap_apic_id(int apic, int oldid, int newid)
1446{
1447 int x;
1448 int oapic;
1449
1450
1451 if (oldid == newid)
1452 return; /* Nothing to do */
1453
1454 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1455 apic, oldid, newid);
1456
1457 /* Swap physical APIC IDs in interrupt entries */
1458 for (x = 0; x < nintrs; x++) {
1459 if (io_apic_ints[x].dst_apic_id == oldid)
1460 io_apic_ints[x].dst_apic_id = newid;
1461 else if (io_apic_ints[x].dst_apic_id == newid)
1462 io_apic_ints[x].dst_apic_id = oldid;
1463 }
1464
1465 /* Swap physical APIC IDs in IO_TO_ID mappings */
1466 for (oapic = 0; oapic < mp_napics; oapic++)
1467 if (IO_TO_ID(oapic) == newid)
1468 break;
1469
1470 if (oapic < mp_napics) {
1471 kprintf("Changing APIC ID for IO APIC #%d from "
1472 "%d to %d in MP table\n",
1473 oapic, newid, oldid);
1474 IO_TO_ID(oapic) = oldid;
1475 }
1476 IO_TO_ID(apic) = newid;
1477}
1478
1479
1480static void
1481fix_id_to_io_mapping(void)
1482{
1483 int x;
1484
1485 for (x = 0; x < NAPICID; x++)
1486 ID_TO_IO(x) = -1;
1487
1488 for (x = 0; x <= mp_naps; x++)
1489 if (CPU_TO_ID(x) < NAPICID)
1490 ID_TO_IO(CPU_TO_ID(x)) = x;
1491
1492 for (x = 0; x < mp_napics; x++)
1493 if (IO_TO_ID(x) < NAPICID)
1494 ID_TO_IO(IO_TO_ID(x)) = x;
1495}
1496
1497
1498static int
1499first_free_apic_id(void)
1500{
1501 int freeid, x;
1502
1503 for (freeid = 0; freeid < NAPICID; freeid++) {
1504 for (x = 0; x <= mp_naps; x++)
1505 if (CPU_TO_ID(x) == freeid)
1506 break;
1507 if (x <= mp_naps)
1508 continue;
1509 for (x = 0; x < mp_napics; x++)
1510 if (IO_TO_ID(x) == freeid)
1511 break;
1512 if (x < mp_napics)
1513 continue;
1514 return freeid;
1515 }
1516 return freeid;
1517}
1518
1519
1520static int
1521io_apic_id_acceptable(int apic, int id)
1522{
1523 int cpu; /* Logical CPU number */
1524 int oapic; /* Logical IO APIC number for other IO APIC */
1525
1526 if (id >= NAPICID)
1527 return 0; /* Out of range */
1528
1529 for (cpu = 0; cpu <= mp_naps; cpu++)
1530 if (CPU_TO_ID(cpu) == id)
1531 return 0; /* Conflict with CPU */
1532
1533 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1534 if (IO_TO_ID(oapic) == id)
1535 return 0; /* Conflict with other APIC */
1536
1537 return 1; /* ID is acceptable for IO APIC */
1538}
1539
1540static
1541io_int *
1542io_apic_find_int_entry(int apic, int pin)
1543{
1544 int x;
1545
1546 /* search each of the possible INTerrupt sources */
1547 for (x = 0; x < nintrs; ++x) {
1548 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1549 (pin == io_apic_ints[x].dst_apic_int))
1550 return (&io_apic_ints[x]);
1551 }
1552 return NULL;
1553}
1554
1555#endif
1556
1557/*
1558 * parse an Intel MP specification table
1559 */
1560static void
0eaa8172 1561mptable_fix(void)
46d4e165 1562{
46d4e165 1563#ifdef APIC_IO
c784234d 1564 int x;
46d4e165
JG
1565 int id;
1566 int apic; /* IO APIC unit number */
1567 int freeid; /* Free physical APIC ID */
1568 int physid; /* Current physical IO APIC ID */
1569 io_int *io14;
46d4e165
JG
1570 int bus_0 = 0; /* Stop GCC warning */
1571 int bus_pci = 0; /* Stop GCC warning */
1572 int num_pci_bus;
1573
1574 /*
1575 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1576 * did it wrong. The MP spec says that when more than 1 PCI bus
1577 * exists the BIOS must begin with bus entries for the PCI bus and use
1578 * actual PCI bus numbering. This implies that when only 1 PCI bus
1579 * exists the BIOS can choose to ignore this ordering, and indeed many
1580 * MP motherboards do ignore it. This causes a problem when the PCI
1581 * sub-system makes requests of the MP sub-system based on PCI bus
1582 * numbers. So here we look for the situation and renumber the
1583 * busses and associated INTs in an effort to "make it right".
1584 */
1585
1586 /* find bus 0, PCI bus, count the number of PCI busses */
1587 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1588 if (bus_data[x].bus_id == 0) {
1589 bus_0 = x;
1590 }
1591 if (bus_data[x].bus_type == PCI) {
1592 ++num_pci_bus;
1593 bus_pci = x;
1594 }
1595 }
1596 /*
1597 * bus_0 == slot of bus with ID of 0
1598 * bus_pci == slot of last PCI bus encountered
1599 */
1600
1601 /* check the 1 PCI bus case for sanity */
1602 /* if it is number 0 all is well */
1603 if (num_pci_bus == 1 &&
1604 bus_data[bus_pci].bus_id != 0) {
1605
1606 /* mis-numbered, swap with whichever bus uses slot 0 */
1607
1608 /* swap the bus entry types */
1609 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1610 bus_data[bus_0].bus_type = PCI;
1611
46d4e165
JG
1612 /* swap each relavant INTerrupt entry */
1613 id = bus_data[bus_pci].bus_id;
1614 for (x = 0; x < nintrs; ++x) {
1615 if (io_apic_ints[x].src_bus_id == id) {
1616 io_apic_ints[x].src_bus_id = 0;
1617 }
1618 else if (io_apic_ints[x].src_bus_id == 0) {
1619 io_apic_ints[x].src_bus_id = id;
1620 }
1621 }
46d4e165
JG
1622 }
1623
46d4e165
JG
1624 /* Assign IO APIC IDs.
1625 *
1626 * First try the existing ID. If a conflict is detected, try
1627 * the ID in the MP table. If a conflict is still detected, find
1628 * a free id.
1629 *
1630 * We cannot use the ID_TO_IO table before all conflicts has been
1631 * resolved and the table has been corrected.
1632 */
1633 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1634
1635 /* First try to use the value set by the BIOS */
1636 physid = io_apic_get_id(apic);
1637 if (io_apic_id_acceptable(apic, physid)) {
1638 if (IO_TO_ID(apic) != physid)
1639 swap_apic_id(apic, IO_TO_ID(apic), physid);
1640 continue;
1641 }
1642
1643 /* Then check if the value in the MP table is acceptable */
1644 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1645 continue;
1646
1647 /* Last resort, find a free APIC ID and use it */
1648 freeid = first_free_apic_id();
1649 if (freeid >= NAPICID)
1650 panic("No free physical APIC IDs found");
1651
1652 if (io_apic_id_acceptable(apic, freeid)) {
1653 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1654 continue;
1655 }
1656 panic("Free physical APIC ID not usable");
1657 }
1658 fix_id_to_io_mapping();
46d4e165 1659
46d4e165
JG
1660 /* detect and fix broken Compaq MP table */
1661 if (apic_int_type(0, 0) == -1) {
1662 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1663 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1664 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1665 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1666 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1667 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1668 nintrs++;
1669 } else if (apic_int_type(0, 0) == 0) {
1670 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1671 for (x = 0; x < nintrs; ++x)
1672 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1673 (0 == io_apic_ints[x].dst_apic_int)) {
1674 io_apic_ints[x].int_type = 3;
1675 io_apic_ints[x].int_vector = 0xff;
1676 break;
1677 }
1678 }
1679
1680 /*
1681 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1682 * controllers universally come in pairs. If IRQ 14 is specified
1683 * as an ISA interrupt, then IRQ 15 had better be too.
1684 *
1685 * [ Shuttle XPC / AMD Athlon X2 ]
1686 * The MPTable is missing an entry for IRQ 15. Note that the
1687 * ACPI table has an entry for both 14 and 15.
1688 */
1689 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1690 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1691 io14 = io_apic_find_int_entry(0, 14);
1692 io_apic_ints[nintrs] = *io14;
1693 io_apic_ints[nintrs].src_bus_irq = 15;
1694 io_apic_ints[nintrs].dst_apic_int = 15;
1695 nintrs++;
1696 }
1697#endif
1698}
1699
1700#ifdef APIC_IO
1701
1702/* Assign low level interrupt handlers */
1703static void
1704setup_apic_irq_mapping(void)
1705{
1706 int x;
1707 int int_vector;
1708
1709 /* Clear array */
1710 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1711 int_to_apicintpin[x].ioapic = -1;
1712 int_to_apicintpin[x].int_pin = 0;
1713 int_to_apicintpin[x].apic_address = NULL;
1714 int_to_apicintpin[x].redirindex = 0;
1715 }
1716
1717 /* First assign ISA/EISA interrupts */
1718 for (x = 0; x < nintrs; x++) {
1719 int_vector = io_apic_ints[x].src_bus_irq;
1720 if (int_vector < APIC_INTMAPSIZE &&
1721 io_apic_ints[x].int_vector == 0xff &&
1722 int_to_apicintpin[int_vector].ioapic == -1 &&
1723 (apic_int_is_bus_type(x, ISA) ||
1724 apic_int_is_bus_type(x, EISA)) &&
1725 io_apic_ints[x].int_type == 0) {
1726 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1727 io_apic_ints[x].dst_apic_int,
1728 int_vector);
1729 }
1730 }
1731
1732 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1733 for (x = 0; x < nintrs; x++) {
1734 if (io_apic_ints[x].dst_apic_int == 0 &&
1735 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1736 io_apic_ints[x].int_vector == 0xff &&
1737 int_to_apicintpin[0].ioapic == -1 &&
1738 io_apic_ints[x].int_type == 3) {
1739 assign_apic_irq(0, 0, 0);
1740 break;
1741 }
1742 }
662f60ef
SZ
1743
1744 /* Assign PCI interrupts */
1745 for (x = 0; x < nintrs; ++x) {
1746 if (io_apic_ints[x].int_type == 0 &&
1747 io_apic_ints[x].int_vector == 0xff &&
1748 apic_int_is_bus_type(x, PCI))
1749 allocate_apic_irq(x);
1750 }
46d4e165
JG
1751}
1752
1753#endif
1754
40d323b6
MN
1755void
1756mp_set_cpuids(int cpu_id, int apic_id)
1757{
1758 CPU_TO_ID(cpu_id) = apic_id;
1759 ID_TO_CPU(apic_id) = cpu_id;
1760}
1761
46d4e165
JG
1762static int
1763processor_entry(proc_entry_ptr entry, int cpu)
1764{
bfa17615
MN
1765 KKASSERT(cpu > 0);
1766
46d4e165
JG
1767 /* check for usability */
1768 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1769 return 0;
1770
1771 if(entry->apic_id >= NAPICID)
1772 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1773 /* check for BSP flag */
1774 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
40d323b6 1775 mp_set_cpuids(0, entry->apic_id);
46d4e165
JG
1776 return 0; /* its already been counted */
1777 }
1778
1779 /* add another AP to list, if less than max number of CPUs */
1780 else if (cpu < MAXCPU) {
40d323b6 1781 mp_set_cpuids(cpu, entry->apic_id);
46d4e165
JG
1782 return 1;
1783 }
1784
1785 return 0;
1786}
1787
c784234d 1788#ifdef APIC_IO
46d4e165
JG
1789
1790static int
1791bus_entry(bus_entry_ptr entry, int bus)
1792{
1793 int x;
1794 char c, name[8];
1795
1796 /* encode the name into an index */
1797 for (x = 0; x < 6; ++x) {
1798 if ((c = entry->bus_type[x]) == ' ')
1799 break;
1800 name[x] = c;
1801 }
1802 name[x] = '\0';
1803
1804 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1805 panic("unknown bus type: '%s'", name);
1806
1807 bus_data[bus].bus_id = entry->bus_id;
1808 bus_data[bus].bus_type = x;
1809
1810 return 1;
1811}
1812
46d4e165
JG
1813static int
1814io_apic_entry(io_apic_entry_ptr entry, int apic)
1815{
1816 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1817 return 0;
1818
1819 IO_TO_ID(apic) = entry->apic_id;
1820 if (entry->apic_id < NAPICID)
1821 ID_TO_IO(entry->apic_id) = apic;
1822
1823 return 1;
1824}
1825
46d4e165
JG
1826static int
1827lookup_bus_type(char *name)
1828{
1829 int x;
1830
1831 for (x = 0; x < MAX_BUSTYPE; ++x)
1832 if (strcmp(bus_type_table[x].name, name) == 0)
1833 return bus_type_table[x].type;
1834
1835 return UNKNOWN_BUSTYPE;
1836}
1837
46d4e165
JG
1838static int
1839int_entry(int_entry_ptr entry, int intr)
1840{
1841 int apic;
1842
1843 io_apic_ints[intr].int_type = entry->int_type;
1844 io_apic_ints[intr].int_flags = entry->int_flags;
1845 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1846 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1847 if (entry->dst_apic_id == 255) {
1848 /* This signal goes to all IO APICS. Select an IO APIC
1849 with sufficient number of interrupt pins */
1850 for (apic = 0; apic < mp_napics; apic++)
1851 if (((io_apic_read(apic, IOAPIC_VER) &
1852 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1853 entry->dst_apic_int)
1854 break;
1855 if (apic < mp_napics)
1856 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1857 else
1858 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1859 } else
1860 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1861 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1862
1863 return 1;
1864}
1865
1866static int
1867apic_int_is_bus_type(int intr, int bus_type)
1868{
1869 int bus;
1870
1871 for (bus = 0; bus < mp_nbusses; ++bus)
1872 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1873 && ((int) bus_data[bus].bus_type == bus_type))
1874 return 1;
1875
1876 return 0;
1877}
1878
1879/*
1880 * Given a traditional ISA INT mask, return an APIC mask.
1881 */
1882u_int
1883isa_apic_mask(u_int isa_mask)
1884{
1885 int isa_irq;
1886 int apic_pin;
1887
1888#if defined(SKIP_IRQ15_REDIRECT)
1889 if (isa_mask == (1 << 15)) {
1890 kprintf("skipping ISA IRQ15 redirect\n");
1891 return isa_mask;
1892 }
1893#endif /* SKIP_IRQ15_REDIRECT */
1894
1895 isa_irq = ffs(isa_mask); /* find its bit position */
1896 if (isa_irq == 0) /* doesn't exist */
1897 return 0;
1898 --isa_irq; /* make it zero based */
1899
1900 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1901 if (apic_pin == -1)
1902 return 0;
1903
1904 return (1 << apic_pin); /* convert pin# to a mask */
1905}
1906
1907/*
1908 * Determine which APIC pin an ISA/EISA INT is attached to.
1909 */
1910#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1911#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1912#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1913#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1914
1915#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1916int
1917isa_apic_irq(int isa_irq)
1918{
1919 int intr;
1920
1921 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1922 if (INTTYPE(intr) == 0) { /* standard INT */
1923 if (SRCBUSIRQ(intr) == isa_irq) {
1924 if (apic_int_is_bus_type(intr, ISA) ||
1925 apic_int_is_bus_type(intr, EISA)) {
1926 if (INTIRQ(intr) == 0xff)
1927 return -1; /* unassigned */
1928 return INTIRQ(intr); /* found */
1929 }
1930 }
1931 }
1932 }
1933 return -1; /* NOT found */
1934}
1935
1936
1937/*
1938 * Determine which APIC pin a PCI INT is attached to.
1939 */
1940#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1941#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1942#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1943int
1944pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1945{
1946 int intr;
1947
1948 --pciInt; /* zero based */
1949
1950 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1951 if ((INTTYPE(intr) == 0) /* standard INT */
1952 && (SRCBUSID(intr) == pciBus)
1953 && (SRCBUSDEVICE(intr) == pciDevice)
1954 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1955 if (apic_int_is_bus_type(intr, PCI)) {
662f60ef
SZ
1956 if (INTIRQ(intr) == 0xff) {
1957 kprintf("IOAPIC: pci_apic_irq() "
1958 "failed\n");
46d4e165 1959 return -1; /* unassigned */
662f60ef 1960 }
46d4e165
JG
1961 return INTIRQ(intr); /* exact match */
1962 }
1963 }
1964 }
1965
1966 return -1; /* NOT found */
1967}
1968
1969int
1970next_apic_irq(int irq)
1971{
1972 int intr, ointr;
1973 int bus, bustype;
1974
1975 bus = 0;
1976 bustype = 0;
1977 for (intr = 0; intr < nintrs; intr++) {
1978 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1979 continue;
1980 bus = SRCBUSID(intr);
1981 bustype = apic_bus_type(bus);
1982 if (bustype != ISA &&
1983 bustype != EISA &&
1984 bustype != PCI)
1985 continue;
1986 break;
1987 }
1988 if (intr >= nintrs) {
1989 return -1;
1990 }
1991 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1992 if (INTTYPE(ointr) != 0)
1993 continue;
1994 if (bus != SRCBUSID(ointr))
1995 continue;
1996 if (bustype == PCI) {
1997 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1998 continue;
1999 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
2000 continue;
2001 }
2002 if (bustype == ISA || bustype == EISA) {
2003 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
2004 continue;
2005 }
2006 if (INTPIN(intr) == INTPIN(ointr))
2007 continue;
2008 break;
2009 }
2010 if (ointr >= nintrs) {
2011 return -1;
2012 }
2013 return INTIRQ(ointr);
2014}
2015#undef SRCBUSLINE
2016#undef SRCBUSDEVICE
2017#undef SRCBUSID
2018#undef SRCBUSIRQ
2019
2020#undef INTPIN
2021#undef INTIRQ
2022#undef INTAPIC
2023#undef INTTYPE
2024
2025#endif
2026
2027/*
2028 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
2029 *
2030 * XXX FIXME:
2031 * Exactly what this means is unclear at this point. It is a solution
2032 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
2033 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
2034 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
2035 * option.
2036 */
2037int
2038undirect_isa_irq(int rirq)
2039{
2040#if defined(READY)
2041 if (bootverbose)
2042 kprintf("Freeing redirected ISA irq %d.\n", rirq);
2043 /** FIXME: tickle the MB redirector chip */
2044 return /* XXX */;
2045#else
2046 if (bootverbose)
2047 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
2048 return 0;
2049#endif /* READY */
2050}
2051
2052
2053/*
2054 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
2055 */
2056int
2057undirect_pci_irq(int rirq)
2058{
2059#if defined(READY)
2060 if (bootverbose)
2061 kprintf("Freeing redirected PCI irq %d.\n", rirq);
2062
2063 /** FIXME: tickle the MB redirector chip */
2064 return /* XXX */;
2065#else
2066 if (bootverbose)
2067 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
2068 rirq);
2069 return 0;
2070#endif /* READY */
2071}
2072
2073
c784234d
MN
2074#ifdef APIC_IO
2075
46d4e165
JG
2076/*
2077 * given a bus ID, return:
2078 * the bus type if found
2079 * -1 if NOT found
2080 */
2081int
2082apic_bus_type(int id)
2083{
2084 int x;
2085
2086 for (x = 0; x < mp_nbusses; ++x)
2087 if (bus_data[x].bus_id == id)
2088 return bus_data[x].bus_type;
2089
2090 return -1;
2091}
2092
46d4e165
JG
2093/*
2094 * given a LOGICAL APIC# and pin#, return:
2095 * the associated src bus ID if found
2096 * -1 if NOT found
2097 */
2098int
2099apic_src_bus_id(int apic, int pin)
2100{
2101 int x;
2102
2103 /* search each of the possible INTerrupt sources */
2104 for (x = 0; x < nintrs; ++x)
2105 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2106 (pin == io_apic_ints[x].dst_apic_int))
2107 return (io_apic_ints[x].src_bus_id);
2108
2109 return -1; /* NOT found */
2110}
2111
2112/*
2113 * given a LOGICAL APIC# and pin#, return:
2114 * the associated src bus IRQ if found
2115 * -1 if NOT found
2116 */
2117int
2118apic_src_bus_irq(int apic, int pin)
2119{
2120 int x;
2121
2122 for (x = 0; x < nintrs; x++)
2123 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2124 (pin == io_apic_ints[x].dst_apic_int))
2125 return (io_apic_ints[x].src_bus_irq);
2126
2127 return -1; /* NOT found */
2128}
2129
2130
2131/*
2132 * given a LOGICAL APIC# and pin#, return:
2133 * the associated INTerrupt type if found
2134 * -1 if NOT found
2135 */
2136int
2137apic_int_type(int apic, int pin)
2138{
2139 int x;
2140
2141 /* search each of the possible INTerrupt sources */
2142 for (x = 0; x < nintrs; ++x) {
2143 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2144 (pin == io_apic_ints[x].dst_apic_int))
2145 return (io_apic_ints[x].int_type);
2146 }
2147 return -1; /* NOT found */
2148}
2149
2150/*
2151 * Return the IRQ associated with an APIC pin
2152 */
2153int
2154apic_irq(int apic, int pin)
2155{
2156 int x;
2157 int res;
2158
2159 for (x = 0; x < nintrs; ++x) {
2160 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2161 (pin == io_apic_ints[x].dst_apic_int)) {
2162 res = io_apic_ints[x].int_vector;
2163 if (res == 0xff)
2164 return -1;
2165 if (apic != int_to_apicintpin[res].ioapic)
2166 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2167 if (pin != int_to_apicintpin[res].int_pin)
2168 panic("apic_irq inconsistent table (2)");
2169 return res;
2170 }
2171 }
2172 return -1;
2173}
2174
2175
2176/*
2177 * given a LOGICAL APIC# and pin#, return:
2178 * the associated trigger mode if found
2179 * -1 if NOT found
2180 */
2181int
2182apic_trigger(int apic, int pin)
2183{
2184 int x;
2185
2186 /* search each of the possible INTerrupt sources */
2187 for (x = 0; x < nintrs; ++x)
2188 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2189 (pin == io_apic_ints[x].dst_apic_int))
2190 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2191
2192 return -1; /* NOT found */
2193}
2194
2195
2196/*
2197 * given a LOGICAL APIC# and pin#, return:
2198 * the associated 'active' level if found
2199 * -1 if NOT found
2200 */
2201int
2202apic_polarity(int apic, int pin)
2203{
2204 int x;
2205
2206 /* search each of the possible INTerrupt sources */
2207 for (x = 0; x < nintrs; ++x)
2208 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2209 (pin == io_apic_ints[x].dst_apic_int))
2210 return (io_apic_ints[x].int_flags & 0x03);
2211
2212 return -1; /* NOT found */
2213}
2214
2215#endif
2216
2217/*
2218 * set data according to MP defaults
2219 * FIXME: probably not complete yet...
2220 */
2221static void
0eaa8172 2222mptable_default(int type)
46d4e165 2223{
bfa17615 2224 int ap_cpu_id, boot_cpu_id;
46d4e165
JG
2225#if defined(APIC_IO)
2226 int io_apic_id;
2227 int pin;
2228#endif /* APIC_IO */
2229
2230#if 0
2231 kprintf(" MP default config type: %d\n", type);
2232 switch (type) {
2233 case 1:
2234 kprintf(" bus: ISA, APIC: 82489DX\n");
2235 break;
2236 case 2:
2237 kprintf(" bus: EISA, APIC: 82489DX\n");
2238 break;
2239 case 3:
2240 kprintf(" bus: EISA, APIC: 82489DX\n");
2241 break;
2242 case 4:
2243 kprintf(" bus: MCA, APIC: 82489DX\n");
2244 break;
2245 case 5:
2246 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2247 break;
2248 case 6:
2249 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2250 break;
2251 case 7:
2252 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2253 break;
2254 default:
2255 kprintf(" future type\n");
2256 break;
2257 /* NOTREACHED */
2258 }
2259#endif /* 0 */
2260
2261 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2262 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2263
2264 /* BSP */
2265 CPU_TO_ID(0) = boot_cpu_id;
2266 ID_TO_CPU(boot_cpu_id) = 0;
2267
2268 /* one and only AP */
2269 CPU_TO_ID(1) = ap_cpu_id;
2270 ID_TO_CPU(ap_cpu_id) = 1;
2271
2272#if defined(APIC_IO)
2273 /* one and only IO APIC */
2274 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2275
2276 /*
2277 * sanity check, refer to MP spec section 3.6.6, last paragraph
2278 * necessary as some hardware isn't properly setting up the IO APIC
2279 */
2280#if defined(REALLY_ANAL_IOAPICID_VALUE)
2281 if (io_apic_id != 2) {
2282#else
2283 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2284#endif /* REALLY_ANAL_IOAPICID_VALUE */
2285 io_apic_set_id(0, 2);
2286 io_apic_id = 2;
2287 }
2288 IO_TO_ID(0) = io_apic_id;
2289 ID_TO_IO(io_apic_id) = 0;
2290#endif /* APIC_IO */
2291
2292 /* fill out bus entries */
2293 switch (type) {
2294 case 1:
2295 case 2:
2296 case 3:
2297 case 4:
2298 case 5:
2299 case 6:
2300 case 7:
c784234d 2301#ifdef APIC_IO
46d4e165
JG
2302 bus_data[0].bus_id = default_data[type - 1][1];
2303 bus_data[0].bus_type = default_data[type - 1][2];
2304 bus_data[1].bus_id = default_data[type - 1][3];
2305 bus_data[1].bus_type = default_data[type - 1][4];
c784234d 2306#endif
46d4e165
JG
2307 break;
2308
2309 /* case 4: case 7: MCA NOT supported */
2310 default: /* illegal/reserved */
2311 panic("BAD default MP config: %d", type);
2312 /* NOTREACHED */
2313 }
2314
2315#if defined(APIC_IO)
2316 /* general cases from MP v1.4, table 5-2 */
2317 for (pin = 0; pin < 16; ++pin) {
2318 io_apic_ints[pin].int_type = 0;
2319 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2320 io_apic_ints[pin].src_bus_id = 0;
2321 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2322 io_apic_ints[pin].dst_apic_id = io_apic_id;
2323 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2324 }
2325
2326 /* special cases from MP v1.4, table 5-2 */
2327 if (type == 2) {
2328 io_apic_ints[2].int_type = 0xff; /* N/C */
2329 io_apic_ints[13].int_type = 0xff; /* N/C */
2330#if !defined(APIC_MIXED_MODE)
2331 /** FIXME: ??? */
2332 panic("sorry, can't support type 2 default yet");
2333#endif /* APIC_MIXED_MODE */
2334 }
2335 else
2336 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2337
2338 if (type == 7)
2339 io_apic_ints[0].int_type = 0xff; /* N/C */
2340 else
2341 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2342#endif /* APIC_IO */
2343}
2344
2345/*
2346 * Map a physical memory address representing I/O into KVA. The I/O
2347 * block is assumed not to cross a page boundary.
2348 */
2349void *
2350permanent_io_mapping(vm_paddr_t pa)
2351{
46d4e165
JG
2352 KKASSERT(pa < 0x100000000LL);
2353
403c36ea 2354 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
46d4e165
JG
2355}
2356
2357/*
2358 * start each AP in our list
2359 */
2360static int
2361start_all_aps(u_int boot_addr)
2362{
2363 vm_offset_t va = boot_address + KERNBASE;
2364 u_int64_t *pt4, *pt3, *pt2;
2365 int x, i, pg;
2366 int shift;
bb467734
MD
2367 int smicount;
2368 int smibest;
2369 int smilast;
46d4e165
JG
2370 u_char mpbiosreason;
2371 u_long mpbioswarmvec;
2372 struct mdglobaldata *gd;
2373 struct privatespace *ps;
46d4e165
JG
2374
2375 POSTCODE(START_ALL_APS_POST);
2376
2377 /* Initialize BSP's local APIC */
2378 apic_initialize(TRUE);
46d4e165
JG
2379
2380 /* install the AP 1st level boot code */
2381 pmap_kenter(va, boot_address);
bfc09ba0 2382 cpu_invlpg((void *)va); /* JG XXX */
46d4e165
JG
2383 bcopy(mptramp_start, (void *)va, bootMP_size);
2384
2385 /* Locate the page tables, they'll be below the trampoline */
2386 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2387 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2388 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2389
2390 /* Create the initial 1GB replicated page tables */
2391 for (i = 0; i < 512; i++) {
2392 /* Each slot of the level 4 pages points to the same level 3 page */
2393 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2394 pt4[i] |= PG_V | PG_RW | PG_U;
2395
2396 /* Each slot of the level 3 pages points to the same level 2 page */
2397 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2398 pt3[i] |= PG_V | PG_RW | PG_U;
2399
2400 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2401 pt2[i] = i * (2 * 1024 * 1024);
2402 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2403 }
2404
2405 /* save the current value of the warm-start vector */
2406 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2407 outb(CMOS_REG, BIOS_RESET);
2408 mpbiosreason = inb(CMOS_DATA);
2409
2410 /* setup a vector to our boot code */
2411 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2412 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2413 outb(CMOS_REG, BIOS_RESET);
2414 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2415
bb467734
MD
2416 /*
2417 * If we have a TSC we can figure out the SMI interrupt rate.
2418 * The SMI does not necessarily use a constant rate. Spend
2419 * up to 250ms trying to figure it out.
2420 */
2421 smibest = 0;
2422 if (cpu_feature & CPUID_TSC) {
2423 set_apic_timer(275000);
2424 smilast = read_apic_timer();
2425 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2426 smicount = smitest();
2427 if (smibest == 0 || smilast - smicount < smibest)
2428 smibest = smilast - smicount;
2429 smilast = smicount;
2430 }
2431 if (smibest > 250000)
2432 smibest = 0;
2433 if (smibest) {
2434 smibest = smibest * (int64_t)1000000 /
2435 get_apic_timer_frequency();
2436 }
2437 }
2438 if (smibest)
2439 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2440 1000000 / smibest, smibest);
2441
46d4e165
JG
2442 /* start each AP */
2443 for (x = 1; x <= mp_naps; ++x) {
2444
2445 /* This is a bit verbose, it will go away soon. */
2446
2447 /* first page of AP's private space */
b2b3ffcd 2448 pg = x * x86_64_btop(sizeof(struct privatespace));
46d4e165
JG
2449
2450 /* allocate new private data page(s) */
2451 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2452 MDGLOBALDATA_BASEALLOC_SIZE);
46d4e165
JG
2453
2454 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2455 bzero(gd, sizeof(*gd));
2456 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2457
2458 /* prime data page for it to use */
2459 mi_gdinit(&gd->mi, x);
2460 cpu_gdinit(gd, x);
2461 gd->gd_CMAP1 = &SMPpt[pg + 0];
2462 gd->gd_CMAP2 = &SMPpt[pg + 1];
2463 gd->gd_CMAP3 = &SMPpt[pg + 2];
2464 gd->gd_PMAP1 = &SMPpt[pg + 3];
2465 gd->gd_CADDR1 = ps->CPAGE1;
2466 gd->gd_CADDR2 = ps->CPAGE2;
2467 gd->gd_CADDR3 = ps->CPAGE3;
bfc09ba0 2468 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
46d4e165
JG
2469 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2470 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2471
2472 /* setup a vector to our boot code */
2473 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2474 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2475 outb(CMOS_REG, BIOS_RESET);
2476 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2477
2478 /*
2479 * Setup the AP boot stack
2480 */
2481 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2482 bootAP = x;
2483
2484 /* attempt to start the Application Processor */
2485 CHECK_INIT(99); /* setup checkpoints */
bb467734 2486 if (!start_ap(gd, boot_addr, smibest)) {
46d4e165
JG
2487 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2488 CHECK_PRINT("trace"); /* show checkpoints */
2489 /* better panic as the AP may be running loose */
2490 kprintf("panic y/n? [y] ");
2491 if (cngetc() != 'n')
2492 panic("bye-bye");
2493 }
2494 CHECK_PRINT("trace"); /* show checkpoints */
2495
2496 /* record its version info */
2497 cpu_apic_versions[x] = cpu_apic_versions[0];
2498 }
2499
2500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2501 ncpus = x;
2502
2503 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2504 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2505 ;
2506 --shift;
2507 ncpus2_shift = shift;
2508 ncpus2 = 1 << shift;
2509 ncpus2_mask = ncpus2 - 1;
2510
2511 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2512 if ((1 << shift) < ncpus)
2513 ++shift;
2514 ncpus_fit = 1 << shift;
2515 ncpus_fit_mask = ncpus_fit - 1;
2516
2517 /* build our map of 'other' CPUs */
2518 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2519 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2520 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2521
2522 /* fill in our (BSP) APIC version */
2523 cpu_apic_versions[0] = lapic->version;
2524
2525 /* restore the warmstart vector */
2526 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2527 outb(CMOS_REG, BIOS_RESET);
2528 outb(CMOS_DATA, mpbiosreason);
2529
2530 /*
2531 * NOTE! The idlestack for the BSP was setup by locore. Finish
2532 * up, clean out the P==V mapping we did earlier.
2533 */
46d4e165
JG
2534 pmap_set_opt();
2535
2536 /* number of APs actually started */
2537 return ncpus - 1;
2538}
2539
2540
2541/*
2542 * load the 1st level AP boot code into base memory.
2543 */
2544
2545/* targets for relocation */
2546extern void bigJump(void);
2547extern void bootCodeSeg(void);
2548extern void bootDataSeg(void);
2549extern void MPentry(void);
2550extern u_int MP_GDT;
2551extern u_int mp_gdtbase;
2552
bfc09ba0
MD
2553#if 0
2554
46d4e165
JG
2555static void
2556install_ap_tramp(u_int boot_addr)
2557{
2558 int x;
2559 int size = *(int *) ((u_long) & bootMP_size);
2560 u_char *src = (u_char *) ((u_long) bootMP);
2561 u_char *dst = (u_char *) boot_addr + KERNBASE;
2562 u_int boot_base = (u_int) bootMP;
2563 u_int8_t *dst8;
2564 u_int16_t *dst16;
2565 u_int32_t *dst32;
2566
2567 POSTCODE(INSTALL_AP_TRAMP_POST);
2568
2569 for (x = 0; x < size; ++x)
2570 *dst++ = *src++;
2571
2572 /*
2573 * modify addresses in code we just moved to basemem. unfortunately we
2574 * need fairly detailed info about mpboot.s for this to work. changes
2575 * to mpboot.s might require changes here.
2576 */
2577
2578 /* boot code is located in KERNEL space */
2579 dst = (u_char *) boot_addr + KERNBASE;
2580
2581 /* modify the lgdt arg */
2582 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2583 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2584
2585 /* modify the ljmp target for MPentry() */
2586 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2587 *dst32 = ((u_int) MPentry - KERNBASE);
2588
2589 /* modify the target for boot code segment */
2590 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2591 dst8 = (u_int8_t *) (dst16 + 1);
2592 *dst16 = (u_int) boot_addr & 0xffff;
2593 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2594
2595 /* modify the target for boot data segment */
2596 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2597 dst8 = (u_int8_t *) (dst16 + 1);
2598 *dst16 = (u_int) boot_addr & 0xffff;
2599 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2600}
2601
bfc09ba0 2602#endif
46d4e165
JG
2603
2604/*
bb467734 2605 * This function starts the AP (application processor) identified
46d4e165
JG
2606 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2607 * to accomplish this. This is necessary because of the nuances
2608 * of the different hardware we might encounter. It ain't pretty,
2609 * but it seems to work.
2610 *
2611 * NOTE: eventually an AP gets to ap_init(), which is called just
2612 * before the AP goes into the LWKT scheduler's idle loop.
2613 */
2614static int
bb467734 2615start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
46d4e165
JG
2616{
2617 int physical_cpu;
2618 int vector;
2619 u_long icr_lo, icr_hi;
2620
2621 POSTCODE(START_AP_POST);
2622
2623 /* get the PHYSICAL APIC ID# */
2624 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2625
2626 /* calculate the vector */
2627 vector = (boot_addr >> 12) & 0xff;
2628
bb467734
MD
2629 /* We don't want anything interfering */
2630 cpu_disable_intr();
2631
46d4e165
JG
2632 /* Make sure the target cpu sees everything */
2633 wbinvd();
2634
2635 /*
bb467734
MD
2636 * Try to detect when a SMI has occurred, wait up to 200ms.
2637 *
2638 * If a SMI occurs during an AP reset but before we issue
2639 * the STARTUP command, the AP may brick. To work around
2640 * this problem we hold off doing the AP startup until
2641 * after we have detected the SMI. Hopefully another SMI
2642 * will not occur before we finish the AP startup.
2643 *
2644 * Retries don't seem to help. SMIs have a window of opportunity
2645 * and if USB->legacy keyboard emulation is enabled in the BIOS
2646 * the interrupt rate can be quite high.
2647 *
2648 * NOTE: Don't worry about the L1 cache load, it might bloat
2649 * ldelta a little but ndelta will be so huge when the SMI
2650 * occurs the detection logic will still work fine.
2651 */
2652 if (smibest) {
2653 set_apic_timer(200000);
2654 smitest();
2655 }
2656
2657 /*
46d4e165
JG
2658 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2659 * and running the target CPU. OR this INIT IPI might be latched (P5
2660 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2661 * ignored.
bb467734
MD
2662 *
2663 * see apic/apicreg.h for icr bit definitions.
2664 *
2665 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
46d4e165
JG
2666 */
2667
bb467734
MD
2668 /*
2669 * Setup the address for the target AP. We can setup
2670 * icr_hi once and then just trigger operations with
2671 * icr_lo.
2672 */
46d4e165
JG
2673 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2674 icr_hi |= (physical_cpu << 24);
46d4e165 2675 icr_lo = lapic->icr_lo & 0xfff00000;
bb467734 2676 lapic->icr_hi = icr_hi;
46d4e165 2677
bb467734
MD
2678 /*
2679 * Do an INIT IPI: assert RESET
2680 *
2681 * Use edge triggered mode to assert INIT
2682 */
2683 lapic->icr_lo = icr_lo | 0x00004500;
46d4e165
JG
2684 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2685 /* spin */ ;
2686
bb467734
MD
2687 /*
2688 * The spec calls for a 10ms delay but we may have to use a
2689 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2690 * interrupt. We have other loops here too and dividing by 2
2691 * doesn't seem to be enough even after subtracting 350us,
2692 * so we divide by 4.
2693 *
2694 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2695 * interrupt was detected we use the full 10ms.
2696 */
2697 if (smibest == 0)
2698 u_sleep(10000);
2699 else if (smibest < 150 * 4 + 350)
2700 u_sleep(150);
2701 else if ((smibest - 350) / 4 < 10000)
2702 u_sleep((smibest - 350) / 4);
2703 else
2704 u_sleep(10000);
46d4e165 2705
bb467734
MD
2706 /*
2707 * Do an INIT IPI: deassert RESET
2708 *
2709 * Use level triggered mode to deassert. It is unclear
2710 * why we need to do this.
2711 */
2712 lapic->icr_lo = icr_lo | 0x00008500;
46d4e165
JG
2713 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2714 /* spin */ ;
bb467734 2715 u_sleep(150); /* wait 150us */
46d4e165
JG
2716
2717 /*
bb467734 2718 * Next we do a STARTUP IPI: the previous INIT IPI might still be
46d4e165
JG
2719 * latched, (P5 bug) this 1st STARTUP would then terminate
2720 * immediately, and the previously started INIT IPI would continue. OR
2721 * the previous INIT IPI has already run. and this STARTUP IPI will
2722 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2723 * will run.
2724 */
46d4e165
JG
2725 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2726 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2727 /* spin */ ;
2728 u_sleep(200); /* wait ~200uS */
2729
2730 /*
bb467734 2731 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
46d4e165
JG
2732 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2733 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2734 * recognized after hardware RESET or INIT IPI.
2735 */
46d4e165
JG
2736 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2737 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2738 /* spin */ ;
bb467734
MD
2739
2740 /* Resume normal operation */
2741 cpu_enable_intr();
46d4e165
JG
2742
2743 /* wait for it to start, see ap_init() */
2744 set_apic_timer(5000000);/* == 5 seconds */
2745 while (read_apic_timer()) {
2746 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2747 return 1; /* return SUCCESS */
2748 }
bb467734 2749
46d4e165
JG
2750 return 0; /* return FAILURE */
2751}
2752
bb467734
MD
2753static
2754int
2755smitest(void)
2756{
2757 int64_t ltsc;
2758 int64_t ntsc;
2759 int64_t ldelta;
2760 int64_t ndelta;
2761 int count;
2762
2763 ldelta = 0;
2764 ndelta = 0;
2765 while (read_apic_timer()) {
2766 ltsc = rdtsc();
2767 for (count = 0; count < 100; ++count)
2768 ntsc = rdtsc(); /* force loop to occur */
2769 if (ldelta) {
2770 ndelta = ntsc - ltsc;
2771 if (ldelta > ndelta)
2772 ldelta = ndelta;
2773 if (ndelta > ldelta * 2)
2774 break;
2775 } else {
2776 ldelta = ntsc - ltsc;
2777 }
2778 }
2779 return(read_apic_timer());
2780}
46d4e165
JG
2781
2782/*
7402df27
MD
2783 * Synchronously flush the TLB on all other CPU's. The current cpu's
2784 * TLB is not flushed. If the caller wishes to flush the current cpu's
2785 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
46d4e165 2786 *
7402df27
MD
2787 * NOTE: If for some reason we were unable to start all cpus we cannot
2788 * safely use broadcast IPIs.
46d4e165 2789 */
7402df27
MD
2790
2791static cpumask_t smp_invltlb_req;
2792
ecf9dec6
MD
2793#define SMP_INVLTLB_DEBUG
2794
46d4e165
JG
2795void
2796smp_invltlb(void)
2797{
2798#ifdef SMP
7402df27 2799 struct mdglobaldata *md = mdcpu;
dd4ef322 2800#ifdef SMP_INVLTLB_DEBUG
7402df27 2801 long count = 0;
dd4ef322 2802 long xcount = 0;
7402df27 2803#endif
9bbe2f36 2804
7402df27
MD
2805 crit_enter_gd(&md->mi);
2806 md->gd_invltlb_ret = 0;
2807 ++md->mi.gd_cnt.v_smpinvltlb;
2808 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
dd4ef322
MD
2809#ifdef SMP_INVLTLB_DEBUG
2810again:
2811#endif
46d4e165
JG
2812 if (smp_startup_mask == smp_active_mask) {
2813 all_but_self_ipi(XINVLTLB_OFFSET);
2814 } else {
7402df27
MD
2815 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2816 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
46d4e165 2817 }
dd4ef322
MD
2818
2819#ifdef SMP_INVLTLB_DEBUG
2820 if (xcount)
2821 kprintf("smp_invltlb: ipi sent\n");
2822#endif
7402df27
MD
2823 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2824 (smp_active_mask & ~md->mi.gd_cpumask)) {
2825 cpu_mfence();
2826 cpu_pause();
dd4ef322 2827#ifdef SMP_INVLTLB_DEBUG
7402df27
MD
2828 /* DEBUGGING */
2829 if (++count == 400000000) {
dd4ef322
MD
2830 print_backtrace(-1);
2831 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2832 "rflags %016jx retry",
7402df27 2833 (long)md->gd_invltlb_ret,
dd4ef322
MD
2834 (long)smp_invltlb_req,
2835 (intmax_t)read_rflags());
2836 __asm __volatile ("sti");
2837 ++xcount;
2838 if (xcount > 2)
2839 lwkt_process_ipiq();
2840 if (xcount > 3) {
2841 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2842 globaldata_t xgd;
2843
2844 kprintf("bcpu %d\n", bcpu);
2845 xgd = globaldata_find(bcpu);
2846 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2847 }
2848 if (xcount > 5)
2849 Debugger("giving up");
2850 count = 0;
2851 goto again;
7402df27 2852 }
46d4e165 2853#endif
7402df27
MD
2854 }
2855 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2856 crit_exit_gd(&md->mi);
9bbe2f36 2857#endif
46d4e165
JG
2858}
2859
7402df27
MD
2860#ifdef SMP
2861
2862/*
2863 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2864 * bother to bump the critical section count or nested interrupt count
2865 * so only do very low level operations here.
2866 */
2867void
2868smp_invltlb_intr(void)
2869{
2870 struct mdglobaldata *md = mdcpu;
2871 struct mdglobaldata *omd;
2872 cpumask_t mask;
2873 int cpu;
2874
7402df27 2875 cpu_mfence();
dd4ef322 2876 mask = smp_invltlb_req;
7402df27
MD
2877 cpu_invltlb();
2878 while (mask) {
2879 cpu = bsfl(mask);
2880 mask &= ~(1 << cpu);
2881 omd = (struct mdglobaldata *)globaldata_find(cpu);
2882 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2883 }
2884}
2885
2886#endif
2887
46d4e165
JG
2888/*
2889 * When called the executing CPU will send an IPI to all other CPUs
2890 * requesting that they halt execution.
2891 *
2892 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2893 *
2894 * - Signals all CPUs in map to stop.
2895 * - Waits for each to stop.
2896 *
2897 * Returns:
2898 * -1: error
2899 * 0: NA
2900 * 1: ok
2901 *
2902 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2903 * from executing at same time.
2904 */
2905int
2906stop_cpus(u_int map)
2907{
2908 map &= smp_active_mask;
2909
2910 /* send the Xcpustop IPI to all CPUs in map */
2911 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2912
2913 while ((stopped_cpus & map) != map)
2914 /* spin */ ;
2915
2916 return 1;
2917}
2918
2919
2920/*
2921 * Called by a CPU to restart stopped CPUs.
2922 *
2923 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2924 *
2925 * - Signals all CPUs in map to restart.
2926 * - Waits for each to restart.
2927 *
2928 * Returns:
2929 * -1: error
2930 * 0: NA
2931 * 1: ok
2932 */
2933int
2934restart_cpus(u_int map)
2935{
2936 /* signal other cpus to restart */
2937 started_cpus = map & smp_active_mask;
2938
2939 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2940 /* spin */ ;
2941
2942 return 1;
2943}
2944
2945/*
2946 * This is called once the mpboot code has gotten us properly relocated
2947 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2948 * and when it returns the scheduler will call the real cpu_idle() main
2949 * loop for the idlethread. Interrupts are disabled on entry and should
2950 * remain disabled at return.
2951 */
2952void
2953ap_init(void)
2954{
2955 u_int apic_id;
2956
2957 /*
2958 * Adjust smp_startup_mask to signal the BSP that we have started
2959 * up successfully. Note that we do not yet hold the BGL. The BSP
2960 * is waiting for our signal.
2961 *
2962 * We can't set our bit in smp_active_mask yet because we are holding
2963 * interrupts physically disabled and remote cpus could deadlock
2964 * trying to send us an IPI.
2965 */
2966 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2967 cpu_mfence();
2968
2969 /*
2970 * Interlock for finalization. Wait until mp_finish is non-zero,
2971 * then get the MP lock.
2972 *
2973 * Note: We are in a critical section.
2974 *
2975 * Note: We have to synchronize td_mpcount to our desired MP state
2976 * before calling cpu_try_mplock().
2977 *
2978 * Note: we are the idle thread, we can only spin.
2979 *
2980 * Note: The load fence is memory volatile and prevents the compiler
2981 * from improperly caching mp_finish, and the cpu from improperly
2982 * caching it.
2983 */
2984 while (mp_finish == 0)
2985 cpu_lfence();
2986 ++curthread->td_mpcount;
2987 while (cpu_try_mplock() == 0)
2988 ;
2989
2990 if (cpu_feature & CPUID_TSC) {
2991 /*
2992 * The BSP is constantly updating tsc0_offset, figure out the
2993 * relative difference to synchronize ktrdump.
2994 */
2995 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2996 }
2997
2998 /* BSP may have changed PTD while we're waiting for the lock */
2999 cpu_invltlb();
3000
3001#if defined(I586_CPU) && !defined(NO_F00F_HACK)
3002 lidt(&r_idt);
3003#endif
3004
3005 /* Build our map of 'other' CPUs. */
3006 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
3007
3008 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
3009
3010 /* A quick check from sanity claus */
3011 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
3012 if (mycpu->gd_cpuid != apic_id) {
3013 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
3014 kprintf("SMP: apic_id = %d\n", apic_id);
3015#if JGXXX
3016 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
3017#endif
3018 panic("cpuid mismatch! boom!!");
3019 }
3020
3021 /* Initialize AP's local APIC for irq's */
3022 apic_initialize(FALSE);
3023
3024 /* Set memory range attributes for this CPU to match the BSP */
3025 mem_range_AP_init();
3026
3027 /*
3028 * Once we go active we must process any IPIQ messages that may
3029 * have been queued, because no actual IPI will occur until we
3030 * set our bit in the smp_active_mask. If we don't the IPI
3031 * message interlock could be left set which would also prevent
3032 * further IPIs.
3033 *
3034 * The idle loop doesn't expect the BGL to be held and while
3035 * lwkt_switch() normally cleans things up this is a special case
3036 * because we returning almost directly into the idle loop.
3037 *
3038 * The idle thread is never placed on the runq, make sure
3039 * nothing we've done put it there.
3040 */
3041 KKASSERT(curthread->td_mpcount == 1);
3042 smp_active_mask |= 1 << mycpu->gd_cpuid;
3043
3044 /*
3045 * Enable interrupts here. idle_restore will also do it, but
3046 * doing it here lets us clean up any strays that got posted to
3047 * the CPU during the AP boot while we are still in a critical
3048 * section.
3049 */
3050 __asm __volatile("sti; pause; pause"::);
3051 mdcpu->gd_fpending = 0;
46d4e165
JG
3052
3053 initclocks_pcpu(); /* clock interrupts (via IPIs) */
3054 lwkt_process_ipiq();
3055
3056 /*
3057 * Releasing the mp lock lets the BSP finish up the SMP init
3058 */
3059 rel_mplock();
3060 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
3061}
3062
3063/*
3064 * Get SMP fully working before we start initializing devices.
3065 */
3066static
3067void
3068ap_finish(void)
3069{
3070 mp_finish = 1;
3071 if (bootverbose)
3072 kprintf("Finish MP startup\n");
3073 if (cpu_feature & CPUID_TSC)
3074 tsc0_offset = rdtsc();
3075 tsc_offsets[0] = 0;
3076 rel_mplock();
3077 while (smp_active_mask != smp_startup_mask) {
3078 cpu_lfence();
3079 if (cpu_feature & CPUID_TSC)
3080 tsc0_offset = rdtsc();
3081 }
3082 while (try_mplock() == 0)
3083 ;
3084 if (bootverbose)
3085 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
3086}
3087
3088SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
3089
3090void
3091cpu_send_ipiq(int dcpu)
3092{
3093 if ((1 << dcpu) & smp_active_mask)
3094 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
3095}
3096
3097#if 0 /* single_apic_ipi_passive() not working yet */
3098/*
3099 * Returns 0 on failure, 1 on success
3100 */
3101int
3102cpu_send_ipiq_passive(int dcpu)
3103{
3104 int r = 0;
3105 if ((1 << dcpu) & smp_active_mask) {
3106 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
3107 APIC_DELMODE_FIXED);
3108 }
3109 return(r);
3110}
3111#endif
3112