pci: Disable memory address decoding before writing 0xffffffff to BAR
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
4d28e78f
SZ
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
984263bc
MD
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83c1faaa
SW
27 *
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
984263bc
MD
29 */
30
92683a33 31#include "opt_acpi.h"
6951547b 32#include "opt_compat_oldpci.h"
984263bc
MD
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
4d28e78f 38#include <sys/linker.h>
984263bc
MD
39#include <sys/fcntl.h>
40#include <sys/conf.h>
41#include <sys/kernel.h>
42#include <sys/queue.h>
638744c5 43#include <sys/sysctl.h>
4d28e78f 44#include <sys/endian.h>
d2f04fe0 45#include <sys/machintr.h>
984263bc 46
941460da
SZ
47#include <machine/msi_machdep.h>
48
984263bc
MD
49#include <vm/vm.h>
50#include <vm/pmap.h>
51#include <vm/vm_extern.h>
52
53#include <sys/bus.h>
984263bc 54#include <sys/rman.h>
4d28e78f 55#include <sys/device.h>
984263bc 56
dc5a7bd2 57#include <sys/pciio.h>
4d28e78f
SZ
58#include <bus/pci/pcireg.h>
59#include <bus/pci/pcivar.h>
60#include <bus/pci/pci_private.h>
984263bc 61
4a5a2d63 62#include "pcib_if.h"
4d28e78f
SZ
63#include "pci_if.h"
64
65#ifdef __HAVE_ACPI
66#include <contrib/dev/acpica/acpi.h>
67#include "acpi_if.h"
68#else
69#define ACPI_PWR_FOR_SLEEP(x, y, z)
70#endif
71
35b72619
SZ
72extern struct dev_ops pcic_ops; /* XXX */
73
3a6dc23c
SZ
74typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
75
4d28e78f
SZ
76static uint32_t pci_mapbase(unsigned mapreg);
77static const char *pci_maptype(unsigned mapreg);
78static int pci_mapsize(unsigned testval);
79static int pci_maprange(unsigned mapreg);
80static void pci_fixancient(pcicfgregs *cfg);
81
82static int pci_porten(device_t pcib, int b, int s, int f);
83static int pci_memen(device_t pcib, int b, int s, int f);
84static void pci_assign_interrupt(device_t bus, device_t dev,
85 int force_route);
86static int pci_add_map(device_t pcib, device_t bus, device_t dev,
87 int b, int s, int f, int reg,
88 struct resource_list *rl, int force, int prefetch);
89static int pci_probe(device_t dev);
90static int pci_attach(device_t dev);
11a49859 91static void pci_child_detached(device_t, device_t);
4d28e78f
SZ
92static void pci_load_vendor_data(void);
93static int pci_describe_parse_line(char **ptr, int *vendor,
94 int *device, char **desc);
95static char *pci_describe_device(device_t dev);
96static int pci_modevent(module_t mod, int what, void *arg);
97static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
98 pcicfgregs *cfg);
3a6dc23c 99static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
4d28e78f
SZ
100static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
101 int reg, uint32_t *data);
102#if 0
103static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
104 int reg, uint32_t data);
105#endif
106static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
107static void pci_disable_msi(device_t dev);
108static void pci_enable_msi(device_t dev, uint64_t address,
109 uint16_t data);
cf8f3133 110static void pci_setup_msix_vector(device_t dev, u_int index,
4d28e78f 111 uint64_t address, uint32_t data);
cf8f3133
SZ
112static void pci_mask_msix_vector(device_t dev, u_int index);
113static void pci_unmask_msix_vector(device_t dev, u_int index);
31646171 114static void pci_mask_msix_allvectors(device_t dev);
f9c942fb 115static struct msix_vector *pci_find_msix_vector(device_t dev, int rid);
4d28e78f
SZ
116static int pci_msi_blacklisted(void);
117static void pci_resume_msi(device_t dev);
118static void pci_resume_msix(device_t dev);
d85e7311
SZ
119static int pcie_slotimpl(const pcicfgregs *);
120static void pci_print_verbose_expr(const pcicfgregs *);
4d28e78f 121
3a6dc23c
SZ
122static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
123static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
124static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
125static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
126static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
127static void pci_read_cap_subvendor(device_t, int, int,
128 pcicfgregs *);
129static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
d85e7311 130static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
3a6dc23c 131
4d28e78f
SZ
132static device_method_t pci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, pci_probe),
135 DEVMETHOD(device_attach, pci_attach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
138 DEVMETHOD(device_suspend, pci_suspend),
139 DEVMETHOD(device_resume, pci_resume),
140
141 /* Bus interface */
142 DEVMETHOD(bus_print_child, pci_print_child),
143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
146 DEVMETHOD(bus_driver_added, pci_driver_added),
11a49859 147 DEVMETHOD(bus_child_detached, pci_child_detached),
4d28e78f
SZ
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150
151 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
152 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
153 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
154 DEVMETHOD(bus_delete_resource, pci_delete_resource),
155 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
156 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
157 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
159 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
160 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
161
162 /* PCI interface */
163 DEVMETHOD(pci_read_config, pci_read_config_method),
164 DEVMETHOD(pci_write_config, pci_write_config_method),
165 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
166 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
167 DEVMETHOD(pci_enable_io, pci_enable_io_method),
168 DEVMETHOD(pci_disable_io, pci_disable_io_method),
169 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
170 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
171 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
172 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
173 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
174 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
175 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
4d28e78f 176 DEVMETHOD(pci_release_msi, pci_release_msi_method),
a7854dd0
SZ
177 DEVMETHOD(pci_alloc_msix_vector, pci_alloc_msix_vector_method),
178 DEVMETHOD(pci_release_msix_vector, pci_release_msix_vector_method),
4d28e78f
SZ
179 DEVMETHOD(pci_msi_count, pci_msi_count_method),
180 DEVMETHOD(pci_msix_count, pci_msix_count_method),
181
182 { 0, 0 }
183};
184
185DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
4a5a2d63 186
4d28e78f 187static devclass_t pci_devclass;
aa2b9d05 188DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
4d28e78f
SZ
189MODULE_VERSION(pci, 1);
190
191static char *pci_vendordata;
192static size_t pci_vendordata_size;
dc5a7bd2 193
984263bc 194
3a6dc23c
SZ
195static const struct pci_read_cap {
196 int cap;
197 pci_read_cap_t read_cap;
198} pci_read_caps[] = {
199 { PCIY_PMG, pci_read_cap_pmgt },
200 { PCIY_HT, pci_read_cap_ht },
201 { PCIY_MSI, pci_read_cap_msi },
202 { PCIY_MSIX, pci_read_cap_msix },
203 { PCIY_VPD, pci_read_cap_vpd },
204 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
205 { PCIY_PCIX, pci_read_cap_pcix },
d85e7311 206 { PCIY_EXPRESS, pci_read_cap_express },
3a6dc23c
SZ
207 { 0, NULL } /* required last entry */
208};
209
984263bc 210struct pci_quirk {
4d28e78f 211 uint32_t devid; /* Vendor/device of the card */
984263bc 212 int type;
4d28e78f
SZ
213#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
214#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
984263bc
MD
215 int arg1;
216 int arg2;
217};
218
219struct pci_quirk pci_quirks[] = {
4d28e78f 220 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
984263bc
MD
221 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
223 /* As does the Serverworks OSB4 (the SMBus mapping register) */
224 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
984263bc 225
4d28e78f
SZ
226 /*
227 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
228 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 */
230 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
232
233 /*
234 * MSI doesn't work on earlier Intel chipsets including
235 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 */
237 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
243 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
244
245 /*
246 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
247 * bridge.
248 */
249 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
250
984263bc
MD
251 { 0 }
252};
253
254/* map register information */
4d28e78f
SZ
255#define PCI_MAPMEM 0x01 /* memory map */
256#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
257#define PCI_MAPPORT 0x04 /* port map */
258
f9c942fb
SZ
259#define PCI_MSIX_RID2VEC(rid) ((rid) - 1) /* rid -> MSI-X vector # */
260#define PCI_MSIX_VEC2RID(vec) ((vec) + 1) /* MSI-X vector # -> rid */
261
4d28e78f
SZ
262struct devlist pci_devq;
263uint32_t pci_generation;
264uint32_t pci_numdevs = 0;
265static int pcie_chipset, pcix_chipset;
266
267/* sysctl vars */
268SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
269
270static int pci_enable_io_modes = 1;
271TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
272SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
273 &pci_enable_io_modes, 1,
274 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
275enable these bits correctly. We'd like to do this all the time, but there\n\
276are some peripherals that this causes problems with.");
984263bc 277
638744c5
HT
278static int pci_do_power_nodriver = 0;
279TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
280SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
281 &pci_do_power_nodriver, 0,
282 "Place a function into D3 state when no driver attaches to it. 0 means\n\
283disable. 1 means conservatively place devices into D3 state. 2 means\n\
6699890a 284aggressively place devices into D3 state. 3 means put absolutely everything\n\
638744c5
HT
285in D3 state.");
286
4d28e78f
SZ
287static int pci_do_power_resume = 1;
288TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
289SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
290 &pci_do_power_resume, 1,
291 "Transition from D3 -> D0 on resume.");
292
293static int pci_do_msi = 1;
294TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
295SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
296 "Enable support for MSI interrupts");
297
4f459073 298static int pci_do_msix = 1;
4d28e78f
SZ
299TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
300SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
301 "Enable support for MSI-X interrupts");
302
303static int pci_honor_msi_blacklist = 1;
304TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
305SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
306 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
307
2c3d7ac8
SZ
308static int pci_msi_cpuid;
309
4d28e78f
SZ
310/* Find a device_t by bus/slot/function in domain 0 */
311
312device_t
313pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
314{
315
316 return (pci_find_dbsf(0, bus, slot, func));
317}
318
319/* Find a device_t by domain/bus/slot/function */
320
984263bc 321device_t
4d28e78f 322pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
984263bc
MD
323{
324 struct pci_devinfo *dinfo;
325
326 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
4d28e78f
SZ
327 if ((dinfo->cfg.domain == domain) &&
328 (dinfo->cfg.bus == bus) &&
984263bc
MD
329 (dinfo->cfg.slot == slot) &&
330 (dinfo->cfg.func == func)) {
331 return (dinfo->cfg.dev);
332 }
333 }
334
335 return (NULL);
336}
337
4d28e78f
SZ
338/* Find a device_t by vendor/device ID */
339
984263bc 340device_t
4d28e78f 341pci_find_device(uint16_t vendor, uint16_t device)
984263bc
MD
342{
343 struct pci_devinfo *dinfo;
344
345 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
346 if ((dinfo->cfg.vendor == vendor) &&
347 (dinfo->cfg.device == device)) {
348 return (dinfo->cfg.dev);
349 }
350 }
351
352 return (NULL);
353}
354
355/* return base address of memory or port map */
356
4d28e78f
SZ
357static uint32_t
358pci_mapbase(uint32_t mapreg)
984263bc 359{
4d28e78f
SZ
360
361 if (PCI_BAR_MEM(mapreg))
362 return (mapreg & PCIM_BAR_MEM_BASE);
363 else
364 return (mapreg & PCIM_BAR_IO_BASE);
984263bc
MD
365}
366
367/* return map type of memory or port map */
368
4d28e78f 369static const char *
984263bc
MD
370pci_maptype(unsigned mapreg)
371{
984263bc 372
4d28e78f
SZ
373 if (PCI_BAR_IO(mapreg))
374 return ("I/O Port");
375 if (mapreg & PCIM_BAR_MEM_PREFETCH)
376 return ("Prefetchable Memory");
377 return ("Memory");
984263bc
MD
378}
379
380/* return log2 of map size decoded for memory or port map */
381
382static int
4d28e78f 383pci_mapsize(uint32_t testval)
984263bc
MD
384{
385 int ln2size;
386
387 testval = pci_mapbase(testval);
388 ln2size = 0;
389 if (testval != 0) {
390 while ((testval & 1) == 0)
391 {
392 ln2size++;
393 testval >>= 1;
394 }
395 }
396 return (ln2size);
397}
398
399/* return log2 of address range supported by map register */
400
401static int
402pci_maprange(unsigned mapreg)
403{
404 int ln2range = 0;
4d28e78f
SZ
405
406 if (PCI_BAR_IO(mapreg))
984263bc 407 ln2range = 32;
4d28e78f
SZ
408 else
409 switch (mapreg & PCIM_BAR_MEM_TYPE) {
410 case PCIM_BAR_MEM_32:
411 ln2range = 32;
412 break;
413 case PCIM_BAR_MEM_1MB:
414 ln2range = 20;
415 break;
416 case PCIM_BAR_MEM_64:
417 ln2range = 64;
418 break;
419 }
984263bc
MD
420 return (ln2range);
421}
422
423/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
424
425static void
426pci_fixancient(pcicfgregs *cfg)
427{
428 if (cfg->hdrtype != 0)
429 return;
430
431 /* PCI to PCI bridges use header type 1 */
432 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
433 cfg->hdrtype = 1;
434}
435
984263bc
MD
436/* extract header type specific config data */
437
438static void
4a5a2d63 439pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 440{
4d28e78f 441#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
984263bc
MD
442 switch (cfg->hdrtype) {
443 case 0:
4a5a2d63
JS
444 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
445 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
984263bc
MD
446 cfg->nummaps = PCI_MAXMAPS_0;
447 break;
448 case 1:
984263bc 449 cfg->nummaps = PCI_MAXMAPS_1;
6951547b
SZ
450#ifdef COMPAT_OLDPCI
451 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
452#endif
984263bc
MD
453 break;
454 case 2:
4a5a2d63
JS
455 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
456 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
984263bc 457 cfg->nummaps = PCI_MAXMAPS_2;
6951547b
SZ
458#ifdef COMPAT_OLDPCI
459 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
460#endif
984263bc
MD
461 break;
462 }
4a5a2d63 463#undef REG
984263bc
MD
464}
465
4d28e78f 466/* read configuration header into pcicfgregs structure */
22457186 467struct pci_devinfo *
4d28e78f 468pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
984263bc 469{
4d28e78f 470#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
984263bc
MD
471 pcicfgregs *cfg = NULL;
472 struct pci_devinfo *devlist_entry;
473 struct devlist *devlist_head;
474
475 devlist_head = &pci_devq;
476
477 devlist_entry = NULL;
478
4d28e78f 479 if (REG(PCIR_DEVVENDOR, 4) != -1) {
efda3bd0 480 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
481
482 cfg = &devlist_entry->cfg;
4d28e78f
SZ
483
484 cfg->domain = d;
4a5a2d63
JS
485 cfg->bus = b;
486 cfg->slot = s;
487 cfg->func = f;
488 cfg->vendor = REG(PCIR_VENDOR, 2);
489 cfg->device = REG(PCIR_DEVICE, 2);
490 cfg->cmdreg = REG(PCIR_COMMAND, 2);
491 cfg->statreg = REG(PCIR_STATUS, 2);
492 cfg->baseclass = REG(PCIR_CLASS, 1);
493 cfg->subclass = REG(PCIR_SUBCLASS, 1);
494 cfg->progif = REG(PCIR_PROGIF, 1);
495 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 496 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
4a5a2d63
JS
497 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
498 cfg->lattimer = REG(PCIR_LATTIMER, 1);
499 cfg->intpin = REG(PCIR_INTPIN, 1);
500 cfg->intline = REG(PCIR_INTLINE, 1);
984263bc 501
4a5a2d63
JS
502 cfg->mingnt = REG(PCIR_MINGNT, 1);
503 cfg->maxlat = REG(PCIR_MAXLAT, 1);
984263bc
MD
504
505 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
506 cfg->hdrtype &= ~PCIM_MFDEV;
507
508 pci_fixancient(cfg);
4a5a2d63 509 pci_hdrtypedata(pcib, b, s, f, cfg);
4d28e78f 510
3a6dc23c 511 pci_read_capabilities(pcib, cfg);
984263bc
MD
512
513 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
514
4d28e78f 515 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
984263bc
MD
516 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
517 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
518 devlist_entry->conf.pc_sel.pc_func = cfg->func;
519 devlist_entry->conf.pc_hdr = cfg->hdrtype;
520
521 devlist_entry->conf.pc_subvendor = cfg->subvendor;
522 devlist_entry->conf.pc_subdevice = cfg->subdevice;
523 devlist_entry->conf.pc_vendor = cfg->vendor;
524 devlist_entry->conf.pc_device = cfg->device;
525
526 devlist_entry->conf.pc_class = cfg->baseclass;
527 devlist_entry->conf.pc_subclass = cfg->subclass;
528 devlist_entry->conf.pc_progif = cfg->progif;
529 devlist_entry->conf.pc_revid = cfg->revid;
530
531 pci_numdevs++;
532 pci_generation++;
533 }
534 return (devlist_entry);
535#undef REG
536}
537
3a6dc23c
SZ
538static int
539pci_fixup_nextptr(int *nextptr0)
540{
541 int nextptr = *nextptr0;
542
543 /* "Next pointer" is only one byte */
ed20d0e3 544 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d", nextptr));
3a6dc23c
SZ
545
546 if (nextptr & 0x3) {
547 /*
548 * PCI local bus spec 3.0:
549 *
550 * "... The bottom two bits of all pointers are reserved
551 * and must be implemented as 00b although software must
552 * mask them to allow for future uses of these bits ..."
553 */
554 if (bootverbose) {
555 kprintf("Illegal PCI extended capability "
556 "offset, fixup 0x%02x -> 0x%02x\n",
557 nextptr, nextptr & ~0x3);
558 }
559 nextptr &= ~0x3;
560 }
561 *nextptr0 = nextptr;
562
563 if (nextptr < 0x40) {
564 if (nextptr != 0) {
565 kprintf("Illegal PCI extended capability "
566 "offset 0x%02x", nextptr);
567 }
568 return 0;
569 }
570 return 1;
571}
572
b4c0a845 573static void
3a6dc23c 574pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
984263bc 575{
3a6dc23c
SZ
576#define REG(n, w) \
577 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
578
579 struct pcicfg_pp *pp = &cfg->pp;
580
581 if (pp->pp_cap)
582 return;
583
584 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
585 pp->pp_status = ptr + PCIR_POWER_STATUS;
586 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
587
588 if ((nextptr - ptr) > PCIR_POWER_DATA) {
589 /*
590 * XXX
591 * We should write to data_select and read back from
592 * data_scale to determine whether data register is
593 * implemented.
594 */
595#ifdef foo
596 pp->pp_data = ptr + PCIR_POWER_DATA;
597#else
598 pp->pp_data = 0;
599#endif
600 }
601
602#undef REG
603}
604
605static void
606pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
607{
b2b3ffcd 608#if defined(__i386__) || defined(__x86_64__)
3a6dc23c
SZ
609
610#define REG(n, w) \
611 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
612
613 struct pcicfg_ht *ht = &cfg->ht;
4d28e78f 614 uint64_t addr;
4d28e78f 615 uint32_t val;
3a6dc23c
SZ
616
617 /* Determine HT-specific capability type. */
618 val = REG(ptr + PCIR_HT_COMMAND, 2);
619
941460da
SZ
620 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
621 cfg->ht.ht_slave = ptr;
622
3a6dc23c
SZ
623 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
624 return;
625
626 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
627 /* Sanity check the mapping window. */
628 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
629 addr <<= 32;
630 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
941460da 631 if (addr != MSI_X86_ADDR_BASE) {
3a6dc23c
SZ
632 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
633 "has non-default MSI window 0x%llx\n",
634 cfg->domain, cfg->bus, cfg->slot, cfg->func,
635 (long long)addr);
636 }
637 } else {
941460da 638 addr = MSI_X86_ADDR_BASE;
3a6dc23c
SZ
639 }
640
641 ht->ht_msimap = ptr;
642 ht->ht_msictrl = val;
643 ht->ht_msiaddr = addr;
644
645#undef REG
646
b2b3ffcd 647#endif /* __i386__ || __x86_64__ */
3a6dc23c
SZ
648}
649
650static void
651pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
652{
653#define REG(n, w) \
654 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
655
656 struct pcicfg_msi *msi = &cfg->msi;
657
658 msi->msi_location = ptr;
659 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
660 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
661
662#undef REG
663}
664
665static void
666pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
667{
668#define REG(n, w) \
669 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
670
671 struct pcicfg_msix *msix = &cfg->msix;
672 uint32_t val;
673
674 msix->msix_location = ptr;
675 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
676 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
677
678 val = REG(ptr + PCIR_MSIX_TABLE, 4);
679 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
680 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
681
682 val = REG(ptr + PCIR_MSIX_PBA, 4);
683 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
684 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
685
f9c942fb
SZ
686 TAILQ_INIT(&msix->msix_vectors);
687
3a6dc23c
SZ
688#undef REG
689}
690
691static void
692pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
693{
694 cfg->vpd.vpd_reg = ptr;
695}
696
697static void
698pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
699{
700#define REG(n, w) \
701 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
702
703 /* Should always be true. */
704 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
705 uint32_t val;
706
707 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
708 cfg->subvendor = val & 0xffff;
709 cfg->subdevice = val >> 16;
710 }
711
712#undef REG
713}
714
715static void
716pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
717{
718 /*
719 * Assume we have a PCI-X chipset if we have
720 * at least one PCI-PCI bridge with a PCI-X
721 * capability. Note that some systems with
722 * PCI-express or HT chipsets might match on
723 * this check as well.
724 */
725 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
726 pcix_chipset = 1;
d85e7311
SZ
727
728 cfg->pcix.pcix_ptr = ptr;
729}
730
731static int
732pcie_slotimpl(const pcicfgregs *cfg)
733{
734 const struct pcicfg_expr *expr = &cfg->expr;
735 uint16_t port_type;
736
737 /*
d85e7311
SZ
738 * - Slot implemented bit is meaningful iff current port is
739 * root port or down stream port.
740 * - Testing for root port or down stream port is meanningful
741 * iff PCI configure has type 1 header.
742 */
743
744 if (cfg->hdrtype != 1)
745 return 0;
746
747 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
748 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
749 return 0;
750
751 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
752 return 0;
753
754 return 1;
3a6dc23c
SZ
755}
756
757static void
d85e7311 758pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
3a6dc23c 759{
d85e7311
SZ
760#define REG(n, w) \
761 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
762
763 struct pcicfg_expr *expr = &cfg->expr;
764
3a6dc23c
SZ
765 /*
766 * Assume we have a PCI-express chipset if we have
767 * at least one PCI-express device.
768 */
769 pcie_chipset = 1;
d85e7311
SZ
770
771 expr->expr_ptr = ptr;
772 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
773
774 /*
d85e7311
SZ
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
777 */
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
780
781#undef REG
3a6dc23c
SZ
782}
783
784static void
785pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
786{
787#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
789
790 uint32_t val;
791 int nextptr, ptrptr;
792
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
795 return;
796 }
0c78fe3f 797
4d28e78f 798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
984263bc 799 case 0:
81c29ce4
SZ
800 case 1:
801 ptrptr = PCIR_CAP_PTR;
984263bc
MD
802 break;
803 case 2:
4d28e78f 804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
984263bc
MD
805 break;
806 default:
3a6dc23c 807 return; /* no capabilities support */
984263bc 808 }
4d28e78f 809 nextptr = REG(ptrptr, 1); /* sanity check? */
984263bc
MD
810
811 /*
812 * Read capability entries.
813 */
3a6dc23c
SZ
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
816 int ptr = nextptr;
817
4d28e78f 818 /* Find the next entry */
4d28e78f 819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
984263bc
MD
820
821 /* Process this entry */
3a6dc23c
SZ
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
4d28e78f
SZ
826 break;
827 }
984263bc
MD
828 }
829 }
941460da
SZ
830
831#if defined(__i386__) || defined(__x86_64__)
832 /*
833 * Enable the MSI mapping window for all HyperTransport
834 * slaves. PCI-PCI bridges have their windows enabled via
835 * PCIB_MAP_MSI().
836 */
837 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
838 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
839 device_printf(pcib,
840 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
841 cfg->domain, cfg->bus, cfg->slot, cfg->func);
842 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
843 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
844 2);
845 }
846#endif
847
4d28e78f 848/* REG and WREG use carry through to next functions */
984263bc
MD
849}
850
4d28e78f
SZ
851/*
852 * PCI Vital Product Data
853 */
854
855#define PCI_VPD_TIMEOUT 1000000
984263bc 856
4d28e78f
SZ
857static int
858pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
984263bc 859{
4d28e78f 860 int count = PCI_VPD_TIMEOUT;
984263bc 861
4d28e78f 862 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
984263bc 863
4d28e78f 864 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
984263bc 865
4d28e78f
SZ
866 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
867 if (--count < 0)
868 return (ENXIO);
869 DELAY(1); /* limit looping */
870 }
871 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
984263bc 872
984263bc
MD
873 return (0);
874}
984263bc 875
4d28e78f
SZ
876#if 0
877static int
878pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
984263bc 879{
4d28e78f
SZ
880 int count = PCI_VPD_TIMEOUT;
881
882 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
883
884 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
885 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
886 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
887 if (--count < 0)
888 return (ENXIO);
889 DELAY(1); /* limit looping */
890 }
891
892 return (0);
893}
894#endif
895
896#undef PCI_VPD_TIMEOUT
897
898struct vpd_readstate {
899 device_t pcib;
900 pcicfgregs *cfg;
901 uint32_t val;
902 int bytesinval;
903 int off;
904 uint8_t cksum;
905};
906
907static int
908vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
909{
910 uint32_t reg;
911 uint8_t byte;
912
913 if (vrs->bytesinval == 0) {
914 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
915 return (ENXIO);
916 vrs->val = le32toh(reg);
917 vrs->off += 4;
918 byte = vrs->val & 0xff;
919 vrs->bytesinval = 3;
920 } else {
921 vrs->val = vrs->val >> 8;
922 byte = vrs->val & 0xff;
923 vrs->bytesinval--;
924 }
925
926 vrs->cksum += byte;
927 *data = byte;
928 return (0);
929}
930
d85e7311
SZ
931int
932pcie_slot_implemented(device_t dev)
933{
934 struct pci_devinfo *dinfo = device_get_ivars(dev);
935
936 return pcie_slotimpl(&dinfo->cfg);
937}
938
4d28e78f
SZ
939void
940pcie_set_max_readrq(device_t dev, uint16_t rqsize)
941{
d85e7311
SZ
942 uint8_t expr_ptr;
943 uint16_t val;
944
945 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
946 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
ed20d0e3 947 panic("%s: invalid max read request size 0x%02x",
d85e7311
SZ
948 device_get_nameunit(dev), rqsize);
949 }
950
951 expr_ptr = pci_get_pciecap_ptr(dev);
952 if (!expr_ptr)
ed20d0e3 953 panic("%s: not PCIe device", device_get_nameunit(dev));
d85e7311
SZ
954
955 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
956 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
957 if (bootverbose)
958 device_printf(dev, "adjust device control 0x%04x", val);
959
960 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
961 val |= rqsize;
962 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
963
964 if (bootverbose)
965 kprintf(" -> 0x%04x\n", val);
966 }
4d28e78f
SZ
967}
968
441580ca
SZ
969uint16_t
970pcie_get_max_readrq(device_t dev)
971{
972 uint8_t expr_ptr;
973 uint16_t val;
974
975 expr_ptr = pci_get_pciecap_ptr(dev);
976 if (!expr_ptr)
ed20d0e3 977 panic("%s: not PCIe device", device_get_nameunit(dev));
441580ca
SZ
978
979 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
980 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
981}
982
4d28e78f
SZ
983static void
984pci_read_vpd(device_t pcib, pcicfgregs *cfg)
985{
986 struct vpd_readstate vrs;
987 int state;
988 int name;
989 int remain;
990 int i;
991 int alloc, off; /* alloc/off for RO/W arrays */
992 int cksumvalid;
993 int dflen;
994 uint8_t byte;
995 uint8_t byte2;
996
997 /* init vpd reader */
998 vrs.bytesinval = 0;
999 vrs.off = 0;
1000 vrs.pcib = pcib;
1001 vrs.cfg = cfg;
1002 vrs.cksum = 0;
1003
1004 state = 0;
1005 name = remain = i = 0; /* shut up stupid gcc */
1006 alloc = off = 0; /* shut up stupid gcc */
1007 dflen = 0; /* shut up stupid gcc */
1008 cksumvalid = -1;
1009 while (state >= 0) {
1010 if (vpd_nextbyte(&vrs, &byte)) {
1011 state = -2;
1012 break;
1013 }
1014#if 0
1015 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1016 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1017 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1018#endif
1019 switch (state) {
1020 case 0: /* item name */
1021 if (byte & 0x80) {
1022 if (vpd_nextbyte(&vrs, &byte2)) {
1023 state = -2;
1024 break;
1025 }
1026 remain = byte2;
1027 if (vpd_nextbyte(&vrs, &byte2)) {
1028 state = -2;
1029 break;
1030 }
1031 remain |= byte2 << 8;
1032 if (remain > (0x7f*4 - vrs.off)) {
1033 state = -1;
1034 kprintf(
1035 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1036 cfg->domain, cfg->bus, cfg->slot,
1037 cfg->func, remain);
1038 }
1039 name = byte & 0x7f;
1040 } else {
1041 remain = byte & 0x7;
1042 name = (byte >> 3) & 0xf;
1043 }
1044 switch (name) {
1045 case 0x2: /* String */
1046 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1047 M_DEVBUF, M_WAITOK);
1048 i = 0;
1049 state = 1;
1050 break;
1051 case 0xf: /* End */
1052 state = -1;
1053 break;
1054 case 0x10: /* VPD-R */
1055 alloc = 8;
1056 off = 0;
1057 cfg->vpd.vpd_ros = kmalloc(alloc *
1058 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1059 M_WAITOK | M_ZERO);
1060 state = 2;
1061 break;
1062 case 0x11: /* VPD-W */
1063 alloc = 8;
1064 off = 0;
1065 cfg->vpd.vpd_w = kmalloc(alloc *
1066 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1067 M_WAITOK | M_ZERO);
1068 state = 5;
1069 break;
1070 default: /* Invalid data, abort */
1071 state = -1;
1072 break;
1073 }
1074 break;
1075
1076 case 1: /* Identifier String */
1077 cfg->vpd.vpd_ident[i++] = byte;
1078 remain--;
1079 if (remain == 0) {
1080 cfg->vpd.vpd_ident[i] = '\0';
1081 state = 0;
1082 }
1083 break;
1084
1085 case 2: /* VPD-R Keyword Header */
1086 if (off == alloc) {
a68a7edf 1087 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1088 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1090 }
1091 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1092 if (vpd_nextbyte(&vrs, &byte2)) {
1093 state = -2;
1094 break;
1095 }
1096 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1097 if (vpd_nextbyte(&vrs, &byte2)) {
1098 state = -2;
1099 break;
1100 }
1101 dflen = byte2;
1102 if (dflen == 0 &&
1103 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1104 2) == 0) {
1105 /*
1106 * if this happens, we can't trust the rest
1107 * of the VPD.
1108 */
1109 kprintf(
1110 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1111 cfg->domain, cfg->bus, cfg->slot,
1112 cfg->func, dflen);
1113 cksumvalid = 0;
1114 state = -1;
1115 break;
1116 } else if (dflen == 0) {
1117 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1118 sizeof(*cfg->vpd.vpd_ros[off].value),
1119 M_DEVBUF, M_WAITOK);
1120 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1121 } else
1122 cfg->vpd.vpd_ros[off].value = kmalloc(
1123 (dflen + 1) *
1124 sizeof(*cfg->vpd.vpd_ros[off].value),
1125 M_DEVBUF, M_WAITOK);
1126 remain -= 3;
1127 i = 0;
1128 /* keep in sync w/ state 3's transistions */
1129 if (dflen == 0 && remain == 0)
1130 state = 0;
1131 else if (dflen == 0)
1132 state = 2;
1133 else
1134 state = 3;
1135 break;
1136
1137 case 3: /* VPD-R Keyword Value */
1138 cfg->vpd.vpd_ros[off].value[i++] = byte;
1139 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1140 "RV", 2) == 0 && cksumvalid == -1) {
1141 if (vrs.cksum == 0)
1142 cksumvalid = 1;
1143 else {
1144 if (bootverbose)
1145 kprintf(
1146 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1147 cfg->domain, cfg->bus,
1148 cfg->slot, cfg->func,
1149 vrs.cksum);
1150 cksumvalid = 0;
1151 state = -1;
1152 break;
1153 }
1154 }
1155 dflen--;
1156 remain--;
1157 /* keep in sync w/ state 2's transistions */
1158 if (dflen == 0)
1159 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1160 if (dflen == 0 && remain == 0) {
1161 cfg->vpd.vpd_rocnt = off;
a68a7edf 1162 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1163 off * sizeof(*cfg->vpd.vpd_ros),
1164 M_DEVBUF, M_WAITOK | M_ZERO);
1165 state = 0;
1166 } else if (dflen == 0)
1167 state = 2;
1168 break;
1169
1170 case 4:
1171 remain--;
1172 if (remain == 0)
1173 state = 0;
1174 break;
1175
1176 case 5: /* VPD-W Keyword Header */
1177 if (off == alloc) {
a68a7edf 1178 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1179 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1180 M_DEVBUF, M_WAITOK | M_ZERO);
1181 }
1182 cfg->vpd.vpd_w[off].keyword[0] = byte;
1183 if (vpd_nextbyte(&vrs, &byte2)) {
1184 state = -2;
1185 break;
1186 }
1187 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1188 if (vpd_nextbyte(&vrs, &byte2)) {
1189 state = -2;
1190 break;
1191 }
1192 cfg->vpd.vpd_w[off].len = dflen = byte2;
1193 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1194 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1195 sizeof(*cfg->vpd.vpd_w[off].value),
1196 M_DEVBUF, M_WAITOK);
1197 remain -= 3;
1198 i = 0;
1199 /* keep in sync w/ state 6's transistions */
1200 if (dflen == 0 && remain == 0)
1201 state = 0;
1202 else if (dflen == 0)
1203 state = 5;
1204 else
1205 state = 6;
1206 break;
1207
1208 case 6: /* VPD-W Keyword Value */
1209 cfg->vpd.vpd_w[off].value[i++] = byte;
1210 dflen--;
1211 remain--;
1212 /* keep in sync w/ state 5's transistions */
1213 if (dflen == 0)
1214 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1215 if (dflen == 0 && remain == 0) {
1216 cfg->vpd.vpd_wcnt = off;
a68a7edf 1217 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1218 off * sizeof(*cfg->vpd.vpd_w),
1219 M_DEVBUF, M_WAITOK | M_ZERO);
1220 state = 0;
1221 } else if (dflen == 0)
1222 state = 5;
1223 break;
1224
1225 default:
1226 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1227 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1228 state);
1229 state = -1;
1230 break;
1231 }
1232 }
1233
1234 if (cksumvalid == 0 || state < -1) {
1235 /* read-only data bad, clean up */
1236 if (cfg->vpd.vpd_ros != NULL) {
1237 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1238 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1239 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1240 cfg->vpd.vpd_ros = NULL;
1241 }
1242 }
1243 if (state < -1) {
1244 /* I/O error, clean up */
1245 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1246 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1247 if (cfg->vpd.vpd_ident != NULL) {
1248 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1249 cfg->vpd.vpd_ident = NULL;
1250 }
1251 if (cfg->vpd.vpd_w != NULL) {
1252 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1253 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1254 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1255 cfg->vpd.vpd_w = NULL;
1256 }
1257 }
1258 cfg->vpd.vpd_cached = 1;
1259#undef REG
1260#undef WREG
1261}
1262
1263int
1264pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1265{
1266 struct pci_devinfo *dinfo = device_get_ivars(child);
1267 pcicfgregs *cfg = &dinfo->cfg;
1268
1269 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1270 pci_read_vpd(device_get_parent(dev), cfg);
1271
1272 *identptr = cfg->vpd.vpd_ident;
1273
1274 if (*identptr == NULL)
1275 return (ENXIO);
1276
1277 return (0);
1278}
1279
1280int
1281pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1282 const char **vptr)
1283{
1284 struct pci_devinfo *dinfo = device_get_ivars(child);
1285 pcicfgregs *cfg = &dinfo->cfg;
1286 int i;
1287
1288 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1289 pci_read_vpd(device_get_parent(dev), cfg);
1290
1291 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1292 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1293 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1294 *vptr = cfg->vpd.vpd_ros[i].value;
1295 }
1296
1297 if (i != cfg->vpd.vpd_rocnt)
1298 return (0);
1299
1300 *vptr = NULL;
1301 return (ENXIO);
1302}
1303
1304/*
1305 * Return the offset in configuration space of the requested extended
1306 * capability entry or 0 if the specified capability was not found.
1307 */
1308int
1309pci_find_extcap_method(device_t dev, device_t child, int capability,
1310 int *capreg)
1311{
1312 struct pci_devinfo *dinfo = device_get_ivars(child);
1313 pcicfgregs *cfg = &dinfo->cfg;
1314 u_int32_t status;
1315 u_int8_t ptr;
1316
1317 /*
1318 * Check the CAP_LIST bit of the PCI status register first.
1319 */
1320 status = pci_read_config(child, PCIR_STATUS, 2);
1321 if (!(status & PCIM_STATUS_CAPPRESENT))
1322 return (ENXIO);
1323
1324 /*
1325 * Determine the start pointer of the capabilities list.
1326 */
1327 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1328 case 0:
1329 case 1:
1330 ptr = PCIR_CAP_PTR;
1331 break;
1332 case 2:
1333 ptr = PCIR_CAP_PTR_2;
1334 break;
1335 default:
1336 /* XXX: panic? */
1337 return (ENXIO); /* no extended capabilities support */
1338 }
1339 ptr = pci_read_config(child, ptr, 1);
1340
1341 /*
1342 * Traverse the capabilities list.
1343 */
1344 while (ptr != 0) {
1345 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1346 if (capreg != NULL)
1347 *capreg = ptr;
1348 return (0);
1349 }
1350 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1351 }
1352
1353 return (ENOENT);
1354}
1355
1356/*
1357 * Support for MSI-X message interrupts.
1358 */
cf8f3133
SZ
1359static void
1360pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1361 uint32_t data)
4d28e78f
SZ
1362{
1363 struct pci_devinfo *dinfo = device_get_ivars(dev);
1364 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1365 uint32_t offset;
1366
f9c942fb 1367 KASSERT(msix->msix_msgnum > index, ("bogus index"));
4d28e78f
SZ
1368 offset = msix->msix_table_offset + index * 16;
1369 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1370 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1371 bus_write_4(msix->msix_table_res, offset + 8, data);
1372
1373 /* Enable MSI -> HT mapping. */
1374 pci_ht_map_msi(dev, address);
1375}
1376
cf8f3133
SZ
1377static void
1378pci_mask_msix_vector(device_t dev, u_int index)
4d28e78f
SZ
1379{
1380 struct pci_devinfo *dinfo = device_get_ivars(dev);
1381 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1382 uint32_t offset, val;
1383
1384 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1385 offset = msix->msix_table_offset + index * 16 + 12;
1386 val = bus_read_4(msix->msix_table_res, offset);
1387 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1388 val |= PCIM_MSIX_VCTRL_MASK;
1389 bus_write_4(msix->msix_table_res, offset, val);
1390 }
1391}
1392
cf8f3133
SZ
1393static void
1394pci_unmask_msix_vector(device_t dev, u_int index)
4d28e78f
SZ
1395{
1396 struct pci_devinfo *dinfo = device_get_ivars(dev);
1397 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1398 uint32_t offset, val;
1399
f9c942fb 1400 KASSERT(msix->msix_msgnum > index, ("bogus index"));
4d28e78f
SZ
1401 offset = msix->msix_table_offset + index * 16 + 12;
1402 val = bus_read_4(msix->msix_table_res, offset);
1403 if (val & PCIM_MSIX_VCTRL_MASK) {
1404 val &= ~PCIM_MSIX_VCTRL_MASK;
1405 bus_write_4(msix->msix_table_res, offset, val);
1406 }
1407}
1408
1409int
cf8f3133 1410pci_pending_msix_vector(device_t dev, u_int index)
4d28e78f
SZ
1411{
1412 struct pci_devinfo *dinfo = device_get_ivars(dev);
1413 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1414 uint32_t offset, bit;
1415
31646171 1416 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
ed20d0e3 1417 ("MSI-X is not setup yet"));
31646171 1418
f9c942fb 1419 KASSERT(msix->msix_msgnum > index, ("bogus index"));
4d28e78f
SZ
1420 offset = msix->msix_pba_offset + (index / 32) * 4;
1421 bit = 1 << index % 32;
1422 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1423}
1424
1425/*
1426 * Restore MSI-X registers and table during resume. If MSI-X is
1427 * enabled then walk the virtual table to restore the actual MSI-X
1428 * table.
1429 */
1430static void
1431pci_resume_msix(device_t dev)
1432{
1433 struct pci_devinfo *dinfo = device_get_ivars(dev);
1434 struct pcicfg_msix *msix = &dinfo->cfg.msix;
4d28e78f 1435
fa36cf1d 1436 if (msix->msix_table_res != NULL) {
f9c942fb
SZ
1437 const struct msix_vector *mv;
1438
31646171 1439 pci_mask_msix_allvectors(dev);
4d28e78f 1440
f9c942fb
SZ
1441 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1442 u_int vector;
1443
1444 if (mv->mv_address == 0)
4d28e78f 1445 continue;
f9c942fb
SZ
1446
1447 vector = PCI_MSIX_RID2VEC(mv->mv_rid);
1448 pci_setup_msix_vector(dev, vector,
1449 mv->mv_address, mv->mv_data);
1450 pci_unmask_msix_vector(dev, vector);
4d28e78f
SZ
1451 }
1452 }
1453 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1454 msix->msix_ctrl, 2);
1455}
1456
1457/*
84ee3613
SZ
1458 * Attempt to allocate one MSI-X message at the specified vector on cpuid.
1459 *
1460 * After this function returns, the MSI-X's rid will be saved in rid0.
4d28e78f
SZ
1461 */
1462int
84ee3613
SZ
1463pci_alloc_msix_vector_method(device_t dev, device_t child, u_int vector,
1464 int *rid0, int cpuid)
4d28e78f
SZ
1465{
1466 struct pci_devinfo *dinfo = device_get_ivars(child);
84ee3613 1467 struct pcicfg_msix *msix = &dinfo->cfg.msix;
f9c942fb 1468 struct msix_vector *mv;
4d28e78f 1469 struct resource_list_entry *rle;
84ee3613 1470 int error, irq, rid;
4d28e78f 1471
84ee3613 1472 KASSERT(msix->msix_table_res != NULL &&
ed20d0e3
SW
1473 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1474 KASSERT(cpuid >= 0 && cpuid < ncpus, ("invalid cpuid %d", cpuid));
84ee3613 1475 KASSERT(vector < msix->msix_msgnum,
ed20d0e3 1476 ("invalid MSI-X vector %u, total %d", vector, msix->msix_msgnum));
4d28e78f 1477
84ee3613 1478 if (bootverbose) {
4d28e78f 1479 device_printf(child,
84ee3613
SZ
1480 "attempting to allocate MSI-X #%u vector (%d supported)\n",
1481 vector, msix->msix_msgnum);
4d28e78f 1482 }
4d28e78f 1483
84ee3613 1484 /* Set rid according to vector number */
f9c942fb
SZ
1485 rid = PCI_MSIX_VEC2RID(vector);
1486
1487 /* Vector has already been allocated */
1488 mv = pci_find_msix_vector(child, rid);
1489 if (mv != NULL)
1490 return EBUSY;
14ae4dce 1491
84ee3613
SZ
1492 /* Allocate a message. */
1493 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq, cpuid);
1494 if (error)
1495 return error;
1496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, rid,
1497 irq, irq, 1, cpuid);
4d28e78f 1498
84ee3613
SZ
1499 if (bootverbose) {
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1501 device_printf(child, "using IRQ %lu for MSI-X on cpu%d\n",
1502 rle->start, cpuid);
4d28e78f
SZ
1503 }
1504
4d28e78f 1505 /* Update counts of alloc'd messages. */
84ee3613
SZ
1506 msix->msix_alloc++;
1507
f9c942fb
SZ
1508 mv = kmalloc(sizeof(*mv), M_DEVBUF, M_WAITOK | M_ZERO);
1509 mv->mv_rid = rid;
1510 TAILQ_INSERT_TAIL(&msix->msix_vectors, mv, mv_link);
1511
84ee3613
SZ
1512 *rid0 = rid;
1513 return 0;
4d28e78f
SZ
1514}
1515
a7854dd0
SZ
1516int
1517pci_release_msix_vector_method(device_t dev, device_t child, int rid)
4d28e78f
SZ
1518{
1519 struct pci_devinfo *dinfo = device_get_ivars(child);
1520 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1521 struct resource_list_entry *rle;
a7854dd0
SZ
1522 struct msix_vector *mv;
1523 int irq, cpuid;
4d28e78f 1524
a7854dd0 1525 KASSERT(msix->msix_table_res != NULL &&
ed20d0e3
SW
1526 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1527 KASSERT(msix->msix_alloc > 0, ("No MSI-X allocated"));
1528 KASSERT(rid > 0, ("invalid rid %d", rid));
4d28e78f 1529
a7854dd0 1530 mv = pci_find_msix_vector(child, rid);
ed20d0e3
SW
1531 KASSERT(mv != NULL, ("MSI-X rid %d is not allocated", rid));
1532 KASSERT(mv->mv_address == 0, ("MSI-X rid %d not teardown", rid));
a7854dd0
SZ
1533
1534 /* Make sure resource is no longer allocated. */
1535 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
ed20d0e3 1536 KASSERT(rle != NULL, ("missing MSI-X resource, rid %d", rid));
a7854dd0 1537 KASSERT(rle->res == NULL,
ed20d0e3 1538 ("MSI-X resource is still allocated, rid %d", rid));
a7854dd0
SZ
1539
1540 irq = rle->start;
1541 cpuid = rle->cpuid;
4d28e78f
SZ
1542
1543 /* Free the resource list entries. */
a7854dd0
SZ
1544 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, rid);
1545
1546 /* Release the IRQ. */
1547 PCIB_RELEASE_MSIX(device_get_parent(dev), child, irq, cpuid);
1548
1549 TAILQ_REMOVE(&msix->msix_vectors, mv, mv_link);
1550 kfree(mv, M_DEVBUF);
1551
1552 msix->msix_alloc--;
4d28e78f
SZ
1553 return (0);
1554}
1555
1556/*
1557 * Return the max supported MSI-X messages this device supports.
1558 * Basically, assuming the MD code can alloc messages, this function
1559 * should return the maximum value that pci_alloc_msix() can return.
1560 * Thus, it is subject to the tunables, etc.
1561 */
1562int
1563pci_msix_count_method(device_t dev, device_t child)
1564{
1565 struct pci_devinfo *dinfo = device_get_ivars(child);
1566 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1567
1568 if (pci_do_msix && msix->msix_location != 0)
1569 return (msix->msix_msgnum);
1570 return (0);
1571}
1572
31646171
SZ
1573int
1574pci_setup_msix(device_t dev)
1575{
1576 struct pci_devinfo *dinfo = device_get_ivars(dev);
1577 pcicfgregs *cfg = &dinfo->cfg;
1578 struct resource_list_entry *rle;
1579 struct resource *table_res, *pba_res;
1580
1581 KASSERT(cfg->msix.msix_table_res == NULL &&
ed20d0e3 1582 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet"));
31646171
SZ
1583
1584 /* If rid 0 is allocated, then fail. */
1585 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1586 if (rle != NULL && rle->res != NULL)
1587 return (ENXIO);
1588
1589 /* Already have allocated MSIs? */
1590 if (cfg->msi.msi_alloc != 0)
1591 return (ENXIO);
1592
1593 /* If MSI is blacklisted for this system, fail. */
1594 if (pci_msi_blacklisted())
1595 return (ENXIO);
1596
1597 /* MSI-X capability present? */
ce92281b
SZ
1598 if (cfg->msix.msix_location == 0 || cfg->msix.msix_msgnum == 0 ||
1599 !pci_do_msix)
31646171
SZ
1600 return (ENODEV);
1601
ac0a3f31
SZ
1602 KASSERT(cfg->msix.msix_alloc == 0 &&
1603 TAILQ_EMPTY(&cfg->msix.msix_vectors),
ed20d0e3 1604 ("MSI-X vector has been allocated"));
ac0a3f31 1605
31646171
SZ
1606 /* Make sure the appropriate BARs are mapped. */
1607 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1608 cfg->msix.msix_table_bar);
1609 if (rle == NULL || rle->res == NULL ||
1610 !(rman_get_flags(rle->res) & RF_ACTIVE))
1611 return (ENXIO);
1612 table_res = rle->res;
1613 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1614 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1615 cfg->msix.msix_pba_bar);
1616 if (rle == NULL || rle->res == NULL ||
1617 !(rman_get_flags(rle->res) & RF_ACTIVE))
1618 return (ENXIO);
1619 }
1620 pba_res = rle->res;
1621
1622 cfg->msix.msix_table_res = table_res;
1623 cfg->msix.msix_pba_res = pba_res;
1624
1625 pci_mask_msix_allvectors(dev);
1626
1627 return 0;
1628}
1629
1630void
1631pci_teardown_msix(device_t dev)
1632{
1633 struct pci_devinfo *dinfo = device_get_ivars(dev);
1634 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1635
1636 KASSERT(msix->msix_table_res != NULL &&
ed20d0e3 1637 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
ac0a3f31 1638 KASSERT(msix->msix_alloc == 0 && TAILQ_EMPTY(&msix->msix_vectors),
ed20d0e3 1639 ("MSI-X vector is still allocated"));
31646171
SZ
1640
1641 pci_mask_msix_allvectors(dev);
1642
1643 msix->msix_table_res = NULL;
1644 msix->msix_pba_res = NULL;
1645}
1646
a39a2984
SZ
1647void
1648pci_enable_msix(device_t dev)
1649{
1650 struct pci_devinfo *dinfo = device_get_ivars(dev);
1651 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1652
1653 KASSERT(msix->msix_table_res != NULL &&
ed20d0e3 1654 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
a39a2984
SZ
1655
1656 /* Update control register to enable MSI-X. */
1657 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1658 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1659 msix->msix_ctrl, 2);
1660}
1661
1662void
1663pci_disable_msix(device_t dev)
1664{
1665 struct pci_devinfo *dinfo = device_get_ivars(dev);
1666 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1667
1668 KASSERT(msix->msix_table_res != NULL &&
ed20d0e3 1669 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
a39a2984
SZ
1670
1671 /* Disable MSI -> HT mapping. */
1672 pci_ht_map_msi(dev, 0);
1673
1674 /* Update control register to disable MSI-X. */
1675 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1676 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1677 msix->msix_ctrl, 2);
1678}
1679
31646171
SZ
1680static void
1681pci_mask_msix_allvectors(device_t dev)
1682{
1683 struct pci_devinfo *dinfo = device_get_ivars(dev);
1684 u_int i;
1685
1686 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1687 pci_mask_msix_vector(dev, i);
1688}
1689
f9c942fb
SZ
1690static struct msix_vector *
1691pci_find_msix_vector(device_t dev, int rid)
1692{
1693 struct pci_devinfo *dinfo = device_get_ivars(dev);
1694 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1695 struct msix_vector *mv;
1696
1697 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1698 if (mv->mv_rid == rid)
1699 return mv;
1700 }
1701 return NULL;
1702}
1703
4d28e78f
SZ
1704/*
1705 * HyperTransport MSI mapping control
1706 */
1707void
1708pci_ht_map_msi(device_t dev, uint64_t addr)
1709{
1710 struct pci_devinfo *dinfo = device_get_ivars(dev);
1711 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1712
1713 if (!ht->ht_msimap)
1714 return;
1715
1716 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1717 ht->ht_msiaddr >> 20 == addr >> 20) {
1718 /* Enable MSI -> HT mapping. */
1719 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1720 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1721 ht->ht_msictrl, 2);
1722 }
1723
a39a2984 1724 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
4d28e78f
SZ
1725 /* Disable MSI -> HT mapping. */
1726 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1727 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1728 ht->ht_msictrl, 2);
1729 }
1730}
1731
1732/*
1733 * Support for MSI message signalled interrupts.
1734 */
1735void
1736pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1737{
1738 struct pci_devinfo *dinfo = device_get_ivars(dev);
1739 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1740
1741 /* Write data and address values. */
1742 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1743 address & 0xffffffff, 4);
1744 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1745 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1746 address >> 32, 4);
1747 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1748 data, 2);
1749 } else
1750 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1751 2);
1752
1753 /* Enable MSI in the control register. */
1754 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1755 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1756 2);
1757
1758 /* Enable MSI -> HT mapping. */
1759 pci_ht_map_msi(dev, address);
1760}
1761
1762void
1763pci_disable_msi(device_t dev)
1764{
1765 struct pci_devinfo *dinfo = device_get_ivars(dev);
1766 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1767
1768 /* Disable MSI -> HT mapping. */
1769 pci_ht_map_msi(dev, 0);
1770
1771 /* Disable MSI in the control register. */
1772 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1773 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1774 2);
1775}
1776
1777/*
1778 * Restore MSI registers during resume. If MSI is enabled then
1779 * restore the data and address registers in addition to the control
1780 * register.
1781 */
1782static void
1783pci_resume_msi(device_t dev)
1784{
1785 struct pci_devinfo *dinfo = device_get_ivars(dev);
1786 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1787 uint64_t address;
1788 uint16_t data;
1789
1790 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1791 address = msi->msi_addr;
1792 data = msi->msi_data;
1793 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1794 address & 0xffffffff, 4);
1795 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1796 pci_write_config(dev, msi->msi_location +
1797 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1798 pci_write_config(dev, msi->msi_location +
1799 PCIR_MSI_DATA_64BIT, data, 2);
1800 } else
1801 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1802 data, 2);
1803 }
1804 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1805 2);
1806}
1807
4d28e78f
SZ
1808/*
1809 * Returns true if the specified device is blacklisted because MSI
1810 * doesn't work.
1811 */
1812int
1813pci_msi_device_blacklisted(device_t dev)
1814{
1815 struct pci_quirk *q;
1816
1817 if (!pci_honor_msi_blacklist)
1818 return (0);
1819
1820 for (q = &pci_quirks[0]; q->devid; q++) {
1821 if (q->devid == pci_get_devid(dev) &&
1822 q->type == PCI_QUIRK_DISABLE_MSI)
1823 return (1);
1824 }
1825 return (0);
1826}
1827
1828/*
1829 * Determine if MSI is blacklisted globally on this sytem. Currently,
1830 * we just check for blacklisted chipsets as represented by the
1831 * host-PCI bridge at device 0:0:0. In the future, it may become
1832 * necessary to check other system attributes, such as the kenv values
1833 * that give the motherboard manufacturer and model number.
1834 */
1835static int
1836pci_msi_blacklisted(void)
1837{
1838 device_t dev;
1839
1840 if (!pci_honor_msi_blacklist)
1841 return (0);
1842
1843 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1844 if (!(pcie_chipset || pcix_chipset))
1845 return (1);
1846
1847 dev = pci_find_bsf(0, 0, 0);
1848 if (dev != NULL)
1849 return (pci_msi_device_blacklisted(dev));
1850 return (0);
1851}
1852
1853/*
2c3d7ac8
SZ
1854 * Attempt to allocate count MSI messages on start_cpuid.
1855 *
1856 * If start_cpuid < 0, then the MSI messages' target CPU will be
1857 * selected automaticly.
1858 *
1859 * If the caller explicitly specified the MSI messages' target CPU,
1860 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1861 * messages on the specified CPU, if the allocation fails due to MD
1862 * does not have enough vectors (EMSGSIZE), then we will try next
1863 * available CPU, until the allocation fails on all CPUs.
1864 *
1865 * EMSGSIZE will be returned, if all available CPUs does not have
1866 * enough vectors for the requested amount of MSI messages. Caller
1867 * should either reduce the amount of MSI messages to be requested,
1868 * or simply giving up using MSI.
1869 *
1870 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1871 * returned in 'rid' array, if the allocation succeeds.
4d28e78f
SZ
1872 */
1873int
2c3d7ac8
SZ
1874pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1875 int start_cpuid)
4d28e78f
SZ
1876{
1877 struct pci_devinfo *dinfo = device_get_ivars(child);
1878 pcicfgregs *cfg = &dinfo->cfg;
1879 struct resource_list_entry *rle;
2c3d7ac8 1880 int error, i, irqs[32], cpuid = 0;
4d28e78f
SZ
1881 uint16_t ctrl;
1882
2c3d7ac8 1883 KASSERT(count != 0 && count <= 32 && powerof2(count),
ed20d0e3
SW
1884 ("invalid MSI count %d", count));
1885 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d", start_cpuid));
4d28e78f
SZ
1886
1887 /* If rid 0 is allocated, then fail. */
1888 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1889 if (rle != NULL && rle->res != NULL)
1890 return (ENXIO);
1891
1892 /* Already have allocated messages? */
fa36cf1d 1893 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_table_res != NULL)
4d28e78f
SZ
1894 return (ENXIO);
1895
1896 /* If MSI is blacklisted for this system, fail. */
1897 if (pci_msi_blacklisted())
1898 return (ENXIO);
1899
1900 /* MSI capability present? */
ce92281b
SZ
1901 if (cfg->msi.msi_location == 0 || cfg->msi.msi_msgnum == 0 ||
1902 !pci_do_msi)
4d28e78f
SZ
1903 return (ENODEV);
1904
ed20d0e3 1905 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d",
2c3d7ac8
SZ
1906 count, cfg->msi.msi_msgnum));
1907
1908 if (bootverbose) {
4d28e78f 1909 device_printf(child,
cf2e81fb
SW
1910 "attempting to allocate %d MSI vector%s (%d supported)\n",
1911 count, count > 1 ? "s" : "", cfg->msi.msi_msgnum);
2c3d7ac8 1912 }
4d28e78f 1913
2c3d7ac8
SZ
1914 if (start_cpuid < 0)
1915 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
4d28e78f 1916
2c3d7ac8
SZ
1917 error = EINVAL;
1918 for (i = 0; i < ncpus; ++i) {
1919 cpuid = (start_cpuid + i) % ncpus;
4d28e78f 1920
2c3d7ac8 1921 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
803a9933 1922 cfg->msi.msi_msgnum, irqs, cpuid);
4d28e78f
SZ
1923 if (error == 0)
1924 break;
2c3d7ac8
SZ
1925 else if (error != EMSGSIZE)
1926 return error;
4d28e78f 1927 }
2c3d7ac8
SZ
1928 if (error)
1929 return error;
4d28e78f
SZ
1930
1931 /*
2c3d7ac8
SZ
1932 * We now have N messages mapped onto SYS_RES_IRQ resources in
1933 * the irqs[] array, so add new resources starting at rid 1.
4d28e78f 1934 */
2c3d7ac8
SZ
1935 for (i = 0; i < count; i++) {
1936 rid[i] = i + 1;
4d28e78f 1937 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
803a9933 1938 irqs[i], irqs[i], 1, cpuid);
2c3d7ac8 1939 }
4d28e78f
SZ
1940
1941 if (bootverbose) {
2c3d7ac8
SZ
1942 if (count == 1) {
1943 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
1944 irqs[0], cpuid);
1945 } else {
4d28e78f
SZ
1946 int run;
1947
1948 /*
1949 * Be fancy and try to print contiguous runs
1950 * of IRQ values as ranges. 'run' is true if
1951 * we are in a range.
1952 */
1953 device_printf(child, "using IRQs %d", irqs[0]);
1954 run = 0;
2c3d7ac8 1955 for (i = 1; i < count; i++) {
4d28e78f
SZ
1956
1957 /* Still in a run? */
1958 if (irqs[i] == irqs[i - 1] + 1) {
1959 run = 1;
1960 continue;
1961 }
1962
1963 /* Finish previous range. */
1964 if (run) {
1965 kprintf("-%d", irqs[i - 1]);
1966 run = 0;
1967 }
1968
1969 /* Start new range. */
1970 kprintf(",%d", irqs[i]);
1971 }
1972
1973 /* Unfinished range? */
1974 if (run)
2c3d7ac8
SZ
1975 kprintf("-%d", irqs[count - 1]);
1976 kprintf(" for MSI on cpu%d\n", cpuid);
4d28e78f
SZ
1977 }
1978 }
1979
2c3d7ac8 1980 /* Update control register with count. */
4d28e78f
SZ
1981 ctrl = cfg->msi.msi_ctrl;
1982 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2c3d7ac8 1983 ctrl |= (ffs(count) - 1) << 4;
4d28e78f
SZ
1984 cfg->msi.msi_ctrl = ctrl;
1985 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1986
1987 /* Update counts of alloc'd messages. */
2c3d7ac8 1988 cfg->msi.msi_alloc = count;
4d28e78f 1989 cfg->msi.msi_handlers = 0;
4d28e78f
SZ
1990 return (0);
1991}
1992
1993/* Release the MSI messages associated with this device. */
1994int
1995pci_release_msi_method(device_t dev, device_t child)
1996{
1997 struct pci_devinfo *dinfo = device_get_ivars(child);
1998 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1999 struct resource_list_entry *rle;
50a5ba22 2000 int i, irqs[32], cpuid = -1;
4d28e78f
SZ
2001
2002 /* Do we have any messages to release? */
2003 if (msi->msi_alloc == 0)
2004 return (ENODEV);
2005 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2006
2007 /* Make sure none of the resources are allocated. */
2008 if (msi->msi_handlers > 0)
2009 return (EBUSY);
2010 for (i = 0; i < msi->msi_alloc; i++) {
2011 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2012 KASSERT(rle != NULL, ("missing MSI resource"));
2013 if (rle->res != NULL)
2014 return (EBUSY);
975cc3f0
SZ
2015 if (i == 0) {
2016 cpuid = rle->cpuid;
2017 KASSERT(cpuid >= 0 && cpuid < ncpus,
ed20d0e3 2018 ("invalid MSI target cpuid %d", cpuid));
975cc3f0
SZ
2019 } else {
2020 KASSERT(rle->cpuid == cpuid,
2021 ("MSI targets different cpus, "
2022 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2023 }
4d28e78f
SZ
2024 irqs[i] = rle->start;
2025 }
2026
2027 /* Update control register with 0 count. */
2028 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2029 ("%s: MSI still enabled", __func__));
2030 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2031 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2032 msi->msi_ctrl, 2);
2033
2034 /* Release the messages. */
975cc3f0
SZ
2035 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2036 cpuid);
4d28e78f
SZ
2037 for (i = 0; i < msi->msi_alloc; i++)
2038 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2039
2040 /* Update alloc count. */
2041 msi->msi_alloc = 0;
2042 msi->msi_addr = 0;
2043 msi->msi_data = 0;
2044 return (0);
2045}
2046
2047/*
2048 * Return the max supported MSI messages this device supports.
2049 * Basically, assuming the MD code can alloc messages, this function
2050 * should return the maximum value that pci_alloc_msi() can return.
2051 * Thus, it is subject to the tunables, etc.
2052 */
2053int
2054pci_msi_count_method(device_t dev, device_t child)
2055{
2056 struct pci_devinfo *dinfo = device_get_ivars(child);
2057 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2058
2059 if (pci_do_msi && msi->msi_location != 0)
2060 return (msi->msi_msgnum);
2061 return (0);
2062}
2063
2064/* kfree pcicfgregs structure and all depending data structures */
2065
2066int
2067pci_freecfg(struct pci_devinfo *dinfo)
2068{
2069 struct devlist *devlist_head;
2070 int i;
2071
2072 devlist_head = &pci_devq;
2073
2074 if (dinfo->cfg.vpd.vpd_reg) {
2075 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2076 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2077 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2078 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2079 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2080 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2081 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2082 }
2083 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2084 kfree(dinfo, M_DEVBUF);
2085
2086 /* increment the generation count */
2087 pci_generation++;
2088
2089 /* we're losing one device */
2090 pci_numdevs--;
2091 return (0);
2092}
2093
2094/*
2095 * PCI power manangement
2096 */
2097int
2098pci_set_powerstate_method(device_t dev, device_t child, int state)
2099{
2100 struct pci_devinfo *dinfo = device_get_ivars(child);
2101 pcicfgregs *cfg = &dinfo->cfg;
f4754a59
HT
2102 uint16_t status;
2103 int result, oldstate, highest, delay;
984263bc 2104
4d28e78f 2105 if (cfg->pp.pp_cap == 0)
f4754a59
HT
2106 return (EOPNOTSUPP);
2107
2108 /*
2109 * Optimize a no state change request away. While it would be OK to
2110 * write to the hardware in theory, some devices have shown odd
2111 * behavior when going from D3 -> D3.
2112 */
2113 oldstate = pci_get_powerstate(child);
2114 if (oldstate == state)
2115 return (0);
2116
2117 /*
2118 * The PCI power management specification states that after a state
2119 * transition between PCI power states, system software must
2120 * guarantee a minimal delay before the function accesses the device.
2121 * Compute the worst case delay that we need to guarantee before we
2122 * access the device. Many devices will be responsive much more
2123 * quickly than this delay, but there are some that don't respond
2124 * instantly to state changes. Transitions to/from D3 state require
2125 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2126 * is done below with DELAY rather than a sleeper function because
2127 * this function can be called from contexts where we cannot sleep.
2128 */
2129 highest = (oldstate > state) ? oldstate : state;
2130 if (highest == PCI_POWERSTATE_D3)
2131 delay = 10000;
2132 else if (highest == PCI_POWERSTATE_D2)
2133 delay = 200;
2134 else
2135 delay = 0;
4d28e78f 2136 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
f4754a59
HT
2137 & ~PCIM_PSTAT_DMASK;
2138 result = 0;
2139 switch (state) {
2140 case PCI_POWERSTATE_D0:
2141 status |= PCIM_PSTAT_D0;
2142 break;
2143 case PCI_POWERSTATE_D1:
4d28e78f 2144 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
f4754a59
HT
2145 return (EOPNOTSUPP);
2146 status |= PCIM_PSTAT_D1;
2147 break;
2148 case PCI_POWERSTATE_D2:
4d28e78f 2149 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
f4754a59
HT
2150 return (EOPNOTSUPP);
2151 status |= PCIM_PSTAT_D2;
2152 break;
2153 case PCI_POWERSTATE_D3:
2154 status |= PCIM_PSTAT_D3;
2155 break;
2156 default:
2157 return (EINVAL);
984263bc 2158 }
f4754a59
HT
2159
2160 if (bootverbose)
2161 kprintf(
4d28e78f
SZ
2162 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2163 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2164 dinfo->cfg.func, oldstate, state);
f4754a59 2165
4d28e78f 2166 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
f4754a59
HT
2167 if (delay)
2168 DELAY(delay);
2169 return (0);
984263bc
MD
2170}
2171
e126caf1 2172int
984263bc
MD
2173pci_get_powerstate_method(device_t dev, device_t child)
2174{
2175 struct pci_devinfo *dinfo = device_get_ivars(child);
2176 pcicfgregs *cfg = &dinfo->cfg;
f4754a59 2177 uint16_t status;
984263bc
MD
2178 int result;
2179
4d28e78f
SZ
2180 if (cfg->pp.pp_cap != 0) {
2181 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
984263bc
MD
2182 switch (status & PCIM_PSTAT_DMASK) {
2183 case PCIM_PSTAT_D0:
2184 result = PCI_POWERSTATE_D0;
2185 break;
2186 case PCIM_PSTAT_D1:
2187 result = PCI_POWERSTATE_D1;
2188 break;
2189 case PCIM_PSTAT_D2:
2190 result = PCI_POWERSTATE_D2;
2191 break;
2192 case PCIM_PSTAT_D3:
2193 result = PCI_POWERSTATE_D3;
2194 break;
2195 default:
2196 result = PCI_POWERSTATE_UNKNOWN;
2197 break;
2198 }
2199 } else {
2200 /* No support, device is always at D0 */
2201 result = PCI_POWERSTATE_D0;
2202 }
f4754a59 2203 return (result);
984263bc
MD
2204}
2205
2206/*
2207 * Some convenience functions for PCI device drivers.
2208 */
2209
2210static __inline void
4d28e78f 2211pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
984263bc 2212{
4d28e78f 2213 uint16_t command;
984263bc 2214
4d28e78f
SZ
2215 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2216 command |= bit;
2217 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2218}
2219
2220static __inline void
4d28e78f
SZ
2221pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2222{
2223 uint16_t command;
984263bc 2224
4d28e78f
SZ
2225 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2226 command &= ~bit;
2227 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2228}
2229
4d28e78f
SZ
2230int
2231pci_enable_busmaster_method(device_t dev, device_t child)
2232{
2233 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2234 return (0);
2235}
984263bc 2236
4d28e78f
SZ
2237int
2238pci_disable_busmaster_method(device_t dev, device_t child)
2239{
2240 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2241 return (0);
2242}
984263bc 2243
4d28e78f
SZ
2244int
2245pci_enable_io_method(device_t dev, device_t child, int space)
ed1bd994 2246{
4d28e78f
SZ
2247 uint16_t command;
2248 uint16_t bit;
2249 char *error;
ed1bd994 2250
4d28e78f
SZ
2251 bit = 0;
2252 error = NULL;
2253
2254 switch(space) {
2255 case SYS_RES_IOPORT:
2256 bit = PCIM_CMD_PORTEN;
2257 error = "port";
ed1bd994 2258 break;
4d28e78f
SZ
2259 case SYS_RES_MEMORY:
2260 bit = PCIM_CMD_MEMEN;
2261 error = "memory";
ed1bd994
MD
2262 break;
2263 default:
4d28e78f 2264 return (EINVAL);
ed1bd994 2265 }
4d28e78f
SZ
2266 pci_set_command_bit(dev, child, bit);
2267 /* Some devices seem to need a brief stall here, what do to? */
2268 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2269 if (command & bit)
2270 return (0);
2271 device_printf(child, "failed to enable %s mapping!\n", error);
2272 return (ENXIO);
ed1bd994 2273}
984263bc 2274
4d28e78f
SZ
2275int
2276pci_disable_io_method(device_t dev, device_t child, int space)
b4c0a845 2277{
4d28e78f
SZ
2278 uint16_t command;
2279 uint16_t bit;
2280 char *error;
b4c0a845 2281
4d28e78f
SZ
2282 bit = 0;
2283 error = NULL;
b4c0a845 2284
4d28e78f
SZ
2285 switch(space) {
2286 case SYS_RES_IOPORT:
2287 bit = PCIM_CMD_PORTEN;
2288 error = "port";
b4c0a845 2289 break;
4d28e78f
SZ
2290 case SYS_RES_MEMORY:
2291 bit = PCIM_CMD_MEMEN;
2292 error = "memory";
b4c0a845
SZ
2293 break;
2294 default:
4d28e78f 2295 return (EINVAL);
b4c0a845 2296 }
4d28e78f
SZ
2297 pci_clear_command_bit(dev, child, bit);
2298 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2299 if (command & bit) {
2300 device_printf(child, "failed to disable %s mapping!\n", error);
2301 return (ENXIO);
b4c0a845 2302 }
4d28e78f 2303 return (0);
b4c0a845
SZ
2304}
2305
4d28e78f
SZ
2306/*
2307 * New style pci driver. Parent device is either a pci-host-bridge or a
2308 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2309 */
2310
22457186 2311void
984263bc
MD
2312pci_print_verbose(struct pci_devinfo *dinfo)
2313{
4d28e78f 2314
984263bc
MD
2315 if (bootverbose) {
2316 pcicfgregs *cfg = &dinfo->cfg;
2317
4d28e78f
SZ
2318 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2319 cfg->vendor, cfg->device, cfg->revid);
2320 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2321 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2322 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2323 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2324 cfg->mfdev);
2325 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2326 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 2327 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
4d28e78f
SZ
2328 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2329 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
984263bc 2330 if (cfg->intpin > 0)
4d28e78f
SZ
2331 kprintf("\tintpin=%c, irq=%d\n",
2332 cfg->intpin +'a' -1, cfg->intline);
2333 if (cfg->pp.pp_cap) {
2334 uint16_t status;
2335
2336 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2337 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2338 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2339 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2340 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2341 status & PCIM_PSTAT_DMASK);
2342 }
2343 if (cfg->msi.msi_location) {
2344 int ctrl;
2345
2346 ctrl = cfg->msi.msi_ctrl;
2347 kprintf("\tMSI supports %d message%s%s%s\n",
2348 cfg->msi.msi_msgnum,
2349 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2350 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2351 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2352 }
2353 if (cfg->msix.msix_location) {
2354 kprintf("\tMSI-X supports %d message%s ",
2355 cfg->msix.msix_msgnum,
2356 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2357 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2358 kprintf("in map 0x%x\n",
2359 cfg->msix.msix_table_bar);
2360 else
2361 kprintf("in maps 0x%x and 0x%x\n",
2362 cfg->msix.msix_table_bar,
2363 cfg->msix.msix_pba_bar);
2364 }
d85e7311 2365 pci_print_verbose_expr(cfg);
984263bc
MD
2366 }
2367}
2368
d85e7311
SZ
2369static void
2370pci_print_verbose_expr(const pcicfgregs *cfg)
2371{
2372 const struct pcicfg_expr *expr = &cfg->expr;
2373 const char *port_name;
2374 uint16_t port_type;
2375
2376 if (!bootverbose)
2377 return;
2378
2379 if (expr->expr_ptr == 0) /* No PCI Express capability */
2380 return;
2381
2382 kprintf("\tPCI Express ver.%d cap=0x%04x",
2383 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
d85e7311
SZ
2384
2385 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2386
2387 switch (port_type) {
2388 case PCIE_END_POINT:
2389 port_name = "DEVICE";
2390 break;
2391 case PCIE_LEG_END_POINT:
2392 port_name = "LEGDEV";
2393 break;
2394 case PCIE_ROOT_PORT:
2395 port_name = "ROOT";
2396 break;
2397 case PCIE_UP_STREAM_PORT:
2398 port_name = "UPSTREAM";
2399 break;
2400 case PCIE_DOWN_STREAM_PORT:
2401 port_name = "DOWNSTRM";
2402 break;
2403 case PCIE_PCIE2PCI_BRIDGE:
2404 port_name = "PCIE2PCI";
2405 break;
2406 case PCIE_PCI2PCIE_BRIDGE:
2407 port_name = "PCI2PCIE";
2408 break;
b3a9cafb
SZ
2409 case PCIE_ROOT_END_POINT:
2410 port_name = "ROOTDEV";
2411 break;
2412 case PCIE_ROOT_EVT_COLL:
2413 port_name = "ROOTEVTC";
2414 break;
d85e7311
SZ
2415 default:
2416 port_name = NULL;
2417 break;
2418 }
2419 if ((port_type == PCIE_ROOT_PORT ||
2420 port_type == PCIE_DOWN_STREAM_PORT) &&
2421 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2422 port_name = NULL;
2423 if (port_name != NULL)
2424 kprintf("[%s]", port_name);
2425
2426 if (pcie_slotimpl(cfg)) {
2427 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2428 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2429 kprintf("[HOTPLUG]");
2430 }
d85e7311
SZ
2431 kprintf("\n");
2432}
2433
984263bc 2434static int
4a5a2d63 2435pci_porten(device_t pcib, int b, int s, int f)
984263bc 2436{
4a5a2d63
JS
2437 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2438 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
2439}
2440
2441static int
4a5a2d63 2442pci_memen(device_t pcib, int b, int s, int f)
984263bc 2443{
4a5a2d63
JS
2444 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2445 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
2446}
2447
2448/*
2449 * Add a resource based on a pci map register. Return 1 if the map
2450 * register is a 32bit map register or 2 if it is a 64bit register.
2451 */
2452static int
4d28e78f
SZ
2453pci_add_map(device_t pcib, device_t bus, device_t dev,
2454 int b, int s, int f, int reg, struct resource_list *rl, int force,
2455 int prefetch)
2456{
2457 uint32_t map;
f020c2db 2458 uint16_t old_cmd;
4d28e78f
SZ
2459 pci_addr_t base;
2460 pci_addr_t start, end, count;
2461 uint8_t ln2size;
2462 uint8_t ln2range;
2463 uint32_t testval;
2464 uint16_t cmd;
984263bc 2465 int type;
4d28e78f
SZ
2466 int barlen;
2467 struct resource *res;
984263bc 2468
4a5a2d63 2469 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
f020c2db
SZ
2470
2471 /* Disable access to device memory */
2472 old_cmd = 0;
2473 if (PCI_BAR_MEM(map)) {
2474 old_cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2475 cmd = old_cmd & ~PCIM_CMD_MEMEN;
2476 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2477 }
2478
4a5a2d63
JS
2479 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2480 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2481 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc 2482
f020c2db
SZ
2483 /* Restore memory access mode */
2484 if (PCI_BAR_MEM(map)) {
2485 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, old_cmd, 2);
2486 }
2487
4d28e78f 2488 if (PCI_BAR_MEM(map)) {
984263bc 2489 type = SYS_RES_MEMORY;
4d28e78f
SZ
2490 if (map & PCIM_BAR_MEM_PREFETCH)
2491 prefetch = 1;
2492 } else
984263bc
MD
2493 type = SYS_RES_IOPORT;
2494 ln2size = pci_mapsize(testval);
2495 ln2range = pci_maprange(testval);
4d28e78f
SZ
2496 base = pci_mapbase(map);
2497 barlen = ln2range == 64 ? 2 : 1;
2498
2499 /*
2500 * For I/O registers, if bottom bit is set, and the next bit up
2501 * isn't clear, we know we have a BAR that doesn't conform to the
2502 * spec, so ignore it. Also, sanity check the size of the data
2503 * areas to the type of memory involved. Memory must be at least
2504 * 16 bytes in size, while I/O ranges must be at least 4.
2505 */
2506 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2507 return (barlen);
2508 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2509 (type == SYS_RES_IOPORT && ln2size < 2))
2510 return (barlen);
2511
2512 if (ln2range == 64)
984263bc 2513 /* Read the other half of a 64bit map register */
4d28e78f
SZ
2514 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2515 if (bootverbose) {
2516 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2517 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2518 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2519 kprintf(", port disabled\n");
2520 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2521 kprintf(", memory disabled\n");
2522 else
2523 kprintf(", enabled\n");
984263bc
MD
2524 }
2525
984263bc 2526 /*
4d28e78f
SZ
2527 * If base is 0, then we have problems. It is best to ignore
2528 * such entries for the moment. These will be allocated later if
2529 * the driver specifically requests them. However, some
2530 * removable busses look better when all resources are allocated,
2531 * so allow '0' to be overriden.
2532 *
2533 * Similarly treat maps whose values is the same as the test value
2534 * read back. These maps have had all f's written to them by the
2535 * BIOS in an attempt to disable the resources.
984263bc 2536 */
4d28e78f
SZ
2537 if (!force && (base == 0 || map == testval))
2538 return (barlen);
2539 if ((u_long)base != base) {
2540 device_printf(bus,
2541 "pci%d:%d:%d:%d bar %#x too many address bits",
2542 pci_get_domain(dev), b, s, f, reg);
2543 return (barlen);
984263bc 2544 }
984263bc 2545
4d28e78f
SZ
2546 /*
2547 * This code theoretically does the right thing, but has
2548 * undesirable side effects in some cases where peripherals
2549 * respond oddly to having these bits enabled. Let the user
2550 * be able to turn them off (since pci_enable_io_modes is 1 by
2551 * default).
2552 */
2553 if (pci_enable_io_modes) {
2554 /* Turn on resources that have been left off by a lazy BIOS */
2555 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2556 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2557 cmd |= PCIM_CMD_PORTEN;
2558 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2559 }
2560 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2561 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2562 cmd |= PCIM_CMD_MEMEN;
2563 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2564 }
2565 } else {
2566 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2567 return (barlen);
2568 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2569 return (barlen);
2570 }
984263bc 2571
4d28e78f
SZ
2572 count = 1 << ln2size;
2573 if (base == 0 || base == pci_mapbase(testval)) {
2574 start = 0; /* Let the parent decide. */
2575 end = ~0ULL;
2576 } else {
2577 start = base;
2578 end = base + (1 << ln2size) - 1;
984263bc 2579 }
1b000e91 2580 resource_list_add(rl, type, reg, start, end, count, -1);
984263bc 2581
4d28e78f
SZ
2582 /*
2583 * Try to allocate the resource for this BAR from our parent
2584 * so that this resource range is already reserved. The
2585 * driver for this device will later inherit this resource in
2586 * pci_alloc_resource().
2587 */
2588 res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,
93fad519 2589 prefetch ? RF_PREFETCHABLE : 0, -1);
4d28e78f
SZ
2590 if (res == NULL) {
2591 /*
d0c4beb1
SZ
2592 * If the allocation fails, delete the resource list
2593 * entry to force pci_alloc_resource() to allocate
2594 * resources from the parent.
4d28e78f
SZ
2595 */
2596 resource_list_delete(rl, type, reg);
d0c4beb1
SZ
2597#ifdef PCI_BAR_CLEAR
2598 /* Clear the BAR */
4d28e78f 2599 start = 0;
d0c4beb1
SZ
2600#else /* !PCI_BAR_CLEAR */
2601 /*
2602 * Don't clear BAR here. Some BIOS lists HPET as a
2603 * PCI function, clearing the BAR causes HPET timer
2604 * stop ticking.
2605 */
2606 if (bootverbose) {
2607 kprintf("pci:%d:%d:%d: resource reservation failed "
bfc09ba0
MD
2608 "%#jx - %#jx\n", b, s, f,
2609 (intmax_t)start, (intmax_t)end);
d0c4beb1
SZ
2610 }
2611 return (barlen);
2612#endif /* PCI_BAR_CLEAR */
2613 } else {
4d28e78f 2614 start = rman_get_start(res);
d0c4beb1 2615 }
4d28e78f
SZ
2616 pci_write_config(dev, reg, start, 4);
2617 if (ln2range == 64)
2618 pci_write_config(dev, reg + 4, start >> 32, 4);
2619 return (barlen);
984263bc
MD
2620}
2621
201eb0a7 2622/*
4d28e78f 2623 * For ATA devices we need to decide early what addressing mode to use.
201eb0a7
TS
2624 * Legacy demands that the primary and secondary ATA ports sits on the
2625 * same addresses that old ISA hardware did. This dictates that we use
4d28e78f 2626 * those addresses and ignore the BAR's if we cannot set PCI native
201eb0a7
TS
2627 * addressing mode.
2628 */
2629static void
4d28e78f
SZ
2630pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2631 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
201eb0a7
TS
2632{
2633 int rid, type, progif;
2634#if 0
2635 /* if this device supports PCI native addressing use it */
2636 progif = pci_read_config(dev, PCIR_PROGIF, 1);
4d28e78f 2637 if ((progif & 0x8a) == 0x8a) {
201eb0a7
TS
2638 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2639 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 2640 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
2641 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2642 }
2643 }
2644#endif
201eb0a7
TS
2645 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2646 type = SYS_RES_IOPORT;
2647 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
4d28e78f
SZ
2648 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2649 prefetchmask & (1 << 0));
2650 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2651 prefetchmask & (1 << 1));
201eb0a7
TS
2652 } else {
2653 rid = PCIR_BAR(0);
1b000e91 2654 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
201eb0a7 2655 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
93fad519 2656 0, -1);
201eb0a7 2657 rid = PCIR_BAR(1);
1b000e91 2658 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
201eb0a7 2659 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
93fad519 2660 0, -1);
201eb0a7
TS
2661 }
2662 if (progif & PCIP_STORAGE_IDE_MODESEC) {
4d28e78f
SZ
2663 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2664 prefetchmask & (1 << 2));
2665 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2666 prefetchmask & (1 << 3));
201eb0a7
TS
2667 } else {
2668 rid = PCIR_BAR(2);
1b000e91 2669 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
201eb0a7 2670 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
93fad519 2671 0, -1);
201eb0a7 2672 rid = PCIR_BAR(3);
1b000e91 2673 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
201eb0a7 2674 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
93fad519 2675 0, -1);
201eb0a7 2676 }
4d28e78f
SZ
2677 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2678 prefetchmask & (1 << 4));
2679 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2680 prefetchmask & (1 << 5));
201eb0a7 2681}
201eb0a7 2682
984263bc 2683static void
4d28e78f
SZ
2684pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2685{
2686 struct pci_devinfo *dinfo = device_get_ivars(dev);
2687 pcicfgregs *cfg = &dinfo->cfg;
2688 char tunable_name[64];
2689 int irq;
2690
2691 /* Has to have an intpin to have an interrupt. */
2692 if (cfg->intpin == 0)
2693 return;
2694
2695 /* Let the user override the IRQ with a tunable. */
2696 irq = PCI_INVALID_IRQ;
2697 ksnprintf(tunable_name, sizeof(tunable_name),
3382759b
SZ
2698 "hw.pci%d.%d.%d.%d.INT%c.irq",
2699 cfg->domain, cfg->bus, cfg->slot, cfg->func, cfg->intpin + 'A' - 1);
2700 if (TUNABLE_INT_FETCH(tunable_name, &irq)) {
2701 if (irq >= 255 || irq <= 0) {
2702 irq = PCI_INVALID_IRQ;
2703 } else {
2704 BUS_CONFIG_INTR(bus, dev, irq,
2705 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2706 }
2707 }
4d28e78f
SZ
2708
2709 /*
2710 * If we didn't get an IRQ via the tunable, then we either use the
2711 * IRQ value in the intline register or we ask the bus to route an
2712 * interrupt for us. If force_route is true, then we only use the
2713 * value in the intline register if the bus was unable to assign an
2714 * IRQ.
2715 */
2716 if (!PCI_INTERRUPT_VALID(irq)) {
2717 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2718 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2719 if (!PCI_INTERRUPT_VALID(irq))
2720 irq = cfg->intline;
2721 }
2722
2723 /* If after all that we don't have an IRQ, just bail. */
2724 if (!PCI_INTERRUPT_VALID(irq))
2725 return;
2726
2727 /* Update the config register if it changed. */
2728 if (irq != cfg->intline) {
2729 cfg->intline = irq;
2730 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2731 }
2732
2733 /* Add this IRQ as rid 0 interrupt resource. */
d2f04fe0 2734 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
bec969af 2735 machintr_legacy_intr_cpuid(irq));
4d28e78f
SZ
2736}
2737
2738void
2739pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
984263bc
MD
2740{
2741 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 2742 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
2743 struct resource_list *rl = &dinfo->resources;
2744 struct pci_quirk *q;
e126caf1 2745 int b, i, f, s;
984263bc 2746
e126caf1
MD
2747 b = cfg->bus;
2748 s = cfg->slot;
2749 f = cfg->func;
4d28e78f
SZ
2750
2751 /* ATA devices needs special map treatment */
201eb0a7
TS
2752 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2753 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
2754 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2755 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2756 !pci_read_config(dev, PCIR_BAR(2), 4))) )
4d28e78f 2757 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
201eb0a7 2758 else
4d28e78f
SZ
2759 for (i = 0; i < cfg->nummaps;)
2760 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2761 rl, force, prefetchmask & (1 << i));
984263bc 2762
4d28e78f
SZ
2763 /*
2764 * Add additional, quirked resources.
2765 */
984263bc
MD
2766 for (q = &pci_quirks[0]; q->devid; q++) {
2767 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2768 && q->type == PCI_QUIRK_MAP_REG)
4d28e78f
SZ
2769 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2770 force, 0);
984263bc
MD
2771 }
2772
4d28e78f 2773 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4d28e78f
SZ
2774 /*
2775 * Try to re-route interrupts. Sometimes the BIOS or
2776 * firmware may leave bogus values in these registers.
2777 * If the re-route fails, then just stick with what we
2778 * have.
2779 */
2780 pci_assign_interrupt(bus, dev, 1);
4d28e78f 2781 }
984263bc
MD
2782}
2783
e126caf1 2784void
4d28e78f 2785pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
984263bc 2786{
4d28e78f 2787#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 2788 device_t pcib = device_get_parent(dev);
e126caf1 2789 struct pci_devinfo *dinfo;
4a5a2d63 2790 int maxslots;
e126caf1
MD
2791 int s, f, pcifunchigh;
2792 uint8_t hdrtype;
2793
4d28e78f
SZ
2794 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2795 ("dinfo_size too small"));
4a5a2d63 2796 maxslots = PCIB_MAXSLOTS(pcib);
57e943f7 2797 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
2798 pcifunchigh = 0;
2799 f = 0;
4d28e78f 2800 DELAY(1);
e126caf1
MD
2801 hdrtype = REG(PCIR_HDRTYPE, 1);
2802 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2803 continue;
2804 if (hdrtype & PCIM_MFDEV)
2805 pcifunchigh = PCI_FUNCMAX;
5e658043 2806 for (f = 0; f <= pcifunchigh; f++) {
4d28e78f
SZ
2807 dinfo = pci_read_device(pcib, domain, busno, s, f,
2808 dinfo_size);
984263bc 2809 if (dinfo != NULL) {
e126caf1 2810 pci_add_child(dev, dinfo);
984263bc
MD
2811 }
2812 }
2813 }
e126caf1
MD
2814#undef REG
2815}
2816
2817void
2818pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2819{
2820 device_t pcib;
2821
2822 pcib = device_get_parent(bus);
2823 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2824 device_set_ivars(dinfo->cfg.dev, dinfo);
4d28e78f 2825 resource_list_init(&dinfo->resources);
638744c5
HT
2826 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2827 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1 2828 pci_print_verbose(dinfo);
4d28e78f 2829 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
984263bc
MD
2830}
2831
2832static int
4a5a2d63 2833pci_probe(device_t dev)
984263bc 2834{
984263bc 2835 device_set_desc(dev, "PCI bus");
4a5a2d63 2836
4d28e78f
SZ
2837 /* Allow other subclasses to override this driver. */
2838 return (-1000);
984263bc
MD
2839}
2840
2841static int
e126caf1
MD
2842pci_attach(device_t dev)
2843{
4d28e78f
SZ
2844 int busno, domain;
2845
2846 /*
2847 * Since there can be multiple independantly numbered PCI
2848 * busses on systems with multiple PCI domains, we can't use
2849 * the unit number to decide which bus we are probing. We ask
2850 * the parent pcib what our domain and bus numbers are.
2851 */
2852 domain = pcib_get_domain(dev);
2853 busno = pcib_get_bus(dev);
2854 if (bootverbose)
2855 device_printf(dev, "domain=%d, physical bus=%d\n",
2856 domain, busno);
e4c9c0c8 2857
4d28e78f 2858 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
e126caf1 2859
4d28e78f
SZ
2860 return (bus_generic_attach(dev));
2861}
2862
2863int
2864pci_suspend(device_t dev)
2865{
2866 int dstate, error, i, numdevs;
2867 device_t acpi_dev, child, *devlist;
2868 struct pci_devinfo *dinfo;
2869
2870 /*
2871 * Save the PCI configuration space for each child and set the
2872 * device in the appropriate power state for this sleep state.
2873 */
2874 acpi_dev = NULL;
2875 if (pci_do_power_resume)
2876 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2877 device_get_children(dev, &devlist, &numdevs);
2878 for (i = 0; i < numdevs; i++) {
2879 child = devlist[i];
2880 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2881 pci_cfg_save(child, dinfo, 0);
2882 }
e126caf1 2883
4d28e78f
SZ
2884 /* Suspend devices before potentially powering them down. */
2885 error = bus_generic_suspend(dev);
2886 if (error) {
2887 kfree(devlist, M_TEMP);
2888 return (error);
2889 }
e126caf1 2890
4d28e78f
SZ
2891 /*
2892 * Always set the device to D3. If ACPI suggests a different
2893 * power state, use it instead. If ACPI is not present, the
2894 * firmware is responsible for managing device power. Skip
2895 * children who aren't attached since they are powered down
2896 * separately. Only manage type 0 devices for now.
2897 */
2898 for (i = 0; acpi_dev && i < numdevs; i++) {
2899 child = devlist[i];
2900 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2901 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2902 dstate = PCI_POWERSTATE_D3;
2903 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2904 pci_set_powerstate(child, dstate);
2905 }
2906 }
2907 kfree(devlist, M_TEMP);
2908 return (0);
e126caf1
MD
2909}
2910
4d28e78f
SZ
2911int
2912pci_resume(device_t dev)
984263bc 2913{
4d28e78f
SZ
2914 int i, numdevs;
2915 device_t acpi_dev, child, *devlist;
2916 struct pci_devinfo *dinfo;
2917
2918 /*
2919 * Set each child to D0 and restore its PCI configuration space.
2920 */
2921 acpi_dev = NULL;
2922 if (pci_do_power_resume)
2923 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2924 device_get_children(dev, &devlist, &numdevs);
2925 for (i = 0; i < numdevs; i++) {
2926 /*
2927 * Notify ACPI we're going to D0 but ignore the result. If
2928 * ACPI is not present, the firmware is responsible for
2929 * managing device power. Only manage type 0 devices for now.
2930 */
2931 child = devlist[i];
2932 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2933 if (acpi_dev && device_is_attached(child) &&
2934 dinfo->cfg.hdrtype == 0) {
2935 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2936 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2937 }
2938
2939 /* Now the device is powered up, restore its config space. */
2940 pci_cfg_restore(child, dinfo);
2941 }
2942 kfree(devlist, M_TEMP);
2943 return (bus_generic_resume(dev));
2944}
2945
2946static void
2947pci_load_vendor_data(void)
2948{
2949 caddr_t vendordata, info;
2950
2951 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2952 info = preload_search_info(vendordata, MODINFO_ADDR);
2953 pci_vendordata = *(char **)info;
2954 info = preload_search_info(vendordata, MODINFO_SIZE);
2955 pci_vendordata_size = *(size_t *)info;
2956 /* terminate the database */
2957 pci_vendordata[pci_vendordata_size] = '\n';
2958 }
2959}
2960
2961void
2962pci_driver_added(device_t dev, driver_t *driver)
2963{
2964 int numdevs;
2965 device_t *devlist;
2966 device_t child;
2967 struct pci_devinfo *dinfo;
2968 int i;
2969
2970 if (bootverbose)
2971 device_printf(dev, "driver added\n");
2972 DEVICE_IDENTIFY(driver, dev);
2973 device_get_children(dev, &devlist, &numdevs);
2974 for (i = 0; i < numdevs; i++) {
2975 child = devlist[i];
2976 if (device_get_state(child) != DS_NOTPRESENT)
2977 continue;
2978 dinfo = device_get_ivars(child);
2979 pci_print_verbose(dinfo);
2980 if (bootverbose)
2981 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2982 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2983 dinfo->cfg.func);
2984 pci_cfg_restore(child, dinfo);
2985 if (device_probe_and_attach(child) != 0)
2986 pci_cfg_save(child, dinfo, 1);
2987 }
2988 kfree(devlist, M_TEMP);
2989}
2990
11a49859
SZ
2991static void
2992pci_child_detached(device_t parent __unused, device_t child)
2993{
2994 /* Turn child's power off */
2995 pci_cfg_save(child, device_get_ivars(child), 1);
2996}
2997
4d28e78f
SZ
2998int
2999pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
0e6f0e28
SZ
3000 driver_intr_t *intr, void *arg, void **cookiep,
3001 lwkt_serialize_t serializer, const char *desc)
4d28e78f 3002{
fb9077ae 3003 int rid, error;
4d28e78f 3004 void *cookie;
fb9077ae 3005
4d28e78f 3006 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
0e6f0e28 3007 arg, &cookie, serializer, desc);
4d28e78f
SZ
3008 if (error)
3009 return (error);
3010
3011 /* If this is not a direct child, just bail out. */
3012 if (device_get_parent(child) != dev) {
3013 *cookiep = cookie;
3014 return(0);
3015 }
3016
4d28e78f
SZ
3017 rid = rman_get_rid(irq);
3018 if (rid == 0) {
3019 /* Make sure that INTx is enabled */
3020 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3021 } else {
f9c942fb
SZ
3022 struct pci_devinfo *dinfo = device_get_ivars(child);
3023 uint64_t addr;
3024 uint32_t data;
3025
4d28e78f
SZ
3026 /*
3027 * Check to see if the interrupt is MSI or MSI-X.
3028 * Ask our parent to map the MSI and give
3029 * us the address and data register values.
3030 * If we fail for some reason, teardown the
3031 * interrupt handler.
3032 */
4d28e78f 3033 if (dinfo->cfg.msi.msi_alloc > 0) {
f9c942fb
SZ
3034 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3035
3036 if (msi->msi_addr == 0) {
3037 KASSERT(msi->msi_handlers == 0,
4d28e78f
SZ
3038 ("MSI has handlers, but vectors not mapped"));
3039 error = PCIB_MAP_MSI(device_get_parent(dev),
0af900e1
SZ
3040 child, rman_get_start(irq), &addr, &data,
3041 rman_get_cpuid(irq));
4d28e78f
SZ
3042 if (error)
3043 goto bad;
f9c942fb
SZ
3044 msi->msi_addr = addr;
3045 msi->msi_data = data;
4d28e78f 3046 pci_enable_msi(child, addr, data);
984263bc 3047 }
f9c942fb 3048 msi->msi_handlers++;
4d28e78f 3049 } else {
f9c942fb
SZ
3050 struct msix_vector *mv;
3051 u_int vector;
3052
4d28e78f 3053 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
ed20d0e3 3054 ("No MSI-X or MSI rid %d allocated", rid));
f9c942fb
SZ
3055
3056 mv = pci_find_msix_vector(child, rid);
3057 KASSERT(mv != NULL,
ed20d0e3 3058 ("MSI-X rid %d is not allocated", rid));
f9c942fb 3059 KASSERT(mv->mv_address == 0,
ed20d0e3 3060 ("MSI-X rid %d has been setup", rid));
f9c942fb
SZ
3061
3062 error = PCIB_MAP_MSI(device_get_parent(dev),
3063 child, rman_get_start(irq), &addr, &data,
3064 rman_get_cpuid(irq));
3065 if (error)
3066 goto bad;
3067 mv->mv_address = addr;
3068 mv->mv_data = data;
3069
3070 vector = PCI_MSIX_RID2VEC(rid);
3071 pci_setup_msix_vector(child, vector,
3072 mv->mv_address, mv->mv_data);
3073 pci_unmask_msix_vector(child, vector);
4d28e78f
SZ
3074 }
3075
3076 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3077 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3078 bad:
3079 if (error) {
3080 (void)bus_generic_teardown_intr(dev, child, irq,
3081 cookie);
3082 return (error);
3083 }
3084 }
4d28e78f
SZ
3085 *cookiep = cookie;
3086 return (0);
3087}
3088
3089int
3090pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3091 void *cookie)
3092{
fb9077ae 3093 int rid, error;
4d28e78f
SZ
3094
3095 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3096 return (EINVAL);
3097
3098 /* If this isn't a direct child, just bail out */
3099 if (device_get_parent(child) != dev)
3100 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3101
4d28e78f
SZ
3102 rid = rman_get_rid(irq);
3103 if (rid == 0) {
3104 /* Mask INTx */
3105 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3106 } else {
f9c942fb
SZ
3107 struct pci_devinfo *dinfo = device_get_ivars(child);
3108
4d28e78f
SZ
3109 /*
3110 * Check to see if the interrupt is MSI or MSI-X. If so,
3111 * decrement the appropriate handlers count and mask the
3112 * MSI-X message, or disable MSI messages if the count
3113 * drops to 0.
3114 */
4d28e78f 3115 if (dinfo->cfg.msi.msi_alloc > 0) {
f9c942fb
SZ
3116 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3117
3118 KASSERT(rid <= msi->msi_alloc,
ed20d0e3 3119 ("MSI-X index too high"));
f9c942fb 3120 KASSERT(msi->msi_handlers > 0,
ed20d0e3 3121 ("MSI rid %d is not setup", rid));
f9c942fb
SZ
3122
3123 msi->msi_handlers--;
3124 if (msi->msi_handlers == 0)
4d28e78f
SZ
3125 pci_disable_msi(child);
3126 } else {
f9c942fb
SZ
3127 struct msix_vector *mv;
3128
4d28e78f 3129 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
f9c942fb
SZ
3130 ("No MSI or MSI-X rid %d allocated", rid));
3131
3132 mv = pci_find_msix_vector(child, rid);
3133 KASSERT(mv != NULL,
ed20d0e3 3134 ("MSI-X rid %d is not allocated", rid));
f9c942fb 3135 KASSERT(mv->mv_address != 0,
ed20d0e3 3136 ("MSI-X rid %d has not been setup", rid));
f9c942fb
SZ
3137
3138 pci_mask_msix_vector(child, PCI_MSIX_RID2VEC(rid));
3139 mv->mv_address = 0;
3140 mv->mv_data = 0;
984263bc
MD
3141 }
3142 }
4d28e78f
SZ
3143 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3144 if (rid > 0)
3145 KASSERT(error == 0,
3146 ("%s: generic teardown failed for MSI/MSI-X", __func__));
4d28e78f 3147 return (error);
984263bc
MD
3148}
3149
e126caf1 3150int
984263bc
MD
3151pci_print_child(device_t dev, device_t child)
3152{
3153 struct pci_devinfo *dinfo;
3154 struct resource_list *rl;
984263bc
MD
3155 int retval = 0;
3156
3157 dinfo = device_get_ivars(child);
984263bc
MD
3158 rl = &dinfo->resources;
3159
3160 retval += bus_print_child_header(dev, child);
3161
4d28e78f
SZ
3162 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3163 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3164 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
984263bc 3165 if (device_get_flags(dev))
85f8e2ea 3166 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 3167
85f8e2ea 3168 retval += kprintf(" at device %d.%d", pci_get_slot(child),
4d28e78f 3169 pci_get_function(child));
984263bc
MD
3170
3171 retval += bus_print_child_footer(dev, child);
3172
3173 return (retval);
3174}
3175
4d28e78f
SZ
3176static struct
3177{
3178 int class;
3179 int subclass;
3180 char *desc;
3181} pci_nomatch_tab[] = {
3182 {PCIC_OLD, -1, "old"},
3183 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3184 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3185 {PCIC_STORAGE, -1, "mass storage"},
3186 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3187 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3188 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3189 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3190 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3191 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3192 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3193 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3194 {PCIC_NETWORK, -1, "network"},
3195 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3196 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3197 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3198 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3199 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3200 {PCIC_DISPLAY, -1, "display"},
3201 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3202 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3203 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3204 {PCIC_MULTIMEDIA, -1, "multimedia"},
3205 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3206 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3207 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3208 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3209 {PCIC_MEMORY, -1, "memory"},
3210 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3211 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3212 {PCIC_BRIDGE, -1, "bridge"},
3213 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3214 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3215 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3216 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3217 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3218 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3219 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3220 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3221 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3222 {PCIC_SIMPLECOMM, -1, "simple comms"},
3223 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3224 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3225 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3226 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3227 {PCIC_BASEPERIPH, -1, "base peripheral"},
3228 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3229 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3230 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3231 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3232 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3233 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3234 {PCIC_INPUTDEV, -1, "input device"},
3235 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3236 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3237 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3238 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3239 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3240 {PCIC_DOCKING, -1, "docking station"},
3241 {PCIC_PROCESSOR, -1, "processor"},
3242 {PCIC_SERIALBUS, -1, "serial bus"},
3243 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3244 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3245 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3246 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3247 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3248 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3249 {PCIC_WIRELESS, -1, "wireless controller"},
3250 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3251 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3252 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3253 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3254 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3255 {PCIC_SATCOM, -1, "satellite communication"},
3256 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3257 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3258 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3259 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3260 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3261 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3262 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3263 {PCIC_DASP, -1, "dasp"},
3264 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3265 {0, 0, NULL}
3266};
3267
e126caf1 3268void
984263bc
MD
3269pci_probe_nomatch(device_t dev, device_t child)
3270{
4d28e78f
SZ
3271 int i;
3272 char *cp, *scp, *device;
984263bc 3273
4d28e78f
SZ
3274 /*
3275 * Look for a listing for this device in a loaded device database.
3276 */
3277 if ((device = pci_describe_device(child)) != NULL) {
3278 device_printf(dev, "<%s>", device);
3279 kfree(device, M_DEVBUF);
3280 } else {
3281 /*
3282 * Scan the class/subclass descriptions for a general
3283 * description.
3284 */
3285 cp = "unknown";
3286 scp = NULL;
3287 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3288 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3289 if (pci_nomatch_tab[i].subclass == -1) {
3290 cp = pci_nomatch_tab[i].desc;
3291 } else if (pci_nomatch_tab[i].subclass ==
3292 pci_get_subclass(child)) {
3293 scp = pci_nomatch_tab[i].desc;
3294 }
3295 }
3296 }
3297 device_printf(dev, "<%s%s%s>",
3298 cp ? cp : "",
3299 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3300 scp ? scp : "");
3301 }
6a45dbfa
SZ
3302 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3303 pci_get_vendor(child), pci_get_device(child),
3304 pci_get_slot(child), pci_get_function(child));
3305 if (pci_get_intpin(child) > 0) {
3306 int irq;
3307
3308 irq = pci_get_irq(child);
3309 if (PCI_INTERRUPT_VALID(irq))
3310 kprintf(" irq %d", irq);
3311 }
3312 kprintf("\n");
3313
638744c5 3314 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
3315}
3316
4d28e78f
SZ
3317/*
3318 * Parse the PCI device database, if loaded, and return a pointer to a
3319 * description of the device.
3320 *
3321 * The database is flat text formatted as follows:
3322 *
3323 * Any line not in a valid format is ignored.
3324 * Lines are terminated with newline '\n' characters.
3325 *
3326 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3327 * the vendor name.
3328 *
3329 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3330 * - devices cannot be listed without a corresponding VENDOR line.
3331 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3332 * another TAB, then the device name.
3333 */
3334
3335/*
3336 * Assuming (ptr) points to the beginning of a line in the database,
3337 * return the vendor or device and description of the next entry.
3338 * The value of (vendor) or (device) inappropriate for the entry type
3339 * is set to -1. Returns nonzero at the end of the database.
3340 *
3341 * Note that this is slightly unrobust in the face of corrupt data;
3342 * we attempt to safeguard against this by spamming the end of the
3343 * database with a newline when we initialise.
3344 */
3345static int
3346pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3347{
3348 char *cp = *ptr;
3349 int left;
3350
3351 *device = -1;
3352 *vendor = -1;
3353 **desc = '\0';
3354 for (;;) {
3355 left = pci_vendordata_size - (cp - pci_vendordata);
3356 if (left <= 0) {
3357 *ptr = cp;
3358 return(1);
3359 }
3360
3361 /* vendor entry? */
3362 if (*cp != '\t' &&
3363 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3364 break;
3365 /* device entry? */
3366 if (*cp == '\t' &&
3367 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3368 break;
3369
3370 /* skip to next line */
3371 while (*cp != '\n' && left > 0) {
3372 cp++;
3373 left--;
3374 }
3375 if (*cp == '\n') {
3376 cp++;
3377 left--;
3378 }
3379 }
3380 /* skip to next line */
3381 while (*cp != '\n' && left > 0) {
3382 cp++;
3383 left--;
3384 }
3385 if (*cp == '\n' && left > 0)
3386 cp++;
3387 *ptr = cp;
3388 return(0);
3389}
3390
3391static char *
3392pci_describe_device(device_t dev)
3393{
3394 int vendor, device;
3395 char *desc, *vp, *dp, *line;
3396
3397 desc = vp = dp = NULL;
3398
3399 /*
3400 * If we have no vendor data, we can't do anything.
3401 */
3402 if (pci_vendordata == NULL)
3403 goto out;
3404
3405 /*
3406 * Scan the vendor data looking for this device
3407 */
3408 line = pci_vendordata;
3409 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3410 goto out;
3411 for (;;) {
3412 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3413 goto out;
3414 if (vendor == pci_get_vendor(dev))
3415 break;
3416 }
3417 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3418 goto out;
3419 for (;;) {
3420 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3421 *dp = 0;
3422 break;
3423 }
3424 if (vendor != -1) {
3425 *dp = 0;
3426 break;
3427 }
3428 if (device == pci_get_device(dev))
3429 break;
3430 }
3431 if (dp[0] == '\0')
3432 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3433 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3434 NULL)
3435 ksprintf(desc, "%s, %s", vp, dp);
3436 out:
3437 if (vp != NULL)
3438 kfree(vp, M_DEVBUF);
3439 if (dp != NULL)
3440 kfree(dp, M_DEVBUF);
3441 return(desc);
3442}
3443
22457186 3444int
4a5a2d63 3445pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
3446{
3447 struct pci_devinfo *dinfo;
3448 pcicfgregs *cfg;
3449
3450 dinfo = device_get_ivars(child);
3451 cfg = &dinfo->cfg;
3452
3453 switch (which) {
4d28e78f
SZ
3454 case PCI_IVAR_ETHADDR:
3455 /*
3456 * The generic accessor doesn't deal with failure, so
3457 * we set the return value, then return an error.
3458 */
3459 *((uint8_t **) result) = NULL;
3460 return (EINVAL);
984263bc
MD
3461 case PCI_IVAR_SUBVENDOR:
3462 *result = cfg->subvendor;
3463 break;
3464 case PCI_IVAR_SUBDEVICE:
3465 *result = cfg->subdevice;
3466 break;
3467 case PCI_IVAR_VENDOR:
3468 *result = cfg->vendor;
3469 break;
3470 case PCI_IVAR_DEVICE:
3471 *result = cfg->device;
3472 break;
3473 case PCI_IVAR_DEVID:
3474 *result = (cfg->device << 16) | cfg->vendor;
3475 break;
3476 case PCI_IVAR_CLASS:
3477 *result = cfg->baseclass;
3478 break;
3479 case PCI_IVAR_SUBCLASS:
3480 *result = cfg->subclass;
3481 break;
3482 case PCI_IVAR_PROGIF:
3483 *result = cfg->progif;
3484 break;
3485 case PCI_IVAR_REVID:
3486 *result = cfg->revid;
3487 break;
3488 case PCI_IVAR_INTPIN:
3489 *result = cfg->intpin;
3490 break;
3491 case PCI_IVAR_IRQ:
3492 *result = cfg->intline;
3493 break;
4d28e78f
SZ
3494 case PCI_IVAR_DOMAIN:
3495 *result = cfg->domain;
3496 break;
984263bc
MD
3497 case PCI_IVAR_BUS:
3498 *result = cfg->bus;
3499 break;
3500 case PCI_IVAR_SLOT:
3501 *result = cfg->slot;
3502 break;
3503 case PCI_IVAR_FUNCTION:
3504 *result = cfg->func;
3505 break;
4d28e78f
SZ
3506 case PCI_IVAR_CMDREG:
3507 *result = cfg->cmdreg;
984263bc 3508 break;
4d28e78f
SZ
3509 case PCI_IVAR_CACHELNSZ:
3510 *result = cfg->cachelnsz;
984263bc 3511 break;
4d28e78f
SZ
3512 case PCI_IVAR_MINGNT:
3513 *result = cfg->mingnt;
c7e4e7eb 3514 break;
4d28e78f
SZ
3515 case PCI_IVAR_MAXLAT:
3516 *result = cfg->maxlat;
c7e4e7eb 3517 break;
4d28e78f
SZ
3518 case PCI_IVAR_LATTIMER:
3519 *result = cfg->lattimer;
0254566f 3520 break;
d85e7311
SZ
3521 case PCI_IVAR_PCIXCAP_PTR:
3522 *result = cfg->pcix.pcix_ptr;
3523 break;
3524 case PCI_IVAR_PCIECAP_PTR:
3525 *result = cfg->expr.expr_ptr;
3526 break;
3527 case PCI_IVAR_VPDCAP_PTR:
3528 *result = cfg->vpd.vpd_reg;
3529 break;
984263bc 3530 default:
4d28e78f 3531 return (ENOENT);
984263bc 3532 }
4d28e78f 3533 return (0);
984263bc
MD
3534}
3535
22457186 3536int
984263bc
MD
3537pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3538{
3539 struct pci_devinfo *dinfo;
984263bc
MD
3540
3541 dinfo = device_get_ivars(child);
984263bc
MD
3542
3543 switch (which) {
4d28e78f
SZ
3544 case PCI_IVAR_INTPIN:
3545 dinfo->cfg.intpin = value;
3546 return (0);
3547 case PCI_IVAR_ETHADDR:
984263bc
MD
3548 case PCI_IVAR_SUBVENDOR:
3549 case PCI_IVAR_SUBDEVICE:
3550 case PCI_IVAR_VENDOR:
3551 case PCI_IVAR_DEVICE:
3552 case PCI_IVAR_DEVID:
3553 case PCI_IVAR_CLASS:
3554 case PCI_IVAR_SUBCLASS:
3555 case PCI_IVAR_PROGIF:
3556 case PCI_IVAR_REVID:
984263bc 3557 case PCI_IVAR_IRQ:
4d28e78f 3558 case PCI_IVAR_DOMAIN:
984263bc
MD
3559 case PCI_IVAR_BUS:
3560 case PCI_IVAR_SLOT:
3561 case PCI_IVAR_FUNCTION:
4d28e78f 3562 return (EINVAL); /* disallow for now */
984263bc 3563
984263bc 3564 default:
4d28e78f
SZ
3565 return (ENOENT);
3566 }
3567}
3568#ifdef notyet
3569#include "opt_ddb.h"
3570#ifdef DDB
3571#include <ddb/ddb.h>
3572#include <sys/cons.h>
3573
3574/*
3575 * List resources based on pci map registers, used for within ddb
3576 */
3577
3578DB_SHOW_COMMAND(pciregs, db_pci_dump)
3579{
3580 struct pci_devinfo *dinfo;
3581 struct devlist *devlist_head;
3582 struct pci_conf *p;
3583 const char *name;
3584 int i, error, none_count;
3585
3586 none_count = 0;
3587 /* get the head of the device queue */
3588 devlist_head = &pci_devq;
3589
3590 /*
3591 * Go through the list of devices and print out devices
3592 */
3593 for (error = 0, i = 0,
3594 dinfo = STAILQ_FIRST(devlist_head);
3595 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3596 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3597
3598 /* Populate pd_name and pd_unit */
3599 name = NULL;
3600 if (dinfo->cfg.dev)
3601 name = device_get_name(dinfo->cfg.dev);
3602
3603 p = &dinfo->conf;
3604 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3605 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3606 (name && *name) ? name : "none",
3607 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3608 none_count++,
3609 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3610 p->pc_sel.pc_func, (p->pc_class << 16) |
3611 (p->pc_subclass << 8) | p->pc_progif,
3612 (p->pc_subdevice << 16) | p->pc_subvendor,
3613 (p->pc_device << 16) | p->pc_vendor,
3614 p->pc_revid, p->pc_hdr);
984263bc 3615 }
984263bc 3616}
4d28e78f
SZ
3617#endif /* DDB */
3618#endif
984263bc 3619
201eb0a7 3620static struct resource *
4d28e78f
SZ
3621pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3622 u_long start, u_long end, u_long count, u_int flags)
201eb0a7
TS
3623{
3624 struct pci_devinfo *dinfo = device_get_ivars(child);
3625 struct resource_list *rl = &dinfo->resources;
3626 struct resource_list_entry *rle;
3627 struct resource *res;
4d28e78f 3628 pci_addr_t map, testval;
201eb0a7
TS
3629 int mapsize;
3630
3631 /*
3632 * Weed out the bogons, and figure out how large the BAR/map
4d28e78f 3633 * is. Bars that read back 0 here are bogus and unimplemented.
201eb0a7 3634 * Note: atapci in legacy mode are special and handled elsewhere
4d28e78f 3635 * in the code. If you have a atapci device in legacy mode and
201eb0a7
TS
3636 * it fails here, that other code is broken.
3637 */
3638 res = NULL;
3639 map = pci_read_config(child, *rid, 4);
3640 pci_write_config(child, *rid, 0xffffffff, 4);
3641 testval = pci_read_config(child, *rid, 4);
4d28e78f
SZ
3642 if (pci_maprange(testval) == 64)
3643 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
201eb0a7
TS
3644 if (pci_mapbase(testval) == 0)
3645 goto out;
4d28e78f
SZ
3646
3647 /*
3648 * Restore the original value of the BAR. We may have reprogrammed
3649 * the BAR of the low-level console device and when booting verbose,
3650 * we need the console device addressable.
3651 */
3652 pci_write_config(child, *rid, map, 4);
3653
3654 if (PCI_BAR_MEM(testval)) {
201eb0a7
TS
3655 if (type != SYS_RES_MEMORY) {
3656 if (bootverbose)
4d28e78f
SZ
3657 device_printf(dev,
3658 "child %s requested type %d for rid %#x,"
3659 " but the BAR says it is an memio\n",
3660 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3661 goto out;
3662 }
3663 } else {
3664 if (type != SYS_RES_IOPORT) {
3665 if (bootverbose)
4d28e78f
SZ
3666 device_printf(dev,
3667 "child %s requested type %d for rid %#x,"
3668 " but the BAR says it is an ioport\n",
3669 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3670 goto out;
3671 }
3672 }
3673 /*
3674 * For real BARs, we need to override the size that
3675 * the driver requests, because that's what the BAR
3676 * actually uses and we would otherwise have a
3677 * situation where we might allocate the excess to
3678 * another driver, which won't work.
3679 */
3680 mapsize = pci_mapsize(testval);
4d28e78f 3681 count = 1UL << mapsize;
201eb0a7 3682 if (RF_ALIGNMENT(flags) < mapsize)
4d28e78f
SZ
3683 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3684 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3685 flags |= RF_PREFETCHABLE;
3686
201eb0a7
TS
3687 /*
3688 * Allocate enough resource, and then write back the
4d28e78f 3689 * appropriate bar for that resource.
201eb0a7
TS
3690 */
3691 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4f7fe8c7 3692 start, end, count, flags, -1);
201eb0a7 3693 if (res == NULL) {
4d28e78f
SZ
3694 device_printf(child,
3695 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3696 count, *rid, type, start, end);
201eb0a7
TS
3697 goto out;
3698 }
1b000e91 3699 resource_list_add(rl, type, *rid, start, end, count, -1);
201eb0a7
TS
3700 rle = resource_list_find(rl, type, *rid);
3701 if (rle == NULL)
3702 panic("pci_alloc_map: unexpectedly can't find resource.");
3703 rle->res = res;
3704 rle->start = rman_get_start(res);
3705 rle->end = rman_get_end(res);
3706 rle->count = count;
3707 if (bootverbose)
4d28e78f
SZ
3708 device_printf(child,
3709 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3710 count, *rid, type, rman_get_start(res));
201eb0a7
TS
3711 map = rman_get_start(res);
3712out:;
3713 pci_write_config(child, *rid, map, 4);
4d28e78f
SZ
3714 if (pci_maprange(testval) == 64)
3715 pci_write_config(child, *rid + 4, map >> 32, 4);
3716 return (res);
201eb0a7 3717}
4d28e78f 3718
201eb0a7 3719
261fa16d 3720struct resource *
984263bc 3721pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4f7fe8c7 3722 u_long start, u_long end, u_long count, u_int flags, int cpuid)
984263bc
MD
3723{
3724 struct pci_devinfo *dinfo = device_get_ivars(child);
3725 struct resource_list *rl = &dinfo->resources;
201eb0a7 3726 struct resource_list_entry *rle;
984263bc 3727 pcicfgregs *cfg = &dinfo->cfg;
09e7d9f3 3728
984263bc
MD
3729 /*
3730 * Perform lazy resource allocation
984263bc
MD
3731 */
3732 if (device_get_parent(child) == dev) {
de67e43b
JS
3733 switch (type) {
3734 case SYS_RES_IRQ:
4d28e78f
SZ
3735 /*
3736 * Can't alloc legacy interrupt once MSI messages
3737 * have been allocated.
3738 */
4d28e78f
SZ
3739 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3740 cfg->msix.msix_alloc > 0))
3741 return (NULL);
4d28e78f
SZ
3742 /*
3743 * If the child device doesn't have an
3744 * interrupt routed and is deserving of an
3745 * interrupt, try to assign it one.
3746 */
3747 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3748 (cfg->intpin != 0))
3749 pci_assign_interrupt(dev, child, 0);
3750 break;
de67e43b
JS
3751 case SYS_RES_IOPORT:
3752 case SYS_RES_MEMORY:
3753 if (*rid < PCIR_BAR(cfg->nummaps)) {
3754 /*
3755 * Enable the I/O mode. We should
3756 * also be assigning resources too
3757 * when none are present. The
3758 * resource_list_alloc kind of sorta does
3759 * this...
3760 */
3761 if (PCI_ENABLE_IO(dev, child, type))
3762 return (NULL);
984263bc 3763 }
201eb0a7
TS
3764 rle = resource_list_find(rl, type, *rid);
3765 if (rle == NULL)
4d28e78f
SZ
3766 return (pci_alloc_map(dev, child, type, rid,
3767 start, end, count, flags));
820c1612 3768 break;
984263bc 3769 }
201eb0a7
TS
3770 /*
3771 * If we've already allocated the resource, then
4d28e78f 3772 * return it now. But first we may need to activate
201eb0a7 3773 * it, since we don't allocate the resource as active
4d28e78f 3774 * above. Normally this would be done down in the
201eb0a7 3775 * nexus, but since we short-circuit that path we have
4d28e78f 3776 * to do its job here. Not sure if we should kfree the
201eb0a7 3777 * resource if it fails to activate.
201eb0a7
TS
3778 */
3779 rle = resource_list_find(rl, type, *rid);
3780 if (rle != NULL && rle->res != NULL) {
3781 if (bootverbose)
4d28e78f
SZ
3782 device_printf(child,
3783 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3784 rman_get_size(rle->res), *rid, type,
3785 rman_get_start(rle->res));
201eb0a7
TS
3786 if ((flags & RF_ACTIVE) &&
3787 bus_generic_activate_resource(dev, child, type,
4d28e78f
SZ
3788 *rid, rle->res) != 0)
3789 return (NULL);
3790 return (rle->res);
201eb0a7 3791 }
984263bc 3792 }
4d28e78f 3793 return (resource_list_alloc(rl, dev, child, type, rid,
4f7fe8c7 3794 start, end, count, flags, cpuid));
984263bc
MD
3795}
3796
4d28e78f
SZ
3797void
3798pci_delete_resource(device_t dev, device_t child, int type, int rid)
984263bc 3799{
4d28e78f
SZ
3800 struct pci_devinfo *dinfo;
3801 struct resource_list *rl;
984263bc
MD
3802 struct resource_list_entry *rle;
3803
4d28e78f
SZ
3804 if (device_get_parent(child) != dev)
3805 return;
984263bc 3806
4d28e78f
SZ
3807 dinfo = device_get_ivars(child);
3808 rl = &dinfo->resources;
3809 rle = resource_list_find(rl, type, rid);
3810 if (rle) {
3811 if (rle->res) {
3812 if (rman_get_device(rle->res) != dev ||
3813 rman_get_flags(rle->res) & RF_ACTIVE) {
3814 device_printf(dev, "delete_resource: "
3815 "Resource still owned by child, oops. "
3816 "(type=%d, rid=%d, addr=%lx)\n",
3817 rle->type, rle->rid,
3818 rman_get_start(rle->res));
3819 return;
3820 }
3821 bus_release_resource(dev, type, rid, rle->res);
3822 }
3823 resource_list_delete(rl, type, rid);
3824 }
3825 /*
3826 * Why do we turn off the PCI configuration BAR when we delete a
3827 * resource? -- imp
3828 */
3829 pci_write_config(child, rid, 0, 4);
3830 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
984263bc
MD
3831}
3832
e126caf1
MD
3833struct resource_list *
3834