gold: Fix hardcoded library search path
[dragonfly.git] / sys / dev / netif / rdp / if_rdpreg.h
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1#ifndef IF_RDPREG_H
2#define IF_RDPREG_H 1
3/*
4 * Copyright (c) 1998 Joerg Wunsch
5 *
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE DEVELOPERS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/i386/isa/if_rdpreg.h,v 1.2 1999/08/28 00:44:49 peter Exp $
a9295349 29 * $DragonFly: src/sys/dev/netif/rdp/if_rdpreg.h,v 1.4 2006/11/07 06:43:23 dillon Exp $
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30 */
31
32/*
33 * Part of the definitions here has been copied over from the REDP
34 * packet driver's REDPPD.INC file. This provides us with the same
35 * set of acronyms as the packet driver is using.
36 *
37 * The packet driver had no copyright, and is believed to be in the
38 * public domain. The author seems to be someone who calls himself
39 * "Chiu", so that's the only acknowledgment i can give here.
40 * Supposedly the author was someone from RealTek.
41 */
42
43/*
44 * We're hanging upon an LPT port, thus suck in the lpt defs as well.
45 */
a9295349 46#include <machine_base/isa/lptreg.h>
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47
48struct rdphdr {
49 /* RTL8002 header that is prepended to the actual packet */
50 u_char unused2[2];
51 u_short pktlen;
52 u_char status; /* copy of RSR for this packet */
53 u_char unused3[3];
54};
55
56/*
57 *
58 * 8 Data Modes are provided:
59 *
60 * +--------+---------------+-------------+
61 * | Mode | Read | Write |
62 * +--------+---------------+-------------+
63 * | 0 | LptCtrl | LptData |
64 * +--------+---------------+-------------+
65 * | 1 | LptCtrl | LptCtrl |
66 * +--------+---------------+-------------+
67 * | 2 | LptCtrl*2 | LptData |
68 * +--------+---------------+-------------+
69 * | 3 | LptCtrl*2 | LptCtrl |
70 * +--------+---------------+-------------+
71 * | 4 | LptData | LptData |
72 * +--------+---------------+-------------+
73 * | 5 | LptData | LptCtrl |
74 * +--------+---------------+-------------+
75 * | 6 | LptData*2 | LptData |
76 * +--------+---------------+-------------+
77 * | 7 | LptData*2 | LptCtrl |
78 * +--------+---------------+-------------+
79 *
80 * Right now, this driver only implements mode 0 (which ought to work
81 * on any standard parallel interface).
82 *
83 */
84
85/*
86 * Page 0 of EPLC registers
87 */
88#define IDR0 0x00 /* Ethernet ID register (R/W) */
89#define IDR1 0x01
90#define IDR2 0x02
91#define IDR3 0x03
92#define IDR4 0x04
93#define IDR5 0x05
94#define TBCR0 0x06 /* transmit byte count (W), 11 bits valid */
95#define TBCR1 0x07
96#define TSR 0x08 /* transmit status (R), cleared upon next tx */
97# define TSR_TOK 1 /* transmit OK */
98# define TSR_TABT 2 /* transmit aborted (excessive collisions) */
99# define TSR_COL 4 /* collision detected */
100# define TSR_CDH 8 /* CD heartbeat detected */
101#define RSR 0x09 /*
102 * receiver status (R), cleared upon next
103 * received packet (but stored in rx buffer
104 * header anyway)
105 */
106# define RSR_ROK 1 /* receive OK */
107# define RSR_CRC 2 /* CRC error */
108# define RSR_FA 4 /* frame alignment error (not multiple of 8) */
109# define RSR_BUFO 0x10 /* rx buffer overflow, packet discarded */
110# define RSR_PUN 0x20 /* packet count underflow (jump command issued
111 * but rx buffer was empty) */
112# define RSR_POV 0x40 /* packet count overflow (more than 254 (?)
113 * packets still in buffer) */
114#define ISR 0x0A /* interrupt status register (R), writing
115 * clears the written bits */
116# define ISR_TOK 1 /* transmission OK (~ TSR_TOK) */
117# define ISR_TER 2 /* transmitter error (~ TSR_TABT) */
118# define ISR_ROK 4 /* receive OK (~ RSR_ROK) */
119# define ISR_RER 8 /* receiver error (~ RSR_CRC|RSR_FA) */
120# define ISR_RBER 0x10 /* rx buffer overflow (POV|PUN|BUFO) */
121#define IMR 0x0B /* interrupt mask register (R/W), bit as ISR */
122#define CMR1 0x0C /* command register 1 (R/W) */
123# define CMR1_BUFE 1 /* (R) rx buffer empty */
124# define CMR1_IRQ 2 /* (R) interrupt request */
125# define CMR1_TRA 4 /* (R) transmission in progress */
126 /* (W) transmit start */
127# define CMR1_TE 0x10 /* (R/W) transmitter enable */
128# define CMR1_RE 0x20 /* (R/W) receiver enable */
129# define CMR1_RST 0x40 /* (R/W) reset; sticks until reset completed */
130# define CMR1_RDPAC 1 /* (W) `rx jump packet', prepare for reading
131 * next packet from ring buffer */
132# define CMR1_WRPAC 2 /* (W) `tx jump packet', packet in tx buffer
133 * is complete and can be sent */
134# define CMR1_RETX 8 /* (W) retransmit (must be accomp'ed by TRA) */
135# define CMR1_MUX 0x80 /* (W) RTL8012: tell the printer MUX to
136 * connect the output pins to the host */
137#define CMR2 0x0D /* command register 2 (R/W) */
138# define CMR2_IRQOUT 1 /* interrupt signal output enabled */
139# define CMR2_RAMTST 2 /* enable RAM test */
140# define CMR2_PAGE 4 /* select register page #1 */
141# define CMR2_IRQINV 8 /* make active IRQ `low' */
142# define CMR2_AMbits 0x30 /* address mode bits: */
143# define CMR2_AM_NONE 0x00 /* 0: accept nothing */
144# define CMR2_AM_PHYS 0x10 /* 1: only physical addr */
145# define CMR2_AM_PB 0x20 /* 2: phys + broadcast */
146# define CMR2_AM_ALL 0x30 /* 3: promiscuous */
147# define CMR2_LBK 0x40 /* enable loopback */
148# define CMR2_SER 0x80 /* save error packet */
149#define MAR 0x0E /* memory access register (?), used for
150 * remote DMA to the 8002's buffer */
151#define PNR TBCR0 /* received packet number (R) */
152#define COLR TBCR1 /* collision count (R) (4 bit valid) */
153
154/*
155 * Page 1 of EPLC registers -- EEPROM control
156 */
157#define PCMR TBCR0 /* port command register */
158/* bits for 93C46 control -- add HNib */
159#define PCMR_SK 0x04 /* serial clock for EEPROM */
160#define PCMR_CS 0x02 /* chip select for EEPROM */
161#define PCMR_DO 0x01 /* DI to EEPROM */
162
163/* EEPROM data, nibbles for 74S288, bits for 93C46 */
164#define PDR TBCR1 /* DO from EEPROM, only bit 0 valid for
165 * serial EEPROM */
166
167/*
168 * The following definitionss define remote DMA command through LptCtrl
169 */
170#define ATFD 3 /* ATFD bit in Lpt's Control register */
171 /* -> ATFD bit is added for Xircom's MUX */
172#define Ctrl_LNibRead (0x08+ATFD) /* specify low nibble */
173#define Ctrl_HNibRead (0+ATFD) /* specify high nibble */
174#define Ctrl_SelData (0x04+ATFD) /* not through LptCtrl but through */
175 /* LptData */
176#define Ctrl_IRQEN 0x10 /* set IRQEN of lpt control register */
177
178/* Here define constants to construct the required read/write commands */
179#define WrAddr 0x40 /* set address of EPLC write register */
180#define RdAddr 0x0C0 /* set address of EPLC read register */
181#define EOR 0x20 /* ORed to make 'end of read',set CSB=1 */
182#define EOW 0x0E0 /* end of write, R/WB=A/DB=CSB=1 */
183#define EOC 0x0E0 /* End Of r/w Command, R/WB=A/DB=CSB=1 */
184#define HNib 0x10
185
186#define MkHi(value) (((value) >> 4) | HNib)
187
188#endif /* IF_RDPREG_H */