gold: Fix hardcoded library search path
[dragonfly.git] / sys / dev / netif / wl / if_wl.h
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1/*
2 * Redistribution and use in source and binary forms, with or without
3 * modification, are permitted provided that the following conditions
4 * are met:
5 * 1. Redistributions of source code must retain all copyright
6 * notices, this list of conditions and the following disclaimer.
7 * 2. The names of the authors may not be used to endorse or promote products
4d9022e3 8 * derived from this software without specific prior written permission
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9 *
10 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
13 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
16 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
17 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * $FreeBSD: src/sys/i386/isa/if_wl.h,v 1.2.6.1 2000/08/03 01:01:20 peter Exp $
16107627 22 * $DragonFly: src/sys/dev/netif/wl/if_wl.h,v 1.3 2005/07/07 15:15:24 joerg Exp $
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23 */
24/* Definitions for WaveLAN driver */
25
26#ifndef _IF_WL_H
27#define _IF_WL_H
28
29#define STATUS_TRIES 15000
30
31#define N_FD 100
32#define N_RBD 100
33#define N_TBD 72
34#define RCVBUFSIZE 540
35#define I82586NULL 0xffff
36
37#define DSF_RUNNING 1
38
39#define MOD_ENAL 1
40#define MOD_PROM 2
41
42typedef struct {
43 rbd_t r;
44 char rbd_pad[2];
45 char rbuffer[RCVBUFSIZE];
46} ru_t;
47
48/* Board 64k RAM layout. Offsets from 0x0000 */
49
50#define OFFSET_RU 0x0000 /* 0x64 * fd_t = 0x898 */
51#define OFFSET_RBD 0x0900 /* 0x64 * ru_t = 0xd7a0 */
52#define OFFSET_CU 0xe0a0 /* 0x100 */
53#define OFFSET_TBD 0xe1a0 /* 0x48 * tbd_t = 0x240 */
54#define OFFSET_TBUF 0xe3e0 /* 0x1bfe */
55#define OFFSET_SCB 0xffde /* 0x1 * scb_t = 0x10 */
56#define OFFSET_ISCP 0xffee /* 0x1 * iscp_t = 0x8 */
57#define OFFSET_SCP 0xfff6 /* 0x1 * scp_t = 0xa */
58
59/* WaveLAN host interface definitions */
60
61#define HACR(base) (base) /* Host Adapter Command Register */
62#define HASR(base) (base) /* Host Adapter Status Register */
63#define MMCR(base) (base+0x2) /* Modem Management Ctrl Register */
64#define PIOR0(base) (base+0x4) /* Program I/O Address Register 0 */
65#define PIOP0(base) (base+0x6) /* Program I/O Port 0 */
66#define PIOR1(base) (base+0x8) /* Program I/O Address Register 1 */
67#define PIOP1(base) (base+0xa) /* Program I/O Port 1 */
68#define PIOR2(base) (base+0xc) /* Program I/O Address Register 2 */
69#define PIOP2(base) (base+0xe) /* Program I/O Port 2 */
70
71/* Program I/O Mode Register values */
72
73#define STATIC_PIO 0 /* Mode 1: static mode */
74#define AUTOINCR_PIO 1 /* Mode 2: auto increment mode */
75#define AUTODECR_PIO 2 /* Mode 3: auto decrement mode */
76#define PARAM_ACCESS_PIO 3 /* Mode 4: LAN parameter access mode */
77#define PIO_MASK 3 /* register mask */
78#define PIOM(cmd,piono) ((u_short)cmd << 10 << (piono * 2))
79
80/* Host Adapter status register definitions */
81
82#define HASR_INTR 0x0001 /* Interrupt request from 82586 */
83#define HASR_MMC_INTR 0x0002 /* Interrupt request from MMC */
84#define HASR_MMC_BUSY 0x0004 /* MMC busy indication */
85#define HASR_PARA_BUSY 0x0008 /* LAN parameter storage area busy */
86
87/* Host Adapter command register definitions */
88
89#define HACR_RESET 0x0001 /* Reset board */
90#define HACR_CA 0x0002 /* Set Channel Attention for 82586 */
91#define HACR_16BITS 0x0004 /* 1==16 bits operation, 0==8 bits */
92#define HACR_OUT1 0x0008 /* General purpose output pin */
93#define HACR_OUT2 0x0010 /* General purpose output pin */
94#define HACR_MASK_82586 0x0020 /* Mask 82586 interrupts, 1==unmask */
95#define HACR_MASK_MMC 0x0040 /* Mask MMC interrupts, 1==unmask */
96#define HACR_INTR_CLEN 0x0080 /* interrupt status clear enable */
97
98#define HACR_DEFAULT (HACR_OUT1 | HACR_OUT2 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2))
99#define HACR_INTRON (HACR_MASK_82586 | HACR_MASK_MMC | HACR_INTR_CLEN)
16107627 100#define CMD(sc) \
984263bc 101 { \
16107627 102 outw(HACR((sc)->base),(sc)->hacr); \
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103 /* delay for 50 us, might only be needed sometimes */ \
104 DELAY(DELAYCONST); \
105 }
106
107/* macro for setting the channel attention bit. No delays here since
108 * it is used in critical sections
109 */
16107627 110#define SET_CHAN_ATTN(sc) \
984263bc 111 { \
16107627 112 outw(HACR((sc)->base),(sc)->hacr | HACR_CA); \
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113 }
114
115
116#define MMC_WRITE(cmd,val) \
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117 while(inw(HASR((sc)->base)) & HASR_MMC_BUSY) ; \
118 outw(MMCR((sc)->base), \
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119 (u_short)(((u_short)(val) << 8) | ((cmd) << 1) | 1))
120
121#endif /* _IF_WL_H */