gold: Fix hardcoded library search path
[dragonfly.git] / sys / dev / serial / rc / rcreg.h
CommitLineData
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1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/i386/isa/rcreg.h,v 1.3.12.1 2000/08/03 01:01:20 peter Exp $
1de703da 28 * $DragonFly: src/sys/dev/serial/rc/rcreg.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
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29 */
30
31/*
32 * Cirrus Logic CD180 -based RISCom/8 board definitions
33 */
34
35/* Oscillator frequency - 19660.08Mhz / 2 */
36#define RC_OSCFREQ 9830400
37
38#define RC_BRD(s) ((s) == 0 ? 0 : \
39 (((RC_OSCFREQ + (s) / 2) / (s)) + CD180_CTICKS/2) / CD180_CTICKS)
40
41#define RC_VALIDADDR(a) ( (a) == 0x220 || (a) == 0x240 || (a) == 0x250 \
42 || (a) == 0x260 || (a) == 0x2A0 || (a) == 0x2B0 \
43 || (a) == 0x300 || (a) == 0x320)
44
45#define RC_VALIDIRQ(i) ((i) < 16 && \
46 "\0\0\0\1\1\1\0\1\0\0\1\1\1\0\0\1"[(i) & 0xF])
47
48/* Riscom/8 board ISA I/O mapping */
49#define RC_IOMAP(r) ((((r) & 07) << 1) | (((r) & ~07) << 7))
50
51/* I/O commands */
52#define RC_OUT(p,i,d) outb(RC_IOMAP(i) + (p), (d))
53#define RC_IN(p,i) inb (RC_IOMAP(i) + (p))
54
55/* Riscom on-board registers (mapping assumed) */
56#define RC_RIREG 0x100 /* Ring Indicator Register (read-only) */
57#define RC_DTREG 0x100 /* DTR Register (write-only) */
58#define RC_BSR 0x101 /* Board Status Register (read-only) */
59#define RC_CTOUT 0x101 /* Clear Timeout (write-only) */
60
61/* Board Status Register */
62#define RC_BSR_TOUT 0x08 /* Timeout */
63#define RC_BSR_RXINT 0x04 /* Receiver Interrupt */
64#define RC_BSR_TXINT 0x02 /* Transmitter Interrupt */
65#define RC_BSR_MOINT 0x01 /* Modem Control Interrupt */
66
67/* Interrupt groups */
68#define RC_MODEMGRP 0x01 /* Modem interrupt group */
69#define RC_RXGRP 0x02 /* Receiver interrupt group */
70#define RC_TXGRP 0x04 /* Transmitter interrupt group */
71
72/* Priority Interrupt Level definitions */
73#define RC_PILR_MODEM (0x80 | RC_MODEMGRP)
74#define RC_PILR_RX (0x80 | RC_RXGRP )
75#define RC_PILR_TX (0x80 | RC_TXGRP )