projects / dragonfly.git / blame
| Commit | Line | Data |
|---|---|---|
| 984263bc MD |
1 | /* |
| 2 | * | |
| 3 | * Copyright (C) 1994, Paul S. LaFollette, Jr. This software may be used, | |
| 4 | * modified, copied, distributed, and sold, in both source and binary form | |
| 5 | * provided that the above copyright and these terms are retained. Under | |
| 6 | * no circumstances is the author responsible for the proper functioning | |
| 7 | * of this software, nor does the author assume any responsibility | |
| 8 | * for damages incurred with its use | |
| 9 | * | |
| 10 | * $FreeBSD: src/sys/i386/isa/ctxreg.h,v 1.5 1999/08/28 00:44:39 peter Exp $ | |
| f8334305 | 11 | * $DragonFly: src/sys/dev/video/ctx/ctxreg.h,v 1.3 2006/10/23 21:50:32 dillon Exp $ |
| 984263bc MD |
12 | */ |
| 13 | ||
| 14 | /* | |
| 15 | * Register and bit definitions for CORTEX-I frame grabber | |
| 16 | */ | |
| 17 | ||
| f8334305 MD |
18 | #ifndef _DEV_VIDEO_CTX_CTXREG_H_ |
| 19 | #define _DEV_VIDEO_CTX_CTXREG_H_ | |
| 984263bc MD |
20 | |
| 21 | /* Control Ports (all are write-only) */ | |
| 22 | ||
| 23 | #define ctx_cp0 0 /* offset to control port 0 */ | |
| 24 | #define ctx_cp1 1 /* offset to control port 1 */ | |
| 25 | #define ctx_lutaddr 2 /* offset to lut address port */ | |
| 26 | #define ctx_lutdata 3 /* offset to lut data port */ | |
| 27 | ||
| 28 | /* Status port (read-only but same address as control port 0) */ | |
| 29 | ||
| 30 | #define ctx_status 0 /* offset to status port */ | |
| 31 | ||
| 32 | /* Bit assignments for control port 0 */ | |
| 33 | ||
| 34 | #define PAGE_SELECT0 1 /* These two bits choose which 1/4 of the */ | |
| 35 | #define PAGE_SELECT1 2 /* video memory is accessible to us. */ | |
| 36 | #define PAGE_ROTATE 4 /* 0 => horizontal access. 1 => vertical */ | |
| 37 | #define ACQUIRE 8 /* set to start frame grab */ | |
| 38 | #define SEE_STORED_VIDEO 16 /* set to allow stored frame to be seen */ | |
| 39 | #define LOW_RESOLUTION 32 /* set to enable 256 x 256 mode */ | |
| 40 | ||
| 41 | /* Bit assignments for control port 1 */ | |
| 42 | ||
| 43 | #define INTERRUPT_ENABLE 1 /* Allow interrupts (we avoid this bit) */ | |
| 44 | #define TRIGGER_ENABLE 2 /* Enable external trigger for frame grab */ | |
| 45 | #define LUT_LOAD_ENABLE 4 /* Allow loading of lookup table */ | |
| 46 | #define BLANK_DISPLAY 8 /* Turn off display */ | |
| 47 | #define AB_SELECT 16 /* Along with HW switch, choose base memory */ | |
| 48 | #define RAM_ENABLE 32 /* Connect video RAM to computer bus */ | |
| 49 | ||
| 50 | /* Bit assignments for status port */ | |
| 51 | ||
| 52 | #define INTERRUPT_STATUS 1 /* Ignored by us */ | |
| 53 | #define ADC_OVERFLOW 2 /* Set if any pixes from camera "too bright"*/ | |
| 54 | #define FIELD 4 /* 0 or 1 shows which interlace field are in*/ | |
| 55 | #define VERTICAL_BLANK 8 /* 1 if in vertical blanking interval */ | |
| 56 | #define TRIGGERED 16 /* 1 if HW trigger contacts closed */ | |
| 57 | #define ACQUIRING_ACK 32 /* 1 if currently grabbing a frame */ | |
| 58 | ||
| 59 | ||
| f8334305 | 60 | #endif /* ifndef _DEV_VIDEO_CTX_CTXREG_H_ */ |