bnx: Group interrupt related fields together
[dragonfly.git] / sys / dev / netif / bnx / if_bnxvar.h
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
35 */
36
37#ifndef _IF_BNXVAR_H_
38#define _IF_BNXVAR_H_
39
40/*
41 * Tigon general information block. This resides in host memory
42 * and contains the status counters, ring control blocks and
43 * producer pointers.
44 */
45
46struct bnx_gib {
47 struct bge_stats bnx_stats;
48 struct bge_rcb bnx_tx_rcb[16];
49 struct bge_rcb bnx_std_rx_rcb;
50 struct bge_rcb bnx_jumbo_rx_rcb;
51 struct bge_rcb bnx_mini_rx_rcb;
52 struct bge_rcb bnx_return_rcb;
53};
54
55#define BNX_MIN_FRAMELEN 60
56#define BNX_MAX_FRAMELEN 1536
57#define BNX_JUMBO_FRAMELEN 9018
58#define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
59
60#define BNX_TIMEOUT 5000
61#define BNX_FIRMWARE_TIMEOUT 100000
62#define BNX_TXCONS_UNSET 0xFFFF /* impossible value */
63
64/*
65 * Other utility macros.
66 */
67#define BNX_INC(x, y) (x) = ((x) + 1) % (y)
68
69/*
70 * Register access macros. The Tigon always uses memory mapped register
71 * accesses and all registers must be accessed with 32 bit operations.
72 */
73
74#define CSR_WRITE_4(sc, reg, val) \
75 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
76
77#define CSR_READ_4(sc, reg) \
78 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
79
80#define BNX_SETBIT(sc, reg, x) \
81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
82
83#define BNX_CLRBIT(sc, reg, x) \
84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
85
86#define BNX_MEMWIN_READ(sc, x, val) \
87do { \
88 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
89 (0xFFFF0000 & x), 4); \
90 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
91} while(0)
92
93#define BNX_MEMWIN_WRITE(sc, x, val) \
94do { \
95 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
96 (0xFFFF0000 & x), 4); \
97 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
98} while(0)
99
100#define RCB_WRITE_4(sc, rcb, offset, val) \
101 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \
102 rcb + offsetof(struct bge_rcb, offset), val)
103
104/*
105 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
106 * values are tuneable. They control the actual amount of buffers
107 * allocated for the standard, mini and jumbo receive rings.
108 */
109
110#define BNX_SSLOTS 256
111#define BNX_MSLOTS 256
112#define BNX_JSLOTS 384
113
114#define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN)
115#define BNX_JLEN (BNX_JRAWLEN + \
116 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t)))
117#define BNX_JPAGESZ PAGE_SIZE
118#define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ)
119#define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID)
120
121struct bnx_softc;
122
123struct bnx_jslot {
124 struct bnx_softc *bnx_sc;
125 void *bnx_buf;
126 bus_addr_t bnx_paddr;
127 int bnx_inuse;
128 int bnx_slot;
129 SLIST_ENTRY(bnx_jslot) jslot_link;
130};
131
132/*
133 * Ring structures. Most of these reside in host memory and we tell
134 * the NIC where they are via the ring control blocks. The exceptions
135 * are the tx and command rings, which live in NIC memory and which
136 * we access via the shared memory window.
137 */
138struct bnx_ring_data {
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139 struct bge_rx_bd *bnx_rx_jumbo_ring;
140 bus_addr_t bnx_rx_jumbo_ring_paddr;
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141 struct bge_status_block *bnx_status_block;
142 bus_addr_t bnx_status_block_paddr;
143 void *bnx_jumbo_buf;
144 struct bnx_gib bnx_info;
145};
146
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147struct bnx_rx_buf {
148 bus_dmamap_t bnx_rx_dmamap;
149 struct mbuf *bnx_rx_mbuf;
150 bus_addr_t bnx_rx_paddr;
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151};
152
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153struct bnx_rx_std_ring {
154 struct bnx_softc *bnx_sc;
155
156 uint16_t bnx_rx_std; /* current prod ring head */
157 struct bge_rx_bd *bnx_rx_std_ring;
158
159 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */
160 struct bnx_rx_buf bnx_rx_std_buf[BGE_STD_RX_RING_CNT];
161
162 bus_dma_tag_t bnx_rx_std_ring_tag;
163 bus_dmamap_t bnx_rx_std_ring_map;
164 bus_addr_t bnx_rx_std_ring_paddr;
165} __cachealign;
166
167struct bnx_rx_ret_ring {
168 struct bnx_softc *bnx_sc;
169 struct bnx_rx_std_ring *bnx_std;
170
171 /* Shadow of bnx_rx_std_ring's bnx_rx_mtag */
172 bus_dma_tag_t bnx_rx_mtag;
173
3a16b7b8 174 volatile uint16_t *bnx_rx_considx;
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175 uint16_t bnx_rx_saved_considx;
176 struct bge_rx_bd *bnx_rx_ret_ring;
177 bus_dmamap_t bnx_rx_tmpmap;
178
179 bus_dma_tag_t bnx_rx_ret_ring_tag;
180 bus_dmamap_t bnx_rx_ret_ring_map;
181 bus_addr_t bnx_rx_ret_ring_paddr;
182} __cachealign;
183
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184/*
185 * Mbuf pointers. We need these to keep track of the virtual addresses
186 * of our mbuf chains since we can only convert from physical to virtual,
187 * not the other way around.
188 */
189struct bnx_chain_data {
190 bus_dma_tag_t bnx_parent_tag;
6c8d8ecc 191 bus_dma_tag_t bnx_rx_jumbo_ring_tag;
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192 bus_dma_tag_t bnx_status_tag;
193 bus_dma_tag_t bnx_jumbo_tag;
6c8d8ecc 194 bus_dmamap_t bnx_rx_jumbo_ring_map;
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195 bus_dmamap_t bnx_status_map;
196 bus_dmamap_t bnx_jumbo_map;
beedf5be 197 struct bnx_rx_buf bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
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198 /* Stick the jumbo mem management stuff here too. */
199 struct bnx_jslot bnx_jslots[BNX_JSLOTS];
200};
201
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202struct bnx_tx_buf {
203 bus_dmamap_t bnx_tx_dmamap;
204 struct mbuf *bnx_tx_mbuf;
205};
206
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207struct bnx_tx_ring {
208 struct bnx_softc *bnx_sc;
3a16b7b8 209 volatile uint16_t *bnx_tx_considx;
79a64343 210 uint16_t bnx_tx_flags;
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211#define BNX_TX_FLAG_SHORTDMA 0x0001
212#define BNX_TX_FLAG_FORCE_DEFRAG 0x0002
33a04907 213 uint16_t bnx_tx_saved_considx;
fa639b88 214 int bnx_tx_cnt;
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215 uint32_t bnx_tx_prodidx;
216 int bnx_tx_wreg;
8bd43d5d 217 int bnx_tx_mbx;
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218
219 struct bge_tx_bd *bnx_tx_ring;
220
221 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */
fa4b1067 222 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT];
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223
224 bus_dma_tag_t bnx_tx_ring_tag;
225 bus_dmamap_t bnx_tx_ring_map;
226 bus_addr_t bnx_tx_ring_paddr;
f33ac8a4 227 int bnx_tx_cpuid;
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228} __cachealign;
229
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230struct bnx_intr_data {
231 struct bnx_softc *bnx_sc;
232 struct bnx_rx_ret_ring *bnx_ret;
233 struct bnx_tx_ring *bnx_txr;
234
235 int bnx_intr_cpuid;
236 struct lwkt_serialize *bnx_intr_serialize;
237 struct callout bnx_intr_timer;
238 void (*bnx_intr_check)(void *);
239 uint16_t bnx_rx_check_considx;
240 uint16_t bnx_tx_check_considx;
241 boolean_t bnx_intr_maylose;
242
243 void *bnx_intr_arg;
244 driver_intr_t *bnx_intr_func;
245 void *bnx_intr_hand;
246 struct resource *bnx_intr_res;
247 int bnx_intr_rid;
248
249 const char *bnx_intr_desc;
250 char bnx_intr_desc0[64];
251} __cachealign;
252
253#define BNX_INTR_MAX 5
254
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255struct bnx_softc {
256 struct arpcom arpcom; /* interface info */
257 device_t bnx_dev;
258 device_t bnx_miibus;
259 bus_space_handle_t bnx_bhandle;
260 bus_space_tag_t bnx_btag;
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261 struct resource *bnx_res;
262 struct ifmedia bnx_ifmedia; /* TBI media info */
263 int bnx_pciecap;
264 uint32_t bnx_status_tag;
265 uint32_t bnx_flags; /* BNX_FLAG_ */
266#define BNX_FLAG_TBI 0x00000001
267#define BNX_FLAG_JUMBO 0x00000002
268#define BNX_FLAG_ONESHOT_MSI 0x00000004
269#define BNX_FLAG_5717_PLUS 0x00000008
270#define BNX_FLAG_MII_SERDES 0x00000010
271#define BNX_FLAG_CPMU 0x00000020
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272#define BNX_FLAG_57765_PLUS 0x00000040
273#define BNX_FLAG_57765_FAMILY 0x00000080
df9ccc98 274#define BNX_FLAG_STATUSTAG_BUG 0x00000100
66deb1c1 275#define BNX_FLAG_TSO 0x00000200
6c8d8ecc 276#define BNX_FLAG_NO_EEPROM 0x10000000
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277
278 uint32_t bnx_chipid;
279 uint32_t bnx_asicrev;
280 uint32_t bnx_chiprev;
281 struct bnx_ring_data bnx_ldata; /* rings */
282 struct bnx_chain_data bnx_cdata; /* mbufs */
beedf5be 283
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284 struct lwkt_serialize bnx_main_serialize;
285
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286 int bnx_tx_ringcnt;
287 struct bnx_tx_ring *bnx_tx_ring;
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288 int bnx_rx_retcnt;
289 struct bnx_rx_ret_ring *bnx_rx_ret_ring;
290 struct bnx_rx_std_ring bnx_rx_std_ring;
291
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292 uint16_t bnx_jumbo; /* current jumo ring head */
293 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead;
294 struct lwkt_serialize bnx_jslot_serializer;
295 uint32_t bnx_rx_coal_ticks;
296 uint32_t bnx_tx_coal_ticks;
297 uint32_t bnx_rx_coal_bds;
298 uint32_t bnx_tx_coal_bds;
299 uint32_t bnx_rx_coal_bds_int;
300 uint32_t bnx_tx_coal_bds_int;
6c8d8ecc 301 uint32_t bnx_mi_mode;
6c8d8ecc 302 int bnx_if_flags;
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303 int bnx_link;
304 int bnx_link_evt;
8ca0f604 305 int bnx_stat_cpuid;
6c8d8ecc 306 struct callout bnx_stat_timer;
b5de76b1 307 struct ifpoll_compat bnx_npoll;
6c8d8ecc 308
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309 int bnx_intr_type;
310 int bnx_intr_cnt;
311 struct bnx_intr_data bnx_intr_data[BNX_INTR_MAX];
df9ccc98 312
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313 struct sysctl_ctx_list bnx_sysctl_ctx;
314 struct sysctl_oid *bnx_sysctl_tree;
315
316 int bnx_phyno;
317 uint32_t bnx_coal_chg;
318#define BNX_RX_COAL_TICKS_CHG 0x01
319#define BNX_TX_COAL_TICKS_CHG 0x02
320#define BNX_RX_COAL_BDS_CHG 0x04
321#define BNX_TX_COAL_BDS_CHG 0x08
322#define BNX_RX_COAL_BDS_INT_CHG 0x40
323#define BNX_TX_COAL_BDS_INT_CHG 0x80
324
325 void (*bnx_link_upd)(struct bnx_softc *, uint32_t);
326 uint32_t bnx_link_chg;
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327
328#define BNX_TSO_NSTATS 45
329 u_long bnx_tsosegs[BNX_TSO_NSTATS];
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330};
331
66deb1c1 332#define BNX_NSEG_NEW 40
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333#define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */
334#define BNX_NSEG_RSVD 4
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335
336/* RX coalesce ticks, unit: us */
337#define BNX_RX_COAL_TICKS_MIN 0
338#define BNX_RX_COAL_TICKS_DEF 160
339#define BNX_RX_COAL_TICKS_MAX 1023
340
341/* TX coalesce ticks, unit: us */
342#define BNX_TX_COAL_TICKS_MIN 0
343#define BNX_TX_COAL_TICKS_DEF 1023
344#define BNX_TX_COAL_TICKS_MAX 1023
345
346/* RX coalesce BDs */
8a382fe7 347#define BNX_RX_COAL_BDS_MIN 0
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348#define BNX_RX_COAL_BDS_DEF 0
349#define BNX_RX_COAL_BDS_INT_DEF 80
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350#define BNX_RX_COAL_BDS_MAX 255
351
352/* TX coalesce BDs */
8a382fe7 353#define BNX_TX_COAL_BDS_MIN 0
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354#define BNX_TX_COAL_BDS_DEF 64
355#define BNX_TX_COAL_BDS_INT_DEF 64
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356#define BNX_TX_COAL_BDS_MAX 255
357
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358/* Number of segments sent before writing to TX related registers */
359#define BNX_TX_WREG_NSEGS 8
360
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361/* Return ring descriptor count */
362#define BNX_RETURN_RING_CNT 512
363
6c8d8ecc 364#endif /* !_IF_BNXVAR_H_ */