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AHCI - Implement parallel port scan and thread each port interrupt.
[dragonfly.git] / sys / dev / disk / ahci / ahci.h
CommitLineData
258223a3
MD		 1/*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19#if defined(__DragonFly__)
20#include "ahci_dragonfly.h"
21#else
22#error "build for OS unknown"
23#endif
24#include "atascsi.h"
25
26/* change to AHCI_DEBUG for dmesg spam */
27#define NO_AHCI_DEBUG
28
29#ifdef AHCI_DEBUG
30#define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
31 while (0)
32#define AHCI_D_TIMEOUT 0x00
33#define AHCI_D_VERBOSE 0x01
34#define AHCI_D_INTR 0x02
35#define AHCI_D_XFER 0x08
36int ahcidebug = AHCI_D_VERBOSE;
37#else
38#define DPRINTF(m, f...)
39#endif
40
41#define AHCI_PCI_BAR 0x24
42#define AHCI_PCI_ATI_SB600_MAGIC 0x40
43#define AHCI_PCI_ATI_SB600_LOCKED 0x01
44#define AHCI_PCI_INTERFACE 0x01
45
46#define AHCI_REG_CAP 0x000 /* HBA Capabilities */
47#define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
48#define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
49#define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
50#define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
51#define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
52#define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
53#define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
54#define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
55#define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
56#define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
57#define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
58#define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
59#define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
60#define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
61#define AHCI_REG_CAP_ISS_G1_2 (0x2<<20) /* Gen 1 and 2 (3 Gbps) */
62#define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
63#define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
64#define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
65#define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
66#define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
67#define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
68#define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
69#define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
70#define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
71 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
72 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
73 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
74 "\010CCCS" "\007EMS" "\006SXS"
75
76#define AHCI_REG_GHC 0x004 /* Global HBA Control */
77#define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
78#define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
79#define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
80#define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
81#define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
82
83#define AHCI_REG_IS 0x008 /* Interrupt Status */
84#define AHCI_REG_PI 0x00c /* Ports Implemented */
85
86#define AHCI_REG_VS 0x010 /* AHCI Version */
87#define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
88#define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
89#define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
90#define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
91
92#define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
93#define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
94
95#define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
96#define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
97#define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
98
99#define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
100#define AHCI_PORT_SIZE 0x80
101
102#define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
103#define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
104#define AHCI_PREG_FB 0x08 /* FIS Base Addr */
105#define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
106
107#define AHCI_PREG_IS 0x10 /* Interrupt Status */
108#define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
109#define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
110#define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
111#define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
112#define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
113#define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
114#define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
115#define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
116#define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
117#define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
118#define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
119#define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
120#define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
121#define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
122#define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
123#define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
124#define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
125#define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
126 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
127 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
128 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
129 "\002PSS" "\001DHRS"
130
131#define AHCI_PREG_IE 0x14 /* Interrupt Enable */
132#define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
133#define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
134#define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
135#define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
136#define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
137#define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
138#define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
139#define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
140#define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
141#define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
142#define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
143#define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
144#define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
145#define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
146#define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
147#define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
148#define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
149#define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
150 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
151 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
152 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
153 "\002PSE" "\001DHRE"
154
155#define AHCI_PREG_CMD 0x18 /* Command and Status */
156#define AHCI_PREG_CMD_ST (1<<0) /* Start */
157#define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
158#define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
159#define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
160#define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
161#define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
162#define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
163#define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
164#define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
165#define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
166#define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
167#define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
168#define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
169#define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
170#define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
171#define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
172#define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
173#define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
174#define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
175#define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
176#define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
177#define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
178#define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
179#define AHCI_PREG_CMD_ICC_IDLE 0x00000000
180#define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
181 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
182 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
183 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
184 "\003POD" "\002SUD" "\001ST"
185
186#define AHCI_PREG_TFD 0x20 /* Task File Data*/
187#define AHCI_PREG_TFD_STS 0xff
188#define AHCI_PREG_TFD_STS_ERR (1<<0)
189#define AHCI_PREG_TFD_STS_DRQ (1<<3)
190#define AHCI_PREG_TFD_STS_BSY (1<<7)
191#define AHCI_PREG_TFD_ERR 0xff00
192
193#define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
194#define AHCI_PREG_SIG 0x24 /* Signature */
195
196#define AHCI_PREG_SSTS 0x28 /* SATA Status */
197#define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
198#define AHCI_PREG_SSTS_DET_NONE 0x0
199#define AHCI_PREG_SSTS_DET_DEV_NE 0x1
200#define AHCI_PREG_SSTS_DET_DEV 0x3
201#define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
202#define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
203#define AHCI_PREG_SSTS_SPD_NONE 0x00
204#define AHCI_PREG_SSTS_SPD_GEN1 0x10
205#define AHCI_PREG_SSTS_SPD_GEN2 0x20
206#define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
207#define AHCI_PREG_SSTS_IPM_NONE 0x000
208#define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
209#define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
210#define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
211
212#define AHCI_PREG_SCTL 0x2c /* SATA Control */
213#define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
214#define AHCI_PREG_SCTL_DET_NONE 0x0
215#define AHCI_PREG_SCTL_DET_INIT 0x1
216#define AHCI_PREG_SCTL_DET_DISABLE 0x4
217#define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
218#define AHCI_PREG_SCTL_SPD_ANY 0x00
219#define AHCI_PREG_SCTL_SPD_GEN1 0x10
220#define AHCI_PREG_SCTL_SPD_GEN2 0x20
221#define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
222#define AHCI_PREG_SCTL_IPM_NONE 0x000
223#define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
224#define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
225#define AHCI_PREG_SCTL_IPM_DISABLED 0x300
3209f581
MD		 226#define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
227#define AHCI_PREG_SCTL_SPM_NONE 0x0000
228#define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000
229#define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000
230#define AHCI_PREG_SCTL_SPM_DISABLED 0x3000
231#define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
232#define AHCI_PREG_SCTL_PMP_SHIFT 16
258223a3
MD		 233
234#define AHCI_PREG_SERR 0x30 /* SATA Error */
258223a3
MD		 235#define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
236#define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
237#define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
238#define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
239#define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
240#define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
1980eff3
MD		 241#define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
242#define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
243#define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
244#define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
245#define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
246#define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
247#define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
248#define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
249#define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
250#define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
251#define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
252
253#define AHCI_PFMT_SERR "\020" \
254 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
255 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
256 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
257 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
258 "\002ERR.M" "\001ERR.I"
258223a3
MD		 259
260#define AHCI_PREG_SACT 0x34 /* SATA Active */
261#define AHCI_PREG_CI 0x38 /* Command Issue */
262#define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
263#define AHCI_PREG_SNTF 0x3c /* SNotification */
264
1980eff3
MD		 265/*
266 * AHCI port multiplier registers
267 */
268#define AHCI_PMREG_SSTS 0 /* use AHCI_PREG_SSTS_ bit defs */
269#define AHCI_PMREG_SERR 1 /* use AHCI_PREG_SERR_ bit defs */
270#define AHCI_PMREG_SCTL 2 /* use AHCI_PREG_SCTL_ bit defs */
3209f581
MD		 271#define AHCI_PMREG_SACT 3 /* (not implemented on PM) */
272
273/*
274 * AHCI port multiplier revision information SCR[1] (see ahci_pm_read)
275 *
276 * Rev 1.1 is the one that should support async notification.
277 */
278#define AHCI_PMREV_PM1_0 0x00000002
279#define AHCI_PMREV_PM1_1 0x00000004
280#define AHCI_PFMT_PM_REV "\20" "\003PM1.1" "\002PM1.0"
281
282/*
283 * GSCR[64] and GSCR[96] - Port Multiplier features available and features
284 * enabled.
285 */
286#define AHCI_PMREG_FEA 64
287#define AHCI_PMREG_FEAEN 96 /* (features enabled) */
288#define AHCI_PMFEA_BIST 0x00000001 /* BIST Support */
289#define AHCI_PMFEA_PMREQ 0x00000002 /* Can issue PMREQp to host */
290#define AHCI_PMFEA_DYNSSC 0x00000004 /* Dynamic SSC transmit enab */
291#define AHCI_PMFEA_ASYNCNOTIFY 0x00000008 /* Async notification */
292
293#define AHCI_PFMT_PM_FEA "\20" \
294 "\004AsyncNotify" \
295 "\003DynamicSSC" \
296 "\002PMREQ" \
297 "\001BIST"
298
299/*
300 * Enable generation of async notify events for individual targets
301 * via the PMEENA register. Each bit in PMEINFO is a wire-or of all
302 * SERROR bits for that target. To enable a new notification event
303 * the SERROR bits in PMSERROR_REGNO must be cleared.
304 */
305#define AHCI_PMREG_EINFO 32 /* error info 16 ports */
306#define AHCI_PMREG_EEENA 33 /* error info enable 16 ports */
1980eff3
MD		 307
308/*
309 * AHCI mapped structures
310 */
258223a3
MD		 311struct ahci_cmd_hdr {
312 u_int16_t flags;
313#define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
314#define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
315#define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
316#define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
317#define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
318#define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
319#define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
320#define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
1980eff3 321#define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
258223a3
MD		 322 u_int16_t prdtl; /* sgl len */
323
324 u_int32_t prdbc; /* transferred byte count */
325
326 u_int32_t ctba_lo;
327 u_int32_t ctba_hi;
328
329 u_int32_t reserved[4];
330} __packed;
331
332struct ahci_rfis {
333 u_int8_t dsfis[28];
334 u_int8_t reserved1[4];
335 u_int8_t psfis[24];
336 u_int8_t reserved2[8];
337 u_int8_t rfis[24];
338 u_int8_t reserved3[4];
339 u_int8_t sdbfis[4];
340 u_int8_t ufis[64];
341 u_int8_t reserved4[96];
342} __packed;
343
344struct ahci_prdt {
345 u_int32_t dba_lo;
346 u_int32_t dba_hi;
347 u_int32_t reserved;
348 u_int32_t flags;
349#define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
350} __packed;
351
352/*
353 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
354 * We need to accomodate MAXPHYS (128K) which is at least 32 entries,
355 * plus one for page slop.
356 *
357 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2)
358 * thus requires MAX_PRDT to be set to 56.
359 */
360#define AHCI_MAX_PRDT 56
1980eff3 361#define AHCI_MAX_PMPORTS 16
258223a3
MD		 362
363#if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
364#error "AHCI_MAX_PRDT is not big enough"
365#endif
366
367struct ahci_cmd_table {
368 u_int8_t cfis[64]; /* Command FIS */
369 u_int8_t acmd[16]; /* ATAPI Command */
370 u_int8_t reserved[48];
371
372 struct ahci_prdt prdt[AHCI_MAX_PRDT];
373} __packed;
374
375#define AHCI_MAX_PORTS 32
376
377struct ahci_dmamem {
378 bus_dma_tag_t adm_tag;
379 bus_dmamap_t adm_map;
380 bus_dma_segment_t adm_seg;
381 bus_addr_t adm_busaddr;
382 caddr_t adm_kva;
383};
384#define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
385#define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
386#define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
387
388struct ahci_softc;
389struct ahci_port;
390struct ahci_device;
391
392struct ahci_ccb {
393 /* ATA xfer associated with this CCB. Must be 1st struct member. */
394 struct ata_xfer ccb_xa;
395 struct callout ccb_timeout;
396
397 int ccb_slot;
398 struct ahci_port *ccb_port;
399
400 bus_dmamap_t ccb_dmamap;
401 struct ahci_cmd_hdr *ccb_cmd_hdr;
402 struct ahci_cmd_table *ccb_cmd_table;
403
404 void (*ccb_done)(struct ahci_ccb *);
405
406 TAILQ_ENTRY(ahci_ccb) ccb_entry;
407};
408
409struct ahci_port {
410 struct ahci_softc *ap_sc;
411 bus_space_handle_t ap_ioh;
412
413 int ap_num;
1980eff3 414 int ap_pmcount;
258223a3
MD		 415 int ap_flags;
416#define AP_F_BUS_REGISTERED 0x0001
417#define AP_F_CAM_ATTACHED 0x0002
1980eff3 418#define AP_F_IN_RESET 0x0004
3209f581
MD		 419#define AP_F_SCAN_RUNNING 0x0008
420#define AP_F_SCAN_REQUESTED 0x0010
f4553de1
MD		 421#define AP_F_SCAN_COMPLETED 0x0020
422#define AP_F_IGNORE_IFS 0x0040
423#define AP_F_IFS_IGNORED 0x0080
424#define AP_F_IFS_OCCURED 0x0100
425 int ap_signal; /* os per-port thread sig */
426 thread_t ap_thread; /* os per-port thread */
427 struct lock ap_lock; /* os per-port lock */
428#define AP_SIGF_INIT 0x0001
429#define AP_SIGF_TIMEOUT 0x0002
430#define AP_SIGF_PORTINT 0x0004
431#define AP_SIGF_STOP 0x8000
258223a3 432 struct cam_sim *ap_sim;
258223a3
MD		 433
434 struct ahci_rfis *ap_rfis;
435 struct ahci_dmamem *ap_dmamem_rfis;
436
437 struct ahci_dmamem *ap_dmamem_cmd_list;
438 struct ahci_dmamem *ap_dmamem_cmd_table;
439
1980eff3
MD		 440 volatile u_int32_t ap_active; /* active CI command bmask */
441 volatile u_int32_t ap_active_cnt; /* active CI command count */
442 volatile u_int32_t ap_sactive; /* active SACT command bmask */
258223a3
MD		 443 struct ahci_ccb *ap_ccbs;
444
445 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
446 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
447 struct lock ap_ccb_lock;
448
1980eff3
MD		 449 int ap_type; /* ATA_PORT_T_xxx */
450 int ap_probe; /* ATA_PROBE_xxx */
451 struct ata_port *ap_ata;
258223a3
MD		 452
453 u_int32_t ap_state;
454#define AP_S_NORMAL 0
455#define AP_S_FATAL_ERROR 1
456
457 /* For error recovery. */
458#ifdef DIAGNOSTIC
459 int ap_err_busy;
460#endif
461 u_int32_t ap_err_saved_sactive;
462 u_int32_t ap_err_saved_active;
463 u_int32_t ap_err_saved_active_cnt;
464
465 u_int8_t ap_err_scratch[512];
466
467 char ap_name[16];
468};
469
1980eff3
MD		 470#define PORTNAME(_ap) ((_ap)->ap_name)
471#define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
258223a3
MD		 472
473struct ahci_softc {
474 device_t sc_dev;
475 const struct ahci_device *sc_ad; /* special casing */
258223a3
MD		 476
477 struct resource *sc_irq; /* bus resources */
478 struct resource *sc_regs; /* bus resources */
479 bus_space_tag_t sc_iot; /* split from sc_regs */
480 bus_space_handle_t sc_ioh; /* split from sc_regs */
481
482 int sc_rid_irq; /* saved bus RIDs */
483 int sc_rid_regs;
484 u_int32_t sc_cap; /* capabilities */
485
486 void *sc_irq_handle; /* installed irq vector */
487
488 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
489 bus_dma_tag_t sc_tag_cmdh;
490 bus_dma_tag_t sc_tag_cmdt;
491 bus_dma_tag_t sc_tag_data;
492
493 int sc_flags;
494#define AHCI_F_NO_NCQ (1<<0)
495#define AHCI_F_IGN_FR (1<<1)
f4553de1 496#define AHCI_F_INT_GOOD (1<<2)
258223a3
MD		 497
498 u_int sc_ncmds;
499
500 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
501
502#ifdef AHCI_COALESCE
503 u_int32_t sc_ccc_mask;
504 u_int32_t sc_ccc_ports;
505 u_int32_t sc_ccc_ports_cur;
506#endif
507};
508#define DEVNAME(_s) ((_s)->sc_dev.dv_xname)
509
510struct ahci_device {
511 pci_vendor_id_t ad_vendor;
512 pci_product_id_t ad_product;
513 int (*ad_attach)(device_t dev);
514 int (*ad_detach)(device_t dev);
515 char *name;
516};
517
518const struct ahci_device *ahci_lookup_device(device_t dev);
519int ahci_init(struct ahci_softc *);
f4553de1 520int ahci_port_init(struct ahci_port *ap, struct ata_port *at);
258223a3 521int ahci_port_alloc(struct ahci_softc *, u_int);
3209f581 522void ahci_port_state_machine(struct ahci_port *ap);
258223a3 523void ahci_port_free(struct ahci_softc *, u_int);
1980eff3 524int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
fd8bd957 525
258223a3
MD		 526u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
527void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
528int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
529u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
530void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
cec85a37
MD		 531int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
532 u_int32_t, u_int32_t);
258223a3 533void ahci_intr(void *);
f4553de1 534void ahci_port_intr(struct ahci_port *ap, int blockable);
258223a3
MD		 535
536int ahci_cam_attach(struct ahci_port *ap);
3209f581 537void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
258223a3 538void ahci_cam_detach(struct ahci_port *ap);
3209f581 539int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
258223a3 540
1980eff3
MD		 541struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
542void ahci_ata_put_xfer(struct ata_xfer *xa);
543int ahci_ata_cmd(struct ata_xfer *xa);
544
545int ahci_pm_identify(struct ahci_port *ap);
3209f581 546int ahci_pm_set_feature(struct ahci_port *ap, int feature, int enable);
1980eff3
MD		 547int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
548int ahci_pm_softreset(struct ahci_port *ap, int target);
549int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
550int ahci_pm_read(struct ahci_port *ap, int target,
551 int which, u_int32_t *res);
552int ahci_pm_write(struct ahci_port *ap, int target,
553 int which, u_int32_t data);
3209f581 554void ahci_pm_check_good(struct ahci_port *ap, int target);
1980eff3
MD		 555void ahci_ata_cmd_timeout(void *arg);
556struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
557void ahci_put_ccb(struct ahci_ccb *ccb);
558int ahci_poll(struct ahci_ccb *ccb, int timeout,
559 void (*timeout_fn)(void *));
560int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
f4553de1 561void ahci_port_thread_core(struct ahci_port *ap, int mask);
1980eff3 562
3209f581 563void ahci_os_sleep(int ticks);
f4553de1
MD		 564void ahci_os_start_port(struct ahci_port *ap);
565void ahci_os_stop_port(struct ahci_port *ap);
566void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
567void ahci_os_lock_port(struct ahci_port *ap);
568int ahci_os_lock_port_nb(struct ahci_port *ap);
569void ahci_os_unlock_port(struct ahci_port *ap);
258223a3
MD		 570
571extern u_int32_t AhciForceGen1;
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