Reorder MP probing
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29#include "opt_cpu.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
37#include <sys/cons.h> /* cngetc() */
38#include <sys/machintr.h>
39
684a93c4
MD
40#include <sys/mplock2.h>
41
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42#include <vm/vm.h>
43#include <vm/vm_param.h>
44#include <vm/pmap.h>
45#include <vm/vm_kern.h>
46#include <vm/vm_extern.h>
47#include <sys/lock.h>
48#include <vm/vm_map.h>
49#include <sys/user.h>
50#ifdef GPROF
51#include <sys/gmon.h>
52#endif
53
54#include <machine/smp.h>
55#include <machine_base/apic/apicreg.h>
56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
58#include <machine_base/apic/mpapic.h>
59#include <machine/psl.h>
60#include <machine/segments.h>
61#include <machine/tss.h>
62#include <machine/specialreg.h>
63#include <machine/globaldata.h>
64
65#include <machine/md_var.h> /* setidt() */
66#include <machine_base/icu/icu.h> /* IPIs */
67#include <machine_base/isa/intr_machdep.h> /* IPIs */
68
69#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
70
71#define WARMBOOT_TARGET 0
72#define WARMBOOT_OFF (KERNBASE + 0x0467)
73#define WARMBOOT_SEG (KERNBASE + 0x0469)
74
75#define BIOS_BASE (0xf0000)
76#define BIOS_SIZE (0x10000)
77#define BIOS_COUNT (BIOS_SIZE/4)
78
79#define CMOS_REG (0x70)
80#define CMOS_DATA (0x71)
81#define BIOS_RESET (0x0f)
82#define BIOS_WARM (0x0a)
83
84#define PROCENTRY_FLAG_EN 0x01
85#define PROCENTRY_FLAG_BP 0x02
86#define IOAPICENTRY_FLAG_EN 0x01
87
88
89/* MP Floating Pointer Structure */
90typedef struct MPFPS {
91 char signature[4];
92 u_int32_t pap;
93 u_char length;
94 u_char spec_rev;
95 u_char checksum;
96 u_char mpfb1;
97 u_char mpfb2;
98 u_char mpfb3;
99 u_char mpfb4;
100 u_char mpfb5;
101} *mpfps_t;
102
103/* MP Configuration Table Header */
104typedef struct MPCTH {
105 char signature[4];
106 u_short base_table_length;
107 u_char spec_rev;
108 u_char checksum;
109 u_char oem_id[8];
110 u_char product_id[12];
a5f51ef3 111 u_int32_t oem_table_pointer;
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112 u_short oem_table_size;
113 u_short entry_count;
a5f51ef3 114 u_int32_t apic_address;
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115 u_short extended_table_length;
116 u_char extended_table_checksum;
117 u_char reserved;
118} *mpcth_t;
119
120
121typedef struct PROCENTRY {
122 u_char type;
123 u_char apic_id;
124 u_char apic_version;
125 u_char cpu_flags;
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126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
128 u_int32_t reserved1;
129 u_int32_t reserved2;
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130} *proc_entry_ptr;
131
132typedef struct BUSENTRY {
133 u_char type;
134 u_char bus_id;
135 char bus_type[6];
136} *bus_entry_ptr;
137
138typedef struct IOAPICENTRY {
139 u_char type;
140 u_char apic_id;
141 u_char apic_version;
142 u_char apic_flags;
a5f51ef3 143 u_int32_t apic_address;
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144} *io_apic_entry_ptr;
145
146typedef struct INTENTRY {
147 u_char type;
148 u_char int_type;
149 u_short int_flags;
150 u_char src_bus_id;
151 u_char src_bus_irq;
152 u_char dst_apic_id;
153 u_char dst_apic_int;
154} *int_entry_ptr;
155
156/* descriptions of MP basetable entries */
157typedef struct BASETABLE_ENTRY {
158 u_char type;
159 u_char length;
160 char name[16];
161} basetable_entry;
162
163/*
164 * this code MUST be enabled here and in mpboot.s.
165 * it follows the very early stages of AP boot by placing values in CMOS ram.
166 * it NORMALLY will never be needed and thus the primitive method for enabling.
167 *
168 */
169#if defined(CHECK_POINTS)
170#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
171#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
172
173#define CHECK_INIT(D); \
174 CHECK_WRITE(0x34, (D)); \
175 CHECK_WRITE(0x35, (D)); \
176 CHECK_WRITE(0x36, (D)); \
177 CHECK_WRITE(0x37, (D)); \
178 CHECK_WRITE(0x38, (D)); \
179 CHECK_WRITE(0x39, (D));
180
181#define CHECK_PRINT(S); \
182 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
183 (S), \
184 CHECK_READ(0x34), \
185 CHECK_READ(0x35), \
186 CHECK_READ(0x36), \
187 CHECK_READ(0x37), \
188 CHECK_READ(0x38), \
189 CHECK_READ(0x39));
190
191#else /* CHECK_POINTS */
192
193#define CHECK_INIT(D)
194#define CHECK_PRINT(S)
195
196#endif /* CHECK_POINTS */
197
198/*
199 * Values to send to the POST hardware.
200 */
201#define MP_BOOTADDRESS_POST 0x10
202#define MP_PROBE_POST 0x11
203#define MPTABLE_PASS1_POST 0x12
204
205#define MP_START_POST 0x13
206#define MP_ENABLE_POST 0x14
207#define MPTABLE_PASS2_POST 0x15
208
209#define START_ALL_APS_POST 0x16
210#define INSTALL_AP_TRAMP_POST 0x17
211#define START_AP_POST 0x18
212
213#define MP_ANNOUNCE_POST 0x19
214
215static int need_hyperthreading_fixup;
216static u_int logical_cpus;
217u_int logical_cpus_mask;
218
219/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
220int current_postcode;
221
222/** XXX FIXME: what system files declare these??? */
223extern struct region_descriptor r_gdt, r_idt;
224
225int bsp_apic_ready = 0; /* flags useability of BSP apic */
226int mp_naps; /* # of Applications processors */
227int mp_nbusses; /* # of busses */
228#ifdef APIC_IO
229int mp_napics; /* # of IO APICs */
230#endif
231int boot_cpu_id; /* designated BSP */
232vm_offset_t cpu_apic_address;
233#ifdef APIC_IO
234vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235u_int32_t *io_apic_versions;
236#endif
237extern int nkpt;
238
239u_int32_t cpu_apic_versions[MAXCPU];
240int64_t tsc0_offset;
241extern int64_t tsc_offsets[];
242
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243extern u_long ebda_addr;
244
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245#ifdef APIC_IO
246struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
247#endif
248
249/*
250 * APIC ID logical/physical mapping structures.
251 * We oversize these to simplify boot-time config.
252 */
253int cpu_num_to_apic_id[NAPICID];
254#ifdef APIC_IO
255int io_num_to_apic_id[NAPICID];
256#endif
257int apic_id_to_logical[NAPICID];
258
259/* AP uses this during bootstrap. Do not staticize. */
260char *bootSTK;
261static int bootAP;
262
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263/*
264 * SMP page table page. Setup by locore to point to a page table
265 * page from which we allocate per-cpu privatespace areas io_apics,
266 * and so forth.
267 */
268
269#define IO_MAPPING_START_INDEX \
270 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
271
272extern pt_entry_t *SMPpt;
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273
274struct pcb stoppcbs[MAXCPU];
275
276extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
277
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278/*
279 * Local data and functions.
280 */
281
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282static u_int boot_address;
283static u_int base_memory;
284static int mp_finish;
285
286static mpfps_t mpfps;
3a918cfd 287static long search_for_sig(u_int32_t target, int count);
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288static void mp_enable(u_int boot_addr);
289
290static void mptable_hyperthread_fixup(u_int id_mask);
291static void mptable_pass1(void);
292static int mptable_pass2(void);
293static void default_mp_table(int type);
294static void fix_mp_table(void);
295#ifdef APIC_IO
296static void setup_apic_irq_mapping(void);
297static int apic_int_is_bus_type(int intr, int bus_type);
298#endif
299static int start_all_aps(u_int boot_addr);
bfc09ba0 300#if 0
46d4e165 301static void install_ap_tramp(u_int boot_addr);
bfc09ba0 302#endif
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303static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
304static int smitest(void);
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305
306static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
307cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
308SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
309static u_int bootMP_size;
310
311/*
312 * Calculate usable address in base memory for AP trampoline code.
313 */
314u_int
315mp_bootaddress(u_int basemem)
316{
317 POSTCODE(MP_BOOTADDRESS_POST);
318
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319 base_memory = basemem;
320
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321 bootMP_size = mptramp_end - mptramp_start;
322 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
323 if (((basemem * 1024) - boot_address) < bootMP_size)
324 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
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325 /* 3 levels of page table pages */
326 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
327
328 return mptramp_pagetables;
329}
330
331
332/*
333 * Look for an Intel MP spec table (ie, SMP capable hardware).
334 */
335int
336mp_probe(void)
337{
3a918cfd 338 long x;
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339 u_long segment;
340 u_int32_t target;
341
342 /*
343 * Make sure our SMPpt[] page table is big enough to hold all the
344 * mappings we need.
345 */
346 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
347
348 POSTCODE(MP_PROBE_POST);
349
350 /* see if EBDA exists */
927c4c1f 351 if (ebda_addr != 0) {
46d4e165 352 /* search first 1K of EBDA */
927c4c1f 353 target = (u_int32_t)ebda_addr;
a9e9c21a 354 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
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355 goto found;
356 } else {
357 /* last 1K of base memory, effective 'top of base' passed in */
358 target = (u_int32_t) (base_memory - 0x400);
a9e9c21a 359 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
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360 goto found;
361 }
362
363 /* search the BIOS */
364 target = (u_int32_t) BIOS_BASE;
a9e9c21a 365 if ((x = search_for_sig(target, BIOS_COUNT)) != -1L)
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366 goto found;
367
368 /* nothing found */
369 mpfps = (mpfps_t)0;
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370 return 0;
371
372found:
46d4e165 373 mpfps = (mpfps_t)x;
46d4e165 374
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375 return 1;
376}
377
378
379/*
380 * Startup the SMP processors.
381 */
382void
383mp_start(void)
384{
385 POSTCODE(MP_START_POST);
a0679cc7 386 mp_enable(boot_address);
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387}
388
389
390/*
391 * Print various information about the SMP system hardware and setup.
392 */
393void
394mp_announce(void)
395{
396 int x;
397
398 POSTCODE(MP_ANNOUNCE_POST);
399
400 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
401 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
402 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
bfc09ba0 403 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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404 for (x = 1; x <= mp_naps; ++x) {
405 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
406 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
bfc09ba0 407 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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408 }
409
410#if defined(APIC_IO)
411 for (x = 0; x < mp_napics; ++x) {
412 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
413 kprintf(", version: 0x%08x", io_apic_versions[x]);
bcdeeecd 414 kprintf(", at 0x%08lx\n", io_apic_address[x]);
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415 }
416#else
417 kprintf(" Warning: APIC I/O disabled\n");
418#endif /* APIC_IO */
419}
420
421/*
422 * AP cpu's call this to sync up protected mode.
423 *
ec073ddc 424 * WARNING! %gs is not set up on entry. This routine sets up %gs.
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425 */
426void
427init_secondary(void)
428{
429 int gsel_tss;
430 int x, myid = bootAP;
431 u_int64_t msr, cr0;
432 struct mdglobaldata *md;
433 struct privatespace *ps;
434
435 ps = &CPU_prvspace[myid];
436
437 gdt_segs[GPROC0_SEL].ssd_base =
438 (long) &ps->mdglobaldata.gd_common_tss;
439 ps->mdglobaldata.mi.gd_prvspace = ps;
440
441 /* We fill the 32-bit segment descriptors */
442 for (x = 0; x < NGDT; x++) {
443 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
444 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
445 }
446 /* And now a 64-bit one */
447 ssdtosyssd(&gdt_segs[GPROC0_SEL],
448 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
449
450 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
451 r_gdt.rd_base = (long) &gdt[myid * NGDT];
452 lgdt(&r_gdt); /* does magic intra-segment return */
453
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454 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
455 wrmsr(MSR_FSBASE, 0); /* User value */
456 wrmsr(MSR_GSBASE, (u_int64_t)ps);
457 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
458
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459 lidt(&r_idt);
460
461#if 0
462 lldt(_default_ldt);
463 mdcpu->gd_currentldt = _default_ldt;
464#endif
465
466 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
467 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
468
469 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
470
471 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
472#if 0 /* JG XXX */
473 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
474#endif
475 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
476 md->gd_common_tssd = *md->gd_tss_gdt;
477#if 0 /* JG XXX */
478 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
479#endif
480 ltr(gsel_tss);
481
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482 /*
483 * Set to a known state:
484 * Set by mpboot.s: CR0_PG, CR0_PE
485 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
486 */
487 cr0 = rcr0();
488 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
489 load_cr0(cr0);
490
491 /* Set up the fast syscall stuff */
492 msr = rdmsr(MSR_EFER) | EFER_SCE;
493 wrmsr(MSR_EFER, msr);
494 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
495 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
496 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
497 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
498 wrmsr(MSR_STAR, msr);
499 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
500
501 pmap_set_opt(); /* PSE/4MB pages, etc */
502#if JGXXX
503 /* Initialize the PAT MSR. */
504 pmap_init_pat();
505#endif
506
507 /* set up CPU registers and state */
508 cpu_setregs();
509
510 /* set up SSE/NX registers */
511 initializecpu();
512
513 /* set up FPU state on the AP */
514 npxinit(__INITIAL_NPXCW__);
ec073ddc
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515
516 /* disable the APIC, just to be SURE */
517 lapic->svr &= ~APIC_SVR_ENABLE;
518
519 /* data returned to BSP */
520 cpu_apic_versions[0] = lapic->version;
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521}
522
523/*******************************************************************
524 * local functions and data
525 */
526
527/*
528 * start the SMP system
529 */
530static void
531mp_enable(u_int boot_addr)
532{
533 int x;
534#if defined(APIC_IO)
535 int apic;
536 u_int ux;
537#endif /* APIC_IO */
538
539 POSTCODE(MP_ENABLE_POST);
540
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541 if (!mp_probe())
542 panic("mp_enable: mp_probe failed\n");
543
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544#if 0 /* JGXXX */
545 /* turn on 4MB of V == P addressing so we can get to MP table */
546 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
547 cpu_invltlb();
2ea1c65d 548#endif
46d4e165 549
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550 /*
551 * We can safely map physical memory into SMPpt after
552 * mptable_pass1() completes.
553 */
554 mptable_pass1();
555
556 if (cpu_apic_address == 0)
f592025a 557 panic("mp_enable: no local apic!\n");
9ad60dda 558
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559 /* examine the MP table for needed info, uses physical addresses */
560 x = mptable_pass2();
561
2ea1c65d 562#if 0 /* JGXXX */
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563 *(int *)PTD = 0;
564 cpu_invltlb();
565#endif /* 0 JGXXX */
566
567 /* can't process default configs till the CPU APIC is pmapped */
568 if (x)
569 default_mp_table(x);
570
571 /* post scan cleanup */
572 fix_mp_table();
573
574#if defined(APIC_IO)
575
576 setup_apic_irq_mapping();
577
578 /* fill the LOGICAL io_apic_versions table */
579 for (apic = 0; apic < mp_napics; ++apic) {
580 ux = io_apic_read(apic, IOAPIC_VER);
581 io_apic_versions[apic] = ux;
582 io_apic_set_id(apic, IO_TO_ID(apic));
583 }
584
585 /* program each IO APIC in the system */
586 for (apic = 0; apic < mp_napics; ++apic)
587 if (io_apic_setup(apic) < 0)
588 panic("IO APIC setup failure");
589
590#endif /* APIC_IO */
591
592 /*
593 * These are required for SMP operation
594 */
595
596 /* install a 'Spurious INTerrupt' vector */
597 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
a4f18b62 598 SDT_SYSIGT, SEL_KPL, 0);
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599
600 /* install an inter-CPU IPI for TLB invalidation */
601 setidt(XINVLTLB_OFFSET, Xinvltlb,
a4f18b62 602 SDT_SYSIGT, SEL_KPL, 0);
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603
604 /* install an inter-CPU IPI for IPIQ messaging */
605 setidt(XIPIQ_OFFSET, Xipiq,
a4f18b62 606 SDT_SYSIGT, SEL_KPL, 0);
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607
608 /* install a timer vector */
609 setidt(XTIMER_OFFSET, Xtimer,
a4f18b62 610 SDT_SYSIGT, SEL_KPL, 0);
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611
612 /* install an inter-CPU IPI for CPU stop/restart */
613 setidt(XCPUSTOP_OFFSET, Xcpustop,
a4f18b62 614 SDT_SYSIGT, SEL_KPL, 0);
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615
616 /* start each Application Processor */
617 start_all_aps(boot_addr);
618}
619
620
621/*
622 * look for the MP spec signature
623 */
624
625/* string defined by the Intel MP Spec as identifying the MP table */
626#define MP_SIG 0x5f504d5f /* _MP_ */
627#define NEXT(X) ((X) += 4)
3a918cfd 628static long
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629search_for_sig(u_int32_t target, int count)
630{
f592025a
MN
631 vm_size_t map_size;
632 u_int32_t *addr;
633 int x, ret;
46d4e165 634
f592025a
MN
635 map_size = count * sizeof(u_int32_t);
636 addr = pmap_mapdev((vm_paddr_t)target, map_size);
46d4e165 637
f592025a
MN
638 ret = -1;
639 for (x = 0; x < count; NEXT(x)) {
640 if (addr[x] == MP_SIG) {
641 /* make array index a byte index */
642 ret = target + (x * sizeof(u_int32_t));
643 break;
644 }
645 }
646 pmap_unmapdev((vm_offset_t)addr, map_size);
647 return ret;
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648}
649
650
651static basetable_entry basetable_entry_types[] =
652{
653 {0, 20, "Processor"},
654 {1, 8, "Bus"},
655 {2, 8, "I/O APIC"},
656 {3, 8, "I/O INT"},
657 {4, 8, "Local INT"}
658};
659
660typedef struct BUSDATA {
661 u_char bus_id;
662 enum busTypes bus_type;
663} bus_datum;
664
665typedef struct INTDATA {
666 u_char int_type;
667 u_short int_flags;
668 u_char src_bus_id;
669 u_char src_bus_irq;
670 u_char dst_apic_id;
671 u_char dst_apic_int;
672 u_char int_vector;
673} io_int, local_int;
674
675typedef struct BUSTYPENAME {
676 u_char type;
677 char name[7];
678} bus_type_name;
679
680static bus_type_name bus_type_table[] =
681{
682 {CBUS, "CBUS"},
683 {CBUSII, "CBUSII"},
684 {EISA, "EISA"},
685 {MCA, "MCA"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {ISA, "ISA"},
688 {MCA, "MCA"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {PCI, "PCI"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
699 {XPRESS, "XPRESS"},
700 {UNKNOWN_BUSTYPE, "---"}
701};
702/* from MP spec v1.4, table 5-1 */
703static int default_data[7][5] =
704{
705/* nbus, id0, type0, id1, type1 */
706 {1, 0, ISA, 255, 255},
707 {1, 0, EISA, 255, 255},
708 {1, 0, EISA, 255, 255},
709 {1, 0, MCA, 255, 255},
710 {2, 0, ISA, 1, PCI},
711 {2, 0, EISA, 1, PCI},
712 {2, 0, MCA, 1, PCI}
713};
714
715
716/* the bus data */
717static bus_datum *bus_data;
718
719#ifdef APIC_IO
720/* the IO INT data, one entry per possible APIC INTerrupt */
721static io_int *io_apic_ints;
722static int nintrs;
723#endif
724
725static int processor_entry (proc_entry_ptr entry, int cpu);
726static int bus_entry (bus_entry_ptr entry, int bus);
727#ifdef APIC_IO
728static int io_apic_entry (io_apic_entry_ptr entry, int apic);
729static int int_entry (int_entry_ptr entry, int intr);
730#endif
731static int lookup_bus_type (char *name);
732
733
734/*
735 * 1st pass on motherboard's Intel MP specification table.
736 *
737 * initializes:
738 * ncpus = 1
739 *
740 * determines:
741 * cpu_apic_address (common to all CPUs)
742 * io_apic_address[N]
743 * mp_naps
744 * mp_nbusses
745 * mp_napics
746 * nintrs
747 */
748static void
749mptable_pass1(void)
750{
751#ifdef APIC_IO
752 int x;
753#endif
754 mpcth_t cth;
755 int totalSize;
756 void* position;
757 int count;
758 int type;
759 u_int id_mask;
760
761 POSTCODE(MPTABLE_PASS1_POST);
762
9ad60dda
MN
763 if (mpfps == NULL)
764 panic("mptable_pass1: MP float pointer is not found\n");
765
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766#ifdef APIC_IO
767 /* clear various tables */
768 for (x = 0; x < NAPICID; ++x) {
769 io_apic_address[x] = ~0; /* IO APIC address table */
770 }
771#endif
772
773 /* init everything to empty */
774 mp_naps = 0;
775 mp_nbusses = 0;
776#ifdef APIC_IO
777 mp_napics = 0;
778 nintrs = 0;
779#endif
780 id_mask = 0;
781
782 /* check for use of 'default' configuration */
783 if (mpfps->mpfb1 != 0) {
784 /* use default addresses */
785 cpu_apic_address = DEFAULT_APIC_BASE;
786#ifdef APIC_IO
787 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
788#endif
789
790 /* fill in with defaults */
791 mp_naps = 2; /* includes BSP */
792 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
793#if defined(APIC_IO)
794 mp_napics = 1;
795 nintrs = 16;
796#endif /* APIC_IO */
797 }
798 else {
bfc09ba0 799 if (mpfps->pap == 0)
46d4e165 800 panic("MP Configuration Table Header MISSING!");
1f71eeb1 801 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
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802
803 cpu_apic_address = (vm_offset_t) cth->apic_address;
804
805 /* walk the table, recording info of interest */
806 totalSize = cth->base_table_length - sizeof(struct MPCTH);
807 position = (u_char *) cth + sizeof(struct MPCTH);
808 count = cth->entry_count;
809
810 while (count--) {
811 switch (type = *(u_char *) position) {
812 case 0: /* processor_entry */
813 if (((proc_entry_ptr)position)->cpu_flags
814 & PROCENTRY_FLAG_EN) {
815 ++mp_naps;
816 id_mask |= 1 <<
817 ((proc_entry_ptr)position)->apic_id;
818 }
819 break;
820 case 1: /* bus_entry */
821 ++mp_nbusses;
822 break;
823 case 2: /* io_apic_entry */
824#ifdef APIC_IO
825 if (((io_apic_entry_ptr)position)->apic_flags
826 & IOAPICENTRY_FLAG_EN)
827 io_apic_address[mp_napics++] =
828 (vm_offset_t)((io_apic_entry_ptr)
829 position)->apic_address;
830#endif
831 break;
832 case 3: /* int_entry */
833#ifdef APIC_IO
834 ++nintrs;
835#endif
836 break;
837 case 4: /* int_entry */
838 break;
839 default:
840 panic("mpfps Base Table HOSED!");
841 /* NOTREACHED */
842 }
843
844 totalSize -= basetable_entry_types[type].length;
845 position = (uint8_t *)position +
846 basetable_entry_types[type].length;
847 }
848 }
849
850 /* qualify the numbers */
851 if (mp_naps > MAXCPU) {
852 kprintf("Warning: only using %d of %d available CPUs!\n",
853 MAXCPU, mp_naps);
854 mp_naps = MAXCPU;
855 }
856
857 /* See if we need to fixup HT logical CPUs. */
858 mptable_hyperthread_fixup(id_mask);
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859
860 --mp_naps; /* subtract the BSP */
861}
862
863
864/*
865 * 2nd pass on motherboard's Intel MP specification table.
866 *
867 * sets:
868 * boot_cpu_id
869 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
870 * CPU_TO_ID(N), logical CPU to APIC ID table
871 * IO_TO_ID(N), logical IO to APIC ID table
872 * bus_data[N]
873 * io_apic_ints[N]
874 */
875static int
876mptable_pass2(void)
877{
878 struct PROCENTRY proc;
879 int x;
880 mpcth_t cth;
881 int totalSize;
882 void* position;
883 int count;
884 int type;
885 int apic, bus, cpu, intr;
886 int i;
887
888 POSTCODE(MPTABLE_PASS2_POST);
889
890 /* Initialize fake proc entry for use with HT fixup. */
891 bzero(&proc, sizeof(proc));
892 proc.type = 0;
893 proc.cpu_flags = PROCENTRY_FLAG_EN;
894
895#ifdef APIC_IO
896 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
897 M_DEVBUF, M_WAITOK);
898 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
899 M_DEVBUF, M_WAITOK | M_ZERO);
900 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
901 M_DEVBUF, M_WAITOK);
902#endif
903 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
904 M_DEVBUF, M_WAITOK);
905
906#ifdef APIC_IO
907 for (i = 0; i < mp_napics; i++) {
908 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
909 }
910#endif
911
912 /* clear various tables */
913 for (x = 0; x < NAPICID; ++x) {
914 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
915#ifdef APIC_IO
916 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
917 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
918#endif
919 }
920
921 /* clear bus data table */
922 for (x = 0; x < mp_nbusses; ++x)
923 bus_data[x].bus_id = 0xff;
924
925#ifdef APIC_IO
926 /* clear IO APIC INT table */
927 for (x = 0; x < (nintrs + 1); ++x) {
928 io_apic_ints[x].int_type = 0xff;
929 io_apic_ints[x].int_vector = 0xff;
930 }
931#endif
932
933 /* setup the cpu/apic mapping arrays */
934 boot_cpu_id = -1;
935
936 /* record whether PIC or virtual-wire mode */
937 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
938
939 /* check for use of 'default' configuration */
940 if (mpfps->mpfb1 != 0)
941 return mpfps->mpfb1; /* return default configuration type */
942
bfc09ba0 943 if (mpfps->pap == 0)
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944 panic("MP Configuration Table Header MISSING!");
945
bfc09ba0 946 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
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947 /* walk the table, recording info of interest */
948 totalSize = cth->base_table_length - sizeof(struct MPCTH);
949 position = (u_char *) cth + sizeof(struct MPCTH);
950 count = cth->entry_count;
951 apic = bus = intr = 0;
952 cpu = 1; /* pre-count the BSP */
953
954 while (count--) {
955 switch (type = *(u_char *) position) {
956 case 0:
957 if (processor_entry(position, cpu))
958 ++cpu;
959
960 if (need_hyperthreading_fixup) {
961 /*
962 * Create fake mptable processor entries
963 * and feed them to processor_entry() to
964 * enumerate the logical CPUs.
965 */
966 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
967 for (i = 1; i < logical_cpus; i++) {
968 proc.apic_id++;
969 processor_entry(&proc, cpu);
970 logical_cpus_mask |= (1 << cpu);
971 cpu++;
972 }
973 }
974 break;
975 case 1:
976 if (bus_entry(position, bus))
977 ++bus;
978 break;
979 case 2:
980#ifdef APIC_IO
981 if (io_apic_entry(position, apic))
982 ++apic;
983#endif
984 break;
985 case 3:
986#ifdef APIC_IO
987 if (int_entry(position, intr))
988 ++intr;
989#endif
990 break;
991 case 4:
992 /* int_entry(position); */
993 break;
994 default:
995 panic("mpfps Base Table HOSED!");
996 /* NOTREACHED */
997 }
998
999 totalSize -= basetable_entry_types[type].length;
1000 position = (uint8_t *)position + basetable_entry_types[type].length;
1001 }
1002
1003 if (boot_cpu_id == -1)
1004 panic("NO BSP found!");
1005
1006 /* report fact that its NOT a default configuration */
1007 return 0;
1008}
1009
1010/*
1011 * Check if we should perform a hyperthreading "fix-up" to
1012 * enumerate any logical CPU's that aren't already listed
1013 * in the table.
1014 *
1015 * XXX: We assume that all of the physical CPUs in the
1016 * system have the same number of logical CPUs.
1017 *
1018 * XXX: We assume that APIC ID's are allocated such that
1019 * the APIC ID's for a physical processor are aligned
1020 * with the number of logical CPU's in the processor.
1021 */
1022static void
1023mptable_hyperthread_fixup(u_int id_mask)
1024{
1025 u_int i, id;
1026
1027 /* Nothing to do if there is no HTT support. */
1028 if ((cpu_feature & CPUID_HTT) == 0)
1029 return;
1030 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1031 if (logical_cpus <= 1)
1032 return;
1033
1034 /*
1035 * For each APIC ID of a CPU that is set in the mask,
1036 * scan the other candidate APIC ID's for this
1037 * physical processor. If any of those ID's are
1038 * already in the table, then kill the fixup.
1039 */
1040 for (id = 0; id <= MAXCPU; id++) {
1041 if ((id_mask & 1 << id) == 0)
1042 continue;
1043 /* First, make sure we are on a logical_cpus boundary. */
1044 if (id % logical_cpus != 0)
1045 return;
1046 for (i = id + 1; i < id + logical_cpus; i++)
1047 if ((id_mask & 1 << i) != 0)
1048 return;
1049 }
1050
1051 /*
1052 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1053 * mp_naps right now.
1054 */
1055 need_hyperthreading_fixup = 1;
1056 mp_naps *= logical_cpus;
1057}
1058
1059#ifdef APIC_IO
1060
1061void
1062assign_apic_irq(int apic, int intpin, int irq)
1063{
1064 int x;
1065
1066 if (int_to_apicintpin[irq].ioapic != -1)
1067 panic("assign_apic_irq: inconsistent table");
1068
1069 int_to_apicintpin[irq].ioapic = apic;
1070 int_to_apicintpin[irq].int_pin = intpin;
1071 int_to_apicintpin[irq].apic_address = ioapic[apic];
1072 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1073
1074 for (x = 0; x < nintrs; x++) {
1075 if ((io_apic_ints[x].int_type == 0 ||
1076 io_apic_ints[x].int_type == 3) &&
1077 io_apic_ints[x].int_vector == 0xff &&
1078 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1079 io_apic_ints[x].dst_apic_int == intpin)
1080 io_apic_ints[x].int_vector = irq;
1081 }
1082}
1083
1084void
1085revoke_apic_irq(int irq)
1086{
1087 int x;
1088 int oldapic;
1089 int oldintpin;
1090
1091 if (int_to_apicintpin[irq].ioapic == -1)
1092 panic("revoke_apic_irq: inconsistent table");
1093
1094 oldapic = int_to_apicintpin[irq].ioapic;
1095 oldintpin = int_to_apicintpin[irq].int_pin;
1096
1097 int_to_apicintpin[irq].ioapic = -1;
1098 int_to_apicintpin[irq].int_pin = 0;
1099 int_to_apicintpin[irq].apic_address = NULL;
1100 int_to_apicintpin[irq].redirindex = 0;
1101
1102 for (x = 0; x < nintrs; x++) {
1103 if ((io_apic_ints[x].int_type == 0 ||
1104 io_apic_ints[x].int_type == 3) &&
1105 io_apic_ints[x].int_vector != 0xff &&
1106 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1107 io_apic_ints[x].dst_apic_int == oldintpin)
1108 io_apic_ints[x].int_vector = 0xff;
1109 }
1110}
1111
1112/*
1113 * Allocate an IRQ
1114 */
1115static void
1116allocate_apic_irq(int intr)
1117{
1118 int apic;
1119 int intpin;
1120 int irq;
1121
1122 if (io_apic_ints[intr].int_vector != 0xff)
1123 return; /* Interrupt handler already assigned */
1124
1125 if (io_apic_ints[intr].int_type != 0 &&
1126 (io_apic_ints[intr].int_type != 3 ||
1127 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1128 io_apic_ints[intr].dst_apic_int == 0)))
1129 return; /* Not INT or ExtInt on != (0, 0) */
1130
1131 irq = 0;
1132 while (irq < APIC_INTMAPSIZE &&
1133 int_to_apicintpin[irq].ioapic != -1)
1134 irq++;
1135
1136 if (irq >= APIC_INTMAPSIZE)
1137 return; /* No free interrupt handlers */
1138
1139 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1140 intpin = io_apic_ints[intr].dst_apic_int;
1141
1142 assign_apic_irq(apic, intpin, irq);
46d4e165
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1143}
1144
1145
1146static void
1147swap_apic_id(int apic, int oldid, int newid)
1148{
1149 int x;
1150 int oapic;
1151
1152
1153 if (oldid == newid)
1154 return; /* Nothing to do */
1155
1156 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1157 apic, oldid, newid);
1158
1159 /* Swap physical APIC IDs in interrupt entries */
1160 for (x = 0; x < nintrs; x++) {
1161 if (io_apic_ints[x].dst_apic_id == oldid)
1162 io_apic_ints[x].dst_apic_id = newid;
1163 else if (io_apic_ints[x].dst_apic_id == newid)
1164 io_apic_ints[x].dst_apic_id = oldid;
1165 }
1166
1167 /* Swap physical APIC IDs in IO_TO_ID mappings */
1168 for (oapic = 0; oapic < mp_napics; oapic++)
1169 if (IO_TO_ID(oapic) == newid)
1170 break;
1171
1172 if (oapic < mp_napics) {
1173 kprintf("Changing APIC ID for IO APIC #%d from "
1174 "%d to %d in MP table\n",
1175 oapic, newid, oldid);
1176 IO_TO_ID(oapic) = oldid;
1177 }
1178 IO_TO_ID(apic) = newid;
1179}
1180
1181
1182static void
1183fix_id_to_io_mapping(void)
1184{
1185 int x;
1186
1187 for (x = 0; x < NAPICID; x++)
1188 ID_TO_IO(x) = -1;
1189
1190 for (x = 0; x <= mp_naps; x++)
1191 if (CPU_TO_ID(x) < NAPICID)
1192 ID_TO_IO(CPU_TO_ID(x)) = x;
1193
1194 for (x = 0; x < mp_napics; x++)
1195 if (IO_TO_ID(x) < NAPICID)
1196 ID_TO_IO(IO_TO_ID(x)) = x;
1197}
1198
1199
1200static int
1201first_free_apic_id(void)
1202{
1203 int freeid, x;
1204
1205 for (freeid = 0; freeid < NAPICID; freeid++) {
1206 for (x = 0; x <= mp_naps; x++)
1207 if (CPU_TO_ID(x) == freeid)
1208 break;
1209 if (x <= mp_naps)
1210 continue;
1211 for (x = 0; x < mp_napics; x++)
1212 if (IO_TO_ID(x) == freeid)
1213 break;
1214 if (x < mp_napics)
1215 continue;
1216 return freeid;
1217 }
1218 return freeid;
1219}
1220
1221
1222static int
1223io_apic_id_acceptable(int apic, int id)
1224{
1225 int cpu; /* Logical CPU number */
1226 int oapic; /* Logical IO APIC number for other IO APIC */
1227
1228 if (id >= NAPICID)
1229 return 0; /* Out of range */
1230
1231 for (cpu = 0; cpu <= mp_naps; cpu++)
1232 if (CPU_TO_ID(cpu) == id)
1233 return 0; /* Conflict with CPU */
1234
1235 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1236 if (IO_TO_ID(oapic) == id)
1237 return 0; /* Conflict with other APIC */
1238
1239 return 1; /* ID is acceptable for IO APIC */
1240}
1241
1242static
1243io_int *
1244io_apic_find_int_entry(int apic, int pin)
1245{
1246 int x;
1247
1248 /* search each of the possible INTerrupt sources */
1249 for (x = 0; x < nintrs; ++x) {
1250 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1251 (pin == io_apic_ints[x].dst_apic_int))
1252 return (&io_apic_ints[x]);
1253 }
1254 return NULL;
1255}
1256
1257#endif
1258
1259/*
1260 * parse an Intel MP specification table
1261 */
1262static void
1263fix_mp_table(void)
1264{
1265 int x;
1266#ifdef APIC_IO
1267 int id;
1268 int apic; /* IO APIC unit number */
1269 int freeid; /* Free physical APIC ID */
1270 int physid; /* Current physical IO APIC ID */
1271 io_int *io14;
1272#endif
1273 int bus_0 = 0; /* Stop GCC warning */
1274 int bus_pci = 0; /* Stop GCC warning */
1275 int num_pci_bus;
1276
1277 /*
1278 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1279 * did it wrong. The MP spec says that when more than 1 PCI bus
1280 * exists the BIOS must begin with bus entries for the PCI bus and use
1281 * actual PCI bus numbering. This implies that when only 1 PCI bus
1282 * exists the BIOS can choose to ignore this ordering, and indeed many
1283 * MP motherboards do ignore it. This causes a problem when the PCI
1284 * sub-system makes requests of the MP sub-system based on PCI bus
1285 * numbers. So here we look for the situation and renumber the
1286 * busses and associated INTs in an effort to "make it right".
1287 */
1288
1289 /* find bus 0, PCI bus, count the number of PCI busses */
1290 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1291 if (bus_data[x].bus_id == 0) {
1292 bus_0 = x;
1293 }
1294 if (bus_data[x].bus_type == PCI) {
1295 ++num_pci_bus;
1296 bus_pci = x;
1297 }
1298 }
1299 /*
1300 * bus_0 == slot of bus with ID of 0
1301 * bus_pci == slot of last PCI bus encountered
1302 */
1303
1304 /* check the 1 PCI bus case for sanity */
1305 /* if it is number 0 all is well */
1306 if (num_pci_bus == 1 &&
1307 bus_data[bus_pci].bus_id != 0) {
1308
1309 /* mis-numbered, swap with whichever bus uses slot 0 */
1310
1311 /* swap the bus entry types */
1312 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1313 bus_data[bus_0].bus_type = PCI;
1314
1315#ifdef APIC_IO
1316 /* swap each relavant INTerrupt entry */
1317 id = bus_data[bus_pci].bus_id;
1318 for (x = 0; x < nintrs; ++x) {
1319 if (io_apic_ints[x].src_bus_id == id) {
1320 io_apic_ints[x].src_bus_id = 0;
1321 }
1322 else if (io_apic_ints[x].src_bus_id == 0) {
1323 io_apic_ints[x].src_bus_id = id;
1324 }
1325 }
1326#endif
1327 }
1328
1329#ifdef APIC_IO
1330 /* Assign IO APIC IDs.
1331 *
1332 * First try the existing ID. If a conflict is detected, try
1333 * the ID in the MP table. If a conflict is still detected, find
1334 * a free id.
1335 *
1336 * We cannot use the ID_TO_IO table before all conflicts has been
1337 * resolved and the table has been corrected.
1338 */
1339 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1340
1341 /* First try to use the value set by the BIOS */
1342 physid = io_apic_get_id(apic);
1343 if (io_apic_id_acceptable(apic, physid)) {
1344 if (IO_TO_ID(apic) != physid)
1345 swap_apic_id(apic, IO_TO_ID(apic), physid);
1346 continue;
1347 }
1348
1349 /* Then check if the value in the MP table is acceptable */
1350 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1351 continue;
1352
1353 /* Last resort, find a free APIC ID and use it */
1354 freeid = first_free_apic_id();
1355 if (freeid >= NAPICID)
1356 panic("No free physical APIC IDs found");
1357
1358 if (io_apic_id_acceptable(apic, freeid)) {
1359 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1360 continue;
1361 }
1362 panic("Free physical APIC ID not usable");
1363 }
1364 fix_id_to_io_mapping();
1365#endif
1366
1367#ifdef APIC_IO
1368 /* detect and fix broken Compaq MP table */
1369 if (apic_int_type(0, 0) == -1) {
1370 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1371 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1372 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1373 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1374 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1375 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1376 nintrs++;
1377 } else if (apic_int_type(0, 0) == 0) {
1378 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1379 for (x = 0; x < nintrs; ++x)
1380 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1381 (0 == io_apic_ints[x].dst_apic_int)) {
1382 io_apic_ints[x].int_type = 3;
1383 io_apic_ints[x].int_vector = 0xff;
1384 break;
1385 }
1386 }
1387
1388 /*
1389 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1390 * controllers universally come in pairs. If IRQ 14 is specified
1391 * as an ISA interrupt, then IRQ 15 had better be too.
1392 *
1393 * [ Shuttle XPC / AMD Athlon X2 ]
1394 * The MPTable is missing an entry for IRQ 15. Note that the
1395 * ACPI table has an entry for both 14 and 15.
1396 */
1397 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1398 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1399 io14 = io_apic_find_int_entry(0, 14);
1400 io_apic_ints[nintrs] = *io14;
1401 io_apic_ints[nintrs].src_bus_irq = 15;
1402 io_apic_ints[nintrs].dst_apic_int = 15;
1403 nintrs++;
1404 }
1405#endif
1406}
1407
1408#ifdef APIC_IO
1409
1410/* Assign low level interrupt handlers */
1411static void
1412setup_apic_irq_mapping(void)
1413{
1414 int x;
1415 int int_vector;
1416
1417 /* Clear array */
1418 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1419 int_to_apicintpin[x].ioapic = -1;
1420 int_to_apicintpin[x].int_pin = 0;
1421 int_to_apicintpin[x].apic_address = NULL;
1422 int_to_apicintpin[x].redirindex = 0;
1423 }
1424
1425 /* First assign ISA/EISA interrupts */
1426 for (x = 0; x < nintrs; x++) {
1427 int_vector = io_apic_ints[x].src_bus_irq;
1428 if (int_vector < APIC_INTMAPSIZE &&
1429 io_apic_ints[x].int_vector == 0xff &&
1430 int_to_apicintpin[int_vector].ioapic == -1 &&
1431 (apic_int_is_bus_type(x, ISA) ||
1432 apic_int_is_bus_type(x, EISA)) &&
1433 io_apic_ints[x].int_type == 0) {
1434 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1435 io_apic_ints[x].dst_apic_int,
1436 int_vector);
1437 }
1438 }
1439
1440 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1441 for (x = 0; x < nintrs; x++) {
1442 if (io_apic_ints[x].dst_apic_int == 0 &&
1443 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1444 io_apic_ints[x].int_vector == 0xff &&
1445 int_to_apicintpin[0].ioapic == -1 &&
1446 io_apic_ints[x].int_type == 3) {
1447 assign_apic_irq(0, 0, 0);
1448 break;
1449 }
1450 }
662f60ef
SZ
1451
1452 /* Assign PCI interrupts */
1453 for (x = 0; x < nintrs; ++x) {
1454 if (io_apic_ints[x].int_type == 0 &&
1455 io_apic_ints[x].int_vector == 0xff &&
1456 apic_int_is_bus_type(x, PCI))
1457 allocate_apic_irq(x);
1458 }
46d4e165
JG
1459}
1460
1461#endif
1462
1463static int
1464processor_entry(proc_entry_ptr entry, int cpu)
1465{
1466 /* check for usability */
1467 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1468 return 0;
1469
1470 if(entry->apic_id >= NAPICID)
1471 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1472 /* check for BSP flag */
1473 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1474 boot_cpu_id = entry->apic_id;
1475 CPU_TO_ID(0) = entry->apic_id;
1476 ID_TO_CPU(entry->apic_id) = 0;
1477 return 0; /* its already been counted */
1478 }
1479
1480 /* add another AP to list, if less than max number of CPUs */
1481 else if (cpu < MAXCPU) {
1482 CPU_TO_ID(cpu) = entry->apic_id;
1483 ID_TO_CPU(entry->apic_id) = cpu;
1484 return 1;
1485 }
1486
1487 return 0;
1488}
1489
1490
1491static int
1492bus_entry(bus_entry_ptr entry, int bus)
1493{
1494 int x;
1495 char c, name[8];
1496
1497 /* encode the name into an index */
1498 for (x = 0; x < 6; ++x) {
1499 if ((c = entry->bus_type[x]) == ' ')
1500 break;
1501 name[x] = c;
1502 }
1503 name[x] = '\0';
1504
1505 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1506 panic("unknown bus type: '%s'", name);
1507
1508 bus_data[bus].bus_id = entry->bus_id;
1509 bus_data[bus].bus_type = x;
1510
1511 return 1;
1512}
1513
1514#ifdef APIC_IO
1515
1516static int
1517io_apic_entry(io_apic_entry_ptr entry, int apic)
1518{
1519 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1520 return 0;
1521
1522 IO_TO_ID(apic) = entry->apic_id;
1523 if (entry->apic_id < NAPICID)
1524 ID_TO_IO(entry->apic_id) = apic;
1525
1526 return 1;
1527}
1528
1529#endif
1530
1531static int
1532lookup_bus_type(char *name)
1533{
1534 int x;
1535
1536 for (x = 0; x < MAX_BUSTYPE; ++x)
1537 if (strcmp(bus_type_table[x].name, name) == 0)
1538 return bus_type_table[x].type;
1539
1540 return UNKNOWN_BUSTYPE;
1541}
1542
1543#ifdef APIC_IO
1544
1545static int
1546int_entry(int_entry_ptr entry, int intr)
1547{
1548 int apic;
1549
1550 io_apic_ints[intr].int_type = entry->int_type;
1551 io_apic_ints[intr].int_flags = entry->int_flags;
1552 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1553 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1554 if (entry->dst_apic_id == 255) {
1555 /* This signal goes to all IO APICS. Select an IO APIC
1556 with sufficient number of interrupt pins */
1557 for (apic = 0; apic < mp_napics; apic++)
1558 if (((io_apic_read(apic, IOAPIC_VER) &
1559 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1560 entry->dst_apic_int)
1561 break;
1562 if (apic < mp_napics)
1563 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1564 else
1565 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1566 } else
1567 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1568 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1569
1570 return 1;
1571}
1572
1573static int
1574apic_int_is_bus_type(int intr, int bus_type)
1575{
1576 int bus;
1577
1578 for (bus = 0; bus < mp_nbusses; ++bus)
1579 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1580 && ((int) bus_data[bus].bus_type == bus_type))
1581 return 1;
1582
1583 return 0;
1584}
1585
1586/*
1587 * Given a traditional ISA INT mask, return an APIC mask.
1588 */
1589u_int
1590isa_apic_mask(u_int isa_mask)
1591{
1592 int isa_irq;
1593 int apic_pin;
1594
1595#if defined(SKIP_IRQ15_REDIRECT)
1596 if (isa_mask == (1 << 15)) {
1597 kprintf("skipping ISA IRQ15 redirect\n");
1598 return isa_mask;
1599 }
1600#endif /* SKIP_IRQ15_REDIRECT */
1601
1602 isa_irq = ffs(isa_mask); /* find its bit position */
1603 if (isa_irq == 0) /* doesn't exist */
1604 return 0;
1605 --isa_irq; /* make it zero based */
1606
1607 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1608 if (apic_pin == -1)
1609 return 0;
1610
1611 return (1 << apic_pin); /* convert pin# to a mask */
1612}
1613
1614/*
1615 * Determine which APIC pin an ISA/EISA INT is attached to.
1616 */
1617#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1618#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1619#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1620#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1621
1622#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1623int
1624isa_apic_irq(int isa_irq)
1625{
1626 int intr;
1627
1628 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1629 if (INTTYPE(intr) == 0) { /* standard INT */
1630 if (SRCBUSIRQ(intr) == isa_irq) {
1631 if (apic_int_is_bus_type(intr, ISA) ||
1632 apic_int_is_bus_type(intr, EISA)) {
1633 if (INTIRQ(intr) == 0xff)
1634 return -1; /* unassigned */
1635 return INTIRQ(intr); /* found */
1636 }
1637 }
1638 }
1639 }
1640 return -1; /* NOT found */
1641}
1642
1643
1644/*
1645 * Determine which APIC pin a PCI INT is attached to.
1646 */
1647#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1648#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1649#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1650int
1651pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1652{
1653 int intr;
1654
1655 --pciInt; /* zero based */
1656
1657 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1658 if ((INTTYPE(intr) == 0) /* standard INT */
1659 && (SRCBUSID(intr) == pciBus)
1660 && (SRCBUSDEVICE(intr) == pciDevice)
1661 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1662 if (apic_int_is_bus_type(intr, PCI)) {
662f60ef
SZ
1663 if (INTIRQ(intr) == 0xff) {
1664 kprintf("IOAPIC: pci_apic_irq() "
1665 "failed\n");
46d4e165 1666 return -1; /* unassigned */
662f60ef 1667 }
46d4e165
JG
1668 return INTIRQ(intr); /* exact match */
1669 }
1670 }
1671 }
1672
1673 return -1; /* NOT found */
1674}
1675
1676int
1677next_apic_irq(int irq)
1678{
1679 int intr, ointr;
1680 int bus, bustype;
1681
1682 bus = 0;
1683 bustype = 0;
1684 for (intr = 0; intr < nintrs; intr++) {
1685 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1686 continue;
1687 bus = SRCBUSID(intr);
1688 bustype = apic_bus_type(bus);
1689 if (bustype != ISA &&
1690 bustype != EISA &&
1691 bustype != PCI)
1692 continue;
1693 break;
1694 }
1695 if (intr >= nintrs) {
1696 return -1;
1697 }
1698 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1699 if (INTTYPE(ointr) != 0)
1700 continue;
1701 if (bus != SRCBUSID(ointr))
1702 continue;
1703 if (bustype == PCI) {
1704 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1705 continue;
1706 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1707 continue;
1708 }
1709 if (bustype == ISA || bustype == EISA) {
1710 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1711 continue;
1712 }
1713 if (INTPIN(intr) == INTPIN(ointr))
1714 continue;
1715 break;
1716 }
1717 if (ointr >= nintrs) {
1718 return -1;
1719 }
1720 return INTIRQ(ointr);
1721}
1722#undef SRCBUSLINE
1723#undef SRCBUSDEVICE
1724#undef SRCBUSID
1725#undef SRCBUSIRQ
1726
1727#undef INTPIN
1728#undef INTIRQ
1729#undef INTAPIC
1730#undef INTTYPE
1731
1732#endif
1733
1734/*
1735 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1736 *
1737 * XXX FIXME:
1738 * Exactly what this means is unclear at this point. It is a solution
1739 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1740 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1741 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1742 * option.
1743 */
1744int
1745undirect_isa_irq(int rirq)
1746{
1747#if defined(READY)
1748 if (bootverbose)
1749 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1750 /** FIXME: tickle the MB redirector chip */
1751 return /* XXX */;
1752#else
1753 if (bootverbose)
1754 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1755 return 0;
1756#endif /* READY */
1757}
1758
1759
1760/*
1761 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1762 */
1763int
1764undirect_pci_irq(int rirq)
1765{
1766#if defined(READY)
1767 if (bootverbose)
1768 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1769
1770 /** FIXME: tickle the MB redirector chip */
1771 return /* XXX */;
1772#else
1773 if (bootverbose)
1774 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1775 rirq);
1776 return 0;
1777#endif /* READY */
1778}
1779
1780
1781/*
1782 * given a bus ID, return:
1783 * the bus type if found
1784 * -1 if NOT found
1785 */
1786int
1787apic_bus_type(int id)
1788{
1789 int x;
1790
1791 for (x = 0; x < mp_nbusses; ++x)
1792 if (bus_data[x].bus_id == id)
1793 return bus_data[x].bus_type;
1794
1795 return -1;
1796}
1797
1798#ifdef APIC_IO
1799
1800/*
1801 * given a LOGICAL APIC# and pin#, return:
1802 * the associated src bus ID if found
1803 * -1 if NOT found
1804 */
1805int
1806apic_src_bus_id(int apic, int pin)
1807{
1808 int x;
1809
1810 /* search each of the possible INTerrupt sources */
1811 for (x = 0; x < nintrs; ++x)
1812 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1813 (pin == io_apic_ints[x].dst_apic_int))
1814 return (io_apic_ints[x].src_bus_id);
1815
1816 return -1; /* NOT found */
1817}
1818
1819/*
1820 * given a LOGICAL APIC# and pin#, return:
1821 * the associated src bus IRQ if found
1822 * -1 if NOT found
1823 */
1824int
1825apic_src_bus_irq(int apic, int pin)
1826{
1827 int x;
1828
1829 for (x = 0; x < nintrs; x++)
1830 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1831 (pin == io_apic_ints[x].dst_apic_int))
1832 return (io_apic_ints[x].src_bus_irq);
1833
1834 return -1; /* NOT found */
1835}
1836
1837
1838/*
1839 * given a LOGICAL APIC# and pin#, return:
1840 * the associated INTerrupt type if found
1841 * -1 if NOT found
1842 */
1843int
1844apic_int_type(int apic, int pin)
1845{
1846 int x;
1847
1848 /* search each of the possible INTerrupt sources */
1849 for (x = 0; x < nintrs; ++x) {
1850 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1851 (pin == io_apic_ints[x].dst_apic_int))
1852 return (io_apic_ints[x].int_type);
1853 }
1854 return -1; /* NOT found */
1855}
1856
1857/*
1858 * Return the IRQ associated with an APIC pin
1859 */
1860int
1861apic_irq(int apic, int pin)
1862{
1863 int x;
1864 int res;
1865
1866 for (x = 0; x < nintrs; ++x) {
1867 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1868 (pin == io_apic_ints[x].dst_apic_int)) {
1869 res = io_apic_ints[x].int_vector;
1870 if (res == 0xff)
1871 return -1;
1872 if (apic != int_to_apicintpin[res].ioapic)
1873 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1874 if (pin != int_to_apicintpin[res].int_pin)
1875 panic("apic_irq inconsistent table (2)");
1876 return res;
1877 }
1878 }
1879 return -1;
1880}
1881
1882
1883/*
1884 * given a LOGICAL APIC# and pin#, return:
1885 * the associated trigger mode if found
1886 * -1 if NOT found
1887 */
1888int
1889apic_trigger(int apic, int pin)
1890{
1891 int x;
1892
1893 /* search each of the possible INTerrupt sources */
1894 for (x = 0; x < nintrs; ++x)
1895 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1896 (pin == io_apic_ints[x].dst_apic_int))
1897 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1898
1899 return -1; /* NOT found */
1900}
1901
1902
1903/*
1904 * given a LOGICAL APIC# and pin#, return:
1905 * the associated 'active' level if found
1906 * -1 if NOT found
1907 */
1908int
1909apic_polarity(int apic, int pin)
1910{
1911 int x;
1912
1913 /* search each of the possible INTerrupt sources */
1914 for (x = 0; x < nintrs; ++x)
1915 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1916 (pin == io_apic_ints[x].dst_apic_int))
1917 return (io_apic_ints[x].int_flags & 0x03);
1918
1919 return -1; /* NOT found */
1920}
1921
1922#endif
1923
1924/*
1925 * set data according to MP defaults
1926 * FIXME: probably not complete yet...
1927 */
1928static void
1929default_mp_table(int type)
1930{
1931 int ap_cpu_id;
1932#if defined(APIC_IO)
1933 int io_apic_id;
1934 int pin;
1935#endif /* APIC_IO */
1936
1937#if 0
1938 kprintf(" MP default config type: %d\n", type);
1939 switch (type) {
1940 case 1:
1941 kprintf(" bus: ISA, APIC: 82489DX\n");
1942 break;
1943 case 2:
1944 kprintf(" bus: EISA, APIC: 82489DX\n");
1945 break;
1946 case 3:
1947 kprintf(" bus: EISA, APIC: 82489DX\n");
1948 break;
1949 case 4:
1950 kprintf(" bus: MCA, APIC: 82489DX\n");
1951 break;
1952 case 5:
1953 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1954 break;
1955 case 6:
1956 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1957 break;
1958 case 7:
1959 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1960 break;
1961 default:
1962 kprintf(" future type\n");
1963 break;
1964 /* NOTREACHED */
1965 }
1966#endif /* 0 */
1967
1968 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1969 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1970
1971 /* BSP */
1972 CPU_TO_ID(0) = boot_cpu_id;
1973 ID_TO_CPU(boot_cpu_id) = 0;
1974
1975 /* one and only AP */
1976 CPU_TO_ID(1) = ap_cpu_id;
1977 ID_TO_CPU(ap_cpu_id) = 1;
1978
1979#if defined(APIC_IO)
1980 /* one and only IO APIC */
1981 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1982
1983 /*
1984 * sanity check, refer to MP spec section 3.6.6, last paragraph
1985 * necessary as some hardware isn't properly setting up the IO APIC
1986 */
1987#if defined(REALLY_ANAL_IOAPICID_VALUE)
1988 if (io_apic_id != 2) {
1989#else
1990 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1991#endif /* REALLY_ANAL_IOAPICID_VALUE */
1992 io_apic_set_id(0, 2);
1993 io_apic_id = 2;
1994 }
1995 IO_TO_ID(0) = io_apic_id;
1996 ID_TO_IO(io_apic_id) = 0;
1997#endif /* APIC_IO */
1998
1999 /* fill out bus entries */
2000 switch (type) {
2001 case 1:
2002 case 2:
2003 case 3:
2004 case 4:
2005 case 5:
2006 case 6:
2007 case 7:
2008 bus_data[0].bus_id = default_data[type - 1][1];
2009 bus_data[0].bus_type = default_data[type - 1][2];
2010 bus_data[1].bus_id = default_data[type - 1][3];
2011 bus_data[1].bus_type = default_data[type - 1][4];
2012 break;
2013
2014 /* case 4: case 7: MCA NOT supported */
2015 default: /* illegal/reserved */
2016 panic("BAD default MP config: %d", type);
2017 /* NOTREACHED */
2018 }
2019
2020#if defined(APIC_IO)
2021 /* general cases from MP v1.4, table 5-2 */
2022 for (pin = 0; pin < 16; ++pin) {
2023 io_apic_ints[pin].int_type = 0;
2024 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2025 io_apic_ints[pin].src_bus_id = 0;
2026 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2027 io_apic_ints[pin].dst_apic_id = io_apic_id;
2028 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2029 }
2030
2031 /* special cases from MP v1.4, table 5-2 */
2032 if (type == 2) {
2033 io_apic_ints[2].int_type = 0xff; /* N/C */
2034 io_apic_ints[13].int_type = 0xff; /* N/C */
2035#if !defined(APIC_MIXED_MODE)
2036 /** FIXME: ??? */
2037 panic("sorry, can't support type 2 default yet");
2038#endif /* APIC_MIXED_MODE */
2039 }
2040 else
2041 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2042
2043 if (type == 7)
2044 io_apic_ints[0].int_type = 0xff; /* N/C */
2045 else
2046 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2047#endif /* APIC_IO */
2048}
2049
2050/*
2051 * Map a physical memory address representing I/O into KVA. The I/O
2052 * block is assumed not to cross a page boundary.
2053 */
2054void *
2055permanent_io_mapping(vm_paddr_t pa)
2056{
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2057 KKASSERT(pa < 0x100000000LL);
2058
403c36ea 2059 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
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JG
2060}
2061
2062/*
2063 * start each AP in our list
2064 */
2065static int
2066start_all_aps(u_int boot_addr)
2067{
2068 vm_offset_t va = boot_address + KERNBASE;
2069 u_int64_t *pt4, *pt3, *pt2;
2070 int x, i, pg;
2071 int shift;
bb467734
MD
2072 int smicount;
2073 int smibest;
2074 int smilast;
46d4e165
JG
2075 u_char mpbiosreason;
2076 u_long mpbioswarmvec;
2077 struct mdglobaldata *gd;
2078 struct privatespace *ps;
46d4e165
JG
2079
2080 POSTCODE(START_ALL_APS_POST);
2081
2082 /* Initialize BSP's local APIC */
2083 apic_initialize(TRUE);
2084 bsp_apic_ready = 1;
2085
2086 /* install the AP 1st level boot code */
2087 pmap_kenter(va, boot_address);
bfc09ba0 2088 cpu_invlpg((void *)va); /* JG XXX */
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2089 bcopy(mptramp_start, (void *)va, bootMP_size);
2090
2091 /* Locate the page tables, they'll be below the trampoline */
2092 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2093 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2094 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2095
2096 /* Create the initial 1GB replicated page tables */
2097 for (i = 0; i < 512; i++) {
2098 /* Each slot of the level 4 pages points to the same level 3 page */
2099 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2100 pt4[i] |= PG_V | PG_RW | PG_U;
2101
2102 /* Each slot of the level 3 pages points to the same level 2 page */
2103 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2104 pt3[i] |= PG_V | PG_RW | PG_U;
2105
2106 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2107 pt2[i] = i * (2 * 1024 * 1024);
2108 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2109 }
2110
2111 /* save the current value of the warm-start vector */
2112 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2113 outb(CMOS_REG, BIOS_RESET);
2114 mpbiosreason = inb(CMOS_DATA);
2115
2116 /* setup a vector to our boot code */
2117 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2118 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2119 outb(CMOS_REG, BIOS_RESET);
2120 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2121
bb467734
MD
2122 /*
2123 * If we have a TSC we can figure out the SMI interrupt rate.
2124 * The SMI does not necessarily use a constant rate. Spend
2125 * up to 250ms trying to figure it out.
2126 */
2127 smibest = 0;
2128 if (cpu_feature & CPUID_TSC) {
2129 set_apic_timer(275000);
2130 smilast = read_apic_timer();
2131 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2132 smicount = smitest();
2133 if (smibest == 0 || smilast - smicount < smibest)
2134 smibest = smilast - smicount;
2135 smilast = smicount;
2136 }
2137 if (smibest > 250000)
2138 smibest = 0;
2139 if (smibest) {
2140 smibest = smibest * (int64_t)1000000 /
2141 get_apic_timer_frequency();
2142 }
2143 }
2144 if (smibest)
2145 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2146 1000000 / smibest, smibest);
2147
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2148 /* start each AP */
2149 for (x = 1; x <= mp_naps; ++x) {
2150
2151 /* This is a bit verbose, it will go away soon. */
2152
2153 /* first page of AP's private space */
b2b3ffcd 2154 pg = x * x86_64_btop(sizeof(struct privatespace));
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2155
2156 /* allocate new private data page(s) */
2157 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2158 MDGLOBALDATA_BASEALLOC_SIZE);
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2159
2160 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2161 bzero(gd, sizeof(*gd));
2162 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2163
2164 /* prime data page for it to use */
2165 mi_gdinit(&gd->mi, x);
2166 cpu_gdinit(gd, x);
2167 gd->gd_CMAP1 = &SMPpt[pg + 0];
2168 gd->gd_CMAP2 = &SMPpt[pg + 1];
2169 gd->gd_CMAP3 = &SMPpt[pg + 2];
2170 gd->gd_PMAP1 = &SMPpt[pg + 3];
2171 gd->gd_CADDR1 = ps->CPAGE1;
2172 gd->gd_CADDR2 = ps->CPAGE2;
2173 gd->gd_CADDR3 = ps->CPAGE3;
bfc09ba0 2174 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
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2175 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2176 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2177
2178 /* setup a vector to our boot code */
2179 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2180 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2181 outb(CMOS_REG, BIOS_RESET);
2182 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2183
2184 /*
2185 * Setup the AP boot stack
2186 */
2187 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2188 bootAP = x;
2189
2190 /* attempt to start the Application Processor */
2191 CHECK_INIT(99); /* setup checkpoints */
bb467734 2192 if (!start_ap(gd, boot_addr, smibest)) {
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2193 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2194 CHECK_PRINT("trace"); /* show checkpoints */
2195 /* better panic as the AP may be running loose */
2196 kprintf("panic y/n? [y] ");
2197 if (cngetc() != 'n')
2198 panic("bye-bye");
2199 }
2200 CHECK_PRINT("trace"); /* show checkpoints */
2201
2202 /* record its version info */
2203 cpu_apic_versions[x] = cpu_apic_versions[0];
2204 }
2205
2206 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2207 ncpus = x;
2208
2209 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2210 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2211 ;
2212 --shift;
2213 ncpus2_shift = shift;
2214 ncpus2 = 1 << shift;
2215 ncpus2_mask = ncpus2 - 1;
2216
2217 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2218 if ((1 << shift) < ncpus)
2219 ++shift;
2220 ncpus_fit = 1 << shift;
2221 ncpus_fit_mask = ncpus_fit - 1;
2222
2223 /* build our map of 'other' CPUs */
2224 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2225 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2226 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2227
2228 /* fill in our (BSP) APIC version */
2229 cpu_apic_versions[0] = lapic->version;
2230
2231 /* restore the warmstart vector */
2232 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2233 outb(CMOS_REG, BIOS_RESET);
2234 outb(CMOS_DATA, mpbiosreason);
2235
2236 /*
2237 * NOTE! The idlestack for the BSP was setup by locore. Finish
2238 * up, clean out the P==V mapping we did earlier.
2239 */
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2240 pmap_set_opt();
2241
2242 /* number of APs actually started */
2243 return ncpus - 1;
2244}
2245
2246
2247/*
2248 * load the 1st level AP boot code into base memory.
2249 */
2250
2251/* targets for relocation */
2252extern void bigJump(void);
2253extern void bootCodeSeg(void);
2254extern void bootDataSeg(void);
2255extern void MPentry(void);
2256extern u_int MP_GDT;
2257extern u_int mp_gdtbase;
2258
bfc09ba0
MD
2259#if 0
2260
46d4e165
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2261static void
2262install_ap_tramp(u_int boot_addr)
2263{
2264 int x;
2265 int size = *(int *) ((u_long) & bootMP_size);
2266 u_char *src = (u_char *) ((u_long) bootMP);
2267 u_char *dst = (u_char *) boot_addr + KERNBASE;
2268 u_int boot_base = (u_int) bootMP;
2269 u_int8_t *dst8;
2270 u_int16_t *dst16;
2271 u_int32_t *dst32;
2272
2273 POSTCODE(INSTALL_AP_TRAMP_POST);
2274
2275 for (x = 0; x < size; ++x)
2276 *dst++ = *src++;
2277
2278 /*
2279 * modify addresses in code we just moved to basemem. unfortunately we
2280 * need fairly detailed info about mpboot.s for this to work. changes
2281 * to mpboot.s might require changes here.
2282 */
2283
2284 /* boot code is located in KERNEL space */
2285 dst = (u_char *) boot_addr + KERNBASE;
2286
2287 /* modify the lgdt arg */
2288 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2289 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2290
2291 /* modify the ljmp target for MPentry() */
2292 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2293 *dst32 = ((u_int) MPentry - KERNBASE);
2294
2295 /* modify the target for boot code segment */
2296 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2297 dst8 = (u_int8_t *) (dst16 + 1);
2298 *dst16 = (u_int) boot_addr & 0xffff;
2299 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2300
2301 /* modify the target for boot data segment */
2302 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2303 dst8 = (u_int8_t *) (dst16 + 1);
2304 *dst16 = (u_int) boot_addr & 0xffff;
2305 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2306}
2307
bfc09ba0 2308#endif
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2309
2310/*
bb467734 2311 * This function starts the AP (application processor) identified
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2312 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2313 * to accomplish this. This is necessary because of the nuances
2314 * of the different hardware we might encounter. It ain't pretty,
2315 * but it seems to work.
2316 *
2317 * NOTE: eventually an AP gets to ap_init(), which is called just
2318 * before the AP goes into the LWKT scheduler's idle loop.
2319 */
2320static int
bb467734 2321start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
46d4e165
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2322{
2323 int physical_cpu;
2324 int vector;
2325 u_long icr_lo, icr_hi;
2326
2327 POSTCODE(START_AP_POST);
2328
2329 /* get the PHYSICAL APIC ID# */
2330 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2331
2332 /* calculate the vector */
2333 vector = (boot_addr >> 12) & 0xff;
2334
bb467734
MD
2335 /* We don't want anything interfering */
2336 cpu_disable_intr();
2337
46d4e165
JG
2338 /* Make sure the target cpu sees everything */
2339 wbinvd();
2340
2341 /*
bb467734
MD
2342 * Try to detect when a SMI has occurred, wait up to 200ms.
2343 *
2344 * If a SMI occurs during an AP reset but before we issue
2345 * the STARTUP command, the AP may brick. To work around
2346 * this problem we hold off doing the AP startup until
2347 * after we have detected the SMI. Hopefully another SMI
2348 * will not occur before we finish the AP startup.
2349 *
2350 * Retries don't seem to help. SMIs have a window of opportunity
2351 * and if USB->legacy keyboard emulation is enabled in the BIOS
2352 * the interrupt rate can be quite high.
2353 *
2354 * NOTE: Don't worry about the L1 cache load, it might bloat
2355 * ldelta a little but ndelta will be so huge when the SMI
2356 * occurs the detection logic will still work fine.
2357 */
2358 if (smibest) {
2359 set_apic_timer(200000);
2360 smitest();
2361 }
2362
2363 /*
46d4e165
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2364 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2365 * and running the target CPU. OR this INIT IPI might be latched (P5
2366 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2367 * ignored.
bb467734
MD
2368 *
2369 * see apic/apicreg.h for icr bit definitions.
2370 *
2371 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
46d4e165
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2372 */
2373
bb467734
MD
2374 /*
2375 * Setup the address for the target AP. We can setup
2376 * icr_hi once and then just trigger operations with
2377 * icr_lo.
2378 */
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2379 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2380 icr_hi |= (physical_cpu << 24);
46d4e165 2381 icr_lo = lapic->icr_lo & 0xfff00000;
bb467734 2382 lapic->icr_hi = icr_hi;
46d4e165 2383
bb467734
MD
2384 /*
2385 * Do an INIT IPI: assert RESET
2386 *
2387 * Use edge triggered mode to assert INIT
2388 */
2389 lapic->icr_lo = icr_lo | 0x00004500;
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2390 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2391 /* spin */ ;
2392
bb467734
MD
2393 /*
2394 * The spec calls for a 10ms delay but we may have to use a
2395 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2396 * interrupt. We have other loops here too and dividing by 2
2397 * doesn't seem to be enough even after subtracting 350us,
2398 * so we divide by 4.
2399 *
2400 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2401 * interrupt was detected we use the full 10ms.
2402 */
2403 if (smibest == 0)
2404 u_sleep(10000);
2405 else if (smibest < 150 * 4 + 350)
2406 u_sleep(150);
2407 else if ((smibest - 350) / 4 < 10000)
2408 u_sleep((smibest - 350) / 4);
2409 else
2410 u_sleep(10000);
46d4e165 2411
bb467734
MD
2412 /*
2413 * Do an INIT IPI: deassert RESET
2414 *
2415 * Use level triggered mode to deassert. It is unclear
2416 * why we need to do this.
2417 */
2418 lapic->icr_lo = icr_lo | 0x00008500;
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2419 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2420 /* spin */ ;
bb467734 2421 u_sleep(150); /* wait 150us */
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2422
2423 /*
bb467734 2424 * Next we do a STARTUP IPI: the previous INIT IPI might still be
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2425 * latched, (P5 bug) this 1st STARTUP would then terminate
2426 * immediately, and the previously started INIT IPI would continue. OR
2427 * the previous INIT IPI has already run. and this STARTUP IPI will
2428 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2429 * will run.
2430 */
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2431 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2432 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2433 /* spin */ ;
2434 u_sleep(200); /* wait ~200uS */
2435
2436 /*
bb467734 2437 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
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2438 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2439 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2440 * recognized after hardware RESET or INIT IPI.
2441 */
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2442 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2443 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2444 /* spin */ ;
bb467734
MD
2445
2446 /* Resume normal operation */
2447 cpu_enable_intr();
46d4e165
JG
2448
2449 /* wait for it to start, see ap_init() */
2450 set_apic_timer(5000000);/* == 5 seconds */
2451 while (read_apic_timer()) {
2452 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2453 return 1; /* return SUCCESS */
2454 }
bb467734 2455
46d4e165
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2456 return 0; /* return FAILURE */
2457}
2458
bb467734
MD
2459static
2460int
2461smitest(void)
2462{
2463 int64_t ltsc;
2464 int64_t ntsc;
2465 int64_t ldelta;
2466 int64_t ndelta;
2467 int count;
2468
2469 ldelta = 0;
2470 ndelta = 0;
2471 while (read_apic_timer()) {
2472 ltsc = rdtsc();
2473 for (count = 0; count < 100; ++count)
2474 ntsc = rdtsc(); /* force loop to occur */
2475 if (ldelta) {
2476 ndelta = ntsc - ltsc;
2477 if (ldelta > ndelta)
2478 ldelta = ndelta;
2479 if (ndelta > ldelta * 2)
2480 break;
2481 } else {
2482 ldelta = ntsc - ltsc;
2483 }
2484 }
2485 return(read_apic_timer());
2486}
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2487
2488/*
2489 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2490 *
2491 * If for some reason we were unable to start all cpus we cannot safely
2492 * use broadcast IPIs.
2493 */
2494void
2495smp_invltlb(void)
2496{
2497#ifdef SMP
2498 if (smp_startup_mask == smp_active_mask) {
2499 all_but_self_ipi(XINVLTLB_OFFSET);
2500 } else {
2501 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2502 APIC_DELMODE_FIXED);
2503 }
2504#endif
2505}
2506
2507/*
2508 * When called the executing CPU will send an IPI to all other CPUs
2509 * requesting that they halt execution.
2510 *
2511 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2512 *
2513 * - Signals all CPUs in map to stop.
2514 * - Waits for each to stop.
2515 *
2516 * Returns:
2517 * -1: error
2518 * 0: NA
2519 * 1: ok
2520 *
2521 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2522 * from executing at same time.
2523 */
2524int
2525stop_cpus(u_int map)
2526{
2527 map &= smp_active_mask;
2528
2529 /* send the Xcpustop IPI to all CPUs in map */
2530 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2531
2532 while ((stopped_cpus & map) != map)
2533 /* spin */ ;
2534
2535 return 1;
2536}
2537
2538
2539/*
2540 * Called by a CPU to restart stopped CPUs.
2541 *
2542 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2543 *
2544 * - Signals all CPUs in map to restart.
2545 * - Waits for each to restart.
2546 *
2547 * Returns:
2548 * -1: error
2549 * 0: NA
2550 * 1: ok
2551 */
2552int
2553restart_cpus(u_int map)
2554{
2555 /* signal other cpus to restart */
2556 started_cpus = map & smp_active_mask;
2557
2558 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2559 /* spin */ ;
2560
2561 return 1;
2562}
2563
2564/*
2565 * This is called once the mpboot code has gotten us properly relocated
2566 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2567 * and when it returns the scheduler will call the real cpu_idle() main
2568 * loop for the idlethread. Interrupts are disabled on entry and should
2569 * remain disabled at return.
2570 */
2571void
2572ap_init(void)
2573{
2574 u_int apic_id;
2575
2576 /*
2577 * Adjust smp_startup_mask to signal the BSP that we have started
2578 * up successfully. Note that we do not yet hold the BGL. The BSP
2579 * is waiting for our signal.
2580 *
2581 * We can't set our bit in smp_active_mask yet because we are holding
2582 * interrupts physically disabled and remote cpus could deadlock
2583 * trying to send us an IPI.
2584 */
2585 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2586 cpu_mfence();
2587
2588 /*
2589 * Interlock for finalization. Wait until mp_finish is non-zero,
2590 * then get the MP lock.
2591 *
2592 * Note: We are in a critical section.
2593 *
2594 * Note: We have to synchronize td_mpcount to our desired MP state
2595 * before calling cpu_try_mplock().
2596 *
2597 * Note: we are the idle thread, we can only spin.
2598 *
2599 * Note: The load fence is memory volatile and prevents the compiler
2600 * from improperly caching mp_finish, and the cpu from improperly
2601 * caching it.
2602 */
2603 while (mp_finish == 0)
2604 cpu_lfence();
2605 ++curthread->td_mpcount;
2606 while (cpu_try_mplock() == 0)
2607 ;
2608
2609 if (cpu_feature & CPUID_TSC) {
2610 /*
2611 * The BSP is constantly updating tsc0_offset, figure out the
2612 * relative difference to synchronize ktrdump.
2613 */
2614 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2615 }
2616
2617 /* BSP may have changed PTD while we're waiting for the lock */
2618 cpu_invltlb();
2619
2620#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2621 lidt(&r_idt);
2622#endif
2623
2624 /* Build our map of 'other' CPUs. */
2625 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2626
2627 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2628
2629 /* A quick check from sanity claus */
2630 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2631 if (mycpu->gd_cpuid != apic_id) {
2632 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2633 kprintf("SMP: apic_id = %d\n", apic_id);
2634#if JGXXX
2635 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2636#endif
2637 panic("cpuid mismatch! boom!!");
2638 }
2639
2640 /* Initialize AP's local APIC for irq's */
2641 apic_initialize(FALSE);
2642
2643 /* Set memory range attributes for this CPU to match the BSP */
2644 mem_range_AP_init();
2645
2646 /*
2647 * Once we go active we must process any IPIQ messages that may
2648 * have been queued, because no actual IPI will occur until we
2649 * set our bit in the smp_active_mask. If we don't the IPI
2650 * message interlock could be left set which would also prevent
2651 * further IPIs.
2652 *
2653 * The idle loop doesn't expect the BGL to be held and while
2654 * lwkt_switch() normally cleans things up this is a special case
2655 * because we returning almost directly into the idle loop.
2656 *
2657 * The idle thread is never placed on the runq, make sure
2658 * nothing we've done put it there.
2659 */
2660 KKASSERT(curthread->td_mpcount == 1);
2661 smp_active_mask |= 1 << mycpu->gd_cpuid;
2662
2663 /*
2664 * Enable interrupts here. idle_restore will also do it, but
2665 * doing it here lets us clean up any strays that got posted to
2666 * the CPU during the AP boot while we are still in a critical
2667 * section.
2668 */
2669 __asm __volatile("sti; pause; pause"::);
2670 mdcpu->gd_fpending = 0;
46d4e165
JG
2671
2672 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2673 lwkt_process_ipiq();
2674
2675 /*
2676 * Releasing the mp lock lets the BSP finish up the SMP init
2677 */
2678 rel_mplock();
2679 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2680}
2681
2682/*
2683 * Get SMP fully working before we start initializing devices.
2684 */
2685static
2686void
2687ap_finish(void)
2688{
2689 mp_finish = 1;
2690 if (bootverbose)
2691 kprintf("Finish MP startup\n");
2692 if (cpu_feature & CPUID_TSC)
2693 tsc0_offset = rdtsc();
2694 tsc_offsets[0] = 0;
2695 rel_mplock();
2696 while (smp_active_mask != smp_startup_mask) {
2697 cpu_lfence();
2698 if (cpu_feature & CPUID_TSC)
2699 tsc0_offset = rdtsc();
2700 }
2701 while (try_mplock() == 0)
2702 ;
2703 if (bootverbose)
2704 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2705}
2706
2707SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2708
2709void
2710cpu_send_ipiq(int dcpu)
2711{
2712 if ((1 << dcpu) & smp_active_mask)
2713 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2714}
2715
2716#if 0 /* single_apic_ipi_passive() not working yet */
2717/*
2718 * Returns 0 on failure, 1 on success
2719 */
2720int
2721cpu_send_ipiq_passive(int dcpu)
2722{
2723 int r = 0;
2724 if ((1 << dcpu) & smp_active_mask) {
2725 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2726 APIC_DELMODE_FIXED);
2727 }
2728 return(r);
2729}
2730#endif
2731