Correct the logical_cpus calculation in mptable_hyperthread_fixup()
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
CommitLineData
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29#include "opt_cpu.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/sysctl.h>
35#include <sys/malloc.h>
36#include <sys/memrange.h>
37#include <sys/cons.h> /* cngetc() */
38#include <sys/machintr.h>
39
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40#include <sys/mplock2.h>
41
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42#include <vm/vm.h>
43#include <vm/vm_param.h>
44#include <vm/pmap.h>
45#include <vm/vm_kern.h>
46#include <vm/vm_extern.h>
47#include <sys/lock.h>
48#include <vm/vm_map.h>
49#include <sys/user.h>
50#ifdef GPROF
51#include <sys/gmon.h>
52#endif
53
54#include <machine/smp.h>
55#include <machine_base/apic/apicreg.h>
56#include <machine/atomic.h>
57#include <machine/cpufunc.h>
58#include <machine_base/apic/mpapic.h>
59#include <machine/psl.h>
60#include <machine/segments.h>
61#include <machine/tss.h>
62#include <machine/specialreg.h>
63#include <machine/globaldata.h>
64
65#include <machine/md_var.h> /* setidt() */
66#include <machine_base/icu/icu.h> /* IPIs */
67#include <machine_base/isa/intr_machdep.h> /* IPIs */
68
69#define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
70
71#define WARMBOOT_TARGET 0
72#define WARMBOOT_OFF (KERNBASE + 0x0467)
73#define WARMBOOT_SEG (KERNBASE + 0x0469)
74
75#define BIOS_BASE (0xf0000)
76#define BIOS_SIZE (0x10000)
77#define BIOS_COUNT (BIOS_SIZE/4)
78
79#define CMOS_REG (0x70)
80#define CMOS_DATA (0x71)
81#define BIOS_RESET (0x0f)
82#define BIOS_WARM (0x0a)
83
84#define PROCENTRY_FLAG_EN 0x01
85#define PROCENTRY_FLAG_BP 0x02
86#define IOAPICENTRY_FLAG_EN 0x01
87
88
89/* MP Floating Pointer Structure */
90typedef struct MPFPS {
91 char signature[4];
92 u_int32_t pap;
93 u_char length;
94 u_char spec_rev;
95 u_char checksum;
96 u_char mpfb1;
97 u_char mpfb2;
98 u_char mpfb3;
99 u_char mpfb4;
100 u_char mpfb5;
101} *mpfps_t;
102
103/* MP Configuration Table Header */
104typedef struct MPCTH {
105 char signature[4];
106 u_short base_table_length;
107 u_char spec_rev;
108 u_char checksum;
109 u_char oem_id[8];
110 u_char product_id[12];
a5f51ef3 111 u_int32_t oem_table_pointer;
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112 u_short oem_table_size;
113 u_short entry_count;
a5f51ef3 114 u_int32_t apic_address;
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115 u_short extended_table_length;
116 u_char extended_table_checksum;
117 u_char reserved;
118} *mpcth_t;
119
120
121typedef struct PROCENTRY {
122 u_char type;
123 u_char apic_id;
124 u_char apic_version;
125 u_char cpu_flags;
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126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
128 u_int32_t reserved1;
129 u_int32_t reserved2;
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130} *proc_entry_ptr;
131
132typedef struct BUSENTRY {
133 u_char type;
134 u_char bus_id;
135 char bus_type[6];
136} *bus_entry_ptr;
137
138typedef struct IOAPICENTRY {
139 u_char type;
140 u_char apic_id;
141 u_char apic_version;
142 u_char apic_flags;
a5f51ef3 143 u_int32_t apic_address;
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144} *io_apic_entry_ptr;
145
146typedef struct INTENTRY {
147 u_char type;
148 u_char int_type;
149 u_short int_flags;
150 u_char src_bus_id;
151 u_char src_bus_irq;
152 u_char dst_apic_id;
153 u_char dst_apic_int;
154} *int_entry_ptr;
155
156/* descriptions of MP basetable entries */
157typedef struct BASETABLE_ENTRY {
158 u_char type;
159 u_char length;
160 char name[16];
161} basetable_entry;
162
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163struct mptable_pos {
164 mpfps_t mp_fps;
165 mpcth_t mp_cth;
166 vm_size_t mp_cth_mapsz;
167};
168
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169/*
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
173 *
174 */
175#if defined(CHECK_POINTS)
176#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178
179#define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
186
187#define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
189 (S), \
190 CHECK_READ(0x34), \
191 CHECK_READ(0x35), \
192 CHECK_READ(0x36), \
193 CHECK_READ(0x37), \
194 CHECK_READ(0x38), \
195 CHECK_READ(0x39));
196
197#else /* CHECK_POINTS */
198
199#define CHECK_INIT(D)
200#define CHECK_PRINT(S)
201
202#endif /* CHECK_POINTS */
203
204/*
205 * Values to send to the POST hardware.
206 */
207#define MP_BOOTADDRESS_POST 0x10
208#define MP_PROBE_POST 0x11
209#define MPTABLE_PASS1_POST 0x12
210
211#define MP_START_POST 0x13
212#define MP_ENABLE_POST 0x14
213#define MPTABLE_PASS2_POST 0x15
214
215#define START_ALL_APS_POST 0x16
216#define INSTALL_AP_TRAMP_POST 0x17
217#define START_AP_POST 0x18
218
219#define MP_ANNOUNCE_POST 0x19
220
221static int need_hyperthreading_fixup;
222static u_int logical_cpus;
223u_int logical_cpus_mask;
224
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225static int madt_probe_test;
226TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
227
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228/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229int current_postcode;
230
231/** XXX FIXME: what system files declare these??? */
232extern struct region_descriptor r_gdt, r_idt;
233
234int bsp_apic_ready = 0; /* flags useability of BSP apic */
235int mp_naps; /* # of Applications processors */
236int mp_nbusses; /* # of busses */
237#ifdef APIC_IO
238int mp_napics; /* # of IO APICs */
239#endif
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240vm_offset_t cpu_apic_address;
241#ifdef APIC_IO
242vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
243u_int32_t *io_apic_versions;
244#endif
245extern int nkpt;
246
247u_int32_t cpu_apic_versions[MAXCPU];
248int64_t tsc0_offset;
249extern int64_t tsc_offsets[];
250
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251extern u_long ebda_addr;
252
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253#ifdef APIC_IO
254struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
255#endif
256
257/*
258 * APIC ID logical/physical mapping structures.
259 * We oversize these to simplify boot-time config.
260 */
261int cpu_num_to_apic_id[NAPICID];
262#ifdef APIC_IO
263int io_num_to_apic_id[NAPICID];
264#endif
265int apic_id_to_logical[NAPICID];
266
267/* AP uses this during bootstrap. Do not staticize. */
268char *bootSTK;
269static int bootAP;
270
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271/*
272 * SMP page table page. Setup by locore to point to a page table
273 * page from which we allocate per-cpu privatespace areas io_apics,
274 * and so forth.
275 */
276
277#define IO_MAPPING_START_INDEX \
278 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
279
280extern pt_entry_t *SMPpt;
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281
282struct pcb stoppcbs[MAXCPU];
283
284extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
285
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286/*
287 * Local data and functions.
288 */
289
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290static u_int boot_address;
291static u_int base_memory;
292static int mp_finish;
293
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294static void mp_enable(u_int boot_addr);
295
f804d15f 296static int mptable_probe(void);
0eaa8172 297static long mptable_search_sig(u_int32_t target, int count);
46d4e165 298static void mptable_hyperthread_fixup(u_int id_mask);
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299static void mptable_pass1(struct mptable_pos *);
300static int mptable_pass2(struct mptable_pos *);
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301static void mptable_default(int type);
302static void mptable_fix(void);
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303static void mptable_map(struct mptable_pos *, vm_paddr_t);
304static void mptable_unmap(struct mptable_pos *);
0eaa8172 305
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306#ifdef APIC_IO
307static void setup_apic_irq_mapping(void);
308static int apic_int_is_bus_type(int intr, int bus_type);
309#endif
310static int start_all_aps(u_int boot_addr);
bfc09ba0 311#if 0
46d4e165 312static void install_ap_tramp(u_int boot_addr);
bfc09ba0 313#endif
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314static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
315static int smitest(void);
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316
317static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
318cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
319SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
320static u_int bootMP_size;
321
322/*
323 * Calculate usable address in base memory for AP trampoline code.
324 */
325u_int
326mp_bootaddress(u_int basemem)
327{
328 POSTCODE(MP_BOOTADDRESS_POST);
329
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330 base_memory = basemem;
331
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332 bootMP_size = mptramp_end - mptramp_start;
333 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
334 if (((basemem * 1024) - boot_address) < bootMP_size)
335 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
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336 /* 3 levels of page table pages */
337 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
338
339 return mptramp_pagetables;
340}
341
342
343/*
344 * Look for an Intel MP spec table (ie, SMP capable hardware).
345 */
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346static int
347mptable_probe(void)
46d4e165 348{
3a918cfd 349 long x;
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350 u_int32_t target;
351
352 /*
353 * Make sure our SMPpt[] page table is big enough to hold all the
354 * mappings we need.
355 */
356 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
357
358 POSTCODE(MP_PROBE_POST);
359
360 /* see if EBDA exists */
927c4c1f 361 if (ebda_addr != 0) {
46d4e165 362 /* search first 1K of EBDA */
927c4c1f 363 target = (u_int32_t)ebda_addr;
0eaa8172 364 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 365 return x;
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366 } else {
367 /* last 1K of base memory, effective 'top of base' passed in */
351254e7 368 target = (u_int32_t)(base_memory - 0x400);
0eaa8172 369 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
351254e7 370 return x;
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371 }
372
373 /* search the BIOS */
351254e7 374 target = (u_int32_t)BIOS_BASE;
0eaa8172 375 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
351254e7 376 return x;
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377
378 /* nothing found */
46d4e165 379 return 0;
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380}
381
382
383/*
384 * Startup the SMP processors.
385 */
386void
387mp_start(void)
388{
389 POSTCODE(MP_START_POST);
a0679cc7 390 mp_enable(boot_address);
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391}
392
393
394/*
395 * Print various information about the SMP system hardware and setup.
396 */
397void
398mp_announce(void)
399{
400 int x;
401
402 POSTCODE(MP_ANNOUNCE_POST);
403
404 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
405 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
406 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
bfc09ba0 407 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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408 for (x = 1; x <= mp_naps; ++x) {
409 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
410 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
bfc09ba0 411 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
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412 }
413
414#if defined(APIC_IO)
415 for (x = 0; x < mp_napics; ++x) {
416 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
417 kprintf(", version: 0x%08x", io_apic_versions[x]);
bcdeeecd 418 kprintf(", at 0x%08lx\n", io_apic_address[x]);
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419 }
420#else
421 kprintf(" Warning: APIC I/O disabled\n");
422#endif /* APIC_IO */
423}
424
425/*
426 * AP cpu's call this to sync up protected mode.
427 *
ec073ddc 428 * WARNING! %gs is not set up on entry. This routine sets up %gs.
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429 */
430void
431init_secondary(void)
432{
433 int gsel_tss;
434 int x, myid = bootAP;
435 u_int64_t msr, cr0;
436 struct mdglobaldata *md;
437 struct privatespace *ps;
438
439 ps = &CPU_prvspace[myid];
440
441 gdt_segs[GPROC0_SEL].ssd_base =
442 (long) &ps->mdglobaldata.gd_common_tss;
443 ps->mdglobaldata.mi.gd_prvspace = ps;
444
445 /* We fill the 32-bit segment descriptors */
446 for (x = 0; x < NGDT; x++) {
447 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
448 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
449 }
450 /* And now a 64-bit one */
451 ssdtosyssd(&gdt_segs[GPROC0_SEL],
452 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
453
454 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
455 r_gdt.rd_base = (long) &gdt[myid * NGDT];
456 lgdt(&r_gdt); /* does magic intra-segment return */
457
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458 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
459 wrmsr(MSR_FSBASE, 0); /* User value */
460 wrmsr(MSR_GSBASE, (u_int64_t)ps);
461 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
462
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463 lidt(&r_idt);
464
465#if 0
466 lldt(_default_ldt);
467 mdcpu->gd_currentldt = _default_ldt;
468#endif
469
470 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
471 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
472
473 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
474
475 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
476#if 0 /* JG XXX */
477 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
478#endif
479 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
480 md->gd_common_tssd = *md->gd_tss_gdt;
481#if 0 /* JG XXX */
482 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
483#endif
484 ltr(gsel_tss);
485
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486 /*
487 * Set to a known state:
488 * Set by mpboot.s: CR0_PG, CR0_PE
489 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
490 */
491 cr0 = rcr0();
492 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
493 load_cr0(cr0);
494
495 /* Set up the fast syscall stuff */
496 msr = rdmsr(MSR_EFER) | EFER_SCE;
497 wrmsr(MSR_EFER, msr);
498 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
499 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
500 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
501 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
502 wrmsr(MSR_STAR, msr);
503 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
504
505 pmap_set_opt(); /* PSE/4MB pages, etc */
506#if JGXXX
507 /* Initialize the PAT MSR. */
508 pmap_init_pat();
509#endif
510
511 /* set up CPU registers and state */
512 cpu_setregs();
513
514 /* set up SSE/NX registers */
515 initializecpu();
516
517 /* set up FPU state on the AP */
518 npxinit(__INITIAL_NPXCW__);
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519
520 /* disable the APIC, just to be SURE */
521 lapic->svr &= ~APIC_SVR_ENABLE;
522
523 /* data returned to BSP */
524 cpu_apic_versions[0] = lapic->version;
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525}
526
527/*******************************************************************
528 * local functions and data
529 */
530
531/*
532 * start the SMP system
533 */
534static void
535mp_enable(u_int boot_addr)
536{
537 int x;
538#if defined(APIC_IO)
539 int apic;
540 u_int ux;
541#endif /* APIC_IO */
91f1c7a4 542 vm_paddr_t mpfps_paddr;
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543
544 POSTCODE(MP_ENABLE_POST);
545
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546 if (madt_probe_test)
547 mpfps_paddr = 0;
548 else
549 mpfps_paddr = mptable_probe();
8e4c6923 550
699b0754 551 if (mpfps_paddr) {
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552 struct mptable_pos mpt;
553
699b0754 554 mptable_map(&mpt, mpfps_paddr);
f592025a 555
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556 /*
557 * We can safely map physical memory into SMPpt after
558 * mptable_pass1() completes.
559 */
560 mptable_pass1(&mpt);
46d4e165 561
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562 if (cpu_apic_address == 0)
563 panic("mp_enable: no local apic!\n");
9ad60dda 564
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565 /* examine the MP table for needed info */
566 x = mptable_pass2(&mpt);
9ad60dda 567
699b0754 568 mptable_unmap(&mpt);
46d4e165 569
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570 /*
571 * can't process default configs till the
572 * CPU APIC is pmapped
573 */
574 if (x)
575 mptable_default(x);
46d4e165 576
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577 /* post scan cleanup */
578 mptable_fix();
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579
580 /*
581 * lapic not mapped yet (pmap_init is called too late)
582 */
583 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
584 sizeof(struct LAPIC));
699b0754 585 } else {
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586 vm_paddr_t madt_paddr;
587 int bsp_apic_id;
588
589 madt_paddr = madt_probe();
590 if (madt_paddr == 0)
699b0754 591 panic("mp_enable: madt_probe failed\n");
46d4e165 592
4ad5917f 593 cpu_apic_address = madt_pass1(madt_paddr);
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594 if (cpu_apic_address == 0)
595 panic("mp_enable: no local apic (madt)!\n");
4ad5917f 596
ff76b364 597 /*
e3dd742d
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598 * lapic not mapped yet (pmap_init is called too late)
599 *
ff76b364
MN
600 * XXX: where is the best place to set lapic?
601 */
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602 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
603 sizeof(struct LAPIC));
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MN
604
605 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
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606 if (madt_pass2(madt_paddr, bsp_apic_id))
607 panic("mp_enable: madt_pass2 failed\n");
699b0754 608 }
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609
610#if defined(APIC_IO)
611
612 setup_apic_irq_mapping();
613
614 /* fill the LOGICAL io_apic_versions table */
615 for (apic = 0; apic < mp_napics; ++apic) {
616 ux = io_apic_read(apic, IOAPIC_VER);
617 io_apic_versions[apic] = ux;
618 io_apic_set_id(apic, IO_TO_ID(apic));
619 }
620
621 /* program each IO APIC in the system */
622 for (apic = 0; apic < mp_napics; ++apic)
623 if (io_apic_setup(apic) < 0)
624 panic("IO APIC setup failure");
625
626#endif /* APIC_IO */
627
628 /*
629 * These are required for SMP operation
630 */
631
632 /* install a 'Spurious INTerrupt' vector */
633 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
a4f18b62 634 SDT_SYSIGT, SEL_KPL, 0);
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635
636 /* install an inter-CPU IPI for TLB invalidation */
637 setidt(XINVLTLB_OFFSET, Xinvltlb,
a4f18b62 638 SDT_SYSIGT, SEL_KPL, 0);
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639
640 /* install an inter-CPU IPI for IPIQ messaging */
641 setidt(XIPIQ_OFFSET, Xipiq,
a4f18b62 642 SDT_SYSIGT, SEL_KPL, 0);
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643
644 /* install a timer vector */
645 setidt(XTIMER_OFFSET, Xtimer,
a4f18b62 646 SDT_SYSIGT, SEL_KPL, 0);
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647
648 /* install an inter-CPU IPI for CPU stop/restart */
649 setidt(XCPUSTOP_OFFSET, Xcpustop,
a4f18b62 650 SDT_SYSIGT, SEL_KPL, 0);
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651
652 /* start each Application Processor */
653 start_all_aps(boot_addr);
654}
655
656
657/*
658 * look for the MP spec signature
659 */
660
661/* string defined by the Intel MP Spec as identifying the MP table */
662#define MP_SIG 0x5f504d5f /* _MP_ */
663#define NEXT(X) ((X) += 4)
3a918cfd 664static long
0eaa8172 665mptable_search_sig(u_int32_t target, int count)
46d4e165 666{
f592025a
MN
667 vm_size_t map_size;
668 u_int32_t *addr;
669 int x, ret;
46d4e165 670
351254e7
MN
671 KKASSERT(target != 0);
672
f592025a
MN
673 map_size = count * sizeof(u_int32_t);
674 addr = pmap_mapdev((vm_paddr_t)target, map_size);
46d4e165 675
351254e7 676 ret = 0;
f592025a
MN
677 for (x = 0; x < count; NEXT(x)) {
678 if (addr[x] == MP_SIG) {
679 /* make array index a byte index */
680 ret = target + (x * sizeof(u_int32_t));
681 break;
682 }
683 }
351254e7 684
f592025a
MN
685 pmap_unmapdev((vm_offset_t)addr, map_size);
686 return ret;
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687}
688
689
690static basetable_entry basetable_entry_types[] =
691{
692 {0, 20, "Processor"},
693 {1, 8, "Bus"},
694 {2, 8, "I/O APIC"},
695 {3, 8, "I/O INT"},
696 {4, 8, "Local INT"}
697};
698
699typedef struct BUSDATA {
700 u_char bus_id;
701 enum busTypes bus_type;
702} bus_datum;
703
704typedef struct INTDATA {
705 u_char int_type;
706 u_short int_flags;
707 u_char src_bus_id;
708 u_char src_bus_irq;
709 u_char dst_apic_id;
710 u_char dst_apic_int;
711 u_char int_vector;
712} io_int, local_int;
713
714typedef struct BUSTYPENAME {
715 u_char type;
716 char name[7];
717} bus_type_name;
718
719static bus_type_name bus_type_table[] =
720{
721 {CBUS, "CBUS"},
722 {CBUSII, "CBUSII"},
723 {EISA, "EISA"},
724 {MCA, "MCA"},
725 {UNKNOWN_BUSTYPE, "---"},
726 {ISA, "ISA"},
727 {MCA, "MCA"},
728 {UNKNOWN_BUSTYPE, "---"},
729 {UNKNOWN_BUSTYPE, "---"},
730 {UNKNOWN_BUSTYPE, "---"},
731 {UNKNOWN_BUSTYPE, "---"},
732 {UNKNOWN_BUSTYPE, "---"},
733 {PCI, "PCI"},
734 {UNKNOWN_BUSTYPE, "---"},
735 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
737 {UNKNOWN_BUSTYPE, "---"},
738 {XPRESS, "XPRESS"},
739 {UNKNOWN_BUSTYPE, "---"}
740};
741/* from MP spec v1.4, table 5-1 */
742static int default_data[7][5] =
743{
744/* nbus, id0, type0, id1, type1 */
745 {1, 0, ISA, 255, 255},
746 {1, 0, EISA, 255, 255},
747 {1, 0, EISA, 255, 255},
748 {1, 0, MCA, 255, 255},
749 {2, 0, ISA, 1, PCI},
750 {2, 0, EISA, 1, PCI},
751 {2, 0, MCA, 1, PCI}
752};
753
754
755/* the bus data */
756static bus_datum *bus_data;
757
758#ifdef APIC_IO
759/* the IO INT data, one entry per possible APIC INTerrupt */
760static io_int *io_apic_ints;
761static int nintrs;
762#endif
763
764static int processor_entry (proc_entry_ptr entry, int cpu);
765static int bus_entry (bus_entry_ptr entry, int bus);
766#ifdef APIC_IO
767static int io_apic_entry (io_apic_entry_ptr entry, int apic);
768static int int_entry (int_entry_ptr entry, int intr);
769#endif
770static int lookup_bus_type (char *name);
771
772
773/*
774 * 1st pass on motherboard's Intel MP specification table.
775 *
46d4e165
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776 * determines:
777 * cpu_apic_address (common to all CPUs)
778 * io_apic_address[N]
779 * mp_naps
780 * mp_nbusses
781 * mp_napics
782 * nintrs
0ecea546
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783 * need_hyperthreading_fixup
784 * logical_cpus
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785 */
786static void
91f1c7a4 787mptable_pass1(struct mptable_pos *mpt)
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788{
789#ifdef APIC_IO
790 int x;
791#endif
91f1c7a4 792 mpfps_t fps;
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793 mpcth_t cth;
794 int totalSize;
795 void* position;
796 int count;
797 int type;
798 u_int id_mask;
799
800 POSTCODE(MPTABLE_PASS1_POST);
801
91f1c7a4
MN
802 fps = mpt->mp_fps;
803 KKASSERT(fps != NULL);
9ad60dda 804
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805#ifdef APIC_IO
806 /* clear various tables */
807 for (x = 0; x < NAPICID; ++x) {
808 io_apic_address[x] = ~0; /* IO APIC address table */
809 }
810#endif
811
812 /* init everything to empty */
813 mp_naps = 0;
814 mp_nbusses = 0;
815#ifdef APIC_IO
816 mp_napics = 0;
817 nintrs = 0;
818#endif
819 id_mask = 0;
820
821 /* check for use of 'default' configuration */
91f1c7a4 822 if (fps->mpfb1 != 0) {
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823 /* use default addresses */
824 cpu_apic_address = DEFAULT_APIC_BASE;
825#ifdef APIC_IO
826 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
827#endif
828
829 /* fill in with defaults */
830 mp_naps = 2; /* includes BSP */
91f1c7a4 831 mp_nbusses = default_data[fps->mpfb1 - 1][0];
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832#if defined(APIC_IO)
833 mp_napics = 1;
834 nintrs = 16;
835#endif /* APIC_IO */
836 }
837 else {
91f1c7a4
MN
838 cth = mpt->mp_cth;
839 if (cth == NULL)
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840 panic("MP Configuration Table Header MISSING!");
841
842 cpu_apic_address = (vm_offset_t) cth->apic_address;
843
844 /* walk the table, recording info of interest */
845 totalSize = cth->base_table_length - sizeof(struct MPCTH);
846 position = (u_char *) cth + sizeof(struct MPCTH);
847 count = cth->entry_count;
848
849 while (count--) {
850 switch (type = *(u_char *) position) {
851 case 0: /* processor_entry */
852 if (((proc_entry_ptr)position)->cpu_flags
853 & PROCENTRY_FLAG_EN) {
854 ++mp_naps;
855 id_mask |= 1 <<
856 ((proc_entry_ptr)position)->apic_id;
857 }
858 break;
859 case 1: /* bus_entry */
860 ++mp_nbusses;
861 break;
862 case 2: /* io_apic_entry */
863#ifdef APIC_IO
864 if (((io_apic_entry_ptr)position)->apic_flags
865 & IOAPICENTRY_FLAG_EN)
866 io_apic_address[mp_napics++] =
867 (vm_offset_t)((io_apic_entry_ptr)
868 position)->apic_address;
869#endif
870 break;
871 case 3: /* int_entry */
872#ifdef APIC_IO
873 ++nintrs;
874#endif
875 break;
876 case 4: /* int_entry */
877 break;
878 default:
879 panic("mpfps Base Table HOSED!");
880 /* NOTREACHED */
881 }
882
883 totalSize -= basetable_entry_types[type].length;
884 position = (uint8_t *)position +
885 basetable_entry_types[type].length;
886 }
887 }
888
889 /* qualify the numbers */
890 if (mp_naps > MAXCPU) {
891 kprintf("Warning: only using %d of %d available CPUs!\n",
892 MAXCPU, mp_naps);
893 mp_naps = MAXCPU;
894 }
895
896 /* See if we need to fixup HT logical CPUs. */
897 mptable_hyperthread_fixup(id_mask);
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898
899 --mp_naps; /* subtract the BSP */
900}
901
902
903/*
904 * 2nd pass on motherboard's Intel MP specification table.
905 *
906 * sets:
0ecea546 907 * logical_cpus_mask
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908 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
909 * CPU_TO_ID(N), logical CPU to APIC ID table
910 * IO_TO_ID(N), logical IO to APIC ID table
911 * bus_data[N]
912 * io_apic_ints[N]
913 */
914static int
91f1c7a4 915mptable_pass2(struct mptable_pos *mpt)
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916{
917 struct PROCENTRY proc;
918 int x;
91f1c7a4 919 mpfps_t fps;
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920 mpcth_t cth;
921 int totalSize;
922 void* position;
923 int count;
924 int type;
925 int apic, bus, cpu, intr;
926 int i;
927
928 POSTCODE(MPTABLE_PASS2_POST);
929
91f1c7a4
MN
930 fps = mpt->mp_fps;
931 KKASSERT(fps != NULL);
932
46d4e165
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933 /* Initialize fake proc entry for use with HT fixup. */
934 bzero(&proc, sizeof(proc));
935 proc.type = 0;
936 proc.cpu_flags = PROCENTRY_FLAG_EN;
937
938#ifdef APIC_IO
939 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
940 M_DEVBUF, M_WAITOK);
941 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
942 M_DEVBUF, M_WAITOK | M_ZERO);
943 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
944 M_DEVBUF, M_WAITOK);
945#endif
946 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
947 M_DEVBUF, M_WAITOK);
948
949#ifdef APIC_IO
950 for (i = 0; i < mp_napics; i++) {
951 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
952 }
953#endif
954
955 /* clear various tables */
956 for (x = 0; x < NAPICID; ++x) {
957 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
958#ifdef APIC_IO
959 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
960 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
961#endif
962 }
963
964 /* clear bus data table */
965 for (x = 0; x < mp_nbusses; ++x)
966 bus_data[x].bus_id = 0xff;
967
968#ifdef APIC_IO
969 /* clear IO APIC INT table */
970 for (x = 0; x < (nintrs + 1); ++x) {
971 io_apic_ints[x].int_type = 0xff;
972 io_apic_ints[x].int_vector = 0xff;
973 }
974#endif
975
46d4e165 976 /* record whether PIC or virtual-wire mode */
91f1c7a4 977 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
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978
979 /* check for use of 'default' configuration */
91f1c7a4
MN
980 if (fps->mpfb1 != 0)
981 return fps->mpfb1; /* return default configuration type */
46d4e165 982
91f1c7a4
MN
983 cth = mpt->mp_cth;
984 if (cth == NULL)
46d4e165
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985 panic("MP Configuration Table Header MISSING!");
986
987 /* walk the table, recording info of interest */
988 totalSize = cth->base_table_length - sizeof(struct MPCTH);
989 position = (u_char *) cth + sizeof(struct MPCTH);
990 count = cth->entry_count;
991 apic = bus = intr = 0;
992 cpu = 1; /* pre-count the BSP */
993
994 while (count--) {
995 switch (type = *(u_char *) position) {
996 case 0:
997 if (processor_entry(position, cpu))
998 ++cpu;
999
1000 if (need_hyperthreading_fixup) {
1001 /*
1002 * Create fake mptable processor entries
1003 * and feed them to processor_entry() to
1004 * enumerate the logical CPUs.
1005 */
1006 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1007 for (i = 1; i < logical_cpus; i++) {
1008 proc.apic_id++;
1009 processor_entry(&proc, cpu);
1010 logical_cpus_mask |= (1 << cpu);
1011 cpu++;
1012 }
1013 }
1014 break;
1015 case 1:
1016 if (bus_entry(position, bus))
1017 ++bus;
1018 break;
1019 case 2:
1020#ifdef APIC_IO
1021 if (io_apic_entry(position, apic))
1022 ++apic;
1023#endif
1024 break;
1025 case 3:
1026#ifdef APIC_IO
1027 if (int_entry(position, intr))
1028 ++intr;
1029#endif
1030 break;
1031 case 4:
1032 /* int_entry(position); */
1033 break;
1034 default:
1035 panic("mpfps Base Table HOSED!");
1036 /* NOTREACHED */
1037 }
1038
1039 totalSize -= basetable_entry_types[type].length;
1040 position = (uint8_t *)position + basetable_entry_types[type].length;
1041 }
1042
bfa17615 1043 if (CPU_TO_ID(0) < 0)
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1044 panic("NO BSP found!");
1045
1046 /* report fact that its NOT a default configuration */
1047 return 0;
1048}
1049
91f1c7a4 1050
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1051/*
1052 * Check if we should perform a hyperthreading "fix-up" to
1053 * enumerate any logical CPU's that aren't already listed
1054 * in the table.
1055 *
1056 * XXX: We assume that all of the physical CPUs in the
1057 * system have the same number of logical CPUs.
1058 *
1059 * XXX: We assume that APIC ID's are allocated such that
1060 * the APIC ID's for a physical processor are aligned
1061 * with the number of logical CPU's in the processor.
1062 */
1063static void
1064mptable_hyperthread_fixup(u_int id_mask)
1065{
f5abf528 1066 int i, id, lcpus_max;
46d4e165 1067
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1068 if ((cpu_feature & CPUID_HTT) == 0)
1069 return;
f5abf528
MN
1070
1071 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1072 if (lcpus_max <= 1)
46d4e165
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1073 return;
1074
f5abf528
MN
1075 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1076 /*
1077 * INSTRUCTION SET REFERENCE, A-M (#253666)
1078 * Page 3-181, Table 3-20
1079 * "The nearest power-of-2 integer that is not smaller
1080 * than EBX[23:16] is the number of unique initial APIC
1081 * IDs reserved for addressing different logical
1082 * processors in a physical package."
1083 */
1084 for (i = 0; ; ++i) {
1085 if ((1 << i) >= lcpus_max) {
1086 lcpus_max = 1 << i;
1087 break;
1088 }
1089 }
1090 }
1091
1092 if (mp_naps == lcpus_max) {
1093 /* We have nothing to fix */
1094 return;
1095 } else if (mp_naps == 1) {
1096 /* XXX this may be incorrect */
1097 logical_cpus = lcpus_max;
1098 } else {
1099 int cur, prev, dist;
1100
1101 /*
1102 * Calculate the distances between two nearest
1103 * APIC IDs. If all such distances are same,
1104 * then it is the number of missing cpus that
1105 * we are going to fill later.
1106 */
1107 dist = cur = prev = -1;
1108 for (id = 0; id < MAXCPU; ++id) {
1109 if ((id_mask & 1 << id) == 0)
1110 continue;
1111
1112 cur = id;
1113 if (prev >= 0) {
1114 int new_dist = cur - prev;
1115
1116 if (dist < 0)
1117 dist = new_dist;
1118
1119 /*
1120 * Make sure that all distances
1121 * between two nearest APIC IDs
1122 * are same.
1123 */
1124 if (dist != new_dist)
1125 return;
1126 }
1127 prev = cur;
1128 }
1129 if (dist == 1)
1130 return;
1131
1132 /* Must be power of 2 */
1133 if (dist & (dist - 1))
1134 return;
1135
1136 /* Can't exceed CPU package capacity */
1137 if (dist > lcpus_max)
1138 logical_cpus = lcpus_max;
1139 else
1140 logical_cpus = dist;
1141 }
1142
46d4e165
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1143 /*
1144 * For each APIC ID of a CPU that is set in the mask,
1145 * scan the other candidate APIC ID's for this
1146 * physical processor. If any of those ID's are
1147 * already in the table, then kill the fixup.
1148 */
f5abf528 1149 for (id = 0; id < MAXCPU; id++) {
46d4e165
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1150 if ((id_mask & 1 << id) == 0)
1151 continue;
1152 /* First, make sure we are on a logical_cpus boundary. */
1153 if (id % logical_cpus != 0)
1154 return;
1155 for (i = id + 1; i < id + logical_cpus; i++)
1156 if ((id_mask & 1 << i) != 0)
1157 return;
1158 }
1159
1160 /*
1161 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1162 * mp_naps right now.
1163 */
1164 need_hyperthreading_fixup = 1;
1165 mp_naps *= logical_cpus;
1166}
1167
91f1c7a4
MN
1168static void
1169mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1170{
1171 mpfps_t fps = NULL;
1172 mpcth_t cth = NULL;
1173 vm_size_t cth_mapsz = 0;
1174
1175 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1176 if (fps->pap != 0) {
1177 /*
1178 * Map configuration table header to get
1179 * the base table size
1180 */
1181 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1182 cth_mapsz = cth->base_table_length;
1183 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1184
1185 /*
1186 * Map the base table
1187 */
1188 cth = pmap_mapdev(fps->pap, cth_mapsz);
1189 }
1190
1191 mpt->mp_fps = fps;
1192 mpt->mp_cth = cth;
1193 mpt->mp_cth_mapsz = cth_mapsz;
1194}
1195
1196static void
1197mptable_unmap(struct mptable_pos *mpt)
1198{
1199 if (mpt->mp_cth != NULL) {
1200 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1201 mpt->mp_cth = NULL;
1202 mpt->mp_cth_mapsz = 0;
1203 }
1204 if (mpt->mp_fps != NULL) {
1205 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1206 mpt->mp_fps = NULL;
1207 }
1208}
1209
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1210#ifdef APIC_IO
1211
1212void
1213assign_apic_irq(int apic, int intpin, int irq)
1214{
1215 int x;
1216
1217 if (int_to_apicintpin[irq].ioapic != -1)
1218 panic("assign_apic_irq: inconsistent table");
1219
1220 int_to_apicintpin[irq].ioapic = apic;
1221 int_to_apicintpin[irq].int_pin = intpin;
1222 int_to_apicintpin[irq].apic_address = ioapic[apic];
1223 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1224
1225 for (x = 0; x < nintrs; x++) {
1226 if ((io_apic_ints[x].int_type == 0 ||
1227 io_apic_ints[x].int_type == 3) &&
1228 io_apic_ints[x].int_vector == 0xff &&
1229 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1230 io_apic_ints[x].dst_apic_int == intpin)
1231 io_apic_ints[x].int_vector = irq;
1232 }
1233}
1234
1235void
1236revoke_apic_irq(int irq)
1237{
1238 int x;
1239 int oldapic;
1240 int oldintpin;
1241
1242 if (int_to_apicintpin[irq].ioapic == -1)
1243 panic("revoke_apic_irq: inconsistent table");
1244
1245 oldapic = int_to_apicintpin[irq].ioapic;
1246 oldintpin = int_to_apicintpin[irq].int_pin;
1247
1248 int_to_apicintpin[irq].ioapic = -1;
1249 int_to_apicintpin[irq].int_pin = 0;
1250 int_to_apicintpin[irq].apic_address = NULL;
1251 int_to_apicintpin[irq].redirindex = 0;
1252
1253 for (x = 0; x < nintrs; x++) {
1254 if ((io_apic_ints[x].int_type == 0 ||
1255 io_apic_ints[x].int_type == 3) &&
1256 io_apic_ints[x].int_vector != 0xff &&
1257 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1258 io_apic_ints[x].dst_apic_int == oldintpin)
1259 io_apic_ints[x].int_vector = 0xff;
1260 }
1261}
1262
1263/*
1264 * Allocate an IRQ
1265 */
1266static void
1267allocate_apic_irq(int intr)
1268{
1269 int apic;
1270 int intpin;
1271 int irq;
1272
1273 if (io_apic_ints[intr].int_vector != 0xff)
1274 return; /* Interrupt handler already assigned */
1275
1276 if (io_apic_ints[intr].int_type != 0 &&
1277 (io_apic_ints[intr].int_type != 3 ||
1278 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1279 io_apic_ints[intr].dst_apic_int == 0)))
1280 return; /* Not INT or ExtInt on != (0, 0) */
1281
1282 irq = 0;
1283 while (irq < APIC_INTMAPSIZE &&
1284 int_to_apicintpin[irq].ioapic != -1)
1285 irq++;
1286
1287 if (irq >= APIC_INTMAPSIZE)
1288 return; /* No free interrupt handlers */
1289
1290 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1291 intpin = io_apic_ints[intr].dst_apic_int;
1292
1293 assign_apic_irq(apic, intpin, irq);
46d4e165
JG
1294}
1295
1296
1297static void
1298swap_apic_id(int apic, int oldid, int newid)
1299{
1300 int x;
1301 int oapic;
1302
1303
1304 if (oldid == newid)
1305 return; /* Nothing to do */
1306
1307 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1308 apic, oldid, newid);
1309
1310 /* Swap physical APIC IDs in interrupt entries */
1311 for (x = 0; x < nintrs; x++) {
1312 if (io_apic_ints[x].dst_apic_id == oldid)
1313 io_apic_ints[x].dst_apic_id = newid;
1314 else if (io_apic_ints[x].dst_apic_id == newid)
1315 io_apic_ints[x].dst_apic_id = oldid;
1316 }
1317
1318 /* Swap physical APIC IDs in IO_TO_ID mappings */
1319 for (oapic = 0; oapic < mp_napics; oapic++)
1320 if (IO_TO_ID(oapic) == newid)
1321 break;
1322
1323 if (oapic < mp_napics) {
1324 kprintf("Changing APIC ID for IO APIC #%d from "
1325 "%d to %d in MP table\n",
1326 oapic, newid, oldid);
1327 IO_TO_ID(oapic) = oldid;
1328 }
1329 IO_TO_ID(apic) = newid;
1330}
1331
1332
1333static void
1334fix_id_to_io_mapping(void)
1335{
1336 int x;
1337
1338 for (x = 0; x < NAPICID; x++)
1339 ID_TO_IO(x) = -1;
1340
1341 for (x = 0; x <= mp_naps; x++)
1342 if (CPU_TO_ID(x) < NAPICID)
1343 ID_TO_IO(CPU_TO_ID(x)) = x;
1344
1345 for (x = 0; x < mp_napics; x++)
1346 if (IO_TO_ID(x) < NAPICID)
1347 ID_TO_IO(IO_TO_ID(x)) = x;
1348}
1349
1350
1351static int
1352first_free_apic_id(void)
1353{
1354 int freeid, x;
1355
1356 for (freeid = 0; freeid < NAPICID; freeid++) {
1357 for (x = 0; x <= mp_naps; x++)
1358 if (CPU_TO_ID(x) == freeid)
1359 break;
1360 if (x <= mp_naps)
1361 continue;
1362 for (x = 0; x < mp_napics; x++)
1363 if (IO_TO_ID(x) == freeid)
1364 break;
1365 if (x < mp_napics)
1366 continue;
1367 return freeid;
1368 }
1369 return freeid;
1370}
1371
1372
1373static int
1374io_apic_id_acceptable(int apic, int id)
1375{
1376 int cpu; /* Logical CPU number */
1377 int oapic; /* Logical IO APIC number for other IO APIC */
1378
1379 if (id >= NAPICID)
1380 return 0; /* Out of range */
1381
1382 for (cpu = 0; cpu <= mp_naps; cpu++)
1383 if (CPU_TO_ID(cpu) == id)
1384 return 0; /* Conflict with CPU */
1385
1386 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1387 if (IO_TO_ID(oapic) == id)
1388 return 0; /* Conflict with other APIC */
1389
1390 return 1; /* ID is acceptable for IO APIC */
1391}
1392
1393static
1394io_int *
1395io_apic_find_int_entry(int apic, int pin)
1396{
1397 int x;
1398
1399 /* search each of the possible INTerrupt sources */
1400 for (x = 0; x < nintrs; ++x) {
1401 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1402 (pin == io_apic_ints[x].dst_apic_int))
1403 return (&io_apic_ints[x]);
1404 }
1405 return NULL;
1406}
1407
1408#endif
1409
1410/*
1411 * parse an Intel MP specification table
1412 */
1413static void
0eaa8172 1414mptable_fix(void)
46d4e165
JG
1415{
1416 int x;
1417#ifdef APIC_IO
1418 int id;
1419 int apic; /* IO APIC unit number */
1420 int freeid; /* Free physical APIC ID */
1421 int physid; /* Current physical IO APIC ID */
1422 io_int *io14;
1423#endif
1424 int bus_0 = 0; /* Stop GCC warning */
1425 int bus_pci = 0; /* Stop GCC warning */
1426 int num_pci_bus;
1427
1428 /*
1429 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1430 * did it wrong. The MP spec says that when more than 1 PCI bus
1431 * exists the BIOS must begin with bus entries for the PCI bus and use
1432 * actual PCI bus numbering. This implies that when only 1 PCI bus
1433 * exists the BIOS can choose to ignore this ordering, and indeed many
1434 * MP motherboards do ignore it. This causes a problem when the PCI
1435 * sub-system makes requests of the MP sub-system based on PCI bus
1436 * numbers. So here we look for the situation and renumber the
1437 * busses and associated INTs in an effort to "make it right".
1438 */
1439
1440 /* find bus 0, PCI bus, count the number of PCI busses */
1441 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1442 if (bus_data[x].bus_id == 0) {
1443 bus_0 = x;
1444 }
1445 if (bus_data[x].bus_type == PCI) {
1446 ++num_pci_bus;
1447 bus_pci = x;
1448 }
1449 }
1450 /*
1451 * bus_0 == slot of bus with ID of 0
1452 * bus_pci == slot of last PCI bus encountered
1453 */
1454
1455 /* check the 1 PCI bus case for sanity */
1456 /* if it is number 0 all is well */
1457 if (num_pci_bus == 1 &&
1458 bus_data[bus_pci].bus_id != 0) {
1459
1460 /* mis-numbered, swap with whichever bus uses slot 0 */
1461
1462 /* swap the bus entry types */
1463 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1464 bus_data[bus_0].bus_type = PCI;
1465
1466#ifdef APIC_IO
1467 /* swap each relavant INTerrupt entry */
1468 id = bus_data[bus_pci].bus_id;
1469 for (x = 0; x < nintrs; ++x) {
1470 if (io_apic_ints[x].src_bus_id == id) {
1471 io_apic_ints[x].src_bus_id = 0;
1472 }
1473 else if (io_apic_ints[x].src_bus_id == 0) {
1474 io_apic_ints[x].src_bus_id = id;
1475 }
1476 }
1477#endif
1478 }
1479
1480#ifdef APIC_IO
1481 /* Assign IO APIC IDs.
1482 *
1483 * First try the existing ID. If a conflict is detected, try
1484 * the ID in the MP table. If a conflict is still detected, find
1485 * a free id.
1486 *
1487 * We cannot use the ID_TO_IO table before all conflicts has been
1488 * resolved and the table has been corrected.
1489 */
1490 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1491
1492 /* First try to use the value set by the BIOS */
1493 physid = io_apic_get_id(apic);
1494 if (io_apic_id_acceptable(apic, physid)) {
1495 if (IO_TO_ID(apic) != physid)
1496 swap_apic_id(apic, IO_TO_ID(apic), physid);
1497 continue;
1498 }
1499
1500 /* Then check if the value in the MP table is acceptable */
1501 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1502 continue;
1503
1504 /* Last resort, find a free APIC ID and use it */
1505 freeid = first_free_apic_id();
1506 if (freeid >= NAPICID)
1507 panic("No free physical APIC IDs found");
1508
1509 if (io_apic_id_acceptable(apic, freeid)) {
1510 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1511 continue;
1512 }
1513 panic("Free physical APIC ID not usable");
1514 }
1515 fix_id_to_io_mapping();
1516#endif
1517
1518#ifdef APIC_IO
1519 /* detect and fix broken Compaq MP table */
1520 if (apic_int_type(0, 0) == -1) {
1521 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1522 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1523 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1524 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1525 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1526 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1527 nintrs++;
1528 } else if (apic_int_type(0, 0) == 0) {
1529 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1530 for (x = 0; x < nintrs; ++x)
1531 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1532 (0 == io_apic_ints[x].dst_apic_int)) {
1533 io_apic_ints[x].int_type = 3;
1534 io_apic_ints[x].int_vector = 0xff;
1535 break;
1536 }
1537 }
1538
1539 /*
1540 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1541 * controllers universally come in pairs. If IRQ 14 is specified
1542 * as an ISA interrupt, then IRQ 15 had better be too.
1543 *
1544 * [ Shuttle XPC / AMD Athlon X2 ]
1545 * The MPTable is missing an entry for IRQ 15. Note that the
1546 * ACPI table has an entry for both 14 and 15.
1547 */
1548 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1549 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1550 io14 = io_apic_find_int_entry(0, 14);
1551 io_apic_ints[nintrs] = *io14;
1552 io_apic_ints[nintrs].src_bus_irq = 15;
1553 io_apic_ints[nintrs].dst_apic_int = 15;
1554 nintrs++;
1555 }
1556#endif
1557}
1558
1559#ifdef APIC_IO
1560
1561/* Assign low level interrupt handlers */
1562static void
1563setup_apic_irq_mapping(void)
1564{
1565 int x;
1566 int int_vector;
1567
1568 /* Clear array */
1569 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1570 int_to_apicintpin[x].ioapic = -1;
1571 int_to_apicintpin[x].int_pin = 0;
1572 int_to_apicintpin[x].apic_address = NULL;
1573 int_to_apicintpin[x].redirindex = 0;
1574 }
1575
1576 /* First assign ISA/EISA interrupts */
1577 for (x = 0; x < nintrs; x++) {
1578 int_vector = io_apic_ints[x].src_bus_irq;
1579 if (int_vector < APIC_INTMAPSIZE &&
1580 io_apic_ints[x].int_vector == 0xff &&
1581 int_to_apicintpin[int_vector].ioapic == -1 &&
1582 (apic_int_is_bus_type(x, ISA) ||
1583 apic_int_is_bus_type(x, EISA)) &&
1584 io_apic_ints[x].int_type == 0) {
1585 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1586 io_apic_ints[x].dst_apic_int,
1587 int_vector);
1588 }
1589 }
1590
1591 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1592 for (x = 0; x < nintrs; x++) {
1593 if (io_apic_ints[x].dst_apic_int == 0 &&
1594 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1595 io_apic_ints[x].int_vector == 0xff &&
1596 int_to_apicintpin[0].ioapic == -1 &&
1597 io_apic_ints[x].int_type == 3) {
1598 assign_apic_irq(0, 0, 0);
1599 break;
1600 }
1601 }
662f60ef
SZ
1602
1603 /* Assign PCI interrupts */
1604 for (x = 0; x < nintrs; ++x) {
1605 if (io_apic_ints[x].int_type == 0 &&
1606 io_apic_ints[x].int_vector == 0xff &&
1607 apic_int_is_bus_type(x, PCI))
1608 allocate_apic_irq(x);
1609 }
46d4e165
JG
1610}
1611
1612#endif
1613
40d323b6
MN
1614void
1615mp_set_cpuids(int cpu_id, int apic_id)
1616{
1617 CPU_TO_ID(cpu_id) = apic_id;
1618 ID_TO_CPU(apic_id) = cpu_id;
1619}
1620
46d4e165
JG
1621static int
1622processor_entry(proc_entry_ptr entry, int cpu)
1623{
bfa17615
MN
1624 KKASSERT(cpu > 0);
1625
46d4e165
JG
1626 /* check for usability */
1627 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1628 return 0;
1629
1630 if(entry->apic_id >= NAPICID)
1631 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1632 /* check for BSP flag */
1633 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
40d323b6 1634 mp_set_cpuids(0, entry->apic_id);
46d4e165
JG
1635 return 0; /* its already been counted */
1636 }
1637
1638 /* add another AP to list, if less than max number of CPUs */
1639 else if (cpu < MAXCPU) {
40d323b6 1640 mp_set_cpuids(cpu, entry->apic_id);
46d4e165
JG
1641 return 1;
1642 }
1643
1644 return 0;
1645}
1646
1647
1648static int
1649bus_entry(bus_entry_ptr entry, int bus)
1650{
1651 int x;
1652 char c, name[8];
1653
1654 /* encode the name into an index */
1655 for (x = 0; x < 6; ++x) {
1656 if ((c = entry->bus_type[x]) == ' ')
1657 break;
1658 name[x] = c;
1659 }
1660 name[x] = '\0';
1661
1662 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1663 panic("unknown bus type: '%s'", name);
1664
1665 bus_data[bus].bus_id = entry->bus_id;
1666 bus_data[bus].bus_type = x;
1667
1668 return 1;
1669}
1670
1671#ifdef APIC_IO
1672
1673static int
1674io_apic_entry(io_apic_entry_ptr entry, int apic)
1675{
1676 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1677 return 0;
1678
1679 IO_TO_ID(apic) = entry->apic_id;
1680 if (entry->apic_id < NAPICID)
1681 ID_TO_IO(entry->apic_id) = apic;
1682
1683 return 1;
1684}
1685
1686#endif
1687
1688static int
1689lookup_bus_type(char *name)
1690{
1691 int x;
1692
1693 for (x = 0; x < MAX_BUSTYPE; ++x)
1694 if (strcmp(bus_type_table[x].name, name) == 0)
1695 return bus_type_table[x].type;
1696
1697 return UNKNOWN_BUSTYPE;
1698}
1699
1700#ifdef APIC_IO
1701
1702static int
1703int_entry(int_entry_ptr entry, int intr)
1704{
1705 int apic;
1706
1707 io_apic_ints[intr].int_type = entry->int_type;
1708 io_apic_ints[intr].int_flags = entry->int_flags;
1709 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1710 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1711 if (entry->dst_apic_id == 255) {
1712 /* This signal goes to all IO APICS. Select an IO APIC
1713 with sufficient number of interrupt pins */
1714 for (apic = 0; apic < mp_napics; apic++)
1715 if (((io_apic_read(apic, IOAPIC_VER) &
1716 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1717 entry->dst_apic_int)
1718 break;
1719 if (apic < mp_napics)
1720 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1721 else
1722 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1723 } else
1724 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1725 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1726
1727 return 1;
1728}
1729
1730static int
1731apic_int_is_bus_type(int intr, int bus_type)
1732{
1733 int bus;
1734
1735 for (bus = 0; bus < mp_nbusses; ++bus)
1736 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1737 && ((int) bus_data[bus].bus_type == bus_type))
1738 return 1;
1739
1740 return 0;
1741}
1742
1743/*
1744 * Given a traditional ISA INT mask, return an APIC mask.
1745 */
1746u_int
1747isa_apic_mask(u_int isa_mask)
1748{
1749 int isa_irq;
1750 int apic_pin;
1751
1752#if defined(SKIP_IRQ15_REDIRECT)
1753 if (isa_mask == (1 << 15)) {
1754 kprintf("skipping ISA IRQ15 redirect\n");
1755 return isa_mask;
1756 }
1757#endif /* SKIP_IRQ15_REDIRECT */
1758
1759 isa_irq = ffs(isa_mask); /* find its bit position */
1760 if (isa_irq == 0) /* doesn't exist */
1761 return 0;
1762 --isa_irq; /* make it zero based */
1763
1764 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1765 if (apic_pin == -1)
1766 return 0;
1767
1768 return (1 << apic_pin); /* convert pin# to a mask */
1769}
1770
1771/*
1772 * Determine which APIC pin an ISA/EISA INT is attached to.
1773 */
1774#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1775#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1776#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1777#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1778
1779#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1780int
1781isa_apic_irq(int isa_irq)
1782{
1783 int intr;
1784
1785 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1786 if (INTTYPE(intr) == 0) { /* standard INT */
1787 if (SRCBUSIRQ(intr) == isa_irq) {
1788 if (apic_int_is_bus_type(intr, ISA) ||
1789 apic_int_is_bus_type(intr, EISA)) {
1790 if (INTIRQ(intr) == 0xff)
1791 return -1; /* unassigned */
1792 return INTIRQ(intr); /* found */
1793 }
1794 }
1795 }
1796 }
1797 return -1; /* NOT found */
1798}
1799
1800
1801/*
1802 * Determine which APIC pin a PCI INT is attached to.
1803 */
1804#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1805#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1806#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1807int
1808pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1809{
1810 int intr;
1811
1812 --pciInt; /* zero based */
1813
1814 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1815 if ((INTTYPE(intr) == 0) /* standard INT */
1816 && (SRCBUSID(intr) == pciBus)
1817 && (SRCBUSDEVICE(intr) == pciDevice)
1818 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1819 if (apic_int_is_bus_type(intr, PCI)) {
662f60ef
SZ
1820 if (INTIRQ(intr) == 0xff) {
1821 kprintf("IOAPIC: pci_apic_irq() "
1822 "failed\n");
46d4e165 1823 return -1; /* unassigned */
662f60ef 1824 }
46d4e165
JG
1825 return INTIRQ(intr); /* exact match */
1826 }
1827 }
1828 }
1829
1830 return -1; /* NOT found */
1831}
1832
1833int
1834next_apic_irq(int irq)
1835{
1836 int intr, ointr;
1837 int bus, bustype;
1838
1839 bus = 0;
1840 bustype = 0;
1841 for (intr = 0; intr < nintrs; intr++) {
1842 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1843 continue;
1844 bus = SRCBUSID(intr);
1845 bustype = apic_bus_type(bus);
1846 if (bustype != ISA &&
1847 bustype != EISA &&
1848 bustype != PCI)
1849 continue;
1850 break;
1851 }
1852 if (intr >= nintrs) {
1853 return -1;
1854 }
1855 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1856 if (INTTYPE(ointr) != 0)
1857 continue;
1858 if (bus != SRCBUSID(ointr))
1859 continue;
1860 if (bustype == PCI) {
1861 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1862 continue;
1863 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1864 continue;
1865 }
1866 if (bustype == ISA || bustype == EISA) {
1867 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1868 continue;
1869 }
1870 if (INTPIN(intr) == INTPIN(ointr))
1871 continue;
1872 break;
1873 }
1874 if (ointr >= nintrs) {
1875 return -1;
1876 }
1877 return INTIRQ(ointr);
1878}
1879#undef SRCBUSLINE
1880#undef SRCBUSDEVICE
1881#undef SRCBUSID
1882#undef SRCBUSIRQ
1883
1884#undef INTPIN
1885#undef INTIRQ
1886#undef INTAPIC
1887#undef INTTYPE
1888
1889#endif
1890
1891/*
1892 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1893 *
1894 * XXX FIXME:
1895 * Exactly what this means is unclear at this point. It is a solution
1896 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1897 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1898 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1899 * option.
1900 */
1901int
1902undirect_isa_irq(int rirq)
1903{
1904#if defined(READY)
1905 if (bootverbose)
1906 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1907 /** FIXME: tickle the MB redirector chip */
1908 return /* XXX */;
1909#else
1910 if (bootverbose)
1911 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1912 return 0;
1913#endif /* READY */
1914}
1915
1916
1917/*
1918 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1919 */
1920int
1921undirect_pci_irq(int rirq)
1922{
1923#if defined(READY)
1924 if (bootverbose)
1925 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1926
1927 /** FIXME: tickle the MB redirector chip */
1928 return /* XXX */;
1929#else
1930 if (bootverbose)
1931 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1932 rirq);
1933 return 0;
1934#endif /* READY */
1935}
1936
1937
1938/*
1939 * given a bus ID, return:
1940 * the bus type if found
1941 * -1 if NOT found
1942 */
1943int
1944apic_bus_type(int id)
1945{
1946 int x;
1947
1948 for (x = 0; x < mp_nbusses; ++x)
1949 if (bus_data[x].bus_id == id)
1950 return bus_data[x].bus_type;
1951
1952 return -1;
1953}
1954
1955#ifdef APIC_IO
1956
1957/*
1958 * given a LOGICAL APIC# and pin#, return:
1959 * the associated src bus ID if found
1960 * -1 if NOT found
1961 */
1962int
1963apic_src_bus_id(int apic, int pin)
1964{
1965 int x;
1966
1967 /* search each of the possible INTerrupt sources */
1968 for (x = 0; x < nintrs; ++x)
1969 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1970 (pin == io_apic_ints[x].dst_apic_int))
1971 return (io_apic_ints[x].src_bus_id);
1972
1973 return -1; /* NOT found */
1974}
1975
1976/*
1977 * given a LOGICAL APIC# and pin#, return:
1978 * the associated src bus IRQ if found
1979 * -1 if NOT found
1980 */
1981int
1982apic_src_bus_irq(int apic, int pin)
1983{
1984 int x;
1985
1986 for (x = 0; x < nintrs; x++)
1987 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1988 (pin == io_apic_ints[x].dst_apic_int))
1989 return (io_apic_ints[x].src_bus_irq);
1990
1991 return -1; /* NOT found */
1992}
1993
1994
1995/*
1996 * given a LOGICAL APIC# and pin#, return:
1997 * the associated INTerrupt type if found
1998 * -1 if NOT found
1999 */
2000int
2001apic_int_type(int apic, int pin)
2002{
2003 int x;
2004
2005 /* search each of the possible INTerrupt sources */
2006 for (x = 0; x < nintrs; ++x) {
2007 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2008 (pin == io_apic_ints[x].dst_apic_int))
2009 return (io_apic_ints[x].int_type);
2010 }
2011 return -1; /* NOT found */
2012}
2013
2014/*
2015 * Return the IRQ associated with an APIC pin
2016 */
2017int
2018apic_irq(int apic, int pin)
2019{
2020 int x;
2021 int res;
2022
2023 for (x = 0; x < nintrs; ++x) {
2024 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2025 (pin == io_apic_ints[x].dst_apic_int)) {
2026 res = io_apic_ints[x].int_vector;
2027 if (res == 0xff)
2028 return -1;
2029 if (apic != int_to_apicintpin[res].ioapic)
2030 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2031 if (pin != int_to_apicintpin[res].int_pin)
2032 panic("apic_irq inconsistent table (2)");
2033 return res;
2034 }
2035 }
2036 return -1;
2037}
2038
2039
2040/*
2041 * given a LOGICAL APIC# and pin#, return:
2042 * the associated trigger mode if found
2043 * -1 if NOT found
2044 */
2045int
2046apic_trigger(int apic, int pin)
2047{
2048 int x;
2049
2050 /* search each of the possible INTerrupt sources */
2051 for (x = 0; x < nintrs; ++x)
2052 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2053 (pin == io_apic_ints[x].dst_apic_int))
2054 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2055
2056 return -1; /* NOT found */
2057}
2058
2059
2060/*
2061 * given a LOGICAL APIC# and pin#, return:
2062 * the associated 'active' level if found
2063 * -1 if NOT found
2064 */
2065int
2066apic_polarity(int apic, int pin)
2067{
2068 int x;
2069
2070 /* search each of the possible INTerrupt sources */
2071 for (x = 0; x < nintrs; ++x)
2072 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2073 (pin == io_apic_ints[x].dst_apic_int))
2074 return (io_apic_ints[x].int_flags & 0x03);
2075
2076 return -1; /* NOT found */
2077}
2078
2079#endif
2080
2081/*
2082 * set data according to MP defaults
2083 * FIXME: probably not complete yet...
2084 */
2085static void
0eaa8172 2086mptable_default(int type)
46d4e165 2087{
bfa17615 2088 int ap_cpu_id, boot_cpu_id;
46d4e165
JG
2089#if defined(APIC_IO)
2090 int io_apic_id;
2091 int pin;
2092#endif /* APIC_IO */
2093
2094#if 0
2095 kprintf(" MP default config type: %d\n", type);
2096 switch (type) {
2097 case 1:
2098 kprintf(" bus: ISA, APIC: 82489DX\n");
2099 break;
2100 case 2:
2101 kprintf(" bus: EISA, APIC: 82489DX\n");
2102 break;
2103 case 3:
2104 kprintf(" bus: EISA, APIC: 82489DX\n");
2105 break;
2106 case 4:
2107 kprintf(" bus: MCA, APIC: 82489DX\n");
2108 break;
2109 case 5:
2110 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2111 break;
2112 case 6:
2113 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2114 break;
2115 case 7:
2116 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2117 break;
2118 default:
2119 kprintf(" future type\n");
2120 break;
2121 /* NOTREACHED */
2122 }
2123#endif /* 0 */
2124
2125 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2126 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2127
2128 /* BSP */
2129 CPU_TO_ID(0) = boot_cpu_id;
2130 ID_TO_CPU(boot_cpu_id) = 0;
2131
2132 /* one and only AP */
2133 CPU_TO_ID(1) = ap_cpu_id;
2134 ID_TO_CPU(ap_cpu_id) = 1;
2135
2136#if defined(APIC_IO)
2137 /* one and only IO APIC */
2138 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2139
2140 /*
2141 * sanity check, refer to MP spec section 3.6.6, last paragraph
2142 * necessary as some hardware isn't properly setting up the IO APIC
2143 */
2144#if defined(REALLY_ANAL_IOAPICID_VALUE)
2145 if (io_apic_id != 2) {
2146#else
2147 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2148#endif /* REALLY_ANAL_IOAPICID_VALUE */
2149 io_apic_set_id(0, 2);
2150 io_apic_id = 2;
2151 }
2152 IO_TO_ID(0) = io_apic_id;
2153 ID_TO_IO(io_apic_id) = 0;
2154#endif /* APIC_IO */
2155
2156 /* fill out bus entries */
2157 switch (type) {
2158 case 1:
2159 case 2:
2160 case 3:
2161 case 4:
2162 case 5:
2163 case 6:
2164 case 7:
2165 bus_data[0].bus_id = default_data[type - 1][1];
2166 bus_data[0].bus_type = default_data[type - 1][2];
2167 bus_data[1].bus_id = default_data[type - 1][3];
2168 bus_data[1].bus_type = default_data[type - 1][4];
2169 break;
2170
2171 /* case 4: case 7: MCA NOT supported */
2172 default: /* illegal/reserved */
2173 panic("BAD default MP config: %d", type);
2174 /* NOTREACHED */
2175 }
2176
2177#if defined(APIC_IO)
2178 /* general cases from MP v1.4, table 5-2 */
2179 for (pin = 0; pin < 16; ++pin) {
2180 io_apic_ints[pin].int_type = 0;
2181 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2182 io_apic_ints[pin].src_bus_id = 0;
2183 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2184 io_apic_ints[pin].dst_apic_id = io_apic_id;
2185 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2186 }
2187
2188 /* special cases from MP v1.4, table 5-2 */
2189 if (type == 2) {
2190 io_apic_ints[2].int_type = 0xff; /* N/C */
2191 io_apic_ints[13].int_type = 0xff; /* N/C */
2192#if !defined(APIC_MIXED_MODE)
2193 /** FIXME: ??? */
2194 panic("sorry, can't support type 2 default yet");
2195#endif /* APIC_MIXED_MODE */
2196 }
2197 else
2198 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2199
2200 if (type == 7)
2201 io_apic_ints[0].int_type = 0xff; /* N/C */
2202 else
2203 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2204#endif /* APIC_IO */
2205}
2206
2207/*
2208 * Map a physical memory address representing I/O into KVA. The I/O
2209 * block is assumed not to cross a page boundary.
2210 */
2211void *
2212permanent_io_mapping(vm_paddr_t pa)
2213{
46d4e165
JG
2214 KKASSERT(pa < 0x100000000LL);
2215
403c36ea 2216 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
46d4e165
JG
2217}
2218
2219/*
2220 * start each AP in our list
2221 */
2222static int
2223start_all_aps(u_int boot_addr)
2224{
2225 vm_offset_t va = boot_address + KERNBASE;
2226 u_int64_t *pt4, *pt3, *pt2;
2227 int x, i, pg;
2228 int shift;
bb467734
MD
2229 int smicount;
2230 int smibest;
2231 int smilast;
46d4e165
JG
2232 u_char mpbiosreason;
2233 u_long mpbioswarmvec;
2234 struct mdglobaldata *gd;
2235 struct privatespace *ps;
46d4e165
JG
2236
2237 POSTCODE(START_ALL_APS_POST);
2238
2239 /* Initialize BSP's local APIC */
2240 apic_initialize(TRUE);
2241 bsp_apic_ready = 1;
2242
2243 /* install the AP 1st level boot code */
2244 pmap_kenter(va, boot_address);
bfc09ba0 2245 cpu_invlpg((void *)va); /* JG XXX */
46d4e165
JG
2246 bcopy(mptramp_start, (void *)va, bootMP_size);
2247
2248 /* Locate the page tables, they'll be below the trampoline */
2249 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2250 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2251 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2252
2253 /* Create the initial 1GB replicated page tables */
2254 for (i = 0; i < 512; i++) {
2255 /* Each slot of the level 4 pages points to the same level 3 page */
2256 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2257 pt4[i] |= PG_V | PG_RW | PG_U;
2258
2259 /* Each slot of the level 3 pages points to the same level 2 page */
2260 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2261 pt3[i] |= PG_V | PG_RW | PG_U;
2262
2263 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2264 pt2[i] = i * (2 * 1024 * 1024);
2265 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2266 }
2267
2268 /* save the current value of the warm-start vector */
2269 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2270 outb(CMOS_REG, BIOS_RESET);
2271 mpbiosreason = inb(CMOS_DATA);
2272
2273 /* setup a vector to our boot code */
2274 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2275 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2276 outb(CMOS_REG, BIOS_RESET);
2277 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2278
bb467734
MD
2279 /*
2280 * If we have a TSC we can figure out the SMI interrupt rate.
2281 * The SMI does not necessarily use a constant rate. Spend
2282 * up to 250ms trying to figure it out.
2283 */
2284 smibest = 0;
2285 if (cpu_feature & CPUID_TSC) {
2286 set_apic_timer(275000);
2287 smilast = read_apic_timer();
2288 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2289 smicount = smitest();
2290 if (smibest == 0 || smilast - smicount < smibest)
2291 smibest = smilast - smicount;
2292 smilast = smicount;
2293 }
2294 if (smibest > 250000)
2295 smibest = 0;
2296 if (smibest) {
2297 smibest = smibest * (int64_t)1000000 /
2298 get_apic_timer_frequency();
2299 }
2300 }
2301 if (smibest)
2302 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2303 1000000 / smibest, smibest);
2304
46d4e165
JG
2305 /* start each AP */
2306 for (x = 1; x <= mp_naps; ++x) {
2307
2308 /* This is a bit verbose, it will go away soon. */
2309
2310 /* first page of AP's private space */
b2b3ffcd 2311 pg = x * x86_64_btop(sizeof(struct privatespace));
46d4e165
JG
2312
2313 /* allocate new private data page(s) */
2314 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2315 MDGLOBALDATA_BASEALLOC_SIZE);
46d4e165
JG
2316
2317 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2318 bzero(gd, sizeof(*gd));
2319 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2320
2321 /* prime data page for it to use */
2322 mi_gdinit(&gd->mi, x);
2323 cpu_gdinit(gd, x);
2324 gd->gd_CMAP1 = &SMPpt[pg + 0];
2325 gd->gd_CMAP2 = &SMPpt[pg + 1];
2326 gd->gd_CMAP3 = &SMPpt[pg + 2];
2327 gd->gd_PMAP1 = &SMPpt[pg + 3];
2328 gd->gd_CADDR1 = ps->CPAGE1;
2329 gd->gd_CADDR2 = ps->CPAGE2;
2330 gd->gd_CADDR3 = ps->CPAGE3;
bfc09ba0 2331 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
46d4e165
JG
2332 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2333 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2334
2335 /* setup a vector to our boot code */
2336 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2337 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2338 outb(CMOS_REG, BIOS_RESET);
2339 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2340
2341 /*
2342 * Setup the AP boot stack
2343 */
2344 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2345 bootAP = x;
2346
2347 /* attempt to start the Application Processor */
2348 CHECK_INIT(99); /* setup checkpoints */
bb467734 2349 if (!start_ap(gd, boot_addr, smibest)) {
46d4e165
JG
2350 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2351 CHECK_PRINT("trace"); /* show checkpoints */
2352 /* better panic as the AP may be running loose */
2353 kprintf("panic y/n? [y] ");
2354 if (cngetc() != 'n')
2355 panic("bye-bye");
2356 }
2357 CHECK_PRINT("trace"); /* show checkpoints */
2358
2359 /* record its version info */
2360 cpu_apic_versions[x] = cpu_apic_versions[0];
2361 }
2362
2363 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2364 ncpus = x;
2365
2366 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2367 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2368 ;
2369 --shift;
2370 ncpus2_shift = shift;
2371 ncpus2 = 1 << shift;
2372 ncpus2_mask = ncpus2 - 1;
2373
2374 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2375 if ((1 << shift) < ncpus)
2376 ++shift;
2377 ncpus_fit = 1 << shift;
2378 ncpus_fit_mask = ncpus_fit - 1;
2379
2380 /* build our map of 'other' CPUs */
2381 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2382 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2383 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2384
2385 /* fill in our (BSP) APIC version */
2386 cpu_apic_versions[0] = lapic->version;
2387
2388 /* restore the warmstart vector */
2389 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2390 outb(CMOS_REG, BIOS_RESET);
2391 outb(CMOS_DATA, mpbiosreason);
2392
2393 /*
2394 * NOTE! The idlestack for the BSP was setup by locore. Finish
2395 * up, clean out the P==V mapping we did earlier.
2396 */
46d4e165
JG
2397 pmap_set_opt();
2398
2399 /* number of APs actually started */
2400 return ncpus - 1;
2401}
2402
2403
2404/*
2405 * load the 1st level AP boot code into base memory.
2406 */
2407
2408/* targets for relocation */
2409extern void bigJump(void);
2410extern void bootCodeSeg(void);
2411extern void bootDataSeg(void);
2412extern void MPentry(void);
2413extern u_int MP_GDT;
2414extern u_int mp_gdtbase;
2415
bfc09ba0
MD
2416#if 0
2417
46d4e165
JG
2418static void
2419install_ap_tramp(u_int boot_addr)
2420{
2421 int x;
2422 int size = *(int *) ((u_long) & bootMP_size);
2423 u_char *src = (u_char *) ((u_long) bootMP);
2424 u_char *dst = (u_char *) boot_addr + KERNBASE;
2425 u_int boot_base = (u_int) bootMP;
2426 u_int8_t *dst8;
2427 u_int16_t *dst16;
2428 u_int32_t *dst32;
2429
2430 POSTCODE(INSTALL_AP_TRAMP_POST);
2431
2432 for (x = 0; x < size; ++x)
2433 *dst++ = *src++;
2434
2435 /*
2436 * modify addresses in code we just moved to basemem. unfortunately we
2437 * need fairly detailed info about mpboot.s for this to work. changes
2438 * to mpboot.s might require changes here.
2439 */
2440
2441 /* boot code is located in KERNEL space */
2442 dst = (u_char *) boot_addr + KERNBASE;
2443
2444 /* modify the lgdt arg */
2445 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2446 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2447
2448 /* modify the ljmp target for MPentry() */
2449 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2450 *dst32 = ((u_int) MPentry - KERNBASE);
2451
2452 /* modify the target for boot code segment */
2453 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2454 dst8 = (u_int8_t *) (dst16 + 1);
2455 *dst16 = (u_int) boot_addr & 0xffff;
2456 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2457
2458 /* modify the target for boot data segment */
2459 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2460 dst8 = (u_int8_t *) (dst16 + 1);
2461 *dst16 = (u_int) boot_addr & 0xffff;
2462 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2463}
2464
bfc09ba0 2465#endif
46d4e165
JG
2466
2467/*
bb467734 2468 * This function starts the AP (application processor) identified
46d4e165
JG
2469 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2470 * to accomplish this. This is necessary because of the nuances
2471 * of the different hardware we might encounter. It ain't pretty,
2472 * but it seems to work.
2473 *
2474 * NOTE: eventually an AP gets to ap_init(), which is called just
2475 * before the AP goes into the LWKT scheduler's idle loop.
2476 */
2477static int
bb467734 2478start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
46d4e165
JG
2479{
2480 int physical_cpu;
2481 int vector;
2482 u_long icr_lo, icr_hi;
2483
2484 POSTCODE(START_AP_POST);
2485
2486 /* get the PHYSICAL APIC ID# */
2487 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2488
2489 /* calculate the vector */
2490 vector = (boot_addr >> 12) & 0xff;
2491
bb467734
MD
2492 /* We don't want anything interfering */
2493 cpu_disable_intr();
2494
46d4e165
JG
2495 /* Make sure the target cpu sees everything */
2496 wbinvd();
2497
2498 /*
bb467734
MD
2499 * Try to detect when a SMI has occurred, wait up to 200ms.
2500 *
2501 * If a SMI occurs during an AP reset but before we issue
2502 * the STARTUP command, the AP may brick. To work around
2503 * this problem we hold off doing the AP startup until
2504 * after we have detected the SMI. Hopefully another SMI
2505 * will not occur before we finish the AP startup.
2506 *
2507 * Retries don't seem to help. SMIs have a window of opportunity
2508 * and if USB->legacy keyboard emulation is enabled in the BIOS
2509 * the interrupt rate can be quite high.
2510 *
2511 * NOTE: Don't worry about the L1 cache load, it might bloat
2512 * ldelta a little but ndelta will be so huge when the SMI
2513 * occurs the detection logic will still work fine.
2514 */
2515 if (smibest) {
2516 set_apic_timer(200000);
2517 smitest();
2518 }
2519
2520 /*
46d4e165
JG
2521 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2522 * and running the target CPU. OR this INIT IPI might be latched (P5
2523 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2524 * ignored.
bb467734
MD
2525 *
2526 * see apic/apicreg.h for icr bit definitions.
2527 *
2528 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
46d4e165
JG
2529 */
2530
bb467734
MD
2531 /*
2532 * Setup the address for the target AP. We can setup
2533 * icr_hi once and then just trigger operations with
2534 * icr_lo.
2535 */
46d4e165
JG
2536 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2537 icr_hi |= (physical_cpu << 24);
46d4e165 2538 icr_lo = lapic->icr_lo & 0xfff00000;
bb467734 2539 lapic->icr_hi = icr_hi;
46d4e165 2540
bb467734
MD
2541 /*
2542 * Do an INIT IPI: assert RESET
2543 *
2544 * Use edge triggered mode to assert INIT
2545 */
2546 lapic->icr_lo = icr_lo | 0x00004500;
46d4e165
JG
2547 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2548 /* spin */ ;
2549
bb467734
MD
2550 /*
2551 * The spec calls for a 10ms delay but we may have to use a
2552 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2553 * interrupt. We have other loops here too and dividing by 2
2554 * doesn't seem to be enough even after subtracting 350us,
2555 * so we divide by 4.
2556 *
2557 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2558 * interrupt was detected we use the full 10ms.
2559 */
2560 if (smibest == 0)
2561 u_sleep(10000);
2562 else if (smibest < 150 * 4 + 350)
2563 u_sleep(150);
2564 else if ((smibest - 350) / 4 < 10000)
2565 u_sleep((smibest - 350) / 4);
2566 else
2567 u_sleep(10000);
46d4e165 2568
bb467734
MD
2569 /*
2570 * Do an INIT IPI: deassert RESET
2571 *
2572 * Use level triggered mode to deassert. It is unclear
2573 * why we need to do this.
2574 */
2575 lapic->icr_lo = icr_lo | 0x00008500;
46d4e165
JG
2576 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2577 /* spin */ ;
bb467734 2578 u_sleep(150); /* wait 150us */
46d4e165
JG
2579
2580 /*
bb467734 2581 * Next we do a STARTUP IPI: the previous INIT IPI might still be
46d4e165
JG
2582 * latched, (P5 bug) this 1st STARTUP would then terminate
2583 * immediately, and the previously started INIT IPI would continue. OR
2584 * the previous INIT IPI has already run. and this STARTUP IPI will
2585 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2586 * will run.
2587 */
46d4e165
JG
2588 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2589 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2590 /* spin */ ;
2591 u_sleep(200); /* wait ~200uS */
2592
2593 /*
bb467734 2594 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
46d4e165
JG
2595 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2596 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2597 * recognized after hardware RESET or INIT IPI.
2598 */
46d4e165
JG
2599 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2600 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2601 /* spin */ ;
bb467734
MD
2602
2603 /* Resume normal operation */
2604 cpu_enable_intr();
46d4e165
JG
2605
2606 /* wait for it to start, see ap_init() */
2607 set_apic_timer(5000000);/* == 5 seconds */
2608 while (read_apic_timer()) {
2609 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2610 return 1; /* return SUCCESS */
2611 }
bb467734 2612
46d4e165
JG
2613 return 0; /* return FAILURE */
2614}
2615
bb467734
MD
2616static
2617int
2618smitest(void)
2619{
2620 int64_t ltsc;
2621 int64_t ntsc;
2622 int64_t ldelta;
2623 int64_t ndelta;
2624 int count;
2625
2626 ldelta = 0;
2627 ndelta = 0;
2628 while (read_apic_timer()) {
2629 ltsc = rdtsc();
2630 for (count = 0; count < 100; ++count)
2631 ntsc = rdtsc(); /* force loop to occur */
2632 if (ldelta) {
2633 ndelta = ntsc - ltsc;
2634 if (ldelta > ndelta)
2635 ldelta = ndelta;
2636 if (ndelta > ldelta * 2)
2637 break;
2638 } else {
2639 ldelta = ntsc - ltsc;
2640 }
2641 }
2642 return(read_apic_timer());
2643}
46d4e165
JG
2644
2645/*
2646 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2647 *
2648 * If for some reason we were unable to start all cpus we cannot safely
2649 * use broadcast IPIs.
2650 */
2651void
2652smp_invltlb(void)
2653{
2654#ifdef SMP
2655 if (smp_startup_mask == smp_active_mask) {
2656 all_but_self_ipi(XINVLTLB_OFFSET);
2657 } else {
2658 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2659 APIC_DELMODE_FIXED);
2660 }
2661#endif
2662}
2663
2664/*
2665 * When called the executing CPU will send an IPI to all other CPUs
2666 * requesting that they halt execution.
2667 *
2668 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2669 *
2670 * - Signals all CPUs in map to stop.
2671 * - Waits for each to stop.
2672 *
2673 * Returns:
2674 * -1: error
2675 * 0: NA
2676 * 1: ok
2677 *
2678 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2679 * from executing at same time.
2680 */
2681int
2682stop_cpus(u_int map)
2683{
2684 map &= smp_active_mask;
2685
2686 /* send the Xcpustop IPI to all CPUs in map */
2687 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2688
2689 while ((stopped_cpus & map) != map)
2690 /* spin */ ;
2691
2692 return 1;
2693}
2694
2695
2696/*
2697 * Called by a CPU to restart stopped CPUs.
2698 *
2699 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2700 *
2701 * - Signals all CPUs in map to restart.
2702 * - Waits for each to restart.
2703 *
2704 * Returns:
2705 * -1: error
2706 * 0: NA
2707 * 1: ok
2708 */
2709int
2710restart_cpus(u_int map)
2711{
2712 /* signal other cpus to restart */
2713 started_cpus = map & smp_active_mask;
2714
2715 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2716 /* spin */ ;
2717
2718 return 1;
2719}
2720
2721/*
2722 * This is called once the mpboot code has gotten us properly relocated
2723 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2724 * and when it returns the scheduler will call the real cpu_idle() main
2725 * loop for the idlethread. Interrupts are disabled on entry and should
2726 * remain disabled at return.
2727 */
2728void
2729ap_init(void)
2730{
2731 u_int apic_id;
2732
2733 /*
2734 * Adjust smp_startup_mask to signal the BSP that we have started
2735 * up successfully. Note that we do not yet hold the BGL. The BSP
2736 * is waiting for our signal.
2737 *
2738 * We can't set our bit in smp_active_mask yet because we are holding
2739 * interrupts physically disabled and remote cpus could deadlock
2740 * trying to send us an IPI.
2741 */
2742 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2743 cpu_mfence();
2744
2745 /*
2746 * Interlock for finalization. Wait until mp_finish is non-zero,
2747 * then get the MP lock.
2748 *
2749 * Note: We are in a critical section.
2750 *
2751 * Note: We have to synchronize td_mpcount to our desired MP state
2752 * before calling cpu_try_mplock().
2753 *
2754 * Note: we are the idle thread, we can only spin.
2755 *
2756 * Note: The load fence is memory volatile and prevents the compiler
2757 * from improperly caching mp_finish, and the cpu from improperly
2758 * caching it.
2759 */
2760 while (mp_finish == 0)
2761 cpu_lfence();
2762 ++curthread->td_mpcount;
2763 while (cpu_try_mplock() == 0)
2764 ;
2765
2766 if (cpu_feature & CPUID_TSC) {
2767 /*
2768 * The BSP is constantly updating tsc0_offset, figure out the
2769 * relative difference to synchronize ktrdump.
2770 */
2771 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2772 }
2773
2774 /* BSP may have changed PTD while we're waiting for the lock */
2775 cpu_invltlb();
2776
2777#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2778 lidt(&r_idt);
2779#endif
2780
2781 /* Build our map of 'other' CPUs. */
2782 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2783
2784 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2785
2786 /* A quick check from sanity claus */
2787 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2788 if (mycpu->gd_cpuid != apic_id) {
2789 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2790 kprintf("SMP: apic_id = %d\n", apic_id);
2791#if JGXXX
2792 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2793#endif
2794 panic("cpuid mismatch! boom!!");
2795 }
2796
2797 /* Initialize AP's local APIC for irq's */
2798 apic_initialize(FALSE);
2799
2800 /* Set memory range attributes for this CPU to match the BSP */
2801 mem_range_AP_init();
2802
2803 /*
2804 * Once we go active we must process any IPIQ messages that may
2805 * have been queued, because no actual IPI will occur until we
2806 * set our bit in the smp_active_mask. If we don't the IPI
2807 * message interlock could be left set which would also prevent
2808 * further IPIs.
2809 *
2810 * The idle loop doesn't expect the BGL to be held and while
2811 * lwkt_switch() normally cleans things up this is a special case
2812 * because we returning almost directly into the idle loop.
2813 *
2814 * The idle thread is never placed on the runq, make sure
2815 * nothing we've done put it there.
2816 */
2817 KKASSERT(curthread->td_mpcount == 1);
2818 smp_active_mask |= 1 << mycpu->gd_cpuid;
2819
2820 /*
2821 * Enable interrupts here. idle_restore will also do it, but
2822 * doing it here lets us clean up any strays that got posted to
2823 * the CPU during the AP boot while we are still in a critical
2824 * section.
2825 */
2826 __asm __volatile("sti; pause; pause"::);
2827 mdcpu->gd_fpending = 0;
46d4e165
JG
2828
2829 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2830 lwkt_process_ipiq();
2831
2832 /*
2833 * Releasing the mp lock lets the BSP finish up the SMP init
2834 */
2835 rel_mplock();
2836 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2837}
2838
2839/*
2840 * Get SMP fully working before we start initializing devices.
2841 */
2842static
2843void
2844ap_finish(void)
2845{
2846 mp_finish = 1;
2847 if (bootverbose)
2848 kprintf("Finish MP startup\n");
2849 if (cpu_feature & CPUID_TSC)
2850 tsc0_offset = rdtsc();
2851 tsc_offsets[0] = 0;
2852 rel_mplock();
2853 while (smp_active_mask != smp_startup_mask) {
2854 cpu_lfence();
2855 if (cpu_feature & CPUID_TSC)
2856 tsc0_offset = rdtsc();
2857 }
2858 while (try_mplock() == 0)
2859 ;
2860 if (bootverbose)
2861 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2862}
2863
2864SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2865
2866void
2867cpu_send_ipiq(int dcpu)
2868{
2869 if ((1 << dcpu) & smp_active_mask)
2870 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2871}
2872
2873#if 0 /* single_apic_ipi_passive() not working yet */
2874/*
2875 * Returns 0 on failure, 1 on success
2876 */
2877int
2878cpu_send_ipiq_passive(int dcpu)
2879{
2880 int r = 0;
2881 if ((1 << dcpu) & smp_active_mask) {
2882 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2883 APIC_DELMODE_FIXED);
2884 }
2885 return(r);
2886}
2887#endif
2888