<machine/specialreg.h>: Whitespace
[dragonfly.git] / sys / cpu / x86_64 / include / specialreg.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
c8fe38ae 3 * Copyright (c) 2008 The DragonFly Project.
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4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $
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32 */
33
34#ifndef _CPU_SPECIALREG_H_
35#define _CPU_SPECIALREG_H_
36
37/*
38 * Bits in 386 special registers:
39 */
40#define CR0_PE 0x00000001 /* Protected mode Enable */
41#define CR0_MP 0x00000002 /* "Math" (fpu) Present */
42#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
43#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
44#define CR0_PG 0x80000000 /* PaGing enable */
45
46/*
47 * Bits in 486 special registers:
48 */
49#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
50#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 all modes) */
52#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
53#define CR0_NW 0x20000000 /* Not Write-through */
54#define CR0_CD 0x40000000 /* Cache Disable */
55
56/*
57 * Bits in PPro special registers
58 */
59#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
60#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
61#define CR4_TSD 0x00000004 /* Time stamp disable */
62#define CR4_DE 0x00000008 /* Debugging extensions */
63#define CR4_PSE 0x00000010 /* Page size extensions */
64#define CR4_PAE 0x00000020 /* Physical address extension */
65#define CR4_MCE 0x00000040 /* Machine check enable */
66#define CR4_PGE 0x00000080 /* Page global enable */
67#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
68#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
69#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
70
71/*
b2b3ffcd 72 * Bits in x86_64 special registers. EFER is 64 bits wide.
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73 */
74#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
75#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
76#define EFER_LMA 0x000000400 /* Long mode active (R) */
77#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
78
79/*
80 * CPUID instruction features register
81 */
82#define CPUID_FPU 0x00000001
83#define CPUID_VME 0x00000002
84#define CPUID_DE 0x00000004
85#define CPUID_PSE 0x00000008
86#define CPUID_TSC 0x00000010
87#define CPUID_MSR 0x00000020
88#define CPUID_PAE 0x00000040
89#define CPUID_MCE 0x00000080
90#define CPUID_CX8 0x00000100
91#define CPUID_APIC 0x00000200
92#define CPUID_B10 0x00000400
93#define CPUID_SEP 0x00000800
94#define CPUID_MTRR 0x00001000
95#define CPUID_PGE 0x00002000
96#define CPUID_MCA 0x00004000
97#define CPUID_CMOV 0x00008000
98#define CPUID_PAT 0x00010000
99#define CPUID_PSE36 0x00020000
100#define CPUID_PSN 0x00040000
101#define CPUID_CLFSH 0x00080000
102#define CPUID_B20 0x00100000
103#define CPUID_DS 0x00200000
104#define CPUID_ACPI 0x00400000
105#define CPUID_MMX 0x00800000
106#define CPUID_FXSR 0x01000000
107#define CPUID_SSE 0x02000000
108#define CPUID_XMM 0x02000000
109#define CPUID_SSE2 0x04000000
110#define CPUID_SS 0x08000000
111#define CPUID_HTT 0x10000000
112#define CPUID_TM 0x20000000
113#define CPUID_IA64 0x40000000
114#define CPUID_PBE 0x80000000
115
116#define CPUID2_SSE3 0x00000001
f8f81a33 117#define CPUID2_PCLMULQDQ 0x00000002
a2a636cc 118#define CPUID2_DTES64 0x00000004
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119#define CPUID2_MON 0x00000008
120#define CPUID2_DS_CPL 0x00000010
121#define CPUID2_VMX 0x00000020
122#define CPUID2_SMX 0x00000040
123#define CPUID2_EST 0x00000080
124#define CPUID2_TM2 0x00000100
125#define CPUID2_SSSE3 0x00000200
126#define CPUID2_CNXTID 0x00000400
127#define CPUID2_CX16 0x00002000
128#define CPUID2_XTPR 0x00004000
129#define CPUID2_PDCM 0x00008000
130#define CPUID2_DCA 0x00040000
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131#define CPUID2_SSE41 0x00080000
132#define CPUID2_SSE42 0x00100000
133#define CPUID2_X2APIC 0x00200000
134#define CPUID2_POPCNT 0x00800000
f8f81a33 135#define CPUID2_AESNI 0x02000000
f6c459b2 136#define CPUID2_VMM 0x80000000
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137
138/*
139 * Important bits in the AMD extended cpuid flags
140 */
141#define AMDID_SYSCALL 0x00000800
142#define AMDID_MP 0x00080000
143#define AMDID_NX 0x00100000
144#define AMDID_EXT_MMX 0x00400000
145#define AMDID_FFXSR 0x01000000
c8fe38ae 146#define AMDID_PAGE1GB 0x04000000
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147#define AMDID_RDTSCP 0x08000000
148#define AMDID_LM 0x20000000
149#define AMDID_EXT_3DNOW 0x40000000
150#define AMDID_3DNOW 0x80000000
151
152#define AMDID2_LAHF 0x00000001
153#define AMDID2_CMP 0x00000002
154#define AMDID2_SVM 0x00000004
155#define AMDID2_EXT_APIC 0x00000008
156#define AMDID2_CR8 0x00000010
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157#define AMDID2_ABM 0x00000020
158#define AMDID2_SSE4A 0x00000040
159#define AMDID2_MAS 0x00000080
d7f50089 160#define AMDID2_PREFETCH 0x00000100
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161#define AMDID2_OSVW 0x00000200
162#define AMDID2_IBS 0x00000400
163#define AMDID2_SSE5 0x00000800
164#define AMDID2_SKINIT 0x00001000
165#define AMDID2_WDT 0x00002000
166
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167/*
168 * CPUID instruction 1 eax info
169 */
170#define CPUID_STEPPING 0x0000000f
171#define CPUID_MODEL 0x000000f0
172#define CPUID_FAMILY 0x00000f00
173#define CPUID_EXT_MODEL 0x000f0000
174#define CPUID_EXT_FAMILY 0x0ff00000
b2b3ffcd 175#define X86_64_CPU_MODEL(id) \
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176 ((((id) & CPUID_MODEL) >> 4) | \
177 (((id) & CPUID_EXT_MODEL) >> 12))
b2b3ffcd 178#define X86_64_CPU_FAMILY(id) \
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179 ((((id) & CPUID_FAMILY) >> 8) + \
180 (((id) & CPUID_EXT_FAMILY) >> 20))
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181
182/*
183 * CPUID instruction 1 ebx info
184 */
185#define CPUID_BRAND_INDEX 0x000000ff
186#define CPUID_CLFUSH_SIZE 0x0000ff00
187#define CPUID_HTT_CORES 0x00ff0000
188#define CPUID_LOCAL_APIC_ID 0xff000000
189
190/*
191 * AMD extended function 8000_0008h ecx info
192 */
193#define AMDID_CMP_CORES 0x000000ff
194
195/*
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196 * CPUID manufacturers identifiers
197 */
198#define AMD_VENDOR_ID "AuthenticAMD"
199#define CENTAUR_VENDOR_ID "CentaurHauls"
200#define INTEL_VENDOR_ID "GenuineIntel"
201
202/*
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203 * Model-specific registers for the i386 family
204 */
205#define MSR_P5_MC_ADDR 0x000
206#define MSR_P5_MC_TYPE 0x001
207#define MSR_TSC 0x010
208#define MSR_P5_CESR 0x011
209#define MSR_P5_CTR0 0x012
210#define MSR_P5_CTR1 0x013
211#define MSR_IA32_PLATFORM_ID 0x017
212#define MSR_APICBASE 0x01b
213#define MSR_EBL_CR_POWERON 0x02a
214#define MSR_TEST_CTL 0x033
215#define MSR_BIOS_UPDT_TRIG 0x079
216#define MSR_BBL_CR_D0 0x088
217#define MSR_BBL_CR_D1 0x089
218#define MSR_BBL_CR_D2 0x08a
219#define MSR_BIOS_SIGN 0x08b
220#define MSR_PERFCTR0 0x0c1
221#define MSR_PERFCTR1 0x0c2
a2a636cc 222#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
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223#define MSR_MTRRcap 0x0fe
224#define MSR_BBL_CR_ADDR 0x116
225#define MSR_BBL_CR_DECC 0x118
226#define MSR_BBL_CR_CTL 0x119
227#define MSR_BBL_CR_TRIG 0x11a
228#define MSR_BBL_CR_BUSY 0x11b
229#define MSR_BBL_CR_CTL3 0x11e
230#define MSR_SYSENTER_CS_MSR 0x174
231#define MSR_SYSENTER_ESP_MSR 0x175
232#define MSR_SYSENTER_EIP_MSR 0x176
233#define MSR_MCG_CAP 0x179
234#define MSR_MCG_STATUS 0x17a
235#define MSR_MCG_CTL 0x17b
236#define MSR_EVNTSEL0 0x186
237#define MSR_EVNTSEL1 0x187
238#define MSR_THERM_CONTROL 0x19a
239#define MSR_THERM_INTERRUPT 0x19b
240#define MSR_THERM_STATUS 0x19c
241#define MSR_IA32_MISC_ENABLE 0x1a0
242#define MSR_DEBUGCTLMSR 0x1d9
243#define MSR_LASTBRANCHFROMIP 0x1db
244#define MSR_LASTBRANCHTOIP 0x1dc
245#define MSR_LASTINTFROMIP 0x1dd
246#define MSR_LASTINTTOIP 0x1de
247#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
248#define MSR_MTRRVarBase 0x200
249#define MSR_MTRR64kBase 0x250
250#define MSR_MTRR16kBase 0x258
251#define MSR_MTRR4kBase 0x268
252#define MSR_PAT 0x277
253#define MSR_MTRRdefType 0x2ff
254#define MSR_MC0_CTL 0x400
255#define MSR_MC0_STATUS 0x401
256#define MSR_MC0_ADDR 0x402
257#define MSR_MC0_MISC 0x403
258#define MSR_MC1_CTL 0x404
259#define MSR_MC1_STATUS 0x405
260#define MSR_MC1_ADDR 0x406
261#define MSR_MC1_MISC 0x407
262#define MSR_MC2_CTL 0x408
263#define MSR_MC2_STATUS 0x409
264#define MSR_MC2_ADDR 0x40a
265#define MSR_MC2_MISC 0x40b
266#define MSR_MC3_CTL 0x40c
267#define MSR_MC3_STATUS 0x40d
268#define MSR_MC3_ADDR 0x40e
269#define MSR_MC3_MISC 0x40f
270#define MSR_MC4_CTL 0x410
271#define MSR_MC4_STATUS 0x411
272#define MSR_MC4_ADDR 0x412
273#define MSR_MC4_MISC 0x413
274
275/*
276 * Constants related to MSR's.
277 */
278#define APICBASE_RESERVED 0x000006ff
279#define APICBASE_BSP 0x00000100
280#define APICBASE_ENABLED 0x00000800
281#define APICBASE_ADDRESS 0xfffff000
282
283/*
284 * PAT modes.
285 */
286#define PAT_UNCACHEABLE 0x00
287#define PAT_WRITE_COMBINING 0x01
288#define PAT_WRITE_THROUGH 0x04
289#define PAT_WRITE_PROTECTED 0x05
290#define PAT_WRITE_BACK 0x06
291#define PAT_UNCACHED 0x07
292#define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
293#define PAT_MASK(i) PAT_VALUE(i, 0xff)
294
295/*
296 * Constants related to MTRRs
297 */
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298#define MTRR_UNCACHEABLE 0x00
299#define MTRR_WRITE_COMBINING 0x01
300#define MTRR_WRITE_THROUGH 0x04
301#define MTRR_WRITE_PROTECTED 0x05
302#define MTRR_WRITE_BACK 0x06
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303#define MTRR_N64K 8 /* numbers of fixed-size entries */
304#define MTRR_N16K 16
305#define MTRR_N4K 64
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306#define MTRR_CAP_WC 0x0000000000000400UL
307#define MTRR_CAP_FIXED 0x0000000000000100UL
308#define MTRR_CAP_VCNT 0x00000000000000ffUL
309#define MTRR_DEF_ENABLE 0x0000000000000800UL
310#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL
311#define MTRR_DEF_TYPE 0x00000000000000ffUL
312#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL
313#define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL
314#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL
315#define MTRR_PHYSMASK_VALID 0x0000000000000800UL
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316
317/* Performance Control Register (5x86 only). */
318#define PCR0 0x20
319#define PCR0_RSTK 0x01 /* Enables return stack */
320#define PCR0_BTB 0x02 /* Enables branch target buffer */
321#define PCR0_LOOP 0x04 /* Enables loop */
322#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
323 serialize pipe. */
324#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
325#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
326#define PCR0_LSSER 0x80 /* Disable reorder */
327
328/* Device Identification Registers */
329#define DIR0 0xfe
330#define DIR1 0xff
331
332/*
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333 * Machine Check register constants.
334 */
335#define MCG_CAP_COUNT 0x000000ff
336#define MCG_CAP_CTL_P 0x00000100
337#define MCG_CAP_EXT_P 0x00000200
338#define MCG_CAP_TES_P 0x00000800
339#define MCG_CAP_EXT_CNT 0x00ff0000
340#define MCG_STATUS_RIPV 0x00000001
341#define MCG_STATUS_EIPV 0x00000002
342#define MCG_STATUS_MCIP 0x00000004
343#define MCG_CTL_ENABLE 0xffffffffffffffffUL
344#define MCG_CTL_DISABLE 0x0000000000000000UL
345#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
346#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
347#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
348#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
349#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL
350#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL
351#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL
352#define MC_STATUS_PCC 0x0200000000000000UL
353#define MC_STATUS_ADDRV 0x0400000000000000UL
354#define MC_STATUS_MISCV 0x0800000000000000UL
355#define MC_STATUS_EN 0x1000000000000000UL
356#define MC_STATUS_UC 0x2000000000000000UL
357#define MC_STATUS_OVER 0x4000000000000000UL
358#define MC_STATUS_VAL 0x8000000000000000UL
359
360/*
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361 * The following four 3-byte registers control the non-cacheable regions.
362 * These registers must be written as three separate bytes.
363 *
364 * NCRx+0: A31-A24 of starting address
365 * NCRx+1: A23-A16 of starting address
366 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
367 *
368 * The non-cacheable region's starting address must be aligned to the
369 * size indicated by the NCR_SIZE_xx field.
370 */
371#define NCR1 0xc4
372#define NCR2 0xc7
373#define NCR3 0xca
374#define NCR4 0xcd
375
376#define NCR_SIZE_0K 0
377#define NCR_SIZE_4K 1
378#define NCR_SIZE_8K 2
379#define NCR_SIZE_16K 3
380#define NCR_SIZE_32K 4
381#define NCR_SIZE_64K 5
382#define NCR_SIZE_128K 6
383#define NCR_SIZE_256K 7
384#define NCR_SIZE_512K 8
385#define NCR_SIZE_1M 9
386#define NCR_SIZE_2M 10
387#define NCR_SIZE_4M 11
388#define NCR_SIZE_8M 12
389#define NCR_SIZE_16M 13
390#define NCR_SIZE_32M 14
391#define NCR_SIZE_4G 15
392
393/*
394 * The address region registers are used to specify the location and
395 * size for the eight address regions.
396 *
397 * ARRx + 0: A31-A24 of start address
398 * ARRx + 1: A23-A16 of start address
399 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
400 */
401#define ARR0 0xc4
402#define ARR1 0xc7
403#define ARR2 0xca
404#define ARR3 0xcd
405#define ARR4 0xd0
406#define ARR5 0xd3
407#define ARR6 0xd6
408#define ARR7 0xd9
409
410#define ARR_SIZE_0K 0
411#define ARR_SIZE_4K 1
412#define ARR_SIZE_8K 2
413#define ARR_SIZE_16K 3
414#define ARR_SIZE_32K 4
415#define ARR_SIZE_64K 5
416#define ARR_SIZE_128K 6
417#define ARR_SIZE_256K 7
418#define ARR_SIZE_512K 8
419#define ARR_SIZE_1M 9
420#define ARR_SIZE_2M 10
421#define ARR_SIZE_4M 11
422#define ARR_SIZE_8M 12
423#define ARR_SIZE_16M 13
424#define ARR_SIZE_32M 14
425#define ARR_SIZE_4G 15
426
427/*
428 * The region control registers specify the attributes associated with
429 * the ARRx addres regions.
430 */
431#define RCR0 0xdc
432#define RCR1 0xdd
433#define RCR2 0xde
434#define RCR3 0xdf
435#define RCR4 0xe0
436#define RCR5 0xe1
437#define RCR6 0xe2
438#define RCR7 0xe3
439
440#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
441#define RCR_RCE 0x01 /* Enables caching for ARR7. */
442#define RCR_WWO 0x02 /* Weak write ordering. */
443#define RCR_WL 0x04 /* Weak locking. */
444#define RCR_WG 0x08 /* Write gathering. */
445#define RCR_WT 0x10 /* Write-through. */
446#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
447
448/* AMD Write Allocate Top-Of-Memory and Control Register */
449#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
450#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
451#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
452
b2b3ffcd 453/* x86_64 MSR's */
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454#define MSR_EFER 0xc0000080 /* extended features */
455#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
456#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
457#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
458#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
459#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
460#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
461#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
462#define MSR_PERFEVSEL0 0xc0010000
463#define MSR_PERFEVSEL1 0xc0010001
464#define MSR_PERFEVSEL2 0xc0010002
465#define MSR_PERFEVSEL3 0xc0010003
466#undef MSR_PERFCTR0
467#undef MSR_PERFCTR1
468#define MSR_PERFCTR0 0xc0010004
469#define MSR_PERFCTR1 0xc0010005
470#define MSR_PERFCTR2 0xc0010006
471#define MSR_PERFCTR3 0xc0010007
472#define MSR_SYSCFG 0xc0010010
473#define MSR_IORRBASE0 0xc0010016
474#define MSR_IORRMASK0 0xc0010017
475#define MSR_IORRBASE1 0xc0010018
476#define MSR_IORRMASK1 0xc0010019
477#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
478#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
a2a636cc 479#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
d7f50089 480
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481/* VIA ACE crypto featureset: for via_feature_rng */
482#define VIA_HAS_RNG 1 /* cpu has RNG */
483
484/* VIA ACE crypto featureset: for via_feature_xcrypt */
485#define VIA_HAS_AES 1 /* cpu has AES */
486#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
487#define VIA_HAS_MM 4 /* cpu has RSA instructions */
488#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
489
490/* Centaur Extended Feature flags */
491#define VIA_CPUID_HAS_RNG 0x000004
492#define VIA_CPUID_DO_RNG 0x000008
493#define VIA_CPUID_HAS_ACE 0x000040
494#define VIA_CPUID_DO_ACE 0x000080
495#define VIA_CPUID_HAS_ACE2 0x000100
496#define VIA_CPUID_DO_ACE2 0x000200
497#define VIA_CPUID_HAS_PHE 0x000400
498#define VIA_CPUID_DO_PHE 0x000800
499#define VIA_CPUID_HAS_PMM 0x001000
500#define VIA_CPUID_DO_PMM 0x002000
501
d7f50089 502#endif /* !_CPU_SPECIALREG_H_ */