kernel: Fix the remaining gcc44 warnings for the kernel.
[dragonfly.git] / sys / dev / disk / sym / sym_hipd.c
CommitLineData
984263bc
MD
1/*
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58/* $FreeBSD: src/sys/dev/sym/sym_hipd.c,v 1.6.2.12 2001/12/02 19:01:10 groudier Exp $ */
59
60#define SYM_DRIVER_NAME "sym-1.6.5-20000902"
61
62/* #define SYM_DEBUG_GENERIC_SUPPORT */
984263bc 63
984263bc
MD
64#include <sys/param.h>
65
66/*
67 * Only use the BUS stuff for PCI under FreeBSD 4 and later versions.
68 * Note that the old BUS stuff also works for FreeBSD 4 and spares
69 * about 1 KB for the driver object file.
70 */
84754cd0 71#if defined(__DragonFly__) || __FreeBSD_version >= 400000
984263bc
MD
72#define FreeBSD_Bus_Dma_Abstraction
73#define FreeBSD_Bus_Io_Abstraction
74#define FreeBSD_Bus_Space_Abstraction
75#endif
76
77/*
78 * Driver configuration options.
79 */
80#include "opt_sym.h"
1f2de5d4 81#include "sym_conf.h"
984263bc
MD
82
83#ifndef FreeBSD_Bus_Io_Abstraction
1f2de5d4 84#include "use_ncr.h" /* To know if the ncr has been configured */
984263bc
MD
85#endif
86
87#include <sys/systm.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#ifdef FreeBSD_Bus_Io_Abstraction
91#include <sys/module.h>
92#include <sys/bus.h>
1f7ab7c9 93#include <sys/rman.h>
984263bc 94#endif
2c9868e4 95#include <sys/thread2.h>
984263bc
MD
96
97#include <sys/proc.h>
98
1f2de5d4
MD
99#include <bus/pci/pcireg.h>
100#include <bus/pci/pcivar.h>
984263bc 101
984263bc
MD
102#include <machine/clock.h>
103
1f2de5d4
MD
104#include <bus/cam/cam.h>
105#include <bus/cam/cam_ccb.h>
106#include <bus/cam/cam_sim.h>
107#include <bus/cam/cam_xpt_sim.h>
108#include <bus/cam/cam_debug.h>
984263bc 109
1f2de5d4
MD
110#include <bus/cam/scsi/scsi_all.h>
111#include <bus/cam/scsi/scsi_message.h>
984263bc
MD
112
113#include <vm/vm.h>
114#include <vm/vm_param.h>
115#include <vm/pmap.h>
116
117/* Short and quite clear integer types */
118typedef int8_t s8;
119typedef int16_t s16;
120typedef int32_t s32;
121typedef u_int8_t u8;
122typedef u_int16_t u16;
123typedef u_int32_t u32;
124
984263bc
MD
125/*
126 * Driver definitions.
127 */
1f2de5d4
MD
128#include "sym_defs.h"
129#include "sym_fw.h"
984263bc
MD
130
131/*
132 * IA32 architecture does not reorder STORES and prevents
133 * LOADS from passing STORES. It is called `program order'
134 * by Intel and allows device drivers to deal with memory
135 * ordering by only ensuring that the code is not reordered
136 * by the compiler when ordering is required.
137 * Other architectures implement a weaker ordering that
138 * requires memory barriers (and also IO barriers when they
139 * make sense) to be used.
140 */
141
b2b3ffcd 142#if defined __i386__ || defined __x86_64__
984263bc 143#define MEMORY_BARRIER() do { ; } while(0)
984263bc
MD
144#elif defined __powerpc__
145#define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
146#elif defined __ia64__
147#define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
148#elif defined __sparc64__
149#define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory")
150#else
151#error "Not supported platform"
152#endif
153
154/*
155 * Portable but silly implemented byte order primitives.
156 * We define the primitives we need, since FreeBSD doesn't
157 * seem to have them yet.
158 */
159#if BYTE_ORDER == BIG_ENDIAN
160
161#define __revb16(x) ( (((u16)(x) & (u16)0x00ffU) << 8) | \
162 (((u16)(x) & (u16)0xff00U) >> 8) )
163#define __revb32(x) ( (((u32)(x) & 0x000000ffU) << 24) | \
164 (((u32)(x) & 0x0000ff00U) << 8) | \
165 (((u32)(x) & 0x00ff0000U) >> 8) | \
166 (((u32)(x) & 0xff000000U) >> 24) )
167
168#define __htole16(v) __revb16(v)
169#define __htole32(v) __revb32(v)
170#define __le16toh(v) __htole16(v)
171#define __le32toh(v) __htole32(v)
172
173static __inline u16 _htole16(u16 v) { return __htole16(v); }
174static __inline u32 _htole32(u32 v) { return __htole32(v); }
175#define _le16toh _htole16
176#define _le32toh _htole32
177
178#else /* LITTLE ENDIAN */
179
180#define __htole16(v) (v)
181#define __htole32(v) (v)
182#define __le16toh(v) (v)
183#define __le32toh(v) (v)
184
185#define _htole16(v) (v)
186#define _htole32(v) (v)
187#define _le16toh(v) (v)
188#define _le32toh(v) (v)
189
190#endif /* BYTE_ORDER */
191
192/*
193 * A la VMS/CAM-3 queue management.
194 */
195
196typedef struct sym_quehead {
197 struct sym_quehead *flink; /* Forward pointer */
198 struct sym_quehead *blink; /* Backward pointer */
199} SYM_QUEHEAD;
200
201#define sym_que_init(ptr) do { \
202 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \
203} while (0)
204
205static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head)
206{
207 return (head->flink == head) ? 0 : head->flink;
208}
209
210static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head)
211{
212 return (head->blink == head) ? 0 : head->blink;
213}
214
215static __inline void __sym_que_add(struct sym_quehead * new,
216 struct sym_quehead * blink,
217 struct sym_quehead * flink)
218{
219 flink->blink = new;
220 new->flink = flink;
221 new->blink = blink;
222 blink->flink = new;
223}
224
225static __inline void __sym_que_del(struct sym_quehead * blink,
226 struct sym_quehead * flink)
227{
228 flink->blink = blink;
229 blink->flink = flink;
230}
231
232static __inline int sym_que_empty(struct sym_quehead *head)
233{
234 return head->flink == head;
235}
236
237static __inline void sym_que_splice(struct sym_quehead *list,
238 struct sym_quehead *head)
239{
240 struct sym_quehead *first = list->flink;
241
242 if (first != list) {
243 struct sym_quehead *last = list->blink;
244 struct sym_quehead *at = head->flink;
245
246 first->blink = head;
247 head->flink = first;
248
249 last->flink = at;
250 at->blink = last;
251 }
252}
253
254#define sym_que_entry(ptr, type, member) \
fddeaa50 255 ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member)))
984263bc
MD
256
257
258#define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
259
260#define sym_remque(el) __sym_que_del((el)->blink, (el)->flink)
261
262#define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink)
263
264static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head)
265{
266 struct sym_quehead *elem = head->flink;
267
268 if (elem != head)
269 __sym_que_del(head, elem->flink);
270 else
271 elem = 0;
272 return elem;
273}
274
275#define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head)
276
277static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head)
278{
279 struct sym_quehead *elem = head->blink;
280
281 if (elem != head)
282 __sym_que_del(elem->blink, head);
283 else
284 elem = 0;
285 return elem;
286}
287
288/*
289 * This one may be useful.
290 */
291#define FOR_EACH_QUEUED_ELEMENT(head, qp) \
292 for (qp = (head)->flink; qp != (head); qp = qp->flink)
293/*
294 * FreeBSD does not offer our kind of queue in the CAM CCB.
295 * So, we have to cast.
296 */
297#define sym_qptr(p) ((struct sym_quehead *) (p))
298
299/*
300 * Simple bitmap operations.
301 */
302#define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))
303#define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))
304#define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))
305
306/*
307 * Number of tasks per device we want to handle.
308 */
309#if SYM_CONF_MAX_TAG_ORDER > 8
310#error "more than 256 tags per logical unit not allowed."
311#endif
312#define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER)
313
314/*
315 * Donnot use more tasks that we can handle.
316 */
317#ifndef SYM_CONF_MAX_TAG
318#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
319#endif
320#if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK
321#undef SYM_CONF_MAX_TAG
322#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
323#endif
324
325/*
326 * This one means 'NO TAG for this job'
327 */
328#define NO_TAG (256)
329
330/*
331 * Number of SCSI targets.
332 */
333#if SYM_CONF_MAX_TARGET > 16
334#error "more than 16 targets not allowed."
335#endif
336
337/*
338 * Number of logical units per target.
339 */
340#if SYM_CONF_MAX_LUN > 64
341#error "more than 64 logical units per target not allowed."
342#endif
343
344/*
345 * Asynchronous pre-scaler (ns). Shall be 40 for
346 * the SCSI timings to be compliant.
347 */
348#define SYM_CONF_MIN_ASYNC (40)
349
350/*
351 * Number of entries in the START and DONE queues.
352 *
353 * We limit to 1 PAGE in order to succeed allocation of
354 * these queues. Each entry is 8 bytes long (2 DWORDS).
355 */
356#ifdef SYM_CONF_MAX_START
357#define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2)
358#else
359#define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2)
360#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
361#endif
362
363#if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8
364#undef SYM_CONF_MAX_QUEUE
365#define SYM_CONF_MAX_QUEUE PAGE_SIZE/8
366#undef SYM_CONF_MAX_START
367#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
368#endif
369
370/*
371 * For this one, we want a short name :-)
372 */
373#define MAX_QUEUE SYM_CONF_MAX_QUEUE
374
984263bc
MD
375/*
376 * Active debugging tags and verbosity.
377 */
378#define DEBUG_ALLOC (0x0001)
379#define DEBUG_PHASE (0x0002)
380#define DEBUG_POLL (0x0004)
381#define DEBUG_QUEUE (0x0008)
382#define DEBUG_RESULT (0x0010)
383#define DEBUG_SCATTER (0x0020)
384#define DEBUG_SCRIPT (0x0040)
385#define DEBUG_TINY (0x0080)
386#define DEBUG_TIMING (0x0100)
387#define DEBUG_NEGO (0x0200)
388#define DEBUG_TAGS (0x0400)
389#define DEBUG_POINTER (0x0800)
390
391#if 0
392static int sym_debug = 0;
393 #define DEBUG_FLAGS sym_debug
394#else
395/* #define DEBUG_FLAGS (0x0631) */
396 #define DEBUG_FLAGS (0x0000)
397
398#endif
399#define sym_verbose (np->verbose)
400
401/*
402 * Insert a delay in micro-seconds and milli-seconds.
403 */
404static void UDELAY(int us) { DELAY(us); }
405static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
406
407/*
408 * Simple power of two buddy-like allocator.
409 *
410 * This simple code is not intended to be fast, but to
411 * provide power of 2 aligned memory allocations.
412 * Since the SCRIPTS processor only supplies 8 bit arithmetic,
413 * this allocator allows simple and fast address calculations
414 * from the SCRIPTS code. In addition, cache line alignment
415 * is guaranteed for power of 2 cache line size.
416 *
417 * This allocator has been developped for the Linux sym53c8xx
418 * driver, since this O/S does not provide naturally aligned
419 * allocations.
420 * It has the advantage of allowing the driver to use private
421 * pages of memory that will be useful if we ever need to deal
422 * with IO MMUs for PCI.
423 */
424
425#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
426#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
427#if 0
428#define MEMO_FREE_UNUSED /* Free unused pages immediately */
429#endif
430#define MEMO_WARN 1
431#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
432#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
433#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
434
efda3bd0
MD
435#define get_pages() kmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_INTWAIT)
436#define free_pages(p) kfree((p), M_DEVBUF)
984263bc
MD
437
438typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
439
440typedef struct m_link { /* Link between free memory chunks */
441 struct m_link *next;
442} m_link_s;
443
444#ifdef FreeBSD_Bus_Dma_Abstraction
445typedef struct m_vtob { /* Virtual to Bus address translation */
446 struct m_vtob *next;
447 bus_dmamap_t dmamap; /* Map for this chunk */
448 m_addr_t vaddr; /* Virtual address */
449 m_addr_t baddr; /* Bus physical address */
450} m_vtob_s;
451/* Hash this stuff a bit to speed up translations */
452#define VTOB_HASH_SHIFT 5
453#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
454#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
455#define VTOB_HASH_CODE(m) \
456 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
457#endif
458
459typedef struct m_pool { /* Memory pool of a given kind */
460#ifdef FreeBSD_Bus_Dma_Abstraction
461 bus_dma_tag_t dev_dmat; /* Identifies the pool */
462 bus_dma_tag_t dmat; /* Tag for our fixed allocations */
463 m_addr_t (*getp)(struct m_pool *);
464#ifdef MEMO_FREE_UNUSED
465 void (*freep)(struct m_pool *, m_addr_t);
466#endif
467#define M_GETP() mp->getp(mp)
468#define M_FREEP(p) mp->freep(mp, p)
469 int nump;
470 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
471 struct m_pool *next;
472#else
473#define M_GETP() get_pages()
474#define M_FREEP(p) free_pages(p)
475#endif /* FreeBSD_Bus_Dma_Abstraction */
476 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1];
477} m_pool_s;
478
479static void *___sym_malloc(m_pool_s *mp, int size)
480{
481 int i = 0;
482 int s = (1 << MEMO_SHIFT);
483 int j;
484 m_addr_t a;
485 m_link_s *h = mp->h;
486
487 if (size > MEMO_CLUSTER_SIZE)
488 return 0;
489
490 while (size > s) {
491 s <<= 1;
492 ++i;
493 }
494
495 j = i;
496 while (!h[j].next) {
497 if (s == MEMO_CLUSTER_SIZE) {
498 h[j].next = (m_link_s *) M_GETP();
499 if (h[j].next)
500 h[j].next->next = 0;
501 break;
502 }
503 ++j;
504 s <<= 1;
505 }
506 a = (m_addr_t) h[j].next;
507 if (a) {
508 h[j].next = h[j].next->next;
509 while (j > i) {
510 j -= 1;
511 s >>= 1;
512 h[j].next = (m_link_s *) (a+s);
513 h[j].next->next = 0;
514 }
515 }
516#ifdef DEBUG
e3869ec7 517 kprintf("___sym_malloc(%d) = %p\n", size, (void *) a);
984263bc
MD
518#endif
519 return (void *) a;
520}
521
522static void ___sym_mfree(m_pool_s *mp, void *ptr, int size)
523{
524 int i = 0;
525 int s = (1 << MEMO_SHIFT);
526 m_link_s *q;
527 m_addr_t a, b;
528 m_link_s *h = mp->h;
529
530#ifdef DEBUG
e3869ec7 531 kprintf("___sym_mfree(%p, %d)\n", ptr, size);
984263bc
MD
532#endif
533
534 if (size > MEMO_CLUSTER_SIZE)
535 return;
536
537 while (size > s) {
538 s <<= 1;
539 ++i;
540 }
541
542 a = (m_addr_t) ptr;
543
544 while (1) {
545#ifdef MEMO_FREE_UNUSED
546 if (s == MEMO_CLUSTER_SIZE) {
547 M_FREEP(a);
548 break;
549 }
550#endif
551 b = a ^ s;
552 q = &h[i];
553 while (q->next && q->next != (m_link_s *) b) {
554 q = q->next;
555 }
556 if (!q->next) {
557 ((m_link_s *) a)->next = h[i].next;
558 h[i].next = (m_link_s *) a;
559 break;
560 }
561 q->next = q->next->next;
562 a = a & b;
563 s <<= 1;
564 ++i;
565 }
566}
567
568static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags)
569{
570 void *p;
571
572 p = ___sym_malloc(mp, size);
573
574 if (DEBUG_FLAGS & DEBUG_ALLOC)
e3869ec7 575 kprintf ("new %-10s[%4d] @%p.\n", name, size, p);
984263bc
MD
576
577 if (p)
578 bzero(p, size);
579 else if (uflags & MEMO_WARN)
e3869ec7 580 kprintf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size);
984263bc
MD
581
582 return p;
583}
584
585#define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN)
586
587static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name)
588{
589 if (DEBUG_FLAGS & DEBUG_ALLOC)
e3869ec7 590 kprintf ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
984263bc
MD
591
592 ___sym_mfree(mp, ptr, size);
593
594}
595
596/*
597 * Default memory pool we donnot need to involve in DMA.
598 */
599#ifndef FreeBSD_Bus_Dma_Abstraction
600/*
601 * Without the `bus dma abstraction', all the memory is assumed
602 * DMAable and a single pool is all what we need.
603 */
604static m_pool_s mp0;
605
606#else
607/*
608 * With the `bus dma abstraction', we use a separate pool for
609 * memory we donnot need to involve in DMA.
610 */
611static m_addr_t ___mp0_getp(m_pool_s *mp)
612{
613 m_addr_t m = (m_addr_t) get_pages();
614 if (m)
615 ++mp->nump;
616 return m;
617}
618
619#ifdef MEMO_FREE_UNUSED
620static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
621{
622 free_pages(m);
623 --mp->nump;
624}
625#endif
626
627#ifdef MEMO_FREE_UNUSED
628static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep};
629#else
630static m_pool_s mp0 = {0, 0, ___mp0_getp};
631#endif
632
633#endif /* FreeBSD_Bus_Dma_Abstraction */
634
635/*
636 * Actual memory allocation routine for non-DMAed memory.
637 */
638static void *sym_calloc(int size, char *name)
639{
640 void *m;
641 /* Lock */
642 m = __sym_calloc(&mp0, size, name);
643 /* Unlock */
644 return m;
645}
646
647/*
648 * Actual memory allocation routine for non-DMAed memory.
649 */
650static void sym_mfree(void *ptr, int size, char *name)
651{
652 /* Lock */
653 __sym_mfree(&mp0, ptr, size, name);
654 /* Unlock */
655}
656
657/*
658 * DMAable pools.
659 */
660#ifndef FreeBSD_Bus_Dma_Abstraction
661/*
662 * Without `bus dma abstraction', all the memory is DMAable, and
663 * only a single pool is needed (vtophys() is our friend).
664 */
665#define __sym_calloc_dma(b, s, n) sym_calloc(s, n)
666#define __sym_mfree_dma(b, p, s, n) sym_mfree(p, s, n)
984263bc 667#define __vtobus(b, p) vtophys(p)
984263bc
MD
668
669#else
670/*
671 * With `bus dma abstraction', we use a separate pool per parent
672 * BUS handle. A reverse table (hashed) is maintained for virtual
673 * to BUS address translation.
674 */
675static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
676{
677 bus_addr_t *baddr;
678 baddr = (bus_addr_t *)arg;
679 *baddr = segs->ds_addr;
680}
681
682static m_addr_t ___dma_getp(m_pool_s *mp)
683{
684 m_vtob_s *vbp;
685 void *vaddr = 0;
686 bus_addr_t baddr = 0;
687
688 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB");
689 if (!vbp)
690 goto out_err;
691
692 if (bus_dmamem_alloc(mp->dmat, &vaddr,
693 BUS_DMA_NOWAIT, &vbp->dmamap))
694 goto out_err;
695 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr,
696 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0);
697 if (baddr) {
698 int hc = VTOB_HASH_CODE(vaddr);
699 vbp->vaddr = (m_addr_t) vaddr;
700 vbp->baddr = (m_addr_t) baddr;
701 vbp->next = mp->vtob[hc];
702 mp->vtob[hc] = vbp;
703 ++mp->nump;
704 return (m_addr_t) vaddr;
705 }
706out_err:
707 if (baddr)
708 bus_dmamap_unload(mp->dmat, vbp->dmamap);
709 if (vaddr)
710 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap);
711 if (vbp->dmamap)
712 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
713 if (vbp)
714 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
715 return 0;
716}
717
718#ifdef MEMO_FREE_UNUSED
719static void ___dma_freep(m_pool_s *mp, m_addr_t m)
720{
721 m_vtob_s **vbpp, *vbp;
722 int hc = VTOB_HASH_CODE(m);
723
724 vbpp = &mp->vtob[hc];
725 while (*vbpp && (*vbpp)->vaddr != m)
726 vbpp = &(*vbpp)->next;
727 if (*vbpp) {
728 vbp = *vbpp;
729 *vbpp = (*vbpp)->next;
730 bus_dmamap_unload(mp->dmat, vbp->dmamap);
731 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap);
732 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
733 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
734 --mp->nump;
735 }
736}
737#endif
738
739static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat)
740{
741 m_pool_s *mp;
742 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next);
743 return mp;
744}
745
746static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat)
747{
748 m_pool_s *mp = 0;
749
750 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL");
751 if (mp) {
752 mp->dev_dmat = dev_dmat;
753 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE,
754 BUS_SPACE_MAXADDR_32BIT,
755 BUS_SPACE_MAXADDR_32BIT,
756 NULL, NULL, MEMO_CLUSTER_SIZE, 1,
757 MEMO_CLUSTER_SIZE, 0, &mp->dmat)) {
758 mp->getp = ___dma_getp;
759#ifdef MEMO_FREE_UNUSED
760 mp->freep = ___dma_freep;
761#endif
762 mp->next = mp0.next;
763 mp0.next = mp;
764 return mp;
765 }
766 }
767 if (mp)
768 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL");
769 return 0;
770}
771
772#ifdef MEMO_FREE_UNUSED
773static void ___del_dma_pool(m_pool_s *p)
774{
775 struct m_pool **pp = &mp0.next;
776
777 while (*pp && *pp != p)
778 pp = &(*pp)->next;
779 if (*pp) {
780 *pp = (*pp)->next;
781 bus_dma_tag_destroy(p->dmat);
782 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL");
783 }
784}
785#endif
786
787static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name)
788{
789 struct m_pool *mp;
790 void *m = 0;
791
792 /* Lock */
793 mp = ___get_dma_pool(dev_dmat);
794 if (!mp)
795 mp = ___cre_dma_pool(dev_dmat);
796 if (mp)
797 m = __sym_calloc(mp, size, name);
798#ifdef MEMO_FREE_UNUSED
799 if (mp && !mp->nump)
800 ___del_dma_pool(mp);
801#endif
802 /* Unlock */
803
804 return m;
805}
806
807static void
808__sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name)
809{
810 struct m_pool *mp;
811
812 /* Lock */
813 mp = ___get_dma_pool(dev_dmat);
814 if (mp)
815 __sym_mfree(mp, m, size, name);
816#ifdef MEMO_FREE_UNUSED
817 if (mp && !mp->nump)
818 ___del_dma_pool(mp);
819#endif
820 /* Unlock */
821}
822
823static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m)
824{
825 m_pool_s *mp;
826 int hc = VTOB_HASH_CODE(m);
827 m_vtob_s *vp = 0;
828 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
829
830 /* Lock */
831 mp = ___get_dma_pool(dev_dmat);
832 if (mp) {
833 vp = mp->vtob[hc];
834 while (vp && (m_addr_t) vp->vaddr != a)
835 vp = vp->next;
836 }
837 /* Unlock */
838 if (!vp)
839 panic("sym: VTOBUS FAILED!\n");
840 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
841}
842
843#endif /* FreeBSD_Bus_Dma_Abstraction */
844
845/*
846 * Verbs for DMAable memory handling.
847 * The _uvptv_ macro avoids a nasty warning about pointer to volatile
848 * being discarded.
849 */
850#define _uvptv_(p) ((void *)((vm_offset_t)(p)))
851#define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n)
852#define _sym_mfree_dma(np, p, s, n) \
853 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n)
854#define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n)
855#define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n)
856#define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p))
857#define vtobus(p) _vtobus(np, p)
858
859
860/*
861 * Print a buffer in hexadecimal format.
862 */
863static void sym_printb_hex (u_char *p, int n)
864{
865 while (n-- > 0)
e3869ec7 866 kprintf (" %x", *p++);
984263bc
MD
867}
868
869/*
870 * Same with a label at beginning and .\n at end.
871 */
872static void sym_printl_hex (char *label, u_char *p, int n)
873{
e3869ec7 874 kprintf ("%s", label);
984263bc 875 sym_printb_hex (p, n);
e3869ec7 876 kprintf (".\n");
984263bc
MD
877}
878
879/*
880 * Return a string for SCSI BUS mode.
881 */
882static char *sym_scsi_bus_mode(int mode)
883{
884 switch(mode) {
885 case SMODE_HVD: return "HVD";
886 case SMODE_SE: return "SE";
887 case SMODE_LVD: return "LVD";
888 }
889 return "??";
890}
891
892/*
893 * Some poor and bogus sync table that refers to Tekram NVRAM layout.
894 */
895#ifdef SYM_CONF_NVRAM_SUPPORT
896static u_char Tekram_sync[16] =
897 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10};
898#endif
899
900/*
901 * Union of supported NVRAM formats.
902 */
903struct sym_nvram {
904 int type;
905#define SYM_SYMBIOS_NVRAM (1)
906#define SYM_TEKRAM_NVRAM (2)
907#ifdef SYM_CONF_NVRAM_SUPPORT
908 union {
909 Symbios_nvram Symbios;
910 Tekram_nvram Tekram;
911 } data;
912#endif
913};
914
915/*
916 * This one is hopefully useless, but actually useful. :-)
917 */
918#ifndef assert
919#define assert(expression) { \
920 if (!(expression)) { \
921 (void)panic( \
922 "assertion \"%s\" failed: file \"%s\", line %d\n", \
923 #expression, \
924 __FILE__, __LINE__); \
925 } \
926}
927#endif
928
929/*
930 * Some provision for a possible big endian mode supported by
931 * Symbios chips (never seen, by the way).
932 * For now, this stuff does not deserve any comments. :)
933 */
934
935#define sym_offb(o) (o)
936#define sym_offw(o) (o)
937
938/*
939 * Some provision for support for BIG ENDIAN CPU.
940 * Btw, FreeBSD does not seem to be ready yet for big endian.
941 */
942
943#if BYTE_ORDER == BIG_ENDIAN
944#define cpu_to_scr(dw) _htole32(dw)
945#define scr_to_cpu(dw) _le32toh(dw)
946#else
947#define cpu_to_scr(dw) (dw)
948#define scr_to_cpu(dw) (dw)
949#endif
950
951/*
952 * Access to the chip IO registers and on-chip RAM.
953 * We use the `bus space' interface under FreeBSD-4 and
954 * later kernel versions.
955 */
956
957#ifdef FreeBSD_Bus_Space_Abstraction
958
959#if defined(SYM_CONF_IOMAPPED)
960
961#define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o)
962#define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o)
963#define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o)
964
965#define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v))
966#define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v))
967#define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v))
968
969#else /* Memory mapped IO */
970
971#define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o)
972#define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o)
973#define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o)
974
975#define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v))
976#define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v))
977#define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v))
978
979#endif /* SYM_CONF_IOMAPPED */
980
981#define OUTRAM_OFF(o, a, l) \
982 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l))
983
984#else /* not defined FreeBSD_Bus_Space_Abstraction */
985
986#if BYTE_ORDER == BIG_ENDIAN
987#error "BIG ENDIAN support requires bus space kernel interface"
988#endif
989
990/*
991 * Access to the chip IO registers and on-chip RAM.
992 * We use legacy MMIO and IO interface for FreeBSD 3.X versions.
993 */
994
995/*
996 * Define some understable verbs for IO and MMIO.
997 */
998#define io_read8(p) scr_to_cpu(inb((p)))
999#define io_read16(p) scr_to_cpu(inw((p)))
1000#define io_read32(p) scr_to_cpu(inl((p)))
1001#define io_write8(p, v) outb((p), cpu_to_scr(v))
1002#define io_write16(p, v) outw((p), cpu_to_scr(v))
1003#define io_write32(p, v) outl((p), cpu_to_scr(v))
1004
984263bc
MD
1005#define mmio_read8(a) scr_to_cpu((*(volatile unsigned char *) (a)))
1006#define mmio_read16(a) scr_to_cpu((*(volatile unsigned short *) (a)))
1007#define mmio_read32(a) scr_to_cpu((*(volatile unsigned int *) (a)))
1008#define mmio_write8(a, b) (*(volatile unsigned char *) (a)) = cpu_to_scr(b)
1009#define mmio_write16(a, b) (*(volatile unsigned short *) (a)) = cpu_to_scr(b)
1010#define mmio_write32(a, b) (*(volatile unsigned int *) (a)) = cpu_to_scr(b)
1011#define memcpy_to_pci(d, s, n) bcopy((s), (void *)(d), (n))
1012
984263bc
MD
1013/*
1014 * Normal IO
1015 */
1016#if defined(SYM_CONF_IOMAPPED)
1017
1018#define INB_OFF(o) io_read8(np->io_port + sym_offb(o))
1019#define OUTB_OFF(o, v) io_write8(np->io_port + sym_offb(o), (v))
1020
1021#define INW_OFF(o) io_read16(np->io_port + sym_offw(o))
1022#define OUTW_OFF(o, v) io_write16(np->io_port + sym_offw(o), (v))
1023
1024#define INL_OFF(o) io_read32(np->io_port + (o))
1025#define OUTL_OFF(o, v) io_write32(np->io_port + (o), (v))
1026
1027#else /* Memory mapped IO */
1028
1029#define INB_OFF(o) mmio_read8(np->mmio_va + sym_offb(o))
1030#define OUTB_OFF(o, v) mmio_write8(np->mmio_va + sym_offb(o), (v))
1031
1032#define INW_OFF(o) mmio_read16(np->mmio_va + sym_offw(o))
1033#define OUTW_OFF(o, v) mmio_write16(np->mmio_va + sym_offw(o), (v))
1034
1035#define INL_OFF(o) mmio_read32(np->mmio_va + (o))
1036#define OUTL_OFF(o, v) mmio_write32(np->mmio_va + (o), (v))
1037
1038#endif
1039
1040#define OUTRAM_OFF(o, a, l) memcpy_to_pci(np->ram_va + (o), (a), (l))
1041
1042#endif /* FreeBSD_Bus_Space_Abstraction */
1043
1044/*
1045 * Common definitions for both bus space and legacy IO methods.
1046 */
1047#define INB(r) INB_OFF(offsetof(struct sym_reg,r))
1048#define INW(r) INW_OFF(offsetof(struct sym_reg,r))
1049#define INL(r) INL_OFF(offsetof(struct sym_reg,r))
1050
1051#define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v))
1052#define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v))
1053#define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v))
1054
1055#define OUTONB(r, m) OUTB(r, INB(r) | (m))
1056#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
1057#define OUTONW(r, m) OUTW(r, INW(r) | (m))
1058#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
1059#define OUTONL(r, m) OUTL(r, INL(r) | (m))
1060#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
1061
1062/*
1063 * We normally want the chip to have a consistent view
1064 * of driver internal data structures when we restart it.
1065 * Thus these macros.
1066 */
1067#define OUTL_DSP(v) \
1068 do { \
1069 MEMORY_BARRIER(); \
1070 OUTL (nc_dsp, (v)); \
1071 } while (0)
1072
1073#define OUTONB_STD() \
1074 do { \
1075 MEMORY_BARRIER(); \
1076 OUTONB (nc_dcntl, (STD|NOCOM)); \
1077 } while (0)
1078
1079/*
1080 * Command control block states.
1081 */
1082#define HS_IDLE (0)
1083#define HS_BUSY (1)
1084#define HS_NEGOTIATE (2) /* sync/wide data transfer*/
1085#define HS_DISCONNECT (3) /* Disconnected by target */
1086#define HS_WAIT (4) /* waiting for resource */
1087
1088#define HS_DONEMASK (0x80)
1089#define HS_COMPLETE (4|HS_DONEMASK)
1090#define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
1091#define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */
1092#define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */
1093
1094/*
1095 * Software Interrupt Codes
1096 */
1097#define SIR_BAD_SCSI_STATUS (1)
1098#define SIR_SEL_ATN_NO_MSG_OUT (2)
1099#define SIR_MSG_RECEIVED (3)
1100#define SIR_MSG_WEIRD (4)
1101#define SIR_NEGO_FAILED (5)
1102#define SIR_NEGO_PROTO (6)
1103#define SIR_SCRIPT_STOPPED (7)
1104#define SIR_REJECT_TO_SEND (8)
1105#define SIR_SWIDE_OVERRUN (9)
1106#define SIR_SODL_UNDERRUN (10)
1107#define SIR_RESEL_NO_MSG_IN (11)
1108#define SIR_RESEL_NO_IDENTIFY (12)
1109#define SIR_RESEL_BAD_LUN (13)
1110#define SIR_TARGET_SELECTED (14)
1111#define SIR_RESEL_BAD_I_T_L (15)
1112#define SIR_RESEL_BAD_I_T_L_Q (16)
1113#define SIR_ABORT_SENT (17)
1114#define SIR_RESEL_ABORTED (18)
1115#define SIR_MSG_OUT_DONE (19)
1116#define SIR_COMPLETE_ERROR (20)
1117#define SIR_DATA_OVERRUN (21)
1118#define SIR_BAD_PHASE (22)
1119#define SIR_MAX (22)
1120
1121/*
1122 * Extended error bit codes.
1123 * xerr_status field of struct sym_ccb.
1124 */
1125#define XE_EXTRA_DATA (1) /* unexpected data phase */
1126#define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */
1127#define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */
1128#define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */
1129#define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */
1130
1131/*
1132 * Negotiation status.
1133 * nego_status field of struct sym_ccb.
1134 */
1135#define NS_SYNC (1)
1136#define NS_WIDE (2)
1137#define NS_PPR (3)
1138
1139/*
1140 * A CCB hashed table is used to retrieve CCB address
1141 * from DSA value.
1142 */
1143#define CCB_HASH_SHIFT 8
1144#define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT)
1145#define CCB_HASH_MASK (CCB_HASH_SIZE-1)
1146#define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK)
1147
1148/*
1149 * Device flags.
1150 */
1151#define SYM_DISC_ENABLED (1)
1152#define SYM_TAGS_ENABLED (1<<1)
1153#define SYM_SCAN_BOOT_DISABLED (1<<2)
1154#define SYM_SCAN_LUNS_DISABLED (1<<3)
1155
1156/*
1157 * Host adapter miscellaneous flags.
1158 */
1159#define SYM_AVOID_BUS_RESET (1)
1160#define SYM_SCAN_TARGETS_HILO (1<<1)
1161
1162/*
1163 * Device quirks.
1164 * Some devices, for example the CHEETAH 2 LVD, disconnects without
1165 * saving the DATA POINTER then reselects and terminates the IO.
1166 * On reselection, the automatic RESTORE DATA POINTER makes the
1167 * CURRENT DATA POINTER not point at the end of the IO.
1168 * This behaviour just breaks our calculation of the residual.
1169 * For now, we just force an AUTO SAVE on disconnection and will
1170 * fix that in a further driver version.
1171 */
1172#define SYM_QUIRK_AUTOSAVE 1
1173
1174/*
1175 * Misc.
1176 */
1177#define SYM_SNOOP_TIMEOUT (10000000)
1178#define SYM_PCI_IO PCIR_MAPS
1179#define SYM_PCI_MMIO (PCIR_MAPS + 4)
1180#define SYM_PCI_RAM (PCIR_MAPS + 8)
1181#define SYM_PCI_RAM64 (PCIR_MAPS + 12)
1182
1183/*
1184 * Back-pointer from the CAM CCB to our data structures.
1185 */
1186#define sym_hcb_ptr spriv_ptr0
1187/* #define sym_ccb_ptr spriv_ptr1 */
1188
1189/*
1190 * We mostly have to deal with pointers.
1191 * Thus these typedef's.
1192 */
1193typedef struct sym_tcb *tcb_p;
1194typedef struct sym_lcb *lcb_p;
1195typedef struct sym_ccb *ccb_p;
1196typedef struct sym_hcb *hcb_p;
1197
1198/*
1199 * Gather negotiable parameters value
1200 */
1201struct sym_trans {
984263bc
MD
1202 u8 scsi_version;
1203 u8 spi_version;
984263bc
MD
1204 u8 period;
1205 u8 offset;
1206 u8 width;
1207 u8 options; /* PPR options */
1208};
1209
1210struct sym_tinfo {
1211 struct sym_trans current;
1212 struct sym_trans goal;
1213 struct sym_trans user;
1214};
1215
1216#define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT
1217#define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT
1218
1219/*
1220 * Global TCB HEADER.
1221 *
1222 * Due to lack of indirect addressing on earlier NCR chips,
1223 * this substructure is copied from the TCB to a global
1224 * address after selection.
1225 * For SYMBIOS chips that support LOAD/STORE this copy is
1226 * not needed and thus not performed.
1227 */
1228struct sym_tcbh {
1229 /*
1230 * Scripts bus addresses of LUN table accessed from scripts.
1231 * LUN #0 is a special case, since multi-lun devices are rare,
1232 * and we we want to speed-up the general case and not waste
1233 * resources.
1234 */
1235 u32 luntbl_sa; /* bus address of this table */
1236 u32 lun0_sa; /* bus address of LCB #0 */
1237 /*
1238 * Actual SYNC/WIDE IO registers value for this target.
1239 * 'sval', 'wval' and 'uval' are read from SCRIPTS and
1240 * so have alignment constraints.
1241 */
1242/*0*/ u_char uval; /* -> SCNTL4 register */
1243/*1*/ u_char sval; /* -> SXFER io register */
1244/*2*/ u_char filler1;
1245/*3*/ u_char wval; /* -> SCNTL3 io register */
1246};
1247
1248/*
1249 * Target Control Block
1250 */
1251struct sym_tcb {
1252 /*
1253 * TCB header.
1254 * Assumed at offset 0.
1255 */
1256/*0*/ struct sym_tcbh head;
1257
1258 /*
1259 * LUN table used by the SCRIPTS processor.
1260 * An array of bus addresses is used on reselection.
1261 */
1262 u32 *luntbl; /* LCBs bus address table */
1263
1264 /*
1265 * LUN table used by the C code.
1266 */
1267 lcb_p lun0p; /* LCB of LUN #0 (usual case) */
1268#if SYM_CONF_MAX_LUN > 1
1269 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */
1270#endif
1271
1272 /*
1273 * Bitmap that tells about LUNs that succeeded at least
1274 * 1 IO and therefore assumed to be a real device.
1275 * Avoid useless allocation of the LCB structure.
1276 */
1277 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];
1278
1279 /*
1280 * Bitmap that tells about LUNs that haven't yet an LCB
1281 * allocated (not discovered or LCB allocation failed).
1282 */
1283 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];
1284
1285 /*
1286 * Transfer capabilities (SIP)
1287 */
1288 struct sym_tinfo tinfo;
1289
1290 /*
1291 * Keep track of the CCB used for the negotiation in order
1292 * to ensure that only 1 negotiation is queued at a time.
1293 */
1294 ccb_p nego_cp; /* CCB used for the nego */
1295
1296 /*
1297 * Set when we want to reset the device.
1298 */
1299 u_char to_reset;
1300
1301 /*
1302 * Other user settable limits and options.
1303 * These limits are read from the NVRAM if present.
1304 */
1305 u_char usrflags;
1306 u_short usrtags;
1307};
1308
1309/*
1310 * Global LCB HEADER.
1311 *
1312 * Due to lack of indirect addressing on earlier NCR chips,
1313 * this substructure is copied from the LCB to a global
1314 * address after selection.
1315 * For SYMBIOS chips that support LOAD/STORE this copy is
1316 * not needed and thus not performed.
1317 */
1318struct sym_lcbh {
1319 /*
1320 * SCRIPTS address jumped by SCRIPTS on reselection.
1321 * For not probed logical units, this address points to
1322 * SCRIPTS that deal with bad LU handling (must be at
1323 * offset zero of the LCB for that reason).
1324 */
1325/*0*/ u32 resel_sa;
1326
1327 /*
1328 * Task (bus address of a CCB) read from SCRIPTS that points
1329 * to the unique ITL nexus allowed to be disconnected.
1330 */
1331 u32 itl_task_sa;
1332
1333 /*
1334 * Task table bus address (read from SCRIPTS).
1335 */
1336 u32 itlq_tbl_sa;
1337};
1338
1339/*
1340 * Logical Unit Control Block
1341 */
1342struct sym_lcb {
1343 /*
1344 * TCB header.
1345 * Assumed at offset 0.
1346 */
1347/*0*/ struct sym_lcbh head;
1348
1349 /*
1350 * Task table read from SCRIPTS that contains pointers to
1351 * ITLQ nexuses. The bus address read from SCRIPTS is
1352 * inside the header.
1353 */
1354 u32 *itlq_tbl; /* Kernel virtual address */
1355
1356 /*
1357 * Busy CCBs management.
1358 */
1359 u_short busy_itlq; /* Number of busy tagged CCBs */
1360 u_short busy_itl; /* Number of busy untagged CCBs */
1361
1362 /*
1363 * Circular tag allocation buffer.
1364 */
1365 u_short ia_tag; /* Tag allocation index */
1366 u_short if_tag; /* Tag release index */
1367 u_char *cb_tags; /* Circular tags buffer */
1368
1369 /*
1370 * Set when we want to clear all tasks.
1371 */
1372 u_char to_clear;
1373
1374 /*
1375 * Capabilities.
1376 */
1377 u_char user_flags;
1378 u_char current_flags;
1379};
1380
1381/*
1382 * Action from SCRIPTS on a task.
1383 * Is part of the CCB, but is also used separately to plug
1384 * error handling action to perform from SCRIPTS.
1385 */
1386struct sym_actscr {
1387 u32 start; /* Jumped by SCRIPTS after selection */
1388 u32 restart; /* Jumped by SCRIPTS on relection */
1389};
1390
1391/*
1392 * Phase mismatch context.
1393 *
1394 * It is part of the CCB and is used as parameters for the
1395 * DATA pointer. We need two contexts to handle correctly the
1396 * SAVED DATA POINTER.
1397 */
1398struct sym_pmc {
1399 struct sym_tblmove sg; /* Updated interrupted SG block */
1400 u32 ret; /* SCRIPT return address */
1401};
1402
1403/*
1404 * LUN control block lookup.
1405 * We use a direct pointer for LUN #0, and a table of
1406 * pointers which is only allocated for devices that support
1407 * LUN(s) > 0.
1408 */
1409#if SYM_CONF_MAX_LUN <= 1
1410#define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0
1411#else
1412#define sym_lp(np, tp, lun) \
1413 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0
1414#endif
1415
1416/*
1417 * Status are used by the host and the script processor.
1418 *
1419 * The last four bytes (status[4]) are copied to the
1420 * scratchb register (declared as scr0..scr3) just after the
1421 * select/reselect, and copied back just after disconnecting.
1422 * Inside the script the XX_REG are used.
1423 */
1424
1425/*
1426 * Last four bytes (script)
1427 */
1428#define QU_REG scr0
1429#define HS_REG scr1
1430#define HS_PRT nc_scr1
1431#define SS_REG scr2
1432#define SS_PRT nc_scr2
1433#define HF_REG scr3
1434#define HF_PRT nc_scr3
1435
1436/*
1437 * Last four bytes (host)
1438 */
1439#define actualquirks phys.head.status[0]
1440#define host_status phys.head.status[1]
1441#define ssss_status phys.head.status[2]
1442#define host_flags phys.head.status[3]
1443
1444/*
1445 * Host flags
1446 */
1447#define HF_IN_PM0 1u
1448#define HF_IN_PM1 (1u<<1)
1449#define HF_ACT_PM (1u<<2)
1450#define HF_DP_SAVED (1u<<3)
1451#define HF_SENSE (1u<<4)
1452#define HF_EXT_ERR (1u<<5)
1453#define HF_DATA_IN (1u<<6)
1454#ifdef SYM_CONF_IARB_SUPPORT
1455#define HF_HINT_IARB (1u<<7)
1456#endif
1457
1458/*
1459 * Global CCB HEADER.
1460 *
1461 * Due to lack of indirect addressing on earlier NCR chips,
1462 * this substructure is copied from the ccb to a global
1463 * address after selection (or reselection) and copied back
1464 * before disconnect.
1465 * For SYMBIOS chips that support LOAD/STORE this copy is
1466 * not needed and thus not performed.
1467 */
1468
1469struct sym_ccbh {
1470 /*
1471 * Start and restart SCRIPTS addresses (must be at 0).
1472 */
1473/*0*/ struct sym_actscr go;
1474
1475 /*
1476 * SCRIPTS jump address that deal with data pointers.
1477 * 'savep' points to the position in the script responsible
1478 * for the actual transfer of data.
1479 * It's written on reception of a SAVE_DATA_POINTER message.
1480 */
1481 u32 savep; /* Jump address to saved data pointer */
1482 u32 lastp; /* SCRIPTS address at end of data */
1483 u32 goalp; /* Not accessed for now from SCRIPTS */
1484
1485 /*
1486 * Status fields.
1487 */
1488 u8 status[4];
1489};
1490
1491/*
1492 * Data Structure Block
1493 *
1494 * During execution of a ccb by the script processor, the
1495 * DSA (data structure address) register points to this
1496 * substructure of the ccb.
1497 */
1498struct sym_dsb {
1499 /*
1500 * CCB header.
1501 * Also assumed at offset 0 of the sym_ccb structure.
1502 */
1503/*0*/ struct sym_ccbh head;
1504
1505 /*
1506 * Phase mismatch contexts.
1507 * We need two to handle correctly the SAVED DATA POINTER.
1508 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic
1509 * for address calculation from SCRIPTS.
1510 */
1511 struct sym_pmc pm0;
1512 struct sym_pmc pm1;
1513
1514 /*
1515 * Table data for Script
1516 */
1517 struct sym_tblsel select;
1518 struct sym_tblmove smsg;
1519 struct sym_tblmove smsg_ext;
1520 struct sym_tblmove cmd;
1521 struct sym_tblmove sense;
1522 struct sym_tblmove wresid;
1523 struct sym_tblmove data [SYM_CONF_MAX_SG];
1524};
1525
1526/*
1527 * Our Command Control Block
1528 */
1529struct sym_ccb {
1530 /*
1531 * This is the data structure which is pointed by the DSA
1532 * register when it is executed by the script processor.
1533 * It must be the first entry.
1534 */
1535 struct sym_dsb phys;
1536
1537 /*
1538 * Pointer to CAM ccb and related stuff.
1539 */
1540 union ccb *cam_ccb; /* CAM scsiio ccb */
1541 u8 cdb_buf[16]; /* Copy of CDB */
1542 u8 *sns_bbuf; /* Bounce buffer for sense data */
1543#define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data)
1544 int data_len; /* Total data length */
1545 int segments; /* Number of SG segments */
1546
1547 /*
1548 * Miscellaneous status'.
1549 */
1550 u_char nego_status; /* Negotiation status */
1551 u_char xerr_status; /* Extended error flags */
1552 u32 extra_bytes; /* Extraneous bytes transferred */
1553
1554 /*
1555 * Message areas.
1556 * We prepare a message to be sent after selection.
1557 * We may use a second one if the command is rescheduled
1558 * due to CHECK_CONDITION or COMMAND TERMINATED.
1559 * Contents are IDENTIFY and SIMPLE_TAG.
1560 * While negotiating sync or wide transfer,
1561 * a SDTR or WDTR message is appended.
1562 */
1563 u_char scsi_smsg [12];
1564 u_char scsi_smsg2[12];
1565
1566 /*
1567 * Auto request sense related fields.
1568 */
1569 u_char sensecmd[6]; /* Request Sense command */
1570 u_char sv_scsi_status; /* Saved SCSI status */
1571 u_char sv_xerr_status; /* Saved extended status */
1572 int sv_resid; /* Saved residual */
1573
1574 /*
1575 * Map for the DMA of user data.
1576 */
1577#ifdef FreeBSD_Bus_Dma_Abstraction
1578 void *arg; /* Argument for some callback */
1579 bus_dmamap_t dmamap; /* DMA map for user data */
1580 u_char dmamapped;
1581#define SYM_DMA_NONE 0
1582#define SYM_DMA_READ 1
1583#define SYM_DMA_WRITE 2
1584#endif
1585 /*
1586 * Other fields.
1587 */
1588 u32 ccb_ba; /* BUS address of this CCB */
1589 u_short tag; /* Tag for this transfer */
1590 /* NO_TAG means no tag */
1591 u_char target;
1592 u_char lun;
1593 ccb_p link_ccbh; /* Host adapter CCB hash chain */
1594 SYM_QUEHEAD
1595 link_ccbq; /* Link to free/busy CCB queue */
1596 u32 startp; /* Initial data pointer */
1597 int ext_sg; /* Extreme data pointer, used */
1598 int ext_ofs; /* to calculate the residual. */
1599 u_char to_abort; /* Want this IO to be aborted */
1600};
1601
1602#define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl))
1603
1604/*
1605 * Host Control Block
1606 */
1607struct sym_hcb {
1608 /*
1609 * Global headers.
1610 * Due to poorness of addressing capabilities, earlier
1611 * chips (810, 815, 825) copy part of the data structures
1612 * (CCB, TCB and LCB) in fixed areas.
1613 */
1614#ifdef SYM_CONF_GENERIC_SUPPORT
1615 struct sym_ccbh ccb_head;
1616 struct sym_tcbh tcb_head;
1617 struct sym_lcbh lcb_head;
1618#endif
1619 /*
1620 * Idle task and invalid task actions and
1621 * their bus addresses.
1622 */
1623 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1624 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1625
1626 /*
1627 * Dummy lun table to protect us against target
1628 * returning bad lun number on reselection.
1629 */
1630 u32 *badluntbl; /* Table physical address */
1631 u32 badlun_sa; /* SCRIPT handler BUS address */
1632
1633 /*
1634 * Bus address of this host control block.
1635 */
1636 u32 hcb_ba;
1637
1638 /*
1639 * Bit 32-63 of the on-chip RAM bus address in LE format.
1640 * The START_RAM64 script loads the MMRS and MMWS from this
1641 * field.
1642 */
1643 u32 scr_ram_seg;
1644
1645 /*
1646 * Chip and controller indentification.
1647 */
1648#ifdef FreeBSD_Bus_Io_Abstraction
1649 device_t device;
1650#else
1651 pcici_t pci_tag;
1652#endif
1653 int unit;
1654 char inst_name[8];
1655
1656 /*
1657 * Initial value of some IO register bits.
1658 * These values are assumed to have been set by BIOS, and may
1659 * be used to probe adapter implementation differences.
1660 */
1661 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1662 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1663 sv_stest1;
1664
1665 /*
1666 * Actual initial value of IO register bits used by the
1667 * driver. They are loaded at initialisation according to
1668 * features that are to be enabled/disabled.
1669 */
1670 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1671 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1672
1673 /*
1674 * Target data.
1675 */
1676 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1677
1678 /*
1679 * Target control block bus address array used by the SCRIPT
1680 * on reselection.
1681 */
1682 u32 *targtbl;
1683 u32 targtbl_ba;
1684
1685 /*
1686 * CAM SIM information for this instance.
1687 */
1688 struct cam_sim *sim;
1689 struct cam_path *path;
1690
1691 /*
1692 * Allocated hardware resources.
1693 */
1694#ifdef FreeBSD_Bus_Io_Abstraction
1695 struct resource *irq_res;
1696 struct resource *io_res;
1697 struct resource *mmio_res;
1698 struct resource *ram_res;
1699 int ram_id;
1700 void *intr;
1701#endif
1702
1703 /*
1704 * Bus stuff.
1705 *
1706 * My understanding of PCI is that all agents must share the
1707 * same addressing range and model.
1708 * But some hardware architecture guys provide complex and
1709 * brain-deaded stuff that makes shit.
1710 * This driver only support PCI compliant implementations and
1711 * deals with part of the BUS stuff complexity only to fit O/S
1712 * requirements.
1713 */
1714#ifdef FreeBSD_Bus_Io_Abstraction
1715 bus_space_handle_t io_bsh;
1716 bus_space_tag_t io_tag;
1717 bus_space_handle_t mmio_bsh;
1718 bus_space_tag_t mmio_tag;
1719 bus_space_handle_t ram_bsh;
1720 bus_space_tag_t ram_tag;
1721#endif
1722
1723 /*
1724 * DMA stuff.
1725 */
1726#ifdef FreeBSD_Bus_Dma_Abstraction
1727 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1728 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1729#endif
1730 /*
1731 * Virtual and physical bus addresses of the chip.
1732 */
1733 vm_offset_t mmio_va; /* MMIO kernel virtual address */
1734 vm_offset_t mmio_pa; /* MMIO CPU physical address */
1735 vm_offset_t mmio_ba; /* MMIO BUS address */
1736 int mmio_ws; /* MMIO Window size */
1737
1738 vm_offset_t ram_va; /* RAM kernel virtual address */
1739 vm_offset_t ram_pa; /* RAM CPU physical address */
1740 vm_offset_t ram_ba; /* RAM BUS address */
1741 int ram_ws; /* RAM window size */
1742 u32 io_port; /* IO port address */
1743
1744 /*
1745 * SCRIPTS virtual and physical bus addresses.
1746 * 'script' is loaded in the on-chip RAM if present.
1747 * 'scripth' stays in main memory for all chips except the
1748 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM.
1749 */
1750 u_char *scripta0; /* Copies of script and scripth */
1751 u_char *scriptb0; /* Copies of script and scripth */
1752 vm_offset_t scripta_ba; /* Actual script and scripth */
1753 vm_offset_t scriptb_ba; /* bus addresses. */
1754 vm_offset_t scriptb0_ba;
1755 u_short scripta_sz; /* Actual size of script A */
1756 u_short scriptb_sz; /* Actual size of script B */
1757
1758 /*
1759 * Bus addresses, setup and patch methods for
1760 * the selected firmware.
1761 */
1762 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1763 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1764 void (*fw_setup)(hcb_p np, struct sym_fw *fw);
1765 void (*fw_patch)(hcb_p np);
1766 char *fw_name;
1767
1768 /*
1769 * General controller parameters and configuration.
1770 */
1771 u_short device_id; /* PCI device id */
1772 u_char revision_id; /* PCI device revision id */
1773 u_int features; /* Chip features map */
1774 u_char myaddr; /* SCSI id of the adapter */
1775 u_char maxburst; /* log base 2 of dwords burst */
1776 u_char maxwide; /* Maximum transfer width */
1777 u_char minsync; /* Min sync period factor (ST) */
1778 u_char maxsync; /* Max sync period factor (ST) */
1779 u_char maxoffs; /* Max scsi offset (ST) */
1780 u_char minsync_dt; /* Min sync period factor (DT) */
1781 u_char maxsync_dt; /* Max sync period factor (DT) */
1782 u_char maxoffs_dt; /* Max scsi offset (DT) */
1783 u_char multiplier; /* Clock multiplier (1,2,4) */
1784 u_char clock_divn; /* Number of clock divisors */
1785 u32 clock_khz; /* SCSI clock frequency in KHz */
1786 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1787 /*
1788 * Start queue management.
1789 * It is filled up by the host processor and accessed by the
1790 * SCRIPTS processor in order to start SCSI commands.
1791 */
1792 volatile /* Prevent code optimizations */
1793 u32 *squeue; /* Start queue virtual address */
1794 u32 squeue_ba; /* Start queue BUS address */
1795 u_short squeueput; /* Next free slot of the queue */
1796 u_short actccbs; /* Number of allocated CCBs */
1797
1798 /*
1799 * Command completion queue.
1800 * It is the same size as the start queue to avoid overflow.
1801 */
1802 u_short dqueueget; /* Next position to scan */
1803 volatile /* Prevent code optimizations */
1804 u32 *dqueue; /* Completion (done) queue */
1805 u32 dqueue_ba; /* Done queue BUS address */
1806
1807 /*
1808 * Miscellaneous buffers accessed by the scripts-processor.
1809 * They shall be DWORD aligned, because they may be read or
1810 * written with a script command.
1811 */
1812 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1813 u_char msgin [8]; /* Buffer for MESSAGE IN */
1814 u32 lastmsg; /* Last SCSI message sent */
1815 u_char scratch; /* Scratch for SCSI receive */
1816
1817 /*
1818 * Miscellaneous configuration and status parameters.
1819 */
1820 u_char usrflags; /* Miscellaneous user flags */
1821 u_char scsi_mode; /* Current SCSI BUS mode */
1822 u_char verbose; /* Verbosity for this controller*/
1823 u32 cache; /* Used for cache test at init. */
1824
1825 /*
1826 * CCB lists and queue.
1827 */
1828 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1829 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1830 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1831
1832 /*
1833 * During error handling and/or recovery,
1834 * active CCBs that are to be completed with
1835 * error or requeued are moved from the busy_ccbq
1836 * to the comp_ccbq prior to completion.
1837 */
1838 SYM_QUEHEAD comp_ccbq;
1839
1840 /*
1841 * CAM CCB pending queue.
1842 */
1843 SYM_QUEHEAD cam_ccbq;
1844
1845 /*
1846 * IMMEDIATE ARBITRATION (IARB) control.
1847 *
1848 * We keep track in 'last_cp' of the last CCB that has been
1849 * queued to the SCRIPTS processor and clear 'last_cp' when
1850 * this CCB completes. If last_cp is not zero at the moment
1851 * we queue a new CCB, we set a flag in 'last_cp' that is
1852 * used by the SCRIPTS as a hint for setting IARB.
1853 * We donnot set more than 'iarb_max' consecutive hints for
1854 * IARB in order to leave devices a chance to reselect.
1855 * By the way, any non zero value of 'iarb_max' is unfair. :)
1856 */
1857#ifdef SYM_CONF_IARB_SUPPORT
1858 u_short iarb_max; /* Max. # consecutive IARB hints*/
1859 u_short iarb_count; /* Actual # of these hints */
1860 ccb_p last_cp;
1861#endif
1862
1863 /*
1864 * Command abort handling.
1865 * We need to synchronize tightly with the SCRIPTS
1866 * processor in order to handle things correctly.
1867 */
1868 u_char abrt_msg[4]; /* Message to send buffer */
1869 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */
1870 struct sym_tblsel abrt_sel; /* Sync params for selection */
1871 u_char istat_sem; /* Tells the chip to stop (SEM) */
1872};
1873
1874#define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl))
1875
1876/*
1877 * Return the name of the controller.
1878 */
1879static __inline char *sym_name(hcb_p np)
1880{
1881 return np->inst_name;
1882}
1883
1884/*--------------------------------------------------------------------------*/
1885/*------------------------------ FIRMWARES ---------------------------------*/
1886/*--------------------------------------------------------------------------*/
1887
1888/*
1889 * This stuff will be moved to a separate source file when
1890 * the driver will be broken into several source modules.
1891 */
1892
1893/*
1894 * Macros used for all firmwares.
1895 */
1896#define SYM_GEN_A(s, label) ((short) offsetof(s, label)),
1897#define SYM_GEN_B(s, label) ((short) offsetof(s, label)),
1898#define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label)
1899#define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label)
1900
1901
1902#ifdef SYM_CONF_GENERIC_SUPPORT
1903/*
1904 * Allocate firmware #1 script area.
1905 */
1906#define SYM_FWA_SCR sym_fw1a_scr
1907#define SYM_FWB_SCR sym_fw1b_scr
1f2de5d4 1908#include "sym_fw1.h"
984263bc
MD
1909struct sym_fwa_ofs sym_fw1a_ofs = {
1910 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1911};
1912struct sym_fwb_ofs sym_fw1b_ofs = {
1913 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1914};
1915#undef SYM_FWA_SCR
1916#undef SYM_FWB_SCR
1917#endif /* SYM_CONF_GENERIC_SUPPORT */
1918
1919/*
1920 * Allocate firmware #2 script area.
1921 */
1922#define SYM_FWA_SCR sym_fw2a_scr
1923#define SYM_FWB_SCR sym_fw2b_scr
1f2de5d4 1924#include "sym_fw2.h"
984263bc
MD
1925struct sym_fwa_ofs sym_fw2a_ofs = {
1926 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1927};
1928struct sym_fwb_ofs sym_fw2b_ofs = {
1929 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1930 SYM_GEN_B(struct SYM_FWB_SCR, start64)
1931 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle)
1932};
1933#undef SYM_FWA_SCR
1934#undef SYM_FWB_SCR
1935
1936#undef SYM_GEN_A
1937#undef SYM_GEN_B
1938#undef PADDR_A
1939#undef PADDR_B
1940
1941#ifdef SYM_CONF_GENERIC_SUPPORT
1942/*
1943 * Patch routine for firmware #1.
1944 */
1945static void
1946sym_fw1_patch(hcb_p np)
1947{
1948 struct sym_fw1a_scr *scripta0;
1949 struct sym_fw1b_scr *scriptb0;
1950
1951 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1952 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1953
1954 /*
1955 * Remove LED support if not needed.
1956 */
1957 if (!(np->features & FE_LED0)) {
1958 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1959 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1960 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1961 }
1962
1963#ifdef SYM_CONF_IARB_SUPPORT
1964 /*
1965 * If user does not want to use IMMEDIATE ARBITRATION
1966 * when we are reselected while attempting to arbitrate,
1967 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1968 */
1969 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1970 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1971#endif
1972 /*
1973 * Patch some data in SCRIPTS.
1974 * - start and done queue initial bus address.
1975 * - target bus address table bus address.
1976 */
1977 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
1978 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
1979 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
1980}
1981#endif /* SYM_CONF_GENERIC_SUPPORT */
1982
1983/*
1984 * Patch routine for firmware #2.
1985 */
1986static void
1987sym_fw2_patch(hcb_p np)
1988{
1989 struct sym_fw2a_scr *scripta0;
1990 struct sym_fw2b_scr *scriptb0;
1991
1992 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
1993 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
1994
1995 /*
1996 * Remove LED support if not needed.
1997 */
1998 if (!(np->features & FE_LED0)) {
1999 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
2000 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
2001 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
2002 }
2003
2004#ifdef SYM_CONF_IARB_SUPPORT
2005 /*
2006 * If user does not want to use IMMEDIATE ARBITRATION
2007 * when we are reselected while attempting to arbitrate,
2008 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
2009 */
2010 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
2011 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
2012#endif
2013 /*
2014 * Patch some variable in SCRIPTS.
2015 * - start and done queue initial bus address.
2016 * - target bus address table bus address.
2017 */
2018 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
2019 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
2020 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
2021
2022 /*
2023 * Remove the load of SCNTL4 on reselection if not a C10.
2024 */
2025 if (!(np->features & FE_C10)) {
2026 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP);
2027 scripta0->resel_scntl4[1] = cpu_to_scr(0);
2028 }
2029
2030 /*
2031 * Remove a couple of work-arounds specific to C1010 if
2032 * they are not desirable. See `sym_fw2.h' for more details.
2033 */
2034 if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
2035 np->revision_id < 0x1 &&
2036 np->pciclk_khz < 60000)) {
2037 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
2038 scripta0->datao_phase[1] = cpu_to_scr(0);
2039 }
2040 if (!(np->device_id == PCI_ID_LSI53C1010 &&
2041 /* np->revision_id < 0xff */ 1)) {
2042 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
2043 scripta0->sel_done[1] = cpu_to_scr(0);
2044 }
2045
2046 /*
2047 * Patch some other variables in SCRIPTS.
2048 * These ones are loaded by the SCRIPTS processor.
2049 */
2050 scriptb0->pm0_data_addr[0] =
2051 cpu_to_scr(np->scripta_ba +
2052 offsetof(struct sym_fw2a_scr, pm0_data));
2053 scriptb0->pm1_data_addr[0] =
2054 cpu_to_scr(np->scripta_ba +
2055 offsetof(struct sym_fw2a_scr, pm1_data));
2056}
2057
2058/*
2059 * Fill the data area in scripts.
2060 * To be done for all firmwares.
2061 */
2062static void
2063sym_fw_fill_data (u32 *in, u32 *out)
2064{
2065 int i;
2066
2067 for (i = 0; i < SYM_CONF_MAX_SG; i++) {
2068 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN;
2069 *in++ = offsetof (struct sym_dsb, data[i]);
2070 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT;
2071 *out++ = offsetof (struct sym_dsb, data[i]);
2072 }
2073}
2074
2075/*
2076 * Setup useful script bus addresses.
2077 * To be done for all firmwares.
2078 */
2079static void
2080sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw)
2081{
2082 u32 *pa;
2083 u_short *po;
2084 int i;
2085
2086 /*
2087 * Build the bus address table for script A
2088 * from the script A offset table.
2089 */
2090 po = (u_short *) fw->a_ofs;
2091 pa = (u32 *) &np->fwa_bas;
2092 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)
2093 pa[i] = np->scripta_ba + po[i];
2094
2095 /*
2096 * Same for script B.
2097 */
2098 po = (u_short *) fw->b_ofs;
2099 pa = (u32 *) &np->fwb_bas;
2100 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)
2101 pa[i] = np->scriptb_ba + po[i];
2102}
2103
2104#ifdef SYM_CONF_GENERIC_SUPPORT
2105/*
2106 * Setup routine for firmware #1.
2107 */
2108static void
2109sym_fw1_setup(hcb_p np, struct sym_fw *fw)
2110{
2111 struct sym_fw1a_scr *scripta0;
2112 struct sym_fw1b_scr *scriptb0;
2113
2114 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
2115 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
2116
2117 /*
2118 * Fill variable parts in scripts.
2119 */
2120 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2121
2122 /*
2123 * Setup bus addresses used from the C code..
2124 */
2125 sym_fw_setup_bus_addresses(np, fw);
2126}
2127#endif /* SYM_CONF_GENERIC_SUPPORT */
2128
2129/*
2130 * Setup routine for firmware #2.
2131 */
2132static void
2133sym_fw2_setup(hcb_p np, struct sym_fw *fw)
2134{
2135 struct sym_fw2a_scr *scripta0;
2136 struct sym_fw2b_scr *scriptb0;
2137
2138 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
2139 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
2140
2141 /*
2142 * Fill variable parts in scripts.
2143 */
2144 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2145
2146 /*
2147 * Setup bus addresses used from the C code..
2148 */
2149 sym_fw_setup_bus_addresses(np, fw);
2150}
2151
2152/*
2153 * Allocate firmware descriptors.
2154 */
2155#ifdef SYM_CONF_GENERIC_SUPPORT
2156static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic");
2157#endif /* SYM_CONF_GENERIC_SUPPORT */
2158static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based");
2159
2160/*
2161 * Find the most appropriate firmware for a chip.
2162 */
2163static struct sym_fw *
2164sym_find_firmware(struct sym_pci_chip *chip)
2165{
2166 if (chip->features & FE_LDSTR)
2167 return &sym_fw2;
2168#ifdef SYM_CONF_GENERIC_SUPPORT
2169 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
2170 return &sym_fw1;
2171#endif
2172 else
2173 return 0;
2174}
2175
2176/*
2177 * Bind a script to physical addresses.
2178 */
2179static void sym_fw_bind_script (hcb_p np, u32 *start, int len)
2180{
2181 u32 opcode, new, old, tmp1, tmp2;
2182 u32 *end, *cur;
2183 int relocs;
2184
2185 cur = start;
2186 end = start + len/4;
2187
2188 while (cur < end) {
2189
2190 opcode = *cur;
2191
2192 /*
2193 * If we forget to change the length
2194 * in scripts, a field will be
2195 * padded with 0. This is an illegal
2196 * command.
2197 */
2198 if (opcode == 0) {
e3869ec7 2199 kprintf ("%s: ERROR0 IN SCRIPT at %d.\n",
984263bc
MD
2200 sym_name(np), (int) (cur-start));
2201 MDELAY (10000);
2202 ++cur;
2203 continue;
2204 };
2205
2206 /*
2207 * We use the bogus value 0xf00ff00f ;-)
2208 * to reserve data area in SCRIPTS.
2209 */
2210 if (opcode == SCR_DATA_ZERO) {
2211 *cur++ = 0;
2212 continue;
2213 }
2214
2215 if (DEBUG_FLAGS & DEBUG_SCRIPT)
e3869ec7 2216 kprintf ("%d: <%x>\n", (int) (cur-start),
984263bc
MD
2217 (unsigned)opcode);
2218
2219 /*
2220 * We don't have to decode ALL commands
2221 */
2222 switch (opcode >> 28) {
2223 case 0xf:
2224 /*
2225 * LOAD / STORE DSA relative, don't relocate.
2226 */
2227 relocs = 0;
2228 break;
2229 case 0xe:
2230 /*
2231 * LOAD / STORE absolute.
2232 */
2233 relocs = 1;
2234 break;
2235 case 0xc:
2236 /*
2237 * COPY has TWO arguments.
2238 */
2239 relocs = 2;
2240 tmp1 = cur[1];
2241 tmp2 = cur[2];
2242 if ((tmp1 ^ tmp2) & 3) {
e3869ec7 2243 kprintf ("%s: ERROR1 IN SCRIPT at %d.\n",
984263bc
MD
2244 sym_name(np), (int) (cur-start));
2245 MDELAY (10000);
2246 }
2247 /*
2248 * If PREFETCH feature not enabled, remove
2249 * the NO FLUSH bit if present.
2250 */
2251 if ((opcode & SCR_NO_FLUSH) &&
2252 !(np->features & FE_PFEN)) {
2253 opcode = (opcode & ~SCR_NO_FLUSH);
2254 }
2255 break;
2256 case 0x0:
2257 /*
2258 * MOVE/CHMOV (absolute address)
2259 */
2260 if (!(np->features & FE_WIDE))
2261 opcode = (opcode | OPC_MOVE);
2262 relocs = 1;
2263 break;
2264 case 0x1:
2265 /*
2266 * MOVE/CHMOV (table indirect)
2267 */
2268 if (!(np->features & FE_WIDE))
2269 opcode = (opcode | OPC_MOVE);
2270 relocs = 0;
2271 break;
2272 case 0x8:
2273 /*
2274 * JUMP / CALL
2275 * dont't relocate if relative :-)
2276 */
2277 if (opcode & 0x00800000)
2278 relocs = 0;
2279 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/
2280 relocs = 2;
2281 else
2282 relocs = 1;
2283 break;
2284 case 0x4:
2285 case 0x5:
2286 case 0x6:
2287 case 0x7:
2288 relocs = 1;
2289 break;
2290 default:
2291 relocs = 0;
2292 break;
2293 };
2294
2295 /*
2296 * Scriptify:) the opcode.
2297 */
2298 *cur++ = cpu_to_scr(opcode);
2299
2300 /*
2301 * If no relocation, assume 1 argument
2302 * and just scriptize:) it.
2303 */
2304 if (!relocs) {
2305 *cur = cpu_to_scr(*cur);
2306 ++cur;
2307 continue;
2308 }
2309
2310 /*
2311 * Otherwise performs all needed relocations.
2312 */
2313 while (relocs--) {
2314 old = *cur;
2315
2316 switch (old & RELOC_MASK) {
2317 case RELOC_REGISTER:
2318 new = (old & ~RELOC_MASK) + np->mmio_ba;
2319 break;
2320 case RELOC_LABEL_A:
2321 new = (old & ~RELOC_MASK) + np->scripta_ba;
2322 break;
2323 case RELOC_LABEL_B:
2324 new = (old & ~RELOC_MASK) + np->scriptb_ba;
2325 break;
2326 case RELOC_SOFTC:
2327 new = (old & ~RELOC_MASK) + np->hcb_ba;
2328 break;
2329 case 0:
2330 /*
2331 * Don't relocate a 0 address.
2332 * They are mostly used for patched or
2333 * script self-modified areas.
2334 */
2335 if (old == 0) {
2336 new = old;
2337 break;
2338 }
2339 /* fall through */
2340 default:
2341 new = 0;
2342 panic("sym_fw_bind_script: "
2343 "weird relocation %x\n", old);
2344 break;
2345 }
2346
2347 *cur++ = cpu_to_scr(new);
2348 }
2349 };
2350}
2351
2352/*--------------------------------------------------------------------------*/
5322b646 2353/*--------------------------- END OF FIRMWARES ----------------------------*/
984263bc
MD
2354/*--------------------------------------------------------------------------*/
2355
2356/*
2357 * Function prototypes.
2358 */
2359static void sym_save_initial_setting (hcb_p np);
2360static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram);
2361static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr);
2362static void sym_put_start_queue (hcb_p np, ccb_p cp);
2363static void sym_chip_reset (hcb_p np);
2364static void sym_soft_reset (hcb_p np);
2365static void sym_start_reset (hcb_p np);
2366static int sym_reset_scsi_bus (hcb_p np, int enab_int);
2367static int sym_wakeup_done (hcb_p np);
2368static void sym_flush_busy_queue (hcb_p np, int cam_status);
2369static void sym_flush_comp_queue (hcb_p np, int cam_status);
2370static void sym_init (hcb_p np, int reason);
2371static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp,
2372 u_char *fakp);
2373static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per,
2374 u_char div, u_char fak);
2375static void sym_setwide (hcb_p np, ccb_p cp, u_char wide);
2376static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2377 u_char per, u_char wide, u_char div, u_char fak);
2378static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2379 u_char per, u_char wide, u_char div, u_char fak);
2380static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat);
2381static void sym_intr (void *arg);
2382static void sym_poll (struct cam_sim *sim);
2383static void sym_recover_scsi_int (hcb_p np, u_char hsts);
2384static void sym_int_sto (hcb_p np);
2385static void sym_int_udc (hcb_p np);
2386static void sym_int_sbmc (hcb_p np);
2387static void sym_int_par (hcb_p np, u_short sist);
2388static void sym_int_ma (hcb_p np);
2389static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun,
2390 int task);
2391static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp);
2392static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task);
2393static void sym_sir_task_recovery (hcb_p np, int num);
2394static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);
2395static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs);
2396static int sym_compute_residual (hcb_p np, ccb_p cp);
2397static int sym_show_msg (u_char * msg);
2398static void sym_print_msg (ccb_p cp, char *label, u_char *msg);
2399static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp);
2400static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp);
2401static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp);
2402static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp);
2403static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp);
2404static void sym_int_sir (hcb_p np);
2405static void sym_free_ccb (hcb_p np, ccb_p cp);
2406static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
2407static ccb_p sym_alloc_ccb (hcb_p np);
2408static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
2409static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
2410static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
2411static int sym_snooptest (hcb_p np);
2412static void sym_selectclock(hcb_p np, u_char scntl3);
2413static void sym_getclock (hcb_p np, int mult);
2414static int sym_getpciclock (hcb_p np);
2415static void sym_complete_ok (hcb_p np, ccb_p cp);
2416static void sym_complete_error (hcb_p np, ccb_p cp);
2417static void sym_timeout (void *arg);
2418static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out);
2419static void sym_reset_dev (hcb_p np, union ccb *ccb);
2420static void sym_action (struct cam_sim *sim, union ccb *ccb);
2421static void sym_action1 (struct cam_sim *sim, union ccb *ccb);
2422static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp);
2423static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio,
2424 ccb_p cp);
2425#ifdef FreeBSD_Bus_Dma_Abstraction
2426static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
2427 bus_dma_segment_t *psegs, int nsegs);
2428#else
2429static int sym_scatter_virtual (hcb_p np, ccb_p cp, vm_offset_t vaddr,
2430 vm_size_t len);
2431static int sym_scatter_sg_virtual (hcb_p np, ccb_p cp,
2432 bus_dma_segment_t *psegs, int nsegs);
2433static int sym_scatter_physical (hcb_p np, ccb_p cp, vm_offset_t paddr,
2434 vm_size_t len);
2435#endif
2436static int sym_scatter_sg_physical (hcb_p np, ccb_p cp,
2437 bus_dma_segment_t *psegs, int nsegs);
2438static void sym_action2 (struct cam_sim *sim, union ccb *ccb);
2439static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip,
2440 struct ccb_trans_settings *cts);
2441static void sym_update_dflags(hcb_p np, u_char *flags,
2442 struct ccb_trans_settings *cts);
2443
2444#ifdef FreeBSD_Bus_Io_Abstraction
2445static struct sym_pci_chip *sym_find_pci_chip (device_t dev);
2446static int sym_pci_probe (device_t dev);
2447static int sym_pci_attach (device_t dev);
2448#else
2449static struct sym_pci_chip *sym_find_pci_chip (pcici_t tag);
2450static const char *sym_pci_probe (pcici_t tag, pcidi_t type);
2451static void sym_pci_attach (pcici_t tag, int unit);
2452static int sym_pci_attach2 (pcici_t tag, int unit);
2453#endif
2454
2455static void sym_pci_free (hcb_p np);
2456static int sym_cam_attach (hcb_p np);
2457static void sym_cam_free (hcb_p np);
2458
2459static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram);
2460static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp);
2461static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp);
2462
2463/*
2464 * Print something which allows to retrieve the controler type,
2465 * unit, target, lun concerned by a kernel message.
2466 */
2467static void PRINT_TARGET (hcb_p np, int target)
2468{
e3869ec7 2469 kprintf ("%s:%d:", sym_name(np), target);
984263bc
MD
2470}
2471
2472static void PRINT_LUN(hcb_p np, int target, int lun)
2473{
e3869ec7 2474 kprintf ("%s:%d:%d:", sym_name(np), target, lun);
984263bc
MD
2475}
2476
2477static void PRINT_ADDR (ccb_p cp)
2478{
2479 if (cp && cp->cam_ccb)
2480 xpt_print_path(cp->cam_ccb->ccb_h.path);
2481}
2482
2483/*
2484 * Take into account this ccb in the freeze count.
2485 */
2486static void sym_freeze_cam_ccb(union ccb *ccb)
2487{
2488 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) {
2489 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2490 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2491 xpt_freeze_devq(ccb->ccb_h.path, 1);
2492 }
2493 }
2494}
2495
2496/*
2497 * Set the status field of a CAM CCB.
2498 */
2499static __inline void sym_set_cam_status(union ccb *ccb, cam_status status)
2500{
2501 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2502 ccb->ccb_h.status |= status;
2503}
2504
2505/*
2506 * Get the status field of a CAM CCB.
2507 */
2508static __inline int sym_get_cam_status(union ccb *ccb)
2509{
2510 return ccb->ccb_h.status & CAM_STATUS_MASK;
2511}
2512
2513/*
2514 * Enqueue a CAM CCB.
2515 */
2516static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb)
2517{
2518 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED));
2519 ccb->ccb_h.status = CAM_REQ_INPROG;
2520
ddcafce9
JS
2521 callout_reset(&ccb->ccb_h.timeout_ch, ccb->ccb_h.timeout*hz/1000,
2522 sym_timeout, ccb);
984263bc
MD
2523 ccb->ccb_h.status |= CAM_SIM_QUEUED;
2524 ccb->ccb_h.sym_hcb_ptr = np;
2525
2526 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq);
2527}
2528
2529/*
2530 * Complete a pending CAM CCB.
2531 */
2532static void sym_xpt_done(hcb_p np, union ccb *ccb)
2533{
2534 if (ccb->ccb_h.status & CAM_SIM_QUEUED) {
ddcafce9 2535 callout_stop(&ccb->ccb_h.timeout_ch);
984263bc
MD
2536 sym_remque(sym_qptr(&ccb->ccb_h.sim_links));
2537 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2538 ccb->ccb_h.sym_hcb_ptr = 0;
2539 }
2540 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE)
2541 sym_freeze_cam_ccb(ccb);
2542 xpt_done(ccb);
2543}
2544
2545static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
2546{
2547 sym_set_cam_status(ccb, cam_status);
2548 sym_xpt_done(np, ccb);
2549}
2550
2551/*
2552 * SYMBIOS chip clock divisor table.
2553 *
2554 * Divisors are multiplied by 10,000,000 in order to make
2555 * calculations more simple.
2556 */
2557#define _5M 5000000
2558static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
2559
2560/*
2561 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
2562 * 128 transfers. All chips support at least 16 transfers
2563 * bursts. The 825A, 875 and 895 chips support bursts of up
2564 * to 128 transfers and the 895A and 896 support bursts of up
2565 * to 64 transfers. All other chips support up to 16
2566 * transfers bursts.
2567 *
2568 * For PCI 32 bit data transfers each transfer is a DWORD.
2569 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
2570 *
2571 * We use log base 2 (burst length) as internal code, with
2572 * value 0 meaning "burst disabled".
2573 */
2574
2575/*
2576 * Burst length from burst code.
2577 */
2578#define burst_length(bc) (!(bc))? 0 : 1 << (bc)
2579
2580/*
2581 * Burst code from io register bits.
2582 */
2583#define burst_code(dmode, ctest4, ctest5) \
2584 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
2585
2586/*
2587 * Set initial io register bits from burst code.
2588 */
2589static __inline void sym_init_burst(hcb_p np, u_char bc)
2590{
2591 np->rv_ctest4 &= ~0x80;
2592 np->rv_dmode &= ~(0x3 << 6);
2593 np->rv_ctest5 &= ~0x4;
2594
2595 if (!bc) {
2596 np->rv_ctest4 |= 0x80;
2597 }
2598 else {
2599 --bc;
2600 np->rv_dmode |= ((bc & 0x3) << 6);
2601 np->rv_ctest5 |= (bc & 0x4);
2602 }
2603}
2604
2605
2606/*
2607 * Print out the list of targets that have some flag disabled by user.
2608 */
2609static void sym_print_targets_flag(hcb_p np, int mask, char *msg)
2610{
2611 int cnt;
2612 int i;
2613
2614 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2615 if (i == np->myaddr)
2616 continue;
2617 if (np->target[i].usrflags & mask) {
2618 if (!cnt++)
e3869ec7 2619 kprintf("%s: %s disabled for targets",
984263bc 2620 sym_name(np), msg);
e3869ec7 2621 kprintf(" %d", i);
984263bc
MD
2622 }
2623 }
2624 if (cnt)
e3869ec7 2625 kprintf(".\n");
984263bc
MD
2626}
2627
2628/*
2629 * Save initial settings of some IO registers.
2630 * Assumed to have been set by BIOS.
2631 * We cannot reset the chip prior to reading the
2632 * IO registers, since informations will be lost.
2633 * Since the SCRIPTS processor may be running, this
2634 * is not safe on paper, but it seems to work quite
2635 * well. :)
2636 */
2637static void sym_save_initial_setting (hcb_p np)
2638{
2639 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
2640 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
2641 np->sv_dmode = INB(nc_dmode) & 0xce;
2642 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
2643 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
2644 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
2645 np->sv_gpcntl = INB(nc_gpcntl);
2646 np->sv_stest1 = INB(nc_stest1);
2647 np->sv_stest2 = INB(nc_stest2) & 0x20;
2648 np->sv_stest4 = INB(nc_stest4);
2649 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
2650 np->sv_scntl4 = INB(nc_scntl4);
2651 np->sv_ctest5 = INB(nc_ctest5) & 0x04;
2652 }
2653 else
2654 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
2655}
2656
2657/*
2658 * Prepare io register values used by sym_init() according
2659 * to selected and supported features.
2660 */
2661static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
2662{
2663 u_char burst_max;
2664 u32 period;
2665 int i;
2666
2667 /*
2668 * Wide ?
2669 */
2670 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
2671
2672 /*
2673 * Get the frequency of the chip's clock.
2674 */
2675 if (np->features & FE_QUAD)
2676 np->multiplier = 4;
2677 else if (np->features & FE_DBLR)
2678 np->multiplier = 2;
2679 else
2680 np->multiplier = 1;
2681
2682 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000;
2683 np->clock_khz *= np->multiplier;
2684
2685 if (np->clock_khz != 40000)
2686 sym_getclock(np, np->multiplier);
2687
2688 /*
2689 * Divisor to be used for async (timer pre-scaler).
2690 */
2691 i = np->clock_divn - 1;
2692 while (--i >= 0) {
2693 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
2694 ++i;
2695 break;
2696 }
2697 }
2698 np->rv_scntl3 = i+1;
2699
2700 /*
2701 * The C1010 uses hardwired divisors for async.
2702 * So, we just throw away, the async. divisor.:-)
2703 */
2704 if (np->features & FE_C10)
2705 np->rv_scntl3 = 0;
2706
2707 /*
2708 * Minimum synchronous period factor supported by the chip.
2709 * Btw, 'period' is in tenths of nanoseconds.
2710 */
2711 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
2712 if (period <= 250) np->minsync = 10;
2713 else if (period <= 303) np->minsync = 11;
2714 else if (period <= 500) np->minsync = 12;
2715 else np->minsync = (period + 40 - 1) / 40;
2716
2717 /*
2718 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
2719 */
2720 if (np->minsync < 25 &&
2721 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
2722 np->minsync = 25;
2723 else if (np->minsync < 12 &&
2724 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
2725 np->minsync = 12;
2726
2727 /*
2728 * Maximum synchronous period factor supported by the chip.
2729 */
2730 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
2731 np->maxsync = period > 2540 ? 254 : period / 10;
2732
2733 /*
2734 * If chip is a C1010, guess the sync limits in DT mode.
2735 */
2736 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
2737 if (np->clock_khz == 160000) {
2738 np->minsync_dt = 9;
2739 np->maxsync_dt = 50;
2740 np->maxoffs_dt = 62;
2741 }
2742 }
2743
2744 /*
2745 * 64 bit addressing (895A/896/1010) ?
2746 */
2747 if (np->features & FE_DAC)
2748#if BITS_PER_LONG > 32
2749 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
2750#else
2751 np->rv_ccntl1 |= (DDAC);
2752#endif
2753
2754 /*
2755 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
2756 */
2757 if (np->features & FE_NOPM)
2758 np->rv_ccntl0 |= (ENPMJ);
2759
2760 /*
2761 * C1010 Errata.
2762 * In dual channel mode, contention occurs if internal cycles
2763 * are used. Disable internal cycles.
2764 */
2765 if (np->device_id == PCI_ID_LSI53C1010 &&
2766 np->revision_id < 0x2)
2767 np->rv_ccntl0 |= DILS;
2768
2769 /*
2770 * Select burst length (dwords)
2771 */
2772 burst_max = SYM_SETUP_BURST_ORDER;
2773 if (burst_max == 255)
2774 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
2775 np->sv_ctest5);
2776 if (burst_max > 7)
2777 burst_max = 7;
2778 if (burst_max > np->maxburst)
2779 burst_max = np->maxburst;
2780
2781 /*
2782 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
2783 * This chip and the 860 Rev 1 may wrongly use PCI cache line
2784 * based transactions on LOAD/STORE instructions. So we have
2785 * to prevent these chips from using such PCI transactions in
2786 * this driver. The generic ncr driver that does not use
2787 * LOAD/STORE instructions does not need this work-around.
2788 */
2789 if ((np->device_id == PCI_ID_SYM53C810 &&
2790 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
2791 (np->device_id == PCI_ID_SYM53C860 &&
2792 np->revision_id <= 0x1))
2793 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
2794
2795 /*
2796 * Select all supported special features.
2797 * If we are using on-board RAM for scripts, prefetch (PFEN)
2798 * does not help, but burst op fetch (BOF) does.
2799 * Disabling PFEN makes sure BOF will be used.
2800 */
2801 if (np->features & FE_ERL)
2802 np->rv_dmode |= ERL; /* Enable Read Line */
2803 if (np->features & FE_BOF)
2804 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
2805 if (np->features & FE_ERMP)
2806 np->rv_dmode |= ERMP; /* Enable Read Multiple */
2807#if 1
2808 if ((np->features & FE_PFEN) && !np->ram_ba)
2809#else
2810 if (np->features & FE_PFEN)
2811#endif
2812 np->rv_dcntl |= PFEN; /* Prefetch Enable */
2813 if (np->features & FE_CLSE)
2814 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
2815 if (np->features & FE_WRIE)
2816 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
2817 if (np->features & FE_DFS)
2818 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
2819
2820 /*
2821 * Select some other
2822 */
2823 if (SYM_SETUP_PCI_PARITY)
2824 np->rv_ctest4 |= MPEE; /* Master parity checking */
2825 if (SYM_SETUP_SCSI_PARITY)
2826 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
2827
2828 /*
2829 * Get parity checking, host ID and verbose mode from NVRAM
2830 */
2831 np->myaddr = 255;
2832 sym_nvram_setup_host (np, nvram);
2833
2834 /*
2835 * Get SCSI addr of host adapter (set by bios?).
2836 */
2837 if (np->myaddr == 255) {
2838 np->myaddr = INB(nc_scid) & 0x07;
2839 if (!np->myaddr)
2840 np->myaddr = SYM_SETUP_HOST_ID;
2841 }
2842
2843 /*
2844 * Prepare initial io register bits for burst length
2845 */
2846 sym_init_burst(np, burst_max);
2847
2848 /*
2849 * Set SCSI BUS mode.
2850 * - LVD capable chips (895/895A/896/1010) report the
2851 * current BUS mode through the STEST4 IO register.
2852 * - For previous generation chips (825/825A/875),
2853 * user has to tell us how to check against HVD,
2854 * since a 100% safe algorithm is not possible.
2855 */
2856 np->scsi_mode = SMODE_SE;
2857 if (np->features & (FE_ULTRA2|FE_ULTRA3))
2858 np->scsi_mode = (np->sv_stest4 & SMODE);
2859 else if (np->features & FE_DIFF) {
2860 if (SYM_SETUP_SCSI_DIFF == 1) {
2861 if (np->sv_scntl3) {
2862 if (np->sv_stest2 & 0x20)
2863 np->scsi_mode = SMODE_HVD;
2864 }
2865 else if (nvram->type == SYM_SYMBIOS_NVRAM) {
2866 if (!(INB(nc_gpreg) & 0x08))
2867 np->scsi_mode = SMODE_HVD;
2868 }
2869 }
2870 else if (SYM_SETUP_SCSI_DIFF == 2)
2871 np->scsi_mode = SMODE_HVD;
2872 }
2873 if (np->scsi_mode == SMODE_HVD)
2874 np->rv_stest2 |= 0x20;
2875
2876 /*
2877 * Set LED support from SCRIPTS.
2878 * Ignore this feature for boards known to use a
2879 * specific GPIO wiring and for the 895A, 896
2880 * and 1010 that drive the LED directly.
2881 */
2882 if ((SYM_SETUP_SCSI_LED ||
2883 (nvram->type == SYM_SYMBIOS_NVRAM ||
2884 (nvram->type == SYM_TEKRAM_NVRAM &&
2885 np->device_id == PCI_ID_SYM53C895))) &&
2886 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
2887 np->features |= FE_LED0;
2888
2889 /*
2890 * Set irq mode.
2891 */
2892 switch(SYM_SETUP_IRQ_MODE & 3) {
2893 case 2:
2894 np->rv_dcntl |= IRQM;
2895 break;
2896 case 1:
2897 np->rv_dcntl |= (np->sv_dcntl & IRQM);
2898 break;
2899 default:
2900 break;
2901 }
2902
2903 /*
2904 * Configure targets according to driver setup.
2905 * If NVRAM present get targets setup from NVRAM.
2906 */
2907 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2908 tcb_p tp = &np->target[i];
2909
984263bc
MD
2910 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2;
2911 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2;
984263bc
MD
2912 tp->tinfo.user.period = np->minsync;
2913 tp->tinfo.user.offset = np->maxoffs;
2914 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT;
2915 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
2916 tp->usrtags = SYM_SETUP_MAX_TAG;
2917
2918 sym_nvram_setup_target (np, i, nvram);
2919
2920 /*
2921 * For now, guess PPR/DT support from the period
2922 * and BUS width.
2923 */
2924 if (np->features & FE_ULTRA3) {
2925 if (tp->tinfo.user.period <= 9 &&
2926 tp->tinfo.user.width == BUS_16_BIT) {
2927 tp->tinfo.user.options |= PPR_OPT_DT;
2928 tp->tinfo.user.offset = np->maxoffs_dt;
984263bc 2929 tp->tinfo.user.spi_version = 3;
984263bc
MD
2930 }
2931 }
2932
2933 if (!tp->usrtags)
2934 tp->usrflags &= ~SYM_TAGS_ENABLED;
2935 }
2936
2937 /*
2938 * Let user know about the settings.
2939 */
2940 i = nvram->type;
e3869ec7 2941 kprintf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np),
984263bc
MD
2942 i == SYM_SYMBIOS_NVRAM ? "Symbios" :
2943 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"),
2944 np->myaddr,
2945 (np->features & FE_ULTRA3) ? 80 :
2946 (np->features & FE_ULTRA2) ? 40 :
2947 (np->features & FE_ULTRA) ? 20 : 10,
2948 sym_scsi_bus_mode(np->scsi_mode),
2949 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
2950 /*
2951 * Tell him more on demand.
2952 */
2953 if (sym_verbose) {
e3869ec7 2954 kprintf("%s: %s IRQ line driver%s\n",
984263bc
MD
2955 sym_name(np),
2956 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
2957 np->ram_ba ? ", using on-chip SRAM" : "");
e3869ec7 2958 kprintf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
984263bc 2959 if (np->features & FE_NOPM)
e3869ec7 2960 kprintf("%s: handling phase mismatch from SCRIPTS.\n",
984263bc
MD
2961 sym_name(np));
2962 }
2963 /*
2964 * And still more.
2965 */
2966 if (sym_verbose > 1) {
e3869ec7 2967 kprintf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
984263bc
MD
2968 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2969 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
2970 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
2971
e3869ec7 2972 kprintf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
984263bc
MD
2973 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
2974 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
2975 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
2976 }
2977 /*
2978 * Let user be aware of targets that have some disable flags set.
2979 */
2980 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT");
2981 if (sym_verbose)
2982 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED,
2983 "SCAN FOR LUNS");
2984
2985 return 0;
2986}
2987
2988/*
2989 * Prepare the next negotiation message if needed.
2990 *
2991 * Fill in the part of message buffer that contains the
2992 * negotiation and the nego_status field of the CCB.
2993 * Returns the size of the message in bytes.
2994 */
2995
2996static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr)
2997{
2998 tcb_p tp = &np->target[cp->target];
2999 int msglen = 0;
3000
3001 /*
3002 * Early C1010 chips need a work-around for DT
3003 * data transfer to work.
3004 */
3005 if (!(np->features & FE_U3EN))
3006 tp->tinfo.goal.options = 0;
3007 /*
3008 * negotiate using PPR ?
3009 */
3010 if (tp->tinfo.goal.options & PPR_OPT_MASK)
3011 nego = NS_PPR;
3012 /*
3013 * negotiate wide transfers ?
3014 */
3015 else if (tp->tinfo.current.width != tp->tinfo.goal.width)
3016 nego = NS_WIDE;
3017 /*
3018 * negotiate synchronous transfers?
3019 */
3020 else if (tp->tinfo.current.period != tp->tinfo.goal.period ||
3021 tp->tinfo.current.offset != tp->tinfo.goal.offset)
3022 nego = NS_SYNC;
3023
3024 switch (nego) {
3025 case NS_SYNC:
3026 msgptr[msglen++] = M_EXTENDED;
3027 msgptr[msglen++] = 3;
3028 msgptr[msglen++] = M_X_SYNC_REQ;
3029 msgptr[msglen++] = tp->tinfo.goal.period;
3030 msgptr[msglen++] = tp->tinfo.goal.offset;
3031 break;
3032 case NS_WIDE:
3033 msgptr[msglen++] = M_EXTENDED;
3034 msgptr[msglen++] = 2;
3035 msgptr[msglen++] = M_X_WIDE_REQ;
3036 msgptr[msglen++] = tp->tinfo.goal.width;
3037 break;
3038 case NS_PPR:
3039 msgptr[msglen++] = M_EXTENDED;
3040 msgptr[msglen++] = 6;
3041 msgptr[msglen++] = M_X_PPR_REQ;
3042 msgptr[msglen++] = tp->tinfo.goal.period;
3043 msgptr[msglen++] = 0;
3044 msgptr[msglen++] = tp->tinfo.goal.offset;
3045 msgptr[msglen++] = tp->tinfo.goal.width;
3046 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT;
3047 break;
3048 };
3049
3050 cp->nego_status = nego;
3051
3052 if (nego) {
3053 tp->nego_cp = cp; /* Keep track a nego will be performed */
3054 if (DEBUG_FLAGS & DEBUG_NEGO) {
3055 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" :
3056 nego == NS_WIDE ? "wide msgout" :
3057 "ppr msgout", msgptr);
3058 };
3059 };
3060
3061 return msglen;
3062}
3063
3064/*
3065 * Insert a job into the start queue.
3066 */
3067static void sym_put_start_queue(hcb_p np, ccb_p cp)
3068{
3069 u_short qidx;
3070
3071#ifdef SYM_CONF_IARB_SUPPORT
3072 /*
3073 * If the previously queued CCB is not yet done,
3074 * set the IARB hint. The SCRIPTS will go with IARB
3075 * for this job when starting the previous one.
3076 * We leave devices a chance to win arbitration by
3077 * not using more than 'iarb_max' consecutive
3078 * immediate arbitrations.
3079 */
3080 if (np->last_cp && np->iarb_count < np->iarb_max) {
3081 np->last_cp->host_flags |= HF_HINT_IARB;
3082 ++np->iarb_count;
3083 }
3084 else
3085 np->iarb_count = 0;
3086 np->last_cp = cp;
3087#endif
3088
3089 /*
3090 * Insert first the idle task and then our job.
3091 * The MB should ensure proper ordering.
3092 */
3093 qidx = np->squeueput + 2;
3094 if (qidx >= MAX_QUEUE*2) qidx = 0;
3095
3096 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
3097 MEMORY_BARRIER();
3098 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
3099
3100 np->squeueput = qidx;
3101
3102 if (DEBUG_FLAGS & DEBUG_QUEUE)
e3869ec7 3103 kprintf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
984263bc
MD
3104
3105 /*
3106 * Script processor may be waiting for reselect.
3107 * Wake it up.
3108 */
3109 MEMORY_BARRIER();
3110 OUTB (nc_istat, SIGP|np->istat_sem);
3111}
3112
3113
3114/*
3115 * Soft reset the chip.
3116 *
3117 * Raising SRST when the chip is running may cause
3118 * problems on dual function chips (see below).
3119 * On the other hand, LVD devices need some delay
3120 * to settle and report actual BUS mode in STEST4.
3121 */
3122static void sym_chip_reset (hcb_p np)
3123{
3124 OUTB (nc_istat, SRST);
3125 UDELAY (10);
3126 OUTB (nc_istat, 0);
3127 UDELAY(2000); /* For BUS MODE to settle */
3128}
3129
3130/*
3131 * Soft reset the chip.
3132 *
3133 * Some 896 and 876 chip revisions may hang-up if we set
3134 * the SRST (soft reset) bit at the wrong time when SCRIPTS
3135 * are running.
3136 * So, we need to abort the current operation prior to
3137 * soft resetting the chip.
3138 */
3139static void sym_soft_reset (hcb_p np)
3140{
3141 u_char istat;
3142 int i;
3143
3144 OUTB (nc_istat, CABRT);
3145 for (i = 1000000 ; i ; --i) {
3146 istat = INB (nc_istat);
3147 if (istat & SIP) {
3148 INW (nc_sist);
3149 continue;
3150 }
3151 if (istat & DIP) {
3152 OUTB (nc_istat, 0);
3153 INB (nc_dstat);
3154 break;
3155 }
3156 }
3157 if (!i)
e3869ec7 3158 kprintf("%s: unable to abort current chip operation.\n",
984263bc
MD
3159 sym_name(np));
3160 sym_chip_reset (np);
3161}
3162
3163/*
3164 * Start reset process.
3165 *
3166 * The interrupt handler will reinitialize the chip.
3167 */
3168static void sym_start_reset(hcb_p np)
3169{
3170 (void) sym_reset_scsi_bus(np, 1);
3171}
3172
3173static int sym_reset_scsi_bus(hcb_p np, int enab_int)
3174{
3175 u32 term;
3176 int retv = 0;
3177
3178 sym_soft_reset(np); /* Soft reset the chip */
3179 if (enab_int)
3180 OUTW (nc_sien, RST);
3181 /*
3182 * Enable Tolerant, reset IRQD if present and
3183 * properly set IRQ mode, prior to resetting the bus.
3184 */
3185 OUTB (nc_stest3, TE);
3186 OUTB (nc_dcntl, (np->rv_dcntl & IRQM));
3187 OUTB (nc_scntl1, CRST);
3188 UDELAY (200);
3189
3190 if (!SYM_SETUP_SCSI_BUS_CHECK)
3191 goto out;
3192 /*
3193 * Check for no terminators or SCSI bus shorts to ground.
3194 * Read SCSI data bus, data parity bits and control signals.
3195 * We are expecting RESET to be TRUE and other signals to be
3196 * FALSE.
3197 */
3198 term = INB(nc_sstat0);
3199 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
3200 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
3201 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
3202 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
3203 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
3204
3205 if (!(np->features & FE_WIDE))
3206 term &= 0x3ffff;
3207
3208 if (term != (2<<7)) {
e3869ec7 3209 kprintf("%s: suspicious SCSI data while resetting the BUS.\n",
984263bc 3210 sym_name(np));
e3869ec7 3211 kprintf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
984263bc
MD
3212 "0x%lx, expecting 0x%lx\n",
3213 sym_name(np),
3214 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
3215 (u_long)term, (u_long)(2<<7));
3216 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
3217 retv = 1;
3218 }
3219out:
3220 OUTB (nc_scntl1, 0);
3221 /* MDELAY(100); */
3222 return retv;
3223}
3224
3225/*
3226 * The chip may have completed jobs. Look at the DONE QUEUE.
3227 *
3228 * On architectures that may reorder LOAD/STORE operations,
3229 * a memory barrier may be needed after the reading of the
3230 * so-called `flag' and prior to dealing with the data.
3231 */
3232static int sym_wakeup_done (hcb_p np)
3233{
3234 ccb_p cp;
3235 int i, n;
3236 u32 dsa;
3237
3238 n = 0;
3239 i = np->dqueueget;
3240 while (1) {
3241 dsa = scr_to_cpu(np->dqueue[i]);
3242 if (!dsa)
3243 break;
3244 np->dqueue[i] = 0;
3245 if ((i = i+2) >= MAX_QUEUE*2)
3246 i = 0;
3247
3248 cp = sym_ccb_from_dsa(np, dsa);
3249 if (cp) {
3250 MEMORY_BARRIER();
3251 sym_complete_ok (np, cp);
3252 ++n;
3253 }
3254 else
e3869ec7 3255 kprintf ("%s: bad DSA (%x) in done queue.\n",
984263bc
MD
3256 sym_name(np), (u_int) dsa);
3257 }
3258 np->dqueueget = i;
3259
3260 return n;
3261}
3262
3263/*
3264 * Complete all active CCBs with error.
3265 * Used on CHIP/SCSI RESET.
3266 */
3267static void sym_flush_busy_queue (hcb_p np, int cam_status)
3268{
3269 /*
3270 * Move all active CCBs to the COMP queue
3271 * and flush this queue.
3272 */
3273 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
3274 sym_que_init(&np->busy_ccbq);
3275 sym_flush_comp_queue(np, cam_status);
3276}
3277
3278/*
3279 * Start chip.
3280 *
3281 * 'reason' means:
3282 * 0: initialisation.
3283 * 1: SCSI BUS RESET delivered or received.
3284 * 2: SCSI BUS MODE changed.
3285 */
3286static void sym_init (hcb_p np, int reason)
3287{
3288 int i;
3289 u32 phys;
3290
3291 /*
3292 * Reset chip if asked, otherwise just clear fifos.
3293 */
3294 if (reason == 1)
3295 sym_soft_reset(np);
3296 else {
3297 OUTB (nc_stest3, TE|CSF);
3298 OUTONB (nc_ctest3, CLF);
3299 }
3300
3301 /*
3302 * Clear Start Queue
3303 */
3304 phys = np->squeue_ba;
3305 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3306 np->squeue[i] = cpu_to_scr(np->idletask_ba);
3307 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
3308 }
3309 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3310
3311 /*
3312 * Start at first entry.
3313 */
3314 np->squeueput = 0;
3315
3316 /*
3317 * Clear Done Queue
3318 */
3319 phys = np->dqueue_ba;
3320 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3321 np->dqueue[i] = 0;
3322 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
3323 }
3324 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3325
3326 /*
3327 * Start at first entry.
3328 */
3329 np->dqueueget = 0;
3330
3331 /*
3332 * Install patches in scripts.
3333 * This also let point to first position the start
3334 * and done queue pointers used from SCRIPTS.
3335 */
3336 np->fw_patch(np);
3337
3338 /*
3339 * Wakeup all pending jobs.
3340 */
3341 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);
3342
3343 /*
3344 * Init chip.
3345 */
3346 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */
3347 UDELAY (2000); /* The 895 needs time for the bus mode to settle */
3348
3349 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
3350 /* full arb., ena parity, par->ATN */
3351 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
3352
3353 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
3354
3355 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
3356 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
3357 OUTB (nc_istat , SIGP ); /* Signal Process */
3358 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
3359 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
3360
3361 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
3362 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
3363 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
3364
3365 /* Extended Sreq/Sack filtering not supported on the C10 */
3366 if (np->features & FE_C10)
3367 OUTB (nc_stest2, np->rv_stest2);
3368 else
3369 OUTB (nc_stest2, EXT|np->rv_stest2);
3370
3371 OUTB (nc_stest3, TE); /* TolerANT enable */
3372 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
3373
3374 /*
3375 * For now, disable AIP generation on C1010-66.
3376 */
3377 if (np->device_id == PCI_ID_LSI53C1010_2)
3378 OUTB (nc_aipcntl1, DISAIP);
3379
3380 /*
3381 * C10101 Errata.
3382 * Errant SGE's when in narrow. Write bits 4 & 5 of
3383 * STEST1 register to disable SGE. We probably should do
3384 * that from SCRIPTS for each selection/reselection, but
3385 * I just don't want. :)
3386 */
3387 if (np->device_id == PCI_ID_LSI53C1010 &&
3388 /* np->revision_id < 0xff */ 1)
3389 OUTB (nc_stest1, INB(nc_stest1) | 0x30);
3390
3391 /*
3392 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
3393 * Disable overlapped arbitration for some dual function devices,
3394 * regardless revision id (kind of post-chip-design feature. ;-))
3395 */
3396 if (np->device_id == PCI_ID_SYM53C875)
3397 OUTB (nc_ctest0, (1<<5));
3398 else if (np->device_id == PCI_ID_SYM53C896)
3399 np->rv_ccntl0 |= DPR;
3400
3401 /*
3402 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
3403 * and/or hardware phase mismatch, since only such chips
3404 * seem to support those IO registers.
3405 */
3406 if (np->features & (FE_DAC|FE_NOPM)) {
3407 OUTB (nc_ccntl0, np->rv_ccntl0);
3408 OUTB (nc_ccntl1, np->rv_ccntl1);
3409 }
3410
3411 /*
3412 * If phase mismatch handled by scripts (895A/896/1010),
3413 * set PM jump addresses.
3414 */
3415 if (np->features & FE_NOPM) {
3416 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle));
3417 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle));
3418 }
3419
3420 /*
3421 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
3422 * Also set GPIO5 and clear GPIO6 if hardware LED control.
3423 */
3424 if (np->features & FE_LED0)
3425 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01);
3426 else if (np->features & FE_LEDC)
3427 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20);
3428
3429 /*
3430 * enable ints
3431 */
3432 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
3433 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID);
3434
3435 /*
3436 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
3437 * Try to eat the spurious SBMC interrupt that may occur when
3438 * we reset the chip but not the SCSI BUS (at initialization).
3439 */
3440 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
3441 OUTONW (nc_sien, SBMC);
3442 if (reason == 0) {
3443 MDELAY(100);
3444 INW (nc_sist);
3445 }
3446 np->scsi_mode = INB (nc_stest4) & SMODE;
3447 }
3448
3449 /*
3450 * Fill in target structure.
3451 * Reinitialize usrsync.
3452 * Reinitialize usrwide.
3453 * Prepare sync negotiation according to actual SCSI bus mode.
3454 */
3455 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
3456 tcb_p tp = &np->target[i];
3457
3458 tp->to_reset = 0;
3459 tp->head.sval = 0;
3460 tp->head.wval = np->rv_scntl3;
3461 tp->head.uval = 0;
3462
3463 tp->tinfo.current.period = 0;
3464 tp->tinfo.current.offset = 0;
3465 tp->tinfo.current.width = BUS_8_BIT;
3466 tp->tinfo.current.options = 0;
3467 }
3468
3469 /*
3470 * Download SCSI SCRIPTS to on-chip RAM if present,
3471 * and start script processor.
3472 */
3473 if (np->ram_ba) {
3474 if (sym_verbose > 1)
e3869ec7 3475 kprintf ("%s: Downloading SCSI SCRIPTS.\n",
984263bc
MD
3476 sym_name(np));
3477 if (np->ram_ws == 8192) {
3478 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz);
3479 OUTL (nc_mmws, np->scr_ram_seg);
3480 OUTL (nc_mmrs, np->scr_ram_seg);
3481 OUTL (nc_sfs, np->scr_ram_seg);
3482 phys = SCRIPTB_BA (np, start64);
3483 }
3484 else
3485 phys = SCRIPTA_BA (np, init);
3486 OUTRAM_OFF(0, np->scripta0, np->scripta_sz);
3487 }
3488 else
3489 phys = SCRIPTA_BA (np, init);
3490
3491 np->istat_sem = 0;
3492
3493 OUTL (nc_dsa, np->hcb_ba);
3494 OUTL_DSP (phys);
3495
3496 /*
3497 * Notify the XPT about the RESET condition.
3498 */
3499 if (reason != 0)
3500 xpt_async(AC_BUS_RESET, np->path, NULL);
3501}
3502
3503/*
3504 * Get clock factor and sync divisor for a given
3505 * synchronous factor period.
3506 */
3507static int
3508sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
3509{
3510 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
3511 int div = np->clock_divn; /* Number of divisors supported */
3512 u32 fak; /* Sync factor in sxfer */
3513 u32 per; /* Period in tenths of ns */
3514 u32 kpc; /* (per * clk) */
3515 int ret;
3516
3517 /*
3518 * Compute the synchronous period in tenths of nano-seconds
3519 */
3520 if (dt && sfac <= 9) per = 125;
3521 else if (sfac <= 10) per = 250;
3522 else if (sfac == 11) per = 303;
3523 else if (sfac == 12) per = 500;
3524 else per = 40 * sfac;
3525 ret = per;
3526
3527 kpc = per * clk;
3528 if (dt)
3529 kpc <<= 1;
3530
3531 /*
3532 * For earliest C10 revision 0, we cannot use extra
3533 * clocks for the setting of the SCSI clocking.
3534 * Note that this limits the lowest sync data transfer
3535 * to 5 Mega-transfers per second and may result in
3536 * using higher clock divisors.
3537 */
3538#if 1
3539 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
3540 /*
3541 * Look for the lowest clock divisor that allows an
3542 * output speed not faster than the period.
3543 */
3544 while (div > 0) {
3545 --div;
3546 if (kpc > (div_10M[div] << 2)) {
3547 ++div;
3548 break;
3549 }
3550 }
3551 fak = 0; /* No extra clocks */
3552 if (div == np->clock_divn) { /* Are we too fast ? */
3553 ret = -1;
3554 }
3555 *divp = div;
3556 *fakp = fak;
3557 return ret;
3558 }
3559#endif
3560
3561 /*
3562 * Look for the greatest clock divisor that allows an
3563 * input speed faster than the period.
3564 */
3565 while (div-- > 0)
3566 if (kpc >= (div_10M[div] << 2)) break;
3567
3568 /*
3569 * Calculate the lowest clock factor that allows an output
3570 * speed not faster than the period, and the max output speed.
3571 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
3572 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
3573 */
3574 if (dt) {
3575 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
3576 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
3577 }
3578 else {
3579 fak = (kpc - 1) / div_10M[div] + 1 - 4;
3580 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
3581 }
3582
3583 /*
3584 * Check against our hardware limits, or bugs :).
3585 */
3586 if (fak < 0) {fak = 0; ret = -1;}
3587 if (fak > 2) {fak = 2; ret = -1;}
3588
3589 /*
3590 * Compute and return sync parameters.
3591 */
3592 *divp = div;
3593 *fakp = fak;
3594
3595 return ret;
3596}
3597
3598/*
3599 * Tell the SCSI layer about the new transfer parameters.
3600 */
3601static void
3602sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid)
3603{
3604 struct ccb_trans_settings cts;
3605 struct cam_path *path;
3606 int sts;
3607 tcb_p tp = &np->target[target];
3608
3609 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target,
3610 CAM_LUN_WILDCARD);
3611 if (sts != CAM_REQ_CMP)
3612 return;
3613
3614 bzero(&cts, sizeof(cts));
3615
984263bc
MD
3616#define cts__scsi (cts.proto_specific.scsi)
3617#define cts__spi (cts.xport_specific.spi)
3618
3619 cts.type = CTS_TYPE_CURRENT_SETTINGS;
3620 cts.protocol = PROTO_SCSI;
3621 cts.transport = XPORT_SPI;
3622 cts.protocol_version = tp->tinfo.current.scsi_version;
3623 cts.transport_version = tp->tinfo.current.spi_version;
3624
3625 cts__spi.valid = spi_valid;
3626 if (spi_valid & CTS_SPI_VALID_SYNC_RATE)
3627 cts__spi.sync_period = tp->tinfo.current.period;
3628 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET)
3629 cts__spi.sync_offset = tp->tinfo.current.offset;
3630 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH)
3631 cts__spi.bus_width = tp->tinfo.current.width;
3632 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS)
3633 cts__spi.ppr_options = tp->tinfo.current.options;
3634#undef cts__spi
3635#undef cts__scsi
984263bc
MD
3636 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1);
3637 xpt_async(AC_TRANSFER_NEG, path, &cts);
3638 xpt_free_path(path);
3639}
3640
984263bc
MD
3641#define SYM_SPI_VALID_WDTR \
3642 CTS_SPI_VALID_BUS_WIDTH | \
3643 CTS_SPI_VALID_SYNC_RATE | \
3644 CTS_SPI_VALID_SYNC_OFFSET
3645#define SYM_SPI_VALID_SDTR \
3646 CTS_SPI_VALID_SYNC_RATE | \
3647 CTS_SPI_VALID_SYNC_OFFSET
3648#define SYM_SPI_VALID_PPR \
3649 CTS_SPI_VALID_PPR_OPTIONS | \
3650 CTS_SPI_VALID_BUS_WIDTH | \
3651 CTS_SPI_VALID_SYNC_RATE | \
3652 CTS_SPI_VALID_SYNC_OFFSET
984263bc
MD
3653
3654/*
3655 * We received a WDTR.
3656 * Let everything be aware of the changes.
3657 */
3658static void sym_setwide(hcb_p np, ccb_p cp, u_char wide)
3659{
3660 tcb_p tp = &np->target[cp->target];
3661
3662 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0);
3663
3664 /*
3665 * Tell the SCSI layer about the new transfer parameters.
3666 */
3667 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3668 tp->tinfo.current.offset = 0;
3669 tp->tinfo.current.period = 0;
3670 tp->tinfo.current.options = 0;
3671
3672 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR);
3673}
3674
3675/*
3676 * We received a SDTR.
3677 * Let everything be aware of the changes.
3678 */
3679static void
3680sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
3681{
3682 tcb_p tp = &np->target[cp->target];
3683 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0;
3684
3685 sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
3686
3687 /*
3688 * Tell the SCSI layer about the new transfer parameters.
3689 */
3690 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3691 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3692 tp->tinfo.goal.options = tp->tinfo.current.options = 0;
3693
3694 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR);
3695}
3696
3697/*
3698 * We received a PPR.
3699 * Let everything be aware of the changes.
3700 */
3701static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3702 u_char per, u_char wide, u_char div, u_char fak)
3703{
3704 tcb_p tp = &np->target[cp->target];
3705
3706 sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
3707
3708 /*
3709 * Tell the SCSI layer about the new transfer parameters.
3710 */
3711 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3712 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3713 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3714 tp->tinfo.goal.options = tp->tinfo.current.options = dt;
3715
3716 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR);
3717}
3718
3719/*
3720 * Switch trans mode for current job and it's target.
3721 */
3722static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3723 u_char per, u_char wide, u_char div, u_char fak)
3724{
3725 SYM_QUEHEAD *qp;
3726 union ccb *ccb;
3727 tcb_p tp;
3728 u_char target = INB (nc_sdid) & 0x0f;
3729 u_char sval, wval, uval;
3730
3731 assert (cp);
3732 if (!cp) return;
3733 ccb = cp->cam_ccb;
3734 assert (ccb);
3735 if (!ccb) return;
3736 assert (target == (cp->target & 0xf));
3737 tp = &np->target[target];
3738
3739 sval = tp->head.sval;
3740 wval = tp->head.wval;
3741 uval = tp->head.uval;
3742
3743#if 0
e3869ec7 3744 kprintf("XXXX sval=%x wval=%x uval=%x (%x)\n",
984263bc
MD
3745 sval, wval, uval, np->rv_scntl3);
3746#endif
3747 /*
3748 * Set the offset.
3749 */
3750 if (!(np->features & FE_C10))
3751 sval = (sval & ~0x1f) | ofs;
3752 else
3753 sval = (sval & ~0x3f) | ofs;
3754
3755 /*
3756 * Set the sync divisor and extra clock factor.
3757 */
3758 if (ofs != 0) {
3759 wval = (wval & ~0x70) | ((div+1) << 4);
3760 if (!(np->features & FE_C10))
3761 sval = (sval & ~0xe0) | (fak << 5);
3762 else {
3763 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
3764 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
3765 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
3766 }
3767 }
3768
3769 /*
3770 * Set the bus width.
3771 */
3772 wval = wval & ~EWS;
3773 if (wide != 0)
3774 wval |= EWS;
3775
3776 /*
3777 * Set misc. ultra enable bits.
3778 */
3779 if (np->features & FE_C10) {
3780 uval = uval & ~(U3EN|AIPCKEN);
3781 if (dt) {
3782 assert(np->features & FE_U3EN);
3783 uval |= U3EN;
3784 }
3785 }
3786 else {
3787 wval = wval & ~ULTRA;
3788 if (per <= 12) wval |= ULTRA;
3789 }
3790
3791 /*
3792 * Stop there if sync parameters are unchanged.
3793 */
3794 if (tp->head.sval == sval &&
3795 tp->head.wval == wval &&
3796 tp->head.uval == uval)
3797 return;
3798 tp->head.sval = sval;
3799 tp->head.wval = wval;
3800 tp->head.uval = uval;
3801
3802 /*
3803 * Disable extended Sreq/Sack filtering if per < 50.
3804 * Not supported on the C1010.
3805 */
3806 if (per < 50 && !(np->features & FE_C10))
3807 OUTOFFB (nc_stest2, EXT);
3808
3809 /*
3810 * set actual value and sync_status
3811 */
3812 OUTB (nc_sxfer, tp->head.sval);
3813 OUTB (nc_scntl3, tp->head.wval);
3814
3815 if (np->features & FE_C10) {
3816 OUTB (nc_scntl4, tp->head.uval);
3817 }
3818
3819 /*
3820 * patch ALL busy ccbs of this target.
3821 */
3822 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3823 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3824 if (cp->target != target)
3825 continue;
3826 cp->phys.select.sel_scntl3 = tp->head.wval;
3827 cp->phys.select.sel_sxfer = tp->head.sval;
3828 if (np->features & FE_C10) {
3829 cp->phys.select.sel_scntl4 = tp->head.uval;
3830 }
3831 }
3832}
3833
3834/*
3835 * log message for real hard errors
3836 *
3837 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc).
3838 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
3839 *
3840 * exception register:
3841 * ds: dstat
3842 * si: sist
3843 *
3844 * SCSI bus lines:
3845 * so: control lines as driven by chip.
3846 * si: control lines as seen by chip.
3847 * sd: scsi data lines as seen by chip.
3848 *
3849 * wide/fastmode:
3850 * sxfer: (see the manual)
3851 * scntl3: (see the manual)
3852 *
3853 * current script command:
3854 * dsp: script adress (relative to start of script).
3855 * dbc: first word of script command.
3856 *
3857 * First 24 register of the chip:
3858 * r0..rf
3859 */
3860static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat)
3861{
3862 u32 dsp;
3863 int script_ofs;
3864 int script_size;
3865 char *script_name;
3866 u_char *script_base;
3867 int i;
3868
3869 dsp = INL (nc_dsp);
3870
3871 if (dsp > np->scripta_ba &&
3872 dsp <= np->scripta_ba + np->scripta_sz) {
3873 script_ofs = dsp - np->scripta_ba;
3874 script_size = np->scripta_sz;
3875 script_base = (u_char *) np->scripta0;
3876 script_name = "scripta";
3877 }
3878 else if (np->scriptb_ba < dsp &&
3879 dsp <= np->scriptb_ba + np->scriptb_sz) {
3880 script_ofs = dsp - np->scriptb_ba;
3881 script_size = np->scriptb_sz;
3882 script_base = (u_char *) np->scriptb0;
3883 script_name = "scriptb";
3884 } else {
3885 script_ofs = dsp;
3886 script_size = 0;
3887 script_base = 0;
3888 script_name = "mem";
3889 }
3890
e3869ec7 3891 kprintf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
984263bc
MD
3892 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
3893 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl),
3894 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer),
3895 (unsigned)INB (nc_scntl3), script_name, script_ofs,
3896 (unsigned)INL (nc_dbc));
3897
3898 if (((script_ofs & 3) == 0) &&
3899 (unsigned)script_ofs < script_size) {
e3869ec7 3900 kprintf ("%s: script cmd = %08x\n", sym_name(np),
984263bc
MD
3901 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
3902 }
3903
e3869ec7 3904 kprintf ("%s: regdump:", sym_name(np));
984263bc 3905 for (i=0; i<24;i++)
e3869ec7
SW
3906 kprintf (" %02x", (unsigned)INB_OFF(i));
3907 kprintf (".\n");
984263bc
MD
3908
3909 /*
3910 * PCI BUS error, read the PCI ststus register.
3911 */
3912 if (dstat & (MDPE|BF)) {
3913 u_short pci_sts;
3914#ifdef FreeBSD_Bus_Io_Abstraction
3915 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2);
3916#else
3917 pci_sts = pci_cfgread(np->pci_tag, PCIR_STATUS, 2);
3918#endif
3919 if (pci_sts & 0xf900) {
3920#ifdef FreeBSD_Bus_Io_Abstraction
3921 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2);
3922#else
3923 pci_cfgwrite(np->pci_tag, PCIR_STATUS, pci_sts, 2);
3924#endif
e3869ec7 3925 kprintf("%s: PCI STATUS = 0x%04x\n",
984263bc
MD
3926 sym_name(np), pci_sts & 0xf900);
3927 }
3928 }
3929}
3930
3931/*
3932 * chip interrupt handler
3933 *
3934 * In normal situations, interrupt conditions occur one at
3935 * a time. But when something bad happens on the SCSI BUS,
3936 * the chip may raise several interrupt flags before
3937 * stopping and interrupting the CPU. The additionnal
3938 * interrupt flags are stacked in some extra registers
3939 * after the SIP and/or DIP flag has been raised in the
3940 * ISTAT. After the CPU has read the interrupt condition
3941 * flag from SIST or DSTAT, the chip unstacks the other
3942 * interrupt flags and sets the corresponding bits in
3943 * SIST or DSTAT. Since the chip starts stacking once the
3944 * SIP or DIP flag is set, there is a small window of time
3945 * where the stacking does not occur.
3946 *
3947 * Typically, multiple interrupt conditions may happen in
3948 * the following situations:
3949 *
3950 * - SCSI parity error + Phase mismatch (PAR|MA)
3951 * When an parity error is detected in input phase
3952 * and the device switches to msg-in phase inside a
3953 * block MOV.
3954 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
3955 * When a stupid device does not want to handle the
3956 * recovery of an SCSI parity error.
3957 * - Some combinations of STO, PAR, UDC, ...
3958 * When using non compliant SCSI stuff, when user is
3959 * doing non compliant hot tampering on the BUS, when
3960 * something really bad happens to a device, etc ...
3961 *
3962 * The heuristic suggested by SYMBIOS to handle
3963 * multiple interrupts is to try unstacking all